Light emitting device, optical device and information processing device

Abstract

The light-emitting device includes: a wiring substrate; a substrate disposed on the wiring substrate; a light-emitting element array disposed on the substrate and having a first side and a second side facing each other, and a third side and a fourth side facing each other connecting the first side and the second side; a driving unit disposed on the wiring substrate on the first side side for driving the light-emitting element array; a first circuit element disposed on the substrate on the first side side; a second circuit element disposed on the substrate on the second side side and occupying a larger area on the substrate than the first circuit element; and a wiring member disposed on the third side side and the fourth side side and extending from the upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array.

Description

Technical Field

[0001] The present invention relates to a light emitting device, an optical device and an information processing device. Background Art

[0002] Patent document 1 describes an imaging device comprising: a light source; a light diffusion component having a plurality of lenses arranged adjacent to each other on a predetermined plane and diffusing light emitted by the light source; and an imaging element receiving reflected light obtained by reflecting the light diffused by the light diffusion component from an imaged object, wherein the plurality of lenses are arranged so that the period of interference fringes in the diffused light is less than three pixels.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-54769 Summary of the invention

[0006] Problems to be solved by the invention

[0007] However, in the case where it is desired to reduce the inductance of the circuit driving the light emitting element array, there is a case where wiring such as bonding wires is provided not only on one side of the light emitting element array but also on multiple side sides. Furthermore, there is a case where multiple circuit elements such as light receiving elements and temperature detection elements need to be arranged on the side close to the light emitting element array. In such a case, it is possible to consider a structure in which the circuit elements are arranged on the substrate on the side close to the driving unit of the light emitting element array and on the substrate on the side opposite to the driving unit across the light emitting element array, and wiring such as bonding wires are arranged on the remaining side. However, in the case where the sizes of the multiple circuit elements are different, if a larger circuit element is arranged on the driving unit side, it is difficult to bring the driving unit close to the light emitting element array, and the inductance of the circuit increases.

[0008] At least one embodiment of the present invention provides a light emitting device or the like having a structure that facilitates bringing a driving unit closer to a light emitting element array, compared with a structure in which a circuit element occupying a larger area is disposed on a side of the light emitting element array close to a driving unit.

[0009] Means for solving problems

[0010] According to a first aspect of the present invention, there is provided a light-emitting device comprising: a wiring substrate; a substrate disposed on the wiring substrate; a light-emitting element array disposed on the substrate and having a first side surface and a second side surface opposite to each other, and a third side surface and a fourth side surface opposite to each other connecting the first side surface and the second side surface; a driving unit disposed on the wiring substrate on the first side surface and used to drive the light-emitting element array; a first circuit element disposed on the substrate on the first side surface; a second circuit element disposed on the substrate on the second side surface and occupying a larger area on the substrate than the first circuit element; and a wiring component disposed on the third side surface and the fourth side surface and extending from an upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array.

[0011] According to a second aspect of the present invention, there is provided the light emitting device of the first aspect, wherein at least one of the first circuit element and the second circuit element is a light receiving element that receives light emitted by the light emitting element array.

[0012] According to a third aspect of the present invention, there is provided the light emitting device of the first aspect, wherein at least one of the first circuit element and the second circuit element is a temperature detection element that detects a temperature of the substrate.

[0013] According to a fourth aspect of the present invention, there is provided a light emitting device of the first aspect, wherein one of the first circuit element and the second circuit element is a temperature detecting element for detecting the temperature of the substrate, and the other is a light receiving element for receiving light emitted by the light emitting element array.

[0014] According to a fifth embodiment of the present invention, a light-emitting device of any one of the first to fourth embodiments is provided, wherein the wiring component extending from the upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array is not provided between the first side surface and the first circuit element, and between the second side surface and the second circuit element.

[0015] According to a sixth aspect of the present invention, there is provided the light emitting device of any one of the first to fifth aspects, wherein a light diffusing member for diffusing light emitted from the light emitting element array to the outside is provided on an emission path of the light emitting element array.

[0016] According to the seventh embodiment of the present invention, a light-emitting device of the sixth embodiment is provided, wherein at least one of the first circuit element and the second circuit element is a light-receiving element that receives light emitted by the light-emitting element array, and the light-diffusing component is arranged at a position overlapping with the light-emitting element array and the light-receiving element when viewed from above.

[0017] According to an eighth aspect of the present invention, a light-emitting device of the sixth aspect is provided, wherein one of the first circuit element and the second circuit element is a light-receiving element that receives light emitted by the light-emitting element array, and the other is a circuit element other than the light-receiving element, and when viewed from above, the light-diffusing component is arranged at a position that does not overlap with the circuit elements other than the light-receiving element but overlaps with the light-emitting element array and the light-receiving element.

[0018] According to a ninth aspect of the present invention, there is provided the light emitting device according to any one of the first to eighth aspects, wherein the light emitting element array includes a plurality of light emitting elements connected in parallel to each other.

[0019] According to a tenth aspect of the present invention, there is provided an optical device comprising: a light-emitting device as described in any one of the first to ninth aspects; and a light-receiving unit which receives reflected light emitted from a light-emitting element array of the light-emitting device and reflected by an object to be measured, wherein the light-receiving unit outputs a signal corresponding to the time from when light is emitted from the light-emitting element array to when light is received by the light-receiving unit.

[0020] According to the eleventh aspect of the present invention, there is provided an information processing device comprising: the optical device as described in the tenth aspect; and a shape determination unit for determining the three-dimensional shape of the object to be measured based on reflected light emitted from an array of light-emitting elements possessed by the optical device, reflected by the object to be measured, and received by a light-receiving unit possessed by the optical device.

[0021] According to a twelfth aspect of the present invention, there is provided the information processing device according to the eleventh aspect, comprising: an authentication processing unit that performs authentication processing related to the use of the device based on the identification result of the shape identification unit.

[0022] Effects of the Invention

[0023] According to the first aspect of the invention, the drive unit and the light emitting element array can be brought closer together, compared with a configuration in which a circuit element occupying a large area is provided on the side of the light emitting element array close to the drive unit.

[0024] According to the second aspect of the invention, light emitted from the light emitting element array is received.

[0025] According to the third aspect of the invention, the temperature of the light emitting element array is detected via the substrate.

[0026] According to the fourth aspect of the invention, light emitted from the light emitting element array is received, and the temperature of the light emitting element array is detected via the substrate.

[0027] According to the fifth aspect of the invention, compared with a case where wiring members are provided between the first side surface and the first circuit element and between the second side surface and the second circuit element, it is easier to arrange the circuit element and the light emitting element array close to each other.

[0028] According to the sixth aspect of the invention, compared with a configuration without a light diffusion member, the range irradiated by light emitted from the light emitting element array is wider.

[0029] According to the seventh aspect of the invention, compared with a case where the light diffusing member is not provided at a position overlapping the light emitting element array and the light receiving element, the light receiving element receives more light of the light emitted from the light emitting element array and reflected by the light diffusing member.

[0030] According to the eighth aspect of the invention, the size of the light diffuser can be smaller than when the light diffuser is provided at a position overlapping with the light emitting element array, the light receiving element, and the circuit elements other than the light receiving element.

[0031] According to the ninth aspect of the invention, the intensity of the light irradiated simultaneously is higher than that of a structure in which the light emitting elements are driven individually.

[0032] According to the tenth aspect of the invention, an optical device capable of three-dimensional measurement is provided.

[0033] According to the invention of an eleventh aspect, there is provided an information processing device capable of measuring a three-dimensional shape.

[0034] According to the invention of a twelfth aspect, there is provided an information processing device equipped with an authentication process based on a three-dimensional shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a diagram showing an example of an information processing device.

[0036] Figure 2 It is a block diagram illustrating the structure of an information processing device.

[0037] Figure 3 It is a top view of the light emitting element array.

[0038] Figure 4 It is a diagram for explaining the cross-sectional structure of one VCSEL in the light emitting element array.

[0039] Figure 5 is a diagram illustrating an example of a light diffusion component. Figure 5 The (a) included in is the top view, Figure 5 (b) included therein is a cross-sectional view taken along the VB-VB line of (a).

[0040] Figure 6This is a diagram showing an example of an equivalent circuit for driving a light emitting element array by low-side driving.

[0041] Figure 7 is a diagram illustrating a light emitting device to which this embodiment is applied, Figure 7 The (a) included in is the top view, Figure 7 (b) included in (a) is a cross-sectional view taken along line VIIB-VIIB. Figure 7 (c) included therein is a cross-sectional view taken along line VIIC-VIIC of (a).

[0042] Figure 8 is a diagram for explaining a wiring pattern provided on a wiring substrate and a base material, Figure 8 (a) included in the figure shows the surface of the wiring substrate, Figure 8 (b) included in the figure shows the surface of the substrate, Figure 8 (c) included therein shows the back side of the substrate.

[0043] Fig. 9 FIG. 1 is a plan view illustrating a light-emitting device for comparison to which this embodiment is not applied. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] Generally, an information processing device identifies whether a user who has accessed the information processing device is allowed to access, and only allows the user to use the device, i.e., the information processing device, if the user is authenticated as a user who is allowed to access. So far, methods of authenticating users by passwords, fingerprints, irises, etc. have been used. Recently, a method of authentication with higher security is being sought. This method performs authentication based on a three-dimensional image such as the user's facial shape.

[0046] Here, the information processing device is described by taking a portable information processing terminal as an example, and authenticates the user by recognizing a three-dimensional image of a captured facial shape. It should be noted that the information processing device can be applied to information processing devices other than portable information processing terminals, such as personal computers (PCs), etc.

[0047] Furthermore, the structure, function, method, etc. described in this embodiment can also be applied to the recognition of the three-dimensional shape of the measured object other than the face shape. In other words, it can also be applied to the recognition of the shape of objects other than the face. In addition, the distance to the measured object is not limited.

[0048] (Information Processing Device 1)

[0049] Figure 1is a diagram showing an example of the information processing device 1. As described above, the information processing device 1 is, for example, a portable information processing terminal.

[0050] The information processing device 1 includes a user interface unit (hereinafter referred to as a UI unit) 2 and an optical device 3 for acquiring a three-dimensional image. For example, the UI unit 2 is formed by integrating a display device for displaying information to a user and an input device for inputting instructions for information processing through user operations. The display device is, for example, a liquid crystal display or an organic EL display, and the input device is, for example, a touch panel.

[0051] The optical device 3 includes a light emitting device 4 and a three-dimensional sensor (hereinafter, marked as a 3D sensor) 5. The light emitting device 4 irradiates light toward the object to be measured for obtaining a three-dimensional image, that is, the face in the example described here. The 3D sensor 5 obtains the light that is irradiated by the light emitting device 4 and reflected by the face and returned. Here, it is assumed that a three-dimensional image of the face is obtained based on the so-called Time of Flight (ToF) method based on the flight time of light. In the following, even in the case of obtaining a three-dimensional image of the face, the face will be marked as the object to be measured. It should be noted that a three-dimensional image of an object to be measured other than the face can also be obtained. Sometimes obtaining a three-dimensional image is marked as 3D sensing. The 3D sensor 5 is an example of a light receiving unit.

[0052] It should be noted that the information processing device 1 is configured as a computer including a CPU, a ROM, a RAM, etc. It should be noted that the ROM includes a non-volatile rewritable memory, such as a flash memory. In addition, the application program and constants stored in the ROM are loaded into the RAM and executed by the CPU, thereby operating the information processing device 1 to perform various information processing.

[0053] Figure 2 It is a block diagram illustrating the structure of the information processing device 1.

[0054] The information processing device 1 includes the above-mentioned optical device 3, an optical device control unit 8, and a system control unit 9. The optical device control unit 8 controls the optical device 3. In addition, the optical device control unit 8 includes a shape determination unit 81. The system control unit 9 controls the information processing device 1 as a system. In addition, the system control unit 9 includes an authentication processing unit 91. In addition, the system control unit 9 is connected to the UI unit 2, the speaker 92, and the two-dimensional camera (in Figure 2 Marked as 2D camera) 93 and other connections.

[0055] The following will explain them one by one.

[0056] The light emitting device 4 included in the optical device 3 includes a wiring substrate 10, a substrate 100, a light emitting element array 20, a light diffusion member 30, and a light receiving element for monitoring light quantity (in Figure 2and hereinafter referred to as PD) 40, temperature detection element (in Figure 2 , and hereinafter referred to as TD) 45, a driving unit 50, a holding unit 60, and a capacitor 70. In addition, the light emitting device 4 includes passive elements such as a resistor element 6 and a capacitor 7 to operate the driving unit 50. It should be noted that although two capacitors 70 are shown in the figure, the number of capacitors can be one or more than two. In addition, the number of resistor elements 6 and capacitors 7 can be multiple. Here, sometimes the capacitor 70, the 3D sensor 5, the resistor element 6, the capacitor 7, etc. other than the light emitting element array, PD40 and the driving unit 50 are not distinguished and are uniformly marked as circuit components.

[0057] The light emitting element array 20 , the PD 40 , and the TD 45 are provided on a substrate 100 . The substrate 100 is made of an electrically insulating member. The substrate 100 , the driving unit 50 , the capacitor 70 , the resistor 6 , and the capacitor 7 are provided on a wiring board 10 .

[0058] The light emitting element array 20 is configured as an array in which a plurality of light emitting elements are arranged two-dimensionally (see the following description). Figure 3 ). For example, the light emitting element is a vertical cavity surface emitting laser element (Vertical Cavity Surface Emitting Laser (VCSEL)). Hereinafter, the light emitting element is a vertical cavity surface emitting laser element VCSEL for explanation. And, the vertical cavity surface emitting laser element VCSEL is marked as VCSEL. The light emitting element array 20 emits light in a direction perpendicular to the surface of the wiring substrate 10 or the substrate 100. In the case of three-dimensional sensing by the ToF method, the light emitting element array 20 is required to be driven by the driving unit 50 to emit, for example, a pulse light of more than 100 MHz and a rise time of less than 1 ns (hereinafter, marked as an emitted light pulse). In addition, in the case of facial authentication as an example, the distance of light irradiation is about 10 cm to about 1 m. And, the range for measuring the 3D shape is about 1 m square. Therefore, the light emitting element array 20 is required to have a large output and to efficiently dissipate the heat generated by the light emitting element array 20. It should be noted that the distance of light irradiation is marked as the measurement distance, and the range for measuring the 3D shape of the object to be measured is marked as the measurement range or the irradiation range. In addition, a surface virtually set within the measurement range or the irradiation range is marked as an irradiation surface.

[0059] PD40 is a pin-type photodiode, which outputs an electrical signal corresponding to the amount of light received (hereinafter referred to as the amount of light received), and is composed of a p-type Si region that serves as an anode, an i (intrinsic) type Si region, and an n-type Si region that serves as a cathode. In addition, an anode electrode is provided in the p-type Si region, and a cathode electrode is provided in the n-type Si region. It should be noted that PD40 is an example of a light-receiving element and an example of a first circuit element.

[0060] TD45 is a temperature sensor element that measures the temperature of the substrate 100. For example, TD45 is a surface-mounted negative temperature coefficient thermistor (NTC) or a positive temperature coefficient thermistor (PTC). The resistance value of a negative temperature coefficient thermistor decreases when the temperature rises, and the resistance value of a positive temperature coefficient thermistor rises sharply when the temperature exceeds a certain temperature. TD45 uses the above characteristics to detect the temperature of the substrate 100 to indirectly monitor the temperature of the light-emitting element array 20. Therefore, TD45 can be configured close to the light-emitting element array 20. Thermistors do not have polarity, but other temperature sensor elements have polarity. It should be noted that TD45 is a circuit element other than a light-receiving element and is an example of a second circuit element.

[0061] The light diffuser 30 is provided to cover the light emitting element array 20 and the PD40. That is, the light diffuser 30 is provided at a predetermined distance from the light emitting element array 20 and the PD40 on the substrate 100 by means of a retaining portion 60 provided on the substrate 100. It should be noted that the light diffuser 30 covering the light emitting element array 20 and the PD40 means that the light diffuser 30 is provided on the emission path of the light emitted by the light emitting element array 20, and is provided so that the light emitted by the light emitting element array 20 passes through the light diffuser 30. As described later, in the case of a top view, it refers to a state in which the light emitting element array 20 and the PD40 overlap with the light diffuser 30. Here, the top view refers to the state in which the light emitting element array 20 and the PD40 are overlapped with the light diffuser 30. Figure 3 , Figure 7 (a) and the like are observed on the xy plane. It should be noted that PD40 can be arranged at a position covered by the light diffusion component 30 and arranged close to the light emitting element array 20 to easily receive a portion of the light emitted by the light emitting element array 20 and reflected by the light diffusion component 30. Here, the light diffusion component 30 is set to cover TD45, but the light diffusion component 30 may not cover TD45. If the light diffusion component 30 does not cover TD45, an expensive light diffusion component 30 of a small area can be used.

[0062] The holding portion 60 has walls 61A, 61B, 62A, and 62B that are arranged to surround the light emitting element array 20, the PD 40, and the TD 45. Here, it is assumed that the outer shape of the substrate 100, the outer shape of the light diffusion component 30, and the outer shape of the holding portion 60 are the same. Therefore, the outer edges of the substrate 100, the light diffusion component 30, and the holding portion 60 overlap. It should be noted that the outer shape of the substrate 100 may also be larger than the outer shape of the light diffusion component 30 or the outer shape of the holding portion 60.

[0063] The wiring substrate 10 , the base material 100 , the light emitting element array 20 , the light diffusion member 30 , the driving unit 50 , and the holding unit 60 in the light emitting device 4 will be described in detail later.

[0064] The 3D sensor 5 has a plurality of light receiving units. For example, each light receiving unit is configured to receive a pulsed reflected light (hereinafter, referred to as a light receiving pulse) formed by the outgoing light pulse from the light emitting element array 20 being reflected by the object to be measured, and each light receiving unit accumulates a charge corresponding to the time until the light is received. The 3D sensor 5 is configured as a device having a CMOS structure, wherein each light receiving unit has two gates and a charge storage unit corresponding to the two gates. Furthermore, by alternately applying pulses to the two gates, the generated photoelectrons are transmitted to any one of the two charge storage units at a high speed. Charges corresponding to the phase difference between the outgoing light pulse and the light receiving pulse are accumulated in the two charge storage units. Furthermore, the 3D sensor 5 outputs a digital value corresponding to the phase difference between the outgoing light pulse and the light receiving pulse as a signal for each light receiving unit via an AD converter. That is, the 3D sensor 5 outputs a signal corresponding to the time from the light emitting element array 20 emitting light to the light receiving by the 3D sensor 5. It should be noted that the AD converter can be provided with the 3D sensor 5 or can be arranged outside the 3D sensor 5.

[0065] As described above, in the case of facial authentication, the light emitting element array 20 is required to irradiate light within an irradiation range of about 1m square at a distance of about 10cm to about 1m. In addition, the 3D sensor 5 receives light reflected by the object to be measured, thereby measuring the 3D shape of the object to be measured. Therefore, the light emitting element array 20 is required to have a large output. Therefore, it is required to efficiently dissipate the heat from the light emitting element array 20.

[0066] The shape specifying unit 81 of the optical device control unit 8 acquires the digital value obtained for each light receiving unit from the 3D sensor 5, calculates the distance to the object to be measured for each light receiving unit, and specifies the 3D shape of the object to be measured based on the calculated distance.

[0067] When the determination result determined by the shape determination unit 81, i.e., the 3D shape of the object to be measured, is a 3D shape pre-stored in a ROM or the like, the authentication processing unit 91 of the system control unit 9 performs authentication processing related to the use of the information processing device 1. It should be noted that, for example, the authentication processing related to the use of the information processing device 1 refers to processing to determine whether to allow the use of the present device, i.e., the information processing device 1. For example, when it is determined that the 3D shape of the face of the object to be measured is consistent with the face shape stored in a storage unit such as a ROM, the use of the information processing device 1 including various application programs provided by the information processing device 1 is permitted.

[0068] For example, the shape determination unit 81 and the authentication processing unit 91 are composed of an application program. In addition, the shape determination unit 81 and the authentication processing unit 91 may also be composed of an integrated circuit such as an ASIC or FPGA. Furthermore, the shape determination unit 81 and the authentication processing unit 91 may also be composed of software such as an application program and an integrated circuit such as an ASIC.

[0069] exist Figure 2 , the optical device 3, the optical device control unit 8, and the system control unit 9 are shown separately, but the system control unit 9 may include the optical device control unit 8. In addition, the optical device control unit 8 may be included in the optical device 3. Furthermore, the optical device 3, the optical device control unit 8, and the system control unit 9 may be integrally configured.

[0070] Next, before describing the light emitting device 4, the light emitting element array 20, the light diffusion member 30, and the circuit driving the light emitting element array 20 constituting the light emitting device 4 are described. The circuit driving the light emitting element array 20 includes a driving unit 50, a capacitor 70, a PD 40, and a TD 45.

[0071] (Structure of Light Emitting Element Array 20)

[0072] Figure 3 It is a top view of the light emitting element array 20. The light emitting element array 20 is composed of a plurality of VCSELs arranged in a two-dimensional array. The right direction of the paper is set as the x direction, and the upper direction of the paper is set as the y direction. The direction orthogonal to the x direction and the y direction counterclockwise is set as the z direction. It should be noted that the x, y, and z directions in the drawings are common. It should be noted that the surface refers to the surface on the +z direction side, and the back surface refers to the surface on the -z direction side. The same applies to other situations.

[0073] VCSEL is a light emitting element which is stacked on a semiconductor substrate 200 (see below). Figure 4) is provided with an active area as a light emitting area between the lower multilayer film reflector and the upper multilayer film reflector, and the laser beam is emitted in a direction perpendicular to the semiconductor substrate 200. Therefore, it is easy to perform two-dimensional arraying. For example, the number of VCSELs possessed by the light emitting element array 20 is 100 to 1000. It should be noted that a plurality of VCSELs are connected in parallel to each other and driven in parallel. It should be noted that the number of VCSELs mentioned above is an example, and the number of VCSELs can be set according to the measurement distance and the measurement range.

[0074] On the surface of the light emitting element array 20, an anode electrode 218 (see below) common to a plurality of VCSELs is provided. Figure 4 A cathode electrode 214 is provided on the back side of the light emitting element array 20 (see Figure 4 ). That is, a plurality of VCSELs are connected in parallel. By connecting and driving a plurality of VCSELs in parallel, the intensity of light emitted and irradiated on the object to be measured is high compared to the case where a VCSEL is driven individually.

[0075] Here, the shape of the light emitting element array 20 when viewed from above, that is, the planar shape, is a quadrilateral. Furthermore, the side surface on the +x direction side is marked as side surface 21A, the side surface on the -x direction side is marked as side surface 21B, the side surface on the +y direction side is marked as side surface 22A, and the side surface on the -y direction side is marked as side surface 22B. Side surface 21A is opposite to side surface 21B. Side surface 22A and side surface 22B are connected to side surface 21A and side surface 21B, respectively, and are opposite to each other. Here, side surface 21A is an example of a first side surface, side surface 21B is an example of a second side surface, side surface 22A is an example of a third side surface, and side surface 22B is an example of a fourth side surface.

[0076] (VCSEL structure)

[0077] Figure 4 1 is a diagram for explaining the cross-sectional structure of one VCSEL in the light emitting element array 20. The VCSEL has a λ resonator structure. The upward direction on the paper is defined as the z direction.

[0078] The VCSEL is formed by stacking the following structures in sequence on a semiconductor substrate 200 such as n-type GaAs: an n-type lower distributed Bragg reflector (DBR) 202 in which AlGaAs layers of different Al compositions are alternately overlapped, an active region 206 including a quantum well layer sandwiched by an upper spacer layer and a lower spacer layer, and a p-type upper distributed Bragg reflector 208 in which AlGaAs layers of different Al compositions are alternately overlapped. Hereinafter, the distributed Bragg reflector is labeled as DBR.

[0079] The n-type lower DBR 202 is a stacked body with Al0.9Ga0.1As layer and GaAs layer as a pair, each layer has a thickness of λ / 4nr (where λ is the oscillation wavelength and nr is the refractive index of the medium), and these layers are alternately stacked for 40 periods. The carrier concentration after doping with n-type impurities, i.e. silicon, is, for example, 3×1018cm-3.

[0080] The active region 206 is formed by stacking a lower spacer layer, a quantum well active layer and an upper spacer layer. For example, the lower spacer layer is an undoped Al0.6Ga0.4As layer, the quantum well active layer is an undoped InGaAs quantum well layer and an undoped GaAs barrier layer, and the upper spacer layer is an undoped Al0.6Ga0.4As layer.

[0081] The p-type upper DBR 208 is a stacked body with an Al0.9Ga0.1As layer and a GaAs layer as a pair, the thickness of each layer is λ / 4nr, and these layers are alternately stacked for 29 periods. The carrier concentration after doping with p-type impurities, i.e., carbon, is, for example, 3×1018cm-3. Preferably, a contact layer composed of p-type GaAs is formed on the uppermost layer of the upper DBR 208, and a current limiting layer 210 of p-type AlAs is formed on the lowermost layer of the upper DBR 208 or inside thereof.

[0082] A cylindrical mesa M is formed on the semiconductor substrate 200 by etching the semiconductor layers stacked from the upper DBR 208 to the lower DBR 202. As a result, the current limiting layer 210 is exposed to the side of the mesa M. Through the oxidation process, an oxidized region 210A oxidized from the side of the mesa M and a conductive region 210B surrounded by the oxidized region 210A are formed in the current limiting layer 210. It should be noted that in the oxidation process, the oxidation rate of the AlAs layer is faster than that of the AlGaAs layer, and the oxidized region 210A is oxidized from the side of the mesa M toward the inside at a substantially constant rate, so that the planar shape of the conductive region 210B becomes a shape reflecting the outer shape of the mesa M, that is, a circle, and the center of the circle is substantially consistent with the axial direction of the mesa M (single-point dashed line). In the present embodiment, the mesa M forms a columnar structure.

[0083] A ring-shaped p-side electrode 212 made of a metal such as Ti / Au is formed on the top layer of the mesa M. The p-side electrode 212 is in ohmic contact with a contact layer provided on the upper DBR 208. The inner side of the ring-shaped p-side electrode 212 becomes a light emission port 212A for emitting a laser beam to the outside. That is, in the VCSEL, light is emitted in a direction perpendicular to the semiconductor substrate 200, and the axial direction of the mesa M is the optical axis. Furthermore, a cathode electrode 214 is formed on the back side of the semiconductor substrate 200 as an n-side electrode. It should be noted that the surface of the upper DBR 208 located on the inner side of the p-side electrode 212 is the light emission surface. That is, the optical axis direction of the VCSEL is the light emission direction.

[0084] Furthermore, an insulating layer 216 is provided to cover the surface of the mesa M except for the portion of the p-side electrode 212 connected to the anode electrode (the anode electrode 218 described later) and the light emission port 212A. Furthermore, the anode electrode 218 is provided to be in ohmic contact with the p-side electrode 212 except for the light emission port 212A. It should be noted that the anode electrode 218 is provided to be shared by a plurality of VCSELs. That is, the p-side electrodes 212 of the plurality of VCSELs constituting the light emitting element array 20 are connected in parallel through the anode electrode 218. It should be noted that the anode electrode 218 is an example of an upper surface electrode of the light emitting element array.

[0085] It should be noted that VCSEL can oscillate in a single transverse mode or in multiple transverse modes. For example, the light output of one VCSEL is 4 mW to 8 mW. Therefore, for example, in the case where the light emitting element array 20 is composed of 500 VCSELs, the light output of the light emitting element array 20 is 2 W to 4 W. In such a high-output light emitting element array 20, the heat generated from the light emitting element array 20 is large.

[0086] (Structure of the light diffusion member 30)

[0087] Figure 5 It is a diagram for explaining an example of the light diffusion member 30 . Figure 5 (a) is a top view, Figure 5 (b) is Figure 5 (a) is a cross-sectional view of the VB-VB line. Figure 5 In (a), the right direction of the paper is set as the x direction, and the upward direction of the paper is set as the y direction. The direction perpendicular to the x direction and the y direction is set as the z direction. Figure 5 In (b), the right direction of the paper is the x direction, and the upper direction of the paper is the z direction.

[0088] like Figure 5 As shown in (b), the light diffusion component 30 has a resin layer 32, and the resin layer 32 has concavo-convex shapes for diffusing light formed on the back side of the glass substrate 31, which is parallel and flat on both sides. The light diffusion component 30 further expands the diffusion angle of the light incident from the VCSEL of the light emitting element array 20 and emits the light. That is, the concavo-convex shapes formed on the resin layer 32 of the light diffusion component 30 refract or scatter the light, so that the diffusion angle β of the emitted light is greater than the diffusion angle α of the incident light. That is, as Figure 5As shown, the diffusion angle β of the light emitted from the light diffuser 30 through the light diffuser 30 is greater than the diffusion angle α of the light emitted from the VCSEL (α<β). Therefore, when the light diffuser 30 is used, the area of ​​the irradiation surface of the light emitted from the light emitting element array 20 is expanded compared to the case where the light diffuser 30 is not used. In addition, the light density of the irradiation surface is reduced. It should be noted that light density refers to the radiant illuminance per unit area, and the diffusion angles α and β are the full width at half maximum (FWHM).

[0089] Furthermore, for example, the planar shape of the light diffuser 30 is a quadrilateral, and the width Wx in the x direction and the longitudinal width Wy in the y direction are 1 mm to 10 mm, and the thickness td in the z direction is 0.1 mm to 1 mm. Furthermore, if the light diffuser 30 is of the above size and shape, such a light diffuser is particularly suitable for facial authentication of a portable information processing terminal and measurement at a relatively close distance of about several meters. It should be noted that the planar shape of the light diffuser 30 may also be other shapes such as a polygon or a circle.

[0090] (Circuit for driving the light emitting element array 20)

[0091] When it is desired to drive the light emitting element array 20 at a higher speed, low-side driving can be performed. Low-side driving refers to a structure in which a driving element such as a MOS transistor is located on the downstream side of a current path relative to a driving object such as a VCSEL. Conversely, a structure in which a driving element is located on the upstream side is called high-side driving.

[0092] Figure 6 FIG. 2 is a diagram showing an example of an equivalent circuit for driving the light emitting element array 20 by low-side driving. Figure 6 , VCSELs of the light emitting element array 20, a driving unit 50, a capacitor 70, a power source 82, a PD 40, a light quantity detection resistor 41 for detecting a current flowing through the PD 40, a TD 45, and a temperature detection resistor 46 for detecting a current flowing through the TD 45 are shown. It should be noted that the capacitor 70 is connected in parallel with the power source 82.

[0093] The power supply 82 is provided at Figure 2 The optical device control unit 8 is shown. The power supply 82 generates a DC voltage with a + side as a power supply potential and a - side as a ground potential. The power supply potential is supplied to a power supply line 83, and the ground potential is supplied to a ground line 84.

[0094] As described above, the light emitting element array 20 is composed of a plurality of VCSELs connected in parallel. Figure 4 ) is connected to the power line 83.

[0095] The driving unit 50 includes an n-channel MOS transistor 51 and a signal generating circuit 52 for turning on or off the MOS transistor 51. The drain of the MOS transistor 51 is connected to the cathode electrode 214 (see Figure 4 ) is connected. The source of the MOS transistor 51 is connected to the ground line 84. In addition, the gate of the MOS transistor 51 is connected to the signal generating circuit 52. That is, the MOS transistor 51 of the VCSEL and driving unit 50 is connected in series between the power supply line 83 and the ground line 84. The signal generating circuit 52 generates an "H level" signal for turning on the MOS transistor 51 and an "L level" signal for turning off the MOS transistor 51 under the control of the optical device control unit 8.

[0096] One terminal of the capacitor 70 is connected to the power line 83, and the other terminal is connected to the ground line 84. That is, the capacitor 70 is connected in parallel with the power supply 82. When there are a plurality of capacitors 70, the plurality of capacitors 70 are connected in parallel. It should be noted that the capacitor 70 is, for example, an electrolytic capacitor, a ceramic capacitor, or the like.

[0097] The cathode electrode of the PD 40 is connected to the power line 83, and the anode electrode is connected to one terminal of the light amount detection resistor element 41. In addition, the other terminal of the light amount detection resistor element 41 is connected to the ground line 84. That is, the PD 40 and the light amount detection resistor element 41 are connected in series between the power line 83 and the ground line 84. In addition, the connection point between the PD 40 and the light amount detection resistor element 41, that is, the output terminal 42, is connected to the optical device control unit 8.

[0098] One terminal of the temperature detection resistor element 46 is connected to the power line 83, and the other terminal is connected to one electrode of TD45. In addition, the other electrode of TD45 is connected to the ground line 84. That is, the temperature detection resistor element 46 and TD45 are connected in series between the power line 83 and the ground line 84. In addition, the connection point between the temperature detection resistor element 46 and TD45, that is, the output terminal 47, is connected to the optical device control unit 8.

[0099] Next, a method of driving the light emitting element array 20 which is low-side driving will be described.

[0100] First, assume that the signal generated by the signal generating circuit 52 in the driving section 50 is at an "L level". In this case, the MOS transistor 51 is in an off state. That is, no current flows between the source and the drain of the MOS transistor 51. Therefore, no current flows through the VCSELs connected in series. The VCSELs do not emit light.

[0101] At this time, capacitor 70 is charged by power supply 82. That is, one terminal of capacitor 70 connected to power supply line 83 is at power supply potential, and the other terminal connected to ground line 84 is at ground potential. Capacitor 70 accumulates charge determined by capacitance, power supply voltage (=power supply potential - ground potential) and time.

[0102] Next, when the signal generated by the signal generating circuit 52 in the driving unit 50 becomes "H level", the MOS transistor 51 changes from the off state to the on state. Then, the charge accumulated in the capacitor 70 is discharged, and current flows through the MOS transistor 51 and the VCSEL connected in series, causing the VCSEL to emit light.

[0103] When the signal generated by the signal generating circuit 52 in the driving unit 50 becomes "L level", the MOS transistor 51 changes from the on state to the off state. As a result, the VCSEL stops emitting light. Then, the power supply 82 resumes accumulating charge in the capacitor 70.

[0104] As described above, whenever the signal output from the signal generating circuit 52 changes to the "L level" and the "H level", the MOS transistor 51 is repeatedly turned off and on, and the VCSEL repeatedly performs non-light emission and light emission in the light emission stop state. That is, light pulses are emitted from the VCSEL. The MOS transistor 51 being repeatedly turned on and off is sometimes referred to as a switch. Here, as shown in FIG. Figure 6 As shown in the equivalent circuit of , it is composed of a light emitting element array 20, a MOS transistor 51, a capacitor 70, etc., and the current path leading to the light emitting element array 20 is marked as a circuit or circuit for driving the light emitting element array 20.

[0105] It should be noted that the capacitor 70 may be omitted and charge (current) may be directly supplied from the power supply 82 to the VCSEL. However, by accumulating charge in the capacitor 70, the accumulated charge is discharged when the MOS transistor 51 changes from off to on, and current is rapidly supplied to the VCSEL, thereby shortening the rise time of the light emission of the VCSEL.

[0106] The PD40 is reversely connected between the power line 83 and the ground line 84 via the light amount detection resistor 41. Therefore, in the state where no light is irradiated, no current flows. As described above, when the PD40 receives a part of the light reflected by the light diffusion component 30 in the light emitted by the VCSEL, a current corresponding to the amount of light received flows through the PD40. Therefore, the current flowing through the PD40 is measured as the voltage of the output terminal 42 to detect the light intensity of the light emitting element array 20. Therefore, the optical device control unit 8 controls according to the amount of light received by the PD40 so that the light intensity of the light emitting element array 20 becomes a preset light intensity. For example, when the light intensity of the light emitting element array 20 is less than the preset light intensity, the optical device control unit 8 increases the amount of charge accumulated in the capacitor 70 by increasing the power supply potential of the power supply 82, and increases the current flowing through the VCSEL. On the other hand, when the light intensity of the light emitting element array 20 is greater than the preset light intensity, the power supply potential of the power supply 82 is reduced, the amount of charge accumulated in the capacitor 70 is reduced, and the current flowing through the VCSEL is reduced. Thus, the light intensity of the light emitting element array 20 is controlled.

[0107] In addition, when the amount of light received by the PD 40 is extremely low, it is possible that the light diffusion component 30 is detached or damaged, and the light emitted by the light emitting element array 20 is directly irradiated to the outside. In such a case, the light intensity of the light emitting element array 20 is suppressed by the optical device control unit 8. For example, the light emission from the light emitting element array 20 is stopped, that is, the light irradiation to the object to be measured is stopped.

[0108] As described above, the PD 40 is provided to detect the light intensity of the light emitting element array 20. Therefore, the farther the PD 40 is arranged from the light emitting element array 20, the smaller the amount of light received, and the lower the detection sensitivity of the light intensity of the light emitting element array 20. Therefore, the PD 40 can be arranged near the light emitting element array 20.

[0109] TD45 and the temperature detection resistor 46 are connected in series between the power line 83 and the ground line 84. Therefore, the power supply voltage (=power supply potential-ground potential) of the output terminal 47 becomes a voltage divided by the temperature detection resistor 46 and TD45. For example, in the case where TD45 is a negative characteristic (NTC) thermistor, as described above, as the temperature of the substrate 100 increases, the resistance value decreases. In this way, the voltage of the output terminal 47 decreases as the temperature of the substrate 100 increases. The optical device control unit 8 detects the temperature of the substrate 100, that is, the light emitting element array 20, based on the voltage of the output terminal 47. It should be noted that when the temperature of the light emitting element array 20 exceeds the preset allowable temperature, the operation of the light emitting element array 20 may become unstable or be destroyed. Therefore, when the optical device control unit 8 detects that the temperature of the light emitting element array 20 exceeds the allowable temperature based on the voltage of the output terminal 47, the optical device control unit 8 controls the drive unit 50 to limit the current flowing through the light emitting element array 20, or cuts off the current flowing through the light emitting element array 20. This prevents the light emitting element array 20 from overheating.

[0110] As described above, TD45 is provided to detect the temperature of the light emitting element array 20. Therefore, the farther TD45 is arranged from the light emitting element array 20, the smaller the change in the temperature of TD45 is, and the lower the detection sensitivity of the temperature of the light emitting element array 20 is. Therefore, TD45 can be arranged near the light emitting element array 20.

[0111] That is, the PD 40 and the TD 45 are examples of circuit elements that are preferably arranged close to the light emitting element array 20 .

[0112] (Light emitting device 4)

[0113] Next, the light emitting device 4 will be described in detail.

[0114] Figure 7 It is a diagram for explaining a light emitting device 4 to which this embodiment is applied. Figure 7 (a) is a top view, Figure 7 (b) is Figure 7 (a) is a cross-sectional view taken along line VIIB-VIIB, Figure 7 (c) is Figure 7 (a) is a cross-sectional view of the VIIC-VIIC line. Figure 7 In (a), the right direction of the paper is set as the x direction, the upward direction of the paper is set as the y direction, and the direction orthogonal to the x direction and the y direction is set as the z direction. Figure 7 In (b) and (c), the right direction of the paper is the x direction, and the upper direction of the paper is the z direction. This is also the case in similar drawings shown below.

[0115] like Figure 7 As shown in (b) and (c) of FIG. 1 , the light emitting device 4 includes a substrate 100 and a driving unit 50 on a wiring substrate 10. Furthermore, a light emitting element array 20, a PD 40, a TD 45, and a holding unit 60 are provided on the substrate 100. A light diffusion component 30 is provided on the holding unit 60. Figure 7 As shown in (a) and (c), the light emitting element array 20, PD 40 and TD 45 are covered by the light diffusion component 30. Therefore, PD 40 receives a portion of the light emitted by the light emitting element array 20 and reflected by the back surface of the light diffusion component 30. It should be noted that the holding portion 60 may also be provided on the wiring substrate 10.

[0116] And, if Figure 7 As shown in (a), in the light emitting device 4, the PD40, the light emitting element array 20, the TD45, and the driving unit 50 are arranged in a straight line in the x direction. Here, it is assumed that the area occupied by the PD40 on the substrate 100 is larger than the area occupied by the TD45 on the substrate 100. It should be noted that, hereinafter, the area occupied on the substrate 100 is marked as the occupied area. That is, in the light emitting device 4, the PD40 and the TD45 are arranged close to the light emitting element array 20, but the TD45 with a smaller occupied area is arranged on the side of the light emitting element array 20 close to the driving unit 50, and the PD40 with a larger occupied area is arranged on the side away from the driving unit 50.

[0117] By configuring this, Figure 7 The distance D1 from the end of the light emitting element array 20 close to the driving unit 50 to the driving unit 50 shown in (a) is set shorter than the distance D2 in the comparative example described later. It should be noted that, as described later, the cathode electrode 214 of the light emitting element array 20 and the drain of the MOS transistor 51 of the driving unit 50 (see Figure 6 ) is set to be straight in the x direction. Therefore, when the distance D1 from the end of the light emitting element array 20 close to the driving unit 50 to the driving unit 50 becomes shorter, the cathode wiring pattern 12 for the light emitting element array becomes shorter, and the inductance of the circuit driving the light emitting element array 20 becomes smaller.

[0118] The details are described below.

[0119] For example, the wiring substrate 10 is a 3-layer multilayer substrate. That is, the wiring substrate 10 includes a first conductive layer, a second conductive layer, and a third conductive layer from the side on which the substrate, the driving unit 50, etc. are mounted. Furthermore, an insulating layer is provided between the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer. For example, the third conductive layer is set as a power line 83, and the second conductive layer is set as a ground line 84. Furthermore, through the first conductive layer, anode wiring patterns 11-1 and 11-2 for the light emitting element array constituting a part of the current path to the light emitting element array 20, a cathode wiring pattern 12 for the light emitting element array, an anode wiring pattern 13 for PD constituting a part of the current path to PD40, a cathode wiring pattern 14 for PD, an anode wiring pattern 15 for TD constituting a part of the current path to TD45, and a cathode wiring pattern 16 for TD (refer to the following description) are formed. Figure 8 ). Furthermore, a wiring pattern connecting circuit components such as capacitor 70, resistor 6, capacitor 7, etc. is formed through the first conductive layer, but it is omitted in the figure. In this way, by constituting the wiring substrate 10 as a multi-layer substrate, constituting the power line 83 as the third conductive layer, and constituting the ground line 84 as the second conductive layer, it is easy to suppress the change of the power supply potential and the ground potential. It should be noted that the paths through which the current flows, such as the anode wiring patterns 11-1 and 11-2 for the light-emitting element array, the cathode wiring pattern 12 for the light-emitting element array, the anode wiring pattern 13 for PD, the cathode wiring pattern 14 for PD, the anode wiring pattern 15 for TD, and the cathode wiring pattern 16 for TD, are marked as wiring patterns. In addition, the wiring pattern composed of the first conductive layer is electrically connected to the second conductive layer or the third conductive layer via a through hole. The through hole is, for example, a conductive portion formed by embedding a conductive material in a hole provided to penetrate the wiring substrate 10 in the thickness direction.

[0120] The first conductive layer, the second conductive layer, and the third conductive layer are made of conductive materials such as metals such as copper (Cu) and silver (Ag) or conductive pastes containing these metals, etc. The insulating layer is made of epoxy resin, ceramics, etc., for example.

[0121] The substrate 100 is made of an electrically insulating material. It should be noted that, since the light emitting element array 20 is provided on the substrate 100, the substrate 100 can be made of a component that is electrically insulating and has a higher thermal conductivity than the wiring substrate 10, namely, a heat dissipation component. Electrically insulating heat dissipation components include ceramics such as silicon nitride and aluminum nitride. If the substrate 100 is a heat dissipation component, the heat generated by the light emitting element array 20 is easily conducted to the holding portion 60 and the light diffusion component 30 via the substrate 100 to dissipate the heat, thereby improving the heat dissipation efficiency.

[0122] On the surface of the substrate 100, there are provided anode wiring patterns 111-1F and 111-2F for the light emitting element array, which constitute a part of the current path leading to the light emitting element array 20, a cathode wiring pattern 112F for the light emitting element array, an anode wiring pattern 113F for PD, which constitutes a part of the current path leading to the PD 40, a cathode wiring pattern 114F for PD, an anode wiring pattern 115F for TD, which constitutes a part of the current path leading to the TD 45, and a cathode wiring pattern 116F for TD. It should be noted that on the back side of the substrate 100, there is provided an anode wiring pattern 111-1B for the light emitting element array, which constitutes a part of the current path leading to the light emitting element array 20 (see the following description). Figure 8 (c)) and 111-2B, cathode wiring pattern 112B for light emitting element array, anode wiring pattern 113B for PD constituting a part of the current path leading to PD40 (refer to the following Figure 8 (b)), a cathode wiring pattern 114B for PD, and an anode wiring pattern 115B for TD that constitutes a part of the current path to TD45 (see the following). Figure 8 (c)) and TD cathode wiring pattern 116B. Moreover, on the front and back sides of the substrate 100, wiring patterns with the same number are connected by through holes. For example, Figure 7 As shown in (b), the anode wiring pattern 111-2F for the light emitting element array disposed on the surface and the cathode wiring pattern 111-2B for the light emitting element array disposed on the back are connected through a through hole 111-2V. With regard to the through hole, "V" is added to the number of the wiring pattern to mark it. The through hole here is, for example, a conductive portion formed by embedding a conductive material in a hole disposed through the substrate 100, and electrically connecting the wiring pattern on the surface with the wiring pattern on the back. By connecting the wiring patterns using multiple through holes, the inductance of the circuit is reduced.

[0123] Furthermore, the cathode wiring pattern 112F for the light emitting element array of the substrate 100 and the cathode electrode 214 (see Figure 4 ) are connected by a conductive adhesive or the like. Furthermore, the anode wiring pattern 111-1F for the light emitting element array of the substrate 100 is connected to the anode electrode 218 (see Figure 4 ) is connected to the side surface 22A of the light emitting element array 20 by a bonding wire 23A, and the light emitting element array anode wiring pattern 111-2F of the substrate 100 is connected to the anode electrode 218 of the light emitting element array 20 (refer to Figure 4) is connected by a bonding wire 23B on the side 22B side of the light emitting element array 20. Here, the anode wiring pattern 111-1F for the light emitting element array is arranged on the side 22A side of the light emitting element array 20, and the anode wiring pattern 111-2F for the light emitting element array is arranged on the side 22B side of the light emitting element array 20. In addition, the anode wiring pattern for the light emitting element array is not arranged on the side 21A, 21B side of the light emitting element array 20. Therefore, no bonding wire connecting the anode electrode 218 and the anode wiring pattern for the light emitting element array is arranged on the side 21A, 21B side of the light emitting element array 20. Therefore, an example of a circuit element that is expected to be arranged close to the light emitting element array 20, namely, PD40 and TD45, are arranged close to the light emitting element array 20. Here, the bonding wire (here, the bonding wires 23A, 23B) is an example of a wiring member extending from the upper surface electrode of the light emitting element array 20 toward the outside of the light emitting element array 20.

[0124] It should be noted that the anode wiring pattern 111-1F for the light emitting element array provided on the surface of the substrate 100 is connected to the anode wiring pattern 11-1 for the light emitting element array provided on the wiring substrate 10 via the anode wiring pattern 111-1B for the light emitting element array provided on the back surface. Similarly, the anode wiring pattern 111-2F for the light emitting element array provided on the surface of the substrate 100 is connected to the anode wiring pattern 11-2 for the light emitting element array provided on the wiring substrate 10 via the anode wiring pattern 111-2B for the light emitting element array provided on the back surface. Furthermore, the anode wiring patterns 11-1 and 11-2 for the light emitting element array are connected to one terminal of the capacitor 70. It should be noted that one capacitor 70 may be provided for each of the anode wiring patterns 11-1 and 11-2 for the light emitting element array.

[0125] The cathode electrode of the PD 40 is bonded to the cathode wiring pattern 114F for PD of the substrate 100 by a conductive adhesive, and the anode electrode of the PD 40 is connected to the anode wiring pattern 113F for PD of the substrate 100 by a bonding wire 23C.

[0126] One terminal of TD45 (the terminal on the + side when having polarity) is connected to the TD anode wiring pattern 115F of the substrate 100 via a conductive adhesive or solder, and the other terminal (the terminal on the - side when having polarity) is connected to the TD cathode wiring pattern 116F of the substrate 100 via a conductive adhesive or solder.

[0127] Furthermore, the anode wiring patterns 11-1 and 11-2 for the light emitting element array and the cathode wiring pattern 12 for the light emitting element array provided on the wiring substrate 10 are connected to the anode wiring patterns 111-1B and 111-2B for the light emitting element array and the cathode wiring pattern 112B for the light emitting element array on the back side of the substrate 100, respectively. Similarly, the anode wiring pattern 13 for PD and the cathode wiring pattern 14 for PD provided on the wiring substrate 10 are connected to the anode wiring pattern 113B for PD and the cathode wiring pattern 114B for PD on the back side of the substrate 100, respectively. The anode wiring pattern 15 for TD provided on the wiring substrate 10 (see below) Figure 8 (a)), the TD cathode wiring pattern 16 is respectively connected to the TD anode wiring pattern 115B on the back side of the substrate 100 (see the following description). Figure 8 (c)), TD is connected with cathode wiring pattern 116B. It should be noted that the connection between the wiring pattern of wiring substrate 10 and the wiring pattern of base material 100 is performed by a conductive adhesive or the like.

[0128] And, if Figure 7 As shown in (b), in the cross-sectional view at the line VIIB-VIIB deviating from the center in the y direction to the -y direction side, the anode wiring pattern 11-2 for the light emitting element array of the wiring substrate 10 is connected to the anode wiring pattern 111-2B for the light emitting element array on the back side of the substrate 100. The anode wiring pattern 111-2B for the light emitting element array of the substrate 100 is connected to the anode wiring pattern 111-2F for the light emitting element array on the surface of the substrate 100 via the through hole 111-2V. Furthermore, the anode wiring pattern 111-2F for the light emitting element array of the substrate 100 is connected to the anode electrode 218 (refer to FIG. 21) of the light emitting element array 20 via the bonding wire 23B. Figure 4 )connect.

[0129] Similarly, the PD cathode wiring pattern 14 of the wiring substrate 10 is connected to the PD cathode wiring pattern 114B on the back surface of the substrate 100. The PD cathode wiring pattern 114B of the substrate 100 is connected to the PD cathode wiring pattern 114F on the surface of the substrate 100 via the through hole 114V. Furthermore, the PD cathode wiring pattern 114F of the substrate 100 is connected to the cathode of the PD 40.

[0130] Furthermore, the TD cathode wiring pattern 16 of the wiring substrate 10 is connected to the TD cathode wiring pattern 116B on the back side of the substrate 100. The PD cathode wiring pattern 116B of the substrate 100 is connected to the PD cathode wiring pattern 114F on the surface of the substrate 100 via the through hole 116V. Furthermore, the PD cathode wiring pattern 114F of the substrate 100 is connected to the cathode of the PD 40.

[0131] That is, in the cross section of line VIIB-VIIB, the anode wiring pattern 11-2 for the light emitting element array of the wiring substrate 10, the anode wiring pattern 111-2B for the light emitting element array on the back side of the substrate 100, and the anode wiring pattern 111-2F for the light emitting element array on the front side of the substrate 100 are arranged in a mutually opposed manner. Similarly, the cathode wiring pattern 14 for PD of the wiring substrate 10, the cathode wiring pattern 114B for PD on the back side of the substrate 100, and the cathode wiring pattern 114F for PD on the front side of the substrate 100 are arranged in a mutually opposed manner. Furthermore, the cathode wiring pattern 16 for TD of the wiring substrate 10, the cathode wiring pattern 116B for TD on the back side of the substrate 100, and the cathode wiring pattern 116F for TD on the front side of the substrate 100 are arranged in a mutually opposed manner. It should be noted that, although not shown in the figure, the anode wiring pattern 11-1 for the light emitting element array of the wiring substrate 10, the anode wiring pattern 111-1B for the light emitting element array on the back side of the substrate 100, and the anode wiring pattern 111-1F for the light emitting element array on the surface of the substrate 100 are arranged in a manner opposite to each other.

[0132] On the other hand, Figure 7 As shown in (c), in the cross-sectional view at the VIIC-VIIC line in the center of the y direction, the cathode wiring pattern 12 for the light emitting element array of the wiring substrate 10 is set to extend from the bottom of the light emitting element array 20 to the driving unit 50. In addition, the cathode wiring pattern 12 for the light emitting element array is connected to the cathode wiring pattern 112B for the light emitting element array on the back side of the substrate 100. In addition, the cathode wiring pattern 112B for the light emitting element array is connected to the cathode wiring pattern 112F for the light emitting element array on the surface of the substrate 100 via the through hole 112V. In addition, the cathode wiring pattern 112F for the light emitting element array is connected to the cathode electrode 214 of the light emitting element array 20.

[0133] In addition, the PD cathode wiring pattern 14 of the wiring substrate 10 is connected to the PD cathode wiring pattern 114B on the back side of the substrate 100. Furthermore, the PD cathode wiring pattern 114B is connected to the PD cathode wiring pattern 114F on the surface of the substrate 100 via the through hole 114V. Furthermore, the PD cathode wiring pattern 114F is connected to the cathode electrode of the PD 40. It should be noted that in the cross-sectional view at the line VIIC-VIIC, the PD cathode wiring pattern 14 on the wiring substrate 10 and the PD cathode wiring pattern 114B on the back side of the substrate 100 may not be provided.

[0134] However, in Figure 7In the VIIC-VIIC cross section shown in (c) , neither the TD anode wiring pattern 115F nor the TD cathode wiring pattern 116F on the base material 100 is connected to the light emitting element array cathode wiring pattern 12 provided on the wiring substrate 10 .

[0135] That is, in the cross section of line VIIC-VIIC, the cathode wiring pattern 112B for the light emitting element array on the back side of the substrate 100 and the cathode wiring pattern 112F for the light emitting element array on the front side of the substrate 100 are arranged in a manner opposite to each other, but the cathode wiring pattern 12 for the light emitting element array of the wiring substrate 10 is arranged to extend from the portion opposite to the cathode wiring pattern 112B for the light emitting element array to the driving unit 50. In addition, no wiring pattern opposite to the anode wiring pattern 115F for TD or the cathode wiring pattern 116F for TD is arranged on the back side of the substrate 100. That is, the anode wiring pattern 115F for TD or the cathode wiring pattern 116F for TD on the substrate 100 is three-dimensionally crossed with the cathode wiring pattern 12 for the light emitting element array arranged on the wiring substrate 10 without being electrically connected. That is, the substrate 100 is arranged across the cathode wiring pattern 12 for the light emitting element array. Thus, the cathode wiring pattern 12 for the light emitting element array of the wiring substrate 10 is arranged to extend from the light emitting element array 20 to the driving unit 50 on the back side of the substrate 100, and the arrangement area of ​​TD45 on the substrate 100 is an area overlapping with the cathode wiring pattern 12 for the light emitting element array when viewed from above. It should be noted that if the substrate 100 is not arranged across the cathode wiring pattern 12 for the light emitting element array, but is arranged on one side of the cathode wiring pattern 12 for the light emitting element array in the width direction, the light emitting device 4 will be enlarged.

[0136] As mentioned above, Figure 7 As shown in (a), in the light emitting device 4 to which the first embodiment is applied, the PD40 and the TD45 are arranged close to the light emitting element array 20, and the TD45 with a smaller area than the PD40 is arranged between the light emitting element array 20 and the driving unit 50, thereby reducing the distance D1 between the light emitting element array 20 and the driving unit 50, and setting the wiring pattern (here, the cathode wiring pattern 12 for the light emitting element array) connecting the light emitting element array 20 and the driving unit 50 to a straight line. As a result, the wiring pattern (here, the cathode wiring pattern 12 for the light emitting element array) connecting the light emitting element array 20 and the driving unit 50 becomes shorter, and the increase in circuit inductance is suppressed.

[0137] Next, the wiring patterns provided on the wiring substrate 10 and the base material 100 will be described in detail.

[0138] Figure 8 The diagrams illustrate wiring patterns provided on the wiring board 10 and the base material 100 . Figure 8(a) shows the surface of the wiring substrate 10. Figure 8 (b) shows the surface of the substrate 100. Figure 8 (c) shows the back side of the substrate 100. Figure 8 In (a), the wiring pattern of the first conductive layer of the wiring substrate 10 is shown, and the wiring pattern of the second conductive layer, i.e., the ground line 84, and the wiring pattern of the third conductive layer, i.e., the power line 83, are not shown. The second conductive layer and the third conductive layer are patternless films except for the portion where the through hole for connecting to the wiring pattern formed by the first conductive layer is provided.

[0139] exist Figure 8 The surface of the wiring substrate 10 shown in (a) is provided with anode wiring patterns 11-1, 11-2 for light emitting element array and cathode wiring pattern 12 for light emitting element array. The planar shape of cathode wiring pattern 12 for light emitting element array is a quadrilateral. Anode wiring patterns 11-1, 11-2 for light emitting element array are arranged adjacent to the ±y direction sides of cathode wiring pattern 12 for light emitting element array. Furthermore, anode wiring pattern 13 for PD, cathode wiring pattern 14 for PD, anode wiring pattern 15 for TD and cathode wiring pattern 16 for TD are arranged on the surface of the wiring substrate 10. Anode wiring pattern 13 for PD and cathode wiring pattern 14 for PD are arranged on the -x direction side of cathode wiring pattern 12 for light emitting element array, and anode wiring pattern 15 for TD and cathode wiring pattern 16 for TD are arranged so as to sandwich cathode wiring pattern 12 for light emitting element array from the ±y direction.

[0140] exist Figure 8 The surface of the substrate 100 shown in (b) is provided with anode wiring patterns 111-1F and 111-2F for the light emitting element array and cathode wiring pattern 112F for the light emitting element array. The cathode wiring pattern 112F for the light emitting element array is formed to be Figure 3 The plane shape of the light emitting element array 20 shown in FIG. 1 is a quadrilateral plane shape corresponding to the plane shape of the light emitting element array 20. In addition, the light emitting element array anode wiring patterns 111-1F and 111-2F are arranged adjacent to the ±y direction sides of the light emitting element array cathode wiring pattern 112F. Furthermore, the surface of the substrate 100 is provided with a PD anode wiring pattern 113F, a PD cathode wiring pattern 114F, a TD anode wiring pattern 115F, and a TD cathode wiring pattern 116F.

[0141] exist Figure 8The back side of the substrate 100 shown in (c) is provided with an anode wiring pattern 111-1B for a light emitting element array connected to an anode wiring pattern 111-1F for a light emitting element array via a through hole 111-1V, an anode wiring pattern 111-2B for a light emitting element array connected to an anode wiring pattern 111-2F for a light emitting element array via a through hole 111-2V, a cathode wiring pattern 112B for a light emitting element array connected to a cathode wiring pattern 112F for a light emitting element array via a through hole 112V, an anode wiring pattern 113B for PD connected to an anode wiring pattern 113F for PD via a through hole 113V, a cathode wiring pattern 114B for PD connected to a cathode wiring pattern 114F for PD via a through hole 114V, an anode wiring pattern 115B for TD connected to an anode wiring pattern 115F for TD via a through hole 115V, and a cathode wiring pattern 116B for TD connected to a cathode wiring pattern 116F for TD via a through hole 116V. It should be noted that, on the substrate 100, Figure 8 The wiring pattern on the surface shown in (b) is Figure 8 The wiring pattern on the back side shown in (c) is mirror-inverted except for the anode wiring pattern 115F for TD and the cathode wiring pattern 116F for TD, and the anode wiring pattern 115B for TD and the cathode wiring pattern 116B for TD. That is, in a top view, the wiring pattern on the surface of the substrate 100 and the wiring pattern on the back side of the substrate 100 are arranged in an overlapping manner. It should be noted that the cathode wiring pattern 12 for the light emitting element array is connected to the light emitting element array 20, and is a wiring pattern on the wiring substrate 10 extending from the back side of the substrate 100 toward the driving unit 50.

[0142] On the other hand, regarding the TD anode wiring pattern 115F and the TD cathode wiring pattern 116F, and the TD anode wiring pattern 115B and the TD cathode wiring pattern 116B, the TD anode wiring pattern 115F and the TD cathode wiring pattern 116B on the surface are longer in the y direction than the TD anode wiring pattern 115B and the TD cathode wiring pattern 116B on the back side, and extend to the vicinity of the center portion in the y direction of the substrate 100. Also, near the center portion in the y direction of the substrate 100, two terminals of the TD45 are connected to the TD anode wiring pattern 115F and the TD cathode wiring pattern 116F, respectively.

[0143] And, if in Figure 8If the substrate 100 is arranged at the position surrounded by the dotted line on the wiring substrate 10 shown in (a), the anode wiring patterns 11-1 and 11-2 for the light emitting element array of the wiring substrate 10 are connected to the anode wiring patterns 111-1B and 111-2B for the light emitting element array of the substrate 100, and the cathode wiring pattern 12 for the light emitting element array of the wiring substrate 10 is connected to the cathode wiring pattern 112B for the light emitting element array of the substrate 100. Similarly, the anode wiring pattern 13 for PD of the wiring substrate 10 is connected to the anode wiring pattern 113B for PD of the substrate 100, and the cathode wiring pattern 14 for PD of the wiring substrate 10 is connected to the cathode wiring pattern 114B for PD of the substrate 100. Furthermore, the anode wiring pattern 15 for TD of the wiring substrate 10 is connected to the anode wiring pattern 115B for TD of the substrate 100, and the cathode wiring pattern 16 for TD of the wiring substrate 10 is connected to the cathode wiring pattern 116B for TD of the substrate 100.

[0144] At this time, on the substrate 100, if the TD anode wiring pattern 115B and the TD cathode wiring pattern 116B on the back surface have the same shape as the TD anode wiring pattern 115F and the TD cathode wiring pattern 116F on the front surface, the TD anode wiring pattern 115B and the TD cathode wiring pattern 116B short-circuit the TD anode wiring pattern 115B and the TD cathode wiring pattern 116B for the light emitting element array of the wiring substrate 10. Therefore, on the substrate 100, the length of the TD anode wiring pattern 115B and the TD cathode wiring pattern 116B on the back surface extending toward the center side in the y direction is shortened compared to the TD anode wiring pattern 115F and the TD cathode wiring pattern 116F on the front surface, and the TD anode wiring pattern 115B and the TD cathode wiring pattern 116B for the light emitting element array of the wiring substrate 10 are not short-circuited. That is, in order to configure TD45 between the light emitting element array 20 and the driving unit 50 , a TD anode wiring pattern 115F and a TD cathode wiring pattern 116F are provided on the substrate 100 and are three-dimensionally crossed so as not to short-circuit with the light emitting element array cathode wiring pattern 12 provided on the wiring substrate 10 .

[0145] It should be noted that before the substrate 100 is arranged on the wiring substrate 10, the light emitting element array 20, the PD 40 and the TD 45 are mounted on the substrate 100. That is, the cathode electrode 214 (see FIG. 1 ) of the light emitting element array 20 is bonded to the cathode wiring pattern 112F for the light emitting element array of the substrate 100 by using a conductive adhesive or the like. Figure 4 ). In addition, the anode electrode 218 of the light emitting element array 20 (see Figure 4 ) is connected to the anode wiring patterns 111-1F and 111-2F of the light emitting element array by bonding wires 23A and 23B.

[0146] Furthermore, the cathode electrode of PD40 is bonded to the cathode wiring pattern 114F for PD of the substrate 100 by a conductive adhesive, and the anode electrode of PD40 is connected to the anode wiring pattern 113F for PD of the substrate 100 by a bonding wire 23C. Furthermore, one terminal of TD45 (a + side terminal in the case of polarity) is bonded to the anode wiring pattern 115F for TD of the substrate 100 by a conductive adhesive or solder, and the other terminal of TD45 (a - side terminal in the case of polarity) is bonded to the cathode wiring pattern 116F for TD of the substrate 100 by a conductive adhesive or solder.

[0147] As described above, in the light emitting device 4 of the present embodiment, among the PD 40 and the TD 45 which are expected to be arranged close to the light emitting element array 20, the TD 45 which occupies a smaller area is arranged between the light emitting element array 20 and the driving section 50, so that the driving section 50 and the light emitting element array 20 are easily accessible. In addition, by using the substrate 100, even in a structure in which the TD 45 is arranged between the light emitting element array 20 and the driving section 50, the wiring pattern (here, the cathode wiring pattern 12 for the light emitting element array) connecting the driving section 50 and the light emitting element array 20 is not affected by the TD 45 and is arranged in a straight line. Therefore, the increase in circuit inductance is suppressed.

[0148] In the light emitting device 4 of the present embodiment, among the PD 40 and the TD 45 which are expected to be arranged close to the light emitting element array 20, the TD 45 which occupies a smaller area on the substrate 100 is arranged between the light emitting element array 20 and the driving unit 50, so that the driving unit 50 and the light emitting element array 20 are easily accessible. Hereinafter, for comparison, a light emitting device 4' to which the present embodiment is not applied will be described.

[0149] (Light Emitting Device 4' of Comparative Example)

[0150] Fig. 9 It is a plan view illustrating a light emitting device 4 ′ for comparison to which this embodiment is not applied.

[0151] In the light emitting device 4', the PD 40 occupying a large area on the substrate 100 is disposed between the light emitting element array 20 and the driving unit 50. That is, the light emitting device 4' is Figure 7 The light emitting device 4 shown is a light emitting device in which the arrangement positions of the PD 40 and the TD 45 are changed. The other structures are the same as those of the light emitting device 4, and thus the description thereof is omitted.

[0152] In the light emitting device 4', since the PD 40 occupying a large area is disposed between the light emitting element array 20 and the driving unit 50, the distance D2 between the end of the light emitting element array 20 close to the driving unit 50 and the driving unit 50 is larger than the distance D1 in the light emitting device 4 (D2>D1). That is, since the PD 40 occupies a large area, it is difficult to bring the driving unit 50 close to the light emitting element array 20.

[0153] As described above, the area occupied by PD40 on the substrate 100 is larger than that of TD45, but when the area occupied by PD40 on the substrate 100 is smaller than that of TD45, PD40 can be disposed between the driving unit 50 and the light emitting element array 20. That is, when there are a plurality of circuit elements that are desired to be arranged close to the light emitting element array 20, it is sufficient to dispose the circuit element that occupies a smaller area on the substrate 100 between the driving unit 50 and the light emitting element array 20. Thus, it is easy to bring the driving unit 50 close to the light emitting element array 20. In addition, the increase in circuit inductance is suppressed.

[0154] It should be noted that in this embodiment, a light-amount monitoring light-receiving element (PD40) is described as an example of a first circuit element, and a temperature detection element (TD45) is described as an example of a second circuit element, but other circuit components such as a capacitor 70 that supplies current to the light-emitting element array 20 may also be used as circuit elements.

[0155] It should be noted that in this embodiment, the light diffusion member 30 is used, but a light-transmitting member may be used instead of the light diffusion member 30, for example, a transparent substrate such as a protective cover, a condenser lens, a microlens array or other optical member may be used.

[0156] While the present invention has been described in detail and with reference to specific embodiments, it will be apparent to one skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention.

[0157] This application is based on the Japanese patent application (patent application 2019-053387) filed on March 20, 2019, the contents of which are incorporated herein by reference.

[0158] Description of symbols

[0159] 1: information processing device; 2: user interface (UI) unit; 3: optical device; 4, 4': light emitting device; 5: 3D sensor; 6: resistor element; 7, 70: capacitor; 8: optical device control unit; 9: system control unit; 10: substrate; 11-1, 11-2, 111-1F, 111-2F, 111-1B, 111-2B: anode wiring pattern for light emitting element array; 12, 112F, 112B: cathode wiring pattern for light emitting element array; 13, 113F, 113B: anode wiring pattern for PD; 14, 114F, 114B: cathode wiring pattern for PD; 15, 115F, 115B: anode wiring pattern for TD; 16, 116F, 116B: cathode wiring pattern for TD; 20: light emitting element array; 21A, 21B, 22A, 22B: side surface; 23A, 23B, 23C: bonding wire; 30: light diffusion component; 40: PD (light receiving element for monitoring light quantity); 45: TD (element for temperature detection); 50: driving unit; 51: MOS transistor; 52: signal generating circuit; 60: holding unit; 61A, 61B, 62A, 62B: wall; 81: shape determining unit; 82: power supply; 83: power supply line; 84: ground line; 91: authentication processing unit; 100: substrate; 200: semiconductor substrate; 202: lower DBR; 206: active region; 208: upper DBR; 210: current limiting layer; 210A: oxidation region; 210B: conductive region; 214: cathode electrode; 218: anode electrode; M: table; VCSEL: vertical cavity surface emitting laser element.

Claims

1. A light emitting device, comprising: Wiring substrate; A substrate, which is disposed on the wiring substrate; a light emitting element array disposed on the substrate and having a first side surface and a second side surface facing each other, and a third side surface and a fourth side surface facing each other connecting the first side surface and the second side surface; a driving unit, which is disposed on the wiring substrate on the first side surface and is used to drive the light emitting element array; A first circuit element is disposed on the substrate on the first side surface; a second circuit element disposed on the substrate on the second side surface and occupying a larger area on the substrate than the first circuit element; and a wiring member disposed on the third side surface and the fourth side surface and extending from the upper surface electrode of the light emitting element array toward the outside of the light emitting element array, A light diffusion member for diffusing light emitted from the light emitting element array to the outside is provided on an emission path of the light emitting element array. At least one of the first circuit element and the second circuit element is a light receiving element that receives light emitted by the light emitting element array. The light diffusion member is provided at a position overlapping with the light emitting element array and the light receiving element in a plan view.

2. The light emitting device according to claim 1, wherein At least one of the first circuit element and the second circuit element is a temperature detection element that detects the temperature of the substrate.

3. The light emitting device according to claim 1, wherein One of the first circuit element and the second circuit element is a temperature detection element for detecting the temperature of the substrate, and the other is a light receiving element for receiving light emitted from the light emitting element array.

4. The light emitting device according to any one of claims 1 to 3, wherein: The wiring member extending from the upper surface electrode of the light emitting element array toward the outside of the light emitting element array is not provided between the first side surface and the first circuit element and between the second side surface and the second circuit element.

5. The light emitting device according to claim 1, wherein: One of the first circuit element and the second circuit element is a light receiving element that receives light emitted by the light emitting element array, and the other is a circuit element other than the light receiving element. When viewed from above, the light diffusion component is arranged at a position that does not overlap with circuit elements other than the light receiving element.

6. The light emitting device according to any one of claims 1 to 3, wherein: The light emitting element array includes a plurality of light emitting elements connected in parallel to each other.

7. An optical device comprising: The light emitting device according to any one of claims 1 to 6; and A light receiving unit receives reflected light emitted from the light emitting element array of the light emitting device and reflected by the object to be measured, wherein: The light receiving unit outputs a signal corresponding to a time from when the light emitting element array emits light to when the light receiving unit receives the light.

8. An information processing device comprising: The optical device of claim 7; and A shape determination unit determines a three-dimensional shape of the object to be measured based on reflected light emitted from the light emitting element array provided in the optical device, reflected by the object to be measured, and received by the light receiving unit provided in the optical device.

9. The information processing device according to claim 8, comprising: An authentication processing unit performs authentication processing related to the use of the device based on the determination result of the shape determination unit.

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