Line structure
By forming openings in the dielectric layer and depositing a metal layer, combined with a seed layer and multiple dielectric layers, the problem of minute defects in the metal layer structure in the prior art is solved, realizing a low-cost, high-yield circuit structure and enhancing interlayer adhesion and processability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ADVANCED SEMICON ENG INC
- Filing Date
- 2021-05-07
- Publication Date
- 2026-05-15
AI Technical Summary
Existing technologies for fabricating metal/dielectric layer structures suffer from minor defects such as scratches and abrasive residues. These defects are particularly costly and difficult to completely remove, especially in high-layer products, thus affecting product reliability.
A circuit structure and its formation method are adopted, which forms an opening in the dielectric layer and deposits a metal layer therein, controls the thickness of the metal layer by electroplating, and sets a seed layer and multiple dielectric layers between the dielectric layers, avoiding chemical mechanical polishing process, and forming a defect-free planar structure.
This achieves a low-cost, defect-free circuit structure, improves product yield, avoids micro-scratches and cracks caused by grinding, and enhances the adhesion and processability between layers.
Smart Images
Figure CN113437045B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to circuit structures. Background Technology
[0002] In existing layer stacking technology applications (such as via-to-via, line-to-via, and line-to-line), most are completed by first preparing a metal layer / metallization layer, a back cover dielectric layer / isolation layer, and then performing mechanical chemical polishing (CMP) or mechanical polishing. This process is generally called dual damascene. This method can obtain a planarized multilayer stacked structure. However, many tiny defects (such as scratches, polishing residue, etc.) are often found on the polished surface.
[0003] In addition, CMP or mechanical polishing currently accounts for about 20% to 30% of the total cost, especially in high-layer products (e.g., 2.5D integrated chips, 3D integrated chips, fan-out packages). Summary of the Invention
[0004] In view of the problems existing in related technologies, the purpose of this invention is to provide a circuit structure and a method for forming the same, so as to improve the yield of the circuit structure.
[0005] To achieve the above objectives, embodiments of the present invention provide a circuit structure, comprising: a first dielectric layer having a first opening; a first metal layer located in the first opening, wherein the sidewall of the first metal layer is separated from the first dielectric layer; and a second dielectric layer located on the first dielectric layer, wherein a portion of the second dielectric layer is located between the sidewall of the first metal layer and the inner wall of the first opening.
[0006] In some embodiments, the top surface of the portion of the second dielectric layer located between the sidewall of the first metal layer and the inner wall of the first opening has a notch.
[0007] In some embodiments, the top surface of the first metal layer is lower than the top surface of the second dielectric layer.
[0008] In some embodiments, in a top view, the second dielectric layer is configured to surround the first metal layer.
[0009] In some embodiments, it further includes: a pad structure located in the first dielectric layer, and a first opening located on the pad structure.
[0010] In some embodiments, the lateral dimension of the first opening is smaller than the lateral dimension of the pad structure.
[0011] In some embodiments, the second dielectric layer has a second opening on the first metal layer, the second metal layer is located in the second opening, and the sidewall of the second metal layer is spaced apart from the inner wall of the second opening.
[0012] In some embodiments, the system further includes a third dielectric layer located on the second dielectric layer, the third dielectric layer also being located between the sidewall of the second metal layer and the inner wall of the second opening.
[0013] In some embodiments, a first seed layer and a second seed layer are respectively disposed below the first metal layer and the second metal layer, and the first metal layer and the second metal layer are separated by the second seed layer.
[0014] In some embodiments, the first metal layer and the second metal layer have similar shapes in a top view.
[0015] In some embodiments, the first metal layer and the second metal layer partially overlap.
[0016] Embodiments of this application provide a method for forming a circuit structure, comprising: forming a first opening in a first dielectric layer; forming a first mask layer on the first dielectric layer and in the first opening; removing a portion of the first mask layer to form a first aperture located in the first opening, the first aperture not exposing the inner wall of the first opening; forming a first metal layer in the first aperture; removing the first mask layer; and forming a second dielectric layer between the inner wall of the first opening and the first metal layer and on the first dielectric layer.
[0017] In some embodiments, the top surface of the portion of the second dielectric layer located between the inner wall of the first opening and the first metal layer has a notch.
[0018] In some embodiments, the first metal layer is formed by electroplating.
[0019] In some embodiments, during the electroplating process, the thickness of the first metal layer is controlled such that the height of the first metal layer does not exceed the top surface of the first dielectric layer.
[0020] In some embodiments, after forming the first opening and after forming the first mask layer, a first seed layer is formed on the first dielectric layer and in the first opening.
[0021] In some embodiments, after removing the first mask layer, the first seed layer is patterned using the first metal layer as a mask.
[0022] In some embodiments, after the second dielectric layer is formed, the second dielectric layer has a second opening located on the first metal layer, and a second seed layer is formed on the second dielectric layer and in the second opening.
[0023] In some embodiments, the method further includes: forming a second mask layer on the second seed layer; partially removing the second mask layer to form a second opening in the second opening that exposes the second seed layer, wherein the inner wall of the second opening is not exposed.
[0024] In some embodiments, the method further includes: forming a second metal layer in the second opening; and removing the second mask layer.
[0025] The second seed layer is patterned using the second mask layer as a mask; a third dielectric layer is formed between the inner walls of the second metal layer and the second opening and between the second dielectric layers. Attached Figure Description
[0026] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.
[0027] Figures 1A to 1C The process for forming circuit structures in the prior art is shown.
[0028] Figures 2 to 21 The steps for forming a circuit structure according to an embodiment of this application are shown.
[0029] Figures 22 to 26 Different embodiments of the circuit structure of this application are shown. Detailed Implementation
[0030] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.
[0031] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.
[0032] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values is less than or equal to ±10% of the average of the values (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values can be considered "substantially" the same.
[0033] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.
[0034] Additionally, quantities, ratios, and other numerical values are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly specified as range limits, but also all individual numerical values or subranges covered within the range, as if each numerical value and subrange were explicitly specified.
[0035] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.
[0036] In the application of circuit layer stacking technology, see Figure 1A and Figure 1BTypically, a seed layer 17 and a metal layer 12 are deposited in the vias (exposed pads 15) of the lower dielectric layer 10 (e.g., polyamide (PA)) on chip 13, and then an upper dielectric layer 14 (e.g., polyimide (PI) or silicon dioxide) is applied. Since the metal layer 12 is typically higher than the lower dielectric layer 10, this creates a protruding surface on the upper dielectric layer 14 for stacking the next circuit layer, such as... Figure 1C As shown, a planarization process 11 is used to remove protruding surfaces. Planarization is usually accomplished by chemical mechanical polishing (CMP). However, the CMP process uses abrasive materials (such as abrasive wheels or gauze) and dielectric materials (such as abrasive slurry), which can leave micro-scratches 16 or cracks 18 between the metal layer 12 and the upper dielectric layer 14 after polishing. Therefore, abrasive material can easily remain inside the stacked components, so other materials must be used to remove the residue in subsequent processes. If the residue cannot be completely removed and remains on the product, it will directly affect the reliability of the product.
[0037] The circuit structure and its formation method of this application will be specifically described below with reference to the accompanying drawings.
[0038] See Figure 2 A first dielectric layer 202 is formed on the semiconductor device 200. In this embodiment, the first dielectric layer 202 is an isolation layer, and the semiconductor device 200 is a chip, wafer, or core layer (PNL). A first opening 26 is formed in the first dielectric layer 202 to expose the first pad 204 of the semiconductor device 200.
[0039] See Figure 3 A first seed layer 30 is formed in the first opening 26 and on the first dielectric layer 202. In this embodiment, the first seed layer 30 is formed using a physical deposition (PVD) process.
[0040] See Figure 4 A first mask layer 40 is formed on the first seed layer 30. In an embodiment, the first mask layer 40 may include a photoresist (PR) material, and a first exposure process 41 is performed to cure the first mask layer 40.
[0041] See Figure 5 The first mask layer 40 is patterned to expose the first seed layer 30. A first metal layer 50 is then formed on the exposed first seed layer 30.
[0042] See Figure 6 , Figure 6 The upper half of the image is a top view, and the lower half is a cross-sectional view. The patterned first mask layer 40 is removed, and the first metal layer 50 is used as a mask to remove part of the first seed layer 30 through the first etching process 61. In this embodiment, the first etching process 61 is chemical etching.
[0043] See Figure 7 A second dielectric layer 70 is formed on the first metal layer 50 and the first dielectric layer 202. The second dielectric layer 70 fills the remaining space of the first opening 26, that is, it is formed between the first metal layer 50, the first seed layer 30 and the sidewall of the first opening 26. The top surface of the portion of the second dielectric layer 70 located between the inner wall of the first opening 70 and the first metal layer 50 has a notch 72.
[0044] See Figure 8 An intermediate mask layer 80 is formed on the second dielectric layer 70, and the intermediate mask layer 80 is also formed in the notch 72. In an embodiment, the intermediate mask layer 80 may include a photoresist (PR) material, and a second exposure process 81 is performed to cure the intermediate mask layer 80.
[0045] See Figure 9 The intermediate mask layer 80 is patterned to form a fourth opening 92 that exposes the notch 72, and a third opening 90 that exposes a portion of the second dielectric layer 70 is also formed next to the fourth opening 92. A second etching process is then performed to remove the portion of the second dielectric layer 70 exposed by the fourth opening 92 and the third opening 90. In an embodiment, the second etching process 91 is, for example, a dry etching process using an etching gas.
[0046] See Figure 10 After the second etching process 91, the second dielectric layer 70 remains between the sidewall of the first opening 26 and the first seed layer 30 and the first metal layer 50, and the second dielectric layer 70 forms a second opening 104 in the first opening 26. A second notch 102 formed by the notch 72 remains on the top surface of the portion of the second dielectric layer 70 located between the sidewall of the first opening 26 and the first seed layer 30 and the first metal layer 50. A second seed layer 100 is formed on the second dielectric layer 70, and the second seed layer 100 is formed in the second notch 102.
[0047] See Figure 11 A second mask layer 110 is formed on the second seed layer 100. In an embodiment, the second mask layer 110 may include a photoresist (PR) material, and a third exposure process 111 is performed to cure the second mask layer 110.
[0048] See Figure 12 The second mask layer 110 is patterned to expose the second seed layer 100 located in the second opening 104 and the third opening 90, and a second metal layer 120 is formed on the exposed second seed layer 100.
[0049] See Figure 13 , Figure 13The upper half of the image is a top view, and the lower half is a cross-sectional view. The patterned second mask layer 110 is removed, and the second seed layer 100 is partially removed by a third etching process 131 using the second metal layer 120 as a mask. In this embodiment, the third etching process 131 is chemical etching.
[0050] See Figure 14 A third dielectric layer 140 is formed on the second metal layer 120, and the third dielectric layer 140 is formed between the sidewall of the second metal layer 120 and the inner wall of the second opening 104. The third dielectric layer 140 is also formed in the second notch 102.
[0051] See Figure 15 The above steps are repeated to form a fifth opening 150 in the third dielectric layer 140, a third seed layer 152 located in the fifth opening 150, a third metal layer 154, and a fourth dielectric layer 156 located between the third seed layer 152 and the third metal layer 154 and the inner wall of the fifth opening 150. The fourth dielectric layer 156 is also formed on the third dielectric layer 140. A third mask layer 158 is formed on the fourth dielectric layer 156. In an embodiment, the third mask layer 158 may include a photoresist (PR) material, and a fourth exposure process 151 is performed to cure the third mask layer 158.
[0052] See Figure 16 The third mask layer 158 is patterned to form a sixth opening 160 that exposes a portion of the fourth dielectric layer 156 located above the previously formed metal layer. A fourth etching process 161 is then performed to remove the portion of the fourth dielectric layer 156 exposed by the sixth opening 160. In an embodiment, the fourth etching process 161 is, for example, a dry etching process using an etching gas.
[0053] See Figure 17 Remove the remaining third mask layer 158 and form a fourth seed layer 170 in the sixth opening 160 and on the fourth dielectric layer 156.
[0054] See Figure 18 A fourth mask layer 180 is formed on the fourth dielectric layer 156. In an embodiment, the fourth mask layer 180 may include a photoresist (PR) material, and a fifth exposure process 181 is performed to cure the fourth mask layer 180.
[0055] See Figure 19 The fourth mask layer 180 is patterned to form a seventh opening 190, which is located above the previously formed metal layers and exposes a portion of the fourth seed layer 170. A fourth metal layer 192 is formed on the exposed fourth seed layer 170.
[0056] See Figure 20 , Figure 20 The upper half of the image is a top view, and the lower half is a cross-sectional view. The patterned fourth mask layer 180 is removed, and the fourth seed layer 170 is partially removed by the fifth etching process 201 using the fourth metal layer 192 as a mask. In this embodiment, the fifth etching process 201 is chemical etching.
[0057] See Figure 21 A fifth dielectric layer 210 is formed on the fourth metal layer 192 and the fourth dielectric layer 156, and the fifth dielectric layer 210 is also formed in the remaining space of the seventh opening 190. A chip 212 is formed on the fifth dielectric layer 210 and electrically connected to the underlying fourth metal layer 192. Thus, the circuit structure 2100 of this application is completed. The circuit structure 2100 of this application is not limited to the formation of... Figure 21 The circuit structure 2100 of this application can be terminated at... Figure 21 The circuit structure shown in the previous steps.
[0058] The circuit structure of this application has a special material structure, such as nanotwins, nanocrystals and general crystalline materials, and each metal layer can be, for example, copper, silver, gold, nickel, aluminum, etc.
[0059] The circuit structure of this application has low manufacturing cost and no defects (such as micro-scratches, byproducts and / or micro-cracks) are generated around the conductors because CMP or mechanical polishing processes are not necessary.
[0060] The circuit structure of this application sets a seed layer as a barrier layer (e.g., Ti, Ni, W alloy) between metal layers (e.g., vias, wire-to-vias, wire-to-wires) to avoid thermal and / or electrical diffusion problems.
[0061] In some embodiments, the second dielectric layer 70 and the third dielectric layer 140 are made of different materials and are disposed in pairs. In one embodiment, the second dielectric layer 70 is an active material and the third dielectric layer 140 is a passive material. In other embodiments, the second dielectric layer 70 is a passive material and the third dielectric layer 140 is an active material.
[0062] In some embodiments, the fourth dielectric layer 156 and the fifth dielectric layer 210 are made of different materials and are disposed in pairs. In one embodiment, the fourth dielectric layer 156 is an active material and the fifth dielectric layer 210 is a passive material. In other embodiments, the fourth dielectric layer 156 is a passive material and the fifth dielectric layer 210 is an active material.
[0063] The paired organic and inorganic dielectric layers provide optimal stress balance, effectively solving the warpage problem. This application also enhances the processability and filling capability of each dielectric layer. For the paired organic and inorganic dielectric layers, to minimize warpage, the stress between the two layers satisfies the following equation: σ1=σ2 (σ1=E1·t1·CTE1·ΔT, σ2=E2·t2·CTE2·ΔT), where σ1 represents the stress of the first layer, σ2 represents the stress of the second layer, E1 represents the elastic modulus of the first layer material, CTE1 represents the coefficient of thermal expansion of the first layer, CTE2 represents the coefficient of thermal expansion of the second layer, and ΔT represents the temperature difference between the two layers. Therefore, the thickness between the two layers satisfies the following relationship: t2 / t1=E2·CTE2 / E1·CTE1. In some embodiments, the inorganic material may be silicon, glass, ceramic, oxide (e.g., SiOx, TaOx), nitride (e.g., SiNx), and the organic material may be polyimide (PI), epoxy resin, polybenzoxazole (PBO), flame retardant grade 4 material (FR4), prepreg resin (PP), Ajinomoto build-up film (ABF), or bismaleimide triazine resin (BT).
[0064] In some embodiments, the metal layer of this application is made of copper, gold, aluminum, silver, platinum, or palladium; the seed layer of this application is made of Ni, Ti, W, or their alloys; and the metal material of the pads of the chip of this application is copper, gold, aluminum, silver, platinum, or palladium.
[0065] Figure 22 Different embodiments of the circuit structure of this application are shown, wherein an isolation layer 220 is formed between the chip 200 and the first dielectric layer, and an embedded wire 222 is formed between the chip 200 and the isolation layer 222.
[0066] Figure 23A and Figure 23B The diagram illustrates the shape of any two adjacent metal layers in this application in a top view. For example, in an embodiment, such as... Figure 23A As shown, the first metal layer 50 is formed as a through-hole, and the second metal layer 120 is formed as a wire. In an embodiment, as... Figure 23B As shown, the first metal layer 50 is formed as a conductor, and the second metal layer 120 is formed as a conductor.
[0067] Figure 24 Different embodiments of the circuit structure of this application are shown, wherein the upper half of the figure is a top view taken along line AA' of the lower half of the figure, wherein the first metal layer 50 of this application is formed as two through holes.
[0068] Figure 25Different embodiments of the circuit structure of this application are shown, wherein the upper half of the figure is a top view taken along line AA' of the lower half of the figure, wherein the first metal layer 50 of this application forms a through hole and two conductors.
[0069] In some embodiments, the chip 200 of this application may also be replaced with an organic substrate. In some embodiments, such as Figure 26 As shown, chip 200 can also be replaced by connector 260 that contacts pad 204.
[0070] The fabrication of the circuit structure in this application avoids the defects caused by grinding, thus the interfaces between each layer are all finely machined surfaces, providing a good hybrid bonding interface. Each metal layer in this application can be formed by physical vapor deposition (PVD). PVD-formed metal layers are suitable for the flat and low-roughness sidewall surfaces formed by photolithography on physical vapor deposition (PR). Because PVD-formed metal layers have strong adhesion, there is good adhesion between the metal layer and the dielectric layer formed on it. This application avoids protruding structures in the metal layers during plating, thus preventing protruding surfaces when covering the second dielectric layer, thereby avoiding planarization processes.
[0071] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A circuit structure, characterized in that, include: The first dielectric layer has a first opening; A first metal layer is located in the first opening, and the sidewalls of the first metal layer are separated from the first dielectric layer; A second dielectric layer is located on the first dielectric layer, and a portion of the second dielectric layer is located between the sidewall of the first metal layer and the inner wall of the first opening, wherein the top surface of the portion of the second dielectric layer located between the sidewall of the first metal layer and the inner wall of the first opening has a notch, and the second dielectric layer has a second opening on the first metal layer. A second metal layer is located in the second opening, and the sidewall of the second metal layer is separated from the inner wall of the second opening; A third dielectric layer is located on the second dielectric layer, and the third dielectric layer is also located between the sidewall of the second metal layer and the inner wall of the second opening; A first seed layer and a second seed layer are respectively disposed below the first metal layer and the second metal layer, and the first metal layer and the second metal layer are separated by the second seed layer.
2. The circuit structure according to claim 1, characterized in that, The top surface of the first metal layer is lower than the top surface of the second dielectric layer.
3. The circuit structure according to claim 1, characterized in that, In the top view, the second dielectric layer is configured to surround the first metal layer.
4. The circuit structure according to claim 1, characterized in that, Also includes: A pad structure is located in the first dielectric layer, and the first opening is located on the pad structure.
5. The circuit structure according to claim 4, characterized in that, The lateral dimension of the first opening is smaller than the lateral dimension of the pad structure.
6. The circuit structure according to claim 1, characterized in that, In the top view, the first metal layer and the second metal layer have similar shapes.