Display device and method for manufacturing the same

Abstract

The present invention discloses a display device and a method for manufacturing the display device. The method includes the following steps: providing a display panel divided into a hole area, a pattern area surrounding the hole area, and an active area surrounding at least a portion of the pattern area; providing a packaging substrate on the display panel; forming a conductive pattern on the packaging substrate that overlaps with the hole area; forming a first insulating layer on the conductive pattern; forming a conductive layer on the first insulating layer; and removing a portion of the conductive layer that overlaps with the hole area, a portion of the first insulating layer that overlaps with the hole area, and the conductive pattern to form a module hole.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a display device including an electronic module and a method for manufacturing the display device. Background Art

[0002] Multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, game consoles, etc. include display devices for providing images to users.

[0003] Recently, with the development of display device technology, various display devices are being developed. In addition, for the convenience of users and the aesthetics of products, display devices with larger display areas (or active areas) and smaller non-display areas (or frame areas) are being developed.

[0004] In addition, the display device may include an electronic module that receives external signals or provides output signals to the outside. The electronic module and the display panel are housed in an external housing, etc. to form the display device. Summary of the Invention

[0005] An object of the present invention is to provide a display device with a reduced frame area.

[0006] Another object of the present invention is to provide a display device that can minimize manufacturing defects in a region where an electronic module is arranged.

[0007] According to a feature of the present invention for achieving this purpose, a method for manufacturing a display device includes the following steps: providing a display panel divided into a hole area, a pattern area surrounding the hole area, and an active area surrounding at least a portion of the pattern area on a plane; providing a packaging substrate on the display panel; forming a conductive pattern on the packaging substrate that overlaps with the hole area; forming a first insulating layer on the conductive pattern; forming a conductive layer on the first insulating layer; and removing a portion of the conductive layer that overlaps with the hole area, a portion of the first insulating layer that overlaps with the hole area, and the conductive pattern to form a module hole.

[0008] In an exemplary embodiment, the manufacturing method may further include the following step: forming a second insulating layer on the conductive layer, the second insulating layer overlapping the hole region, the pattern region, and the active region respectively.

[0009] In an exemplary embodiment, the step of forming the module hole may include the following steps: forming a photoresist pattern overlapping the active area and the pattern area on the second insulating layer; etching the first insulating layer and the second insulating layer; etching the conductive pattern; and removing the photoresist pattern.

[0010] In an exemplary embodiment, the step of etching the first insulating layer and the second insulating layer may include providing a first etching gas, and the step of etching the conductive pattern may include providing a second etching gas.

[0011] According to another feature of the present invention, a method for manufacturing a display device includes the following steps: providing a display panel divided into a hole area, a pattern area surrounding the hole area, and an active area surrounding at least a portion of the pattern area on a plane; providing a packaging substrate on the display panel; forming first to third conductive patterns on the packaging substrate that overlap with the active area, the pattern area, and the hole area, respectively; forming a first insulating layer on the first to third conductive patterns; forming a contact hole that exposes a portion of the first conductive pattern; forming an electrode connected to the first conductive pattern through the contact hole; and removing the portion of the first insulating layer that overlaps with the hole area and the third conductive pattern to form a module hole.

[0012] In an exemplary embodiment, the first to third conductive patterns may be spaced apart from each other on a plane.

[0013] In an exemplary embodiment, the step of forming the electrode may include the following steps: forming a conductive layer filling the contact hole; forming a photoresist pattern on the conductive layer; etching the conductive layer to form the electrode; and removing the photoresist pattern.

[0014] In an exemplary embodiment, the manufacturing method may further include the following step: forming a second insulating layer on the electrode, the second insulating layer overlapping the hole region, the pattern region, and the active region respectively.

[0015] In an exemplary embodiment, the step of forming the module hole may include the following steps: forming a photoresist pattern overlapping with the active area and the pattern area on the second insulating layer; etching the first insulating layer and the second insulating layer; etching the third conductive pattern; and removing the photoresist pattern.

[0016] In an exemplary embodiment, etching the first insulating layer and the second insulating layer may include providing a first etching gas, and etching the third conductive pattern may include providing a second etching gas.

[0017] In an exemplary embodiment, the step of forming the module hole may include the following steps: forming a photoresist pattern overlapping the active area and the pattern area on the electrode and the first insulating layer; etching the first insulating layer; etching the third conductive pattern; and removing the photoresist pattern.

[0018] In an exemplary embodiment, the manufacturing method may further include, after the step of removing the photoresist pattern, the step of forming a second insulating layer in the hole region, the pattern region, and the active region.

[0019] In an exemplary embodiment, the packaging substrate may include a glass substrate.

[0020] A display device according to an exemplary embodiment of the present invention includes: an electronic module; and an electronic panel, which is divided in a planar manner into an aperture region overlapping the electronic module, a pattern region surrounding the aperture region, and an active region surrounding at least a portion of the pattern region. The electronic panel may include: a display panel for displaying an image; a packaging substrate covering the display panel; and an input sensing layer disposed on the packaging substrate, wherein the input sensing layer may include a module hole exposing the aperture region of the packaging substrate.

[0021] In an exemplary embodiment, a region of the package substrate overlapping the hole region may have uniform flatness.

[0022] In an exemplary embodiment, the packaging substrate may include a glass substrate.

[0023] In an exemplary embodiment, the input sensing layer may include a first conductive pattern overlapping the active area and a second conductive pattern overlapping the pattern area on the package substrate.

[0024] In an exemplary embodiment, the display device may further include: a first insulating layer on the first conductive pattern and the second conductive pattern, overlapping the active area and the pattern area; and a conductive layer on the first insulating layer.

[0025] In an exemplary embodiment, the conductive layer may be electrically connected to the first conductive pattern through a contact hole penetrating the first insulating layer.

[0026] In an exemplary embodiment, a second insulating layer may be further included on the conductive layer and overlapped with the active area, the pattern area, and the hole area.

[0027] A display device with such a structure can arrange electronic modules within the active area of the display panel. This minimizes the display device's border area and maximizes the active area. In particular, the display device manufacturing method of the present invention can minimize manufacturing defects in the area where the electronic modules are arranged. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0029] Figure 2 is a perspective view of a display device according to another embodiment of the present invention.

[0030] Figure 3 FIG. 1 is a cross-sectional view of an electronic panel included in a display device according to an embodiment of the present invention.

[0031] Figure 4 FIG. 4 is a plan view of a display panel according to an embodiment of the present invention.

[0032] Figure 5 FIG. 4 is a plan view of an input sensing layer according to an embodiment of the present invention.

[0033] Figure 6 is a plan view exemplarily showing a module area of an electronic panel.

[0034] Figure 7 It is along Figure 2 Cross-sectional view of I-I'.

[0035] Figures 8a to 8i is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0036] Figure 9a as well as Figure 9b It is magnified Figure 8i A cross-sectional view taken of the first area shown.

[0037] Figures 10a to 10j is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0038] Figures 11a to 11c is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0039] Figure 12 It is magnified Figure 11c A cross-sectional view taken of the second area.

[0040] Explanation of symbols:

[0041] DD: Display Device

[0042] EP: Electronic Panel

[0043] EM: Electronic Module

[0044] MA: Module Area

[0045] 10, 20, 30, 40, 50: insulation layer

[0046] BL: Base layer

[0047] ECG: Package substrate

[0048] HA: Hole Area

[0049] PA: Pattern Area

[0050] AA: Active Area DETAILED DESCRIPTION

[0051] In this specification, when a certain component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" another component, or "combined with" another component, it means that it can be directly arranged / connected / combined on the other component, or a third component can be arranged between them.

[0052] The same reference numerals refer to the same components. Furthermore, in order to effectively illustrate the technical content, the thicknesses, ratios, and sizes of the components are exaggerated in the drawings. "And / or" indicates that all combinations of more than one possible combination of the related components are included.

[0053] Terms such as first and second can be used to describe a variety of components, but the components should not be limited by the terms. The terms are only used to distinguish one component from another. For example, without departing from the scope of the present invention, the first component can be named as the second component, and similarly, the second component can be named as the first component. Singular expressions include plural expressions as long as the context does not clearly indicate different meanings.

[0054] Furthermore, terms such as “below,” “lower side,” “above,” and “upper side” are used to describe the relationship between the components shown in the drawings. These terms are described as relative concepts based on the directions shown in the drawings.

[0055] Terms such as "including" or "having" should be understood as intending to specify the existence of the features, numbers, steps, operations, constituent elements, parts or their combinations recorded in the specification, and are not intended to preclude the existence or additional possibility of one or more other features or numbers, steps, operations, constituent elements, parts or their combinations.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with that in the context of the relevant art, and unless interpreted in an ideal or excessively formal sense, are explicitly defined in this specification.

[0057] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of a display device DD according to an embodiment of the present invention.

[0059] The display device DD may include various embodiments. For example, the display device DD may include a tablet computer, a notebook computer, a computer, a smart TV, etc. In this embodiment, the display device DD is exemplarily illustrated as a smart phone.

[0060] like Figure 1 As shown, the display device DD can display an image IM on the front surface FS. The front surface FS can be defined as a plane parallel to a plane defined by the first direction DR1 and the second direction DR2. The front surface FS includes a display area DA and a frame area BZA adjacent to the display area DA.

[0061] The display device DD displays the image IM in the display area DA. Figure 1 , a clock and a plurality of icons are illustrated as examples of the image IM.

[0062] The display area DA may have a quadrilateral shape parallel to the first direction DR1 and the second direction DR2 , respectively. However, this is an exemplary example, and the display area DA may have various shapes and is not limited to a certain embodiment.

[0063] The bezel area BZA is adjacent to the display area DA. The bezel area BZA may surround the display area DA. However, this is an illustrative example, and the bezel area BZA may be arranged adjacent to only one side of the display area DA, or may be omitted. The electronic device according to an embodiment of the present invention may include various embodiments and is not limited to any one embodiment.

[0064] The normal direction of the front surface FS may correspond to the thickness direction DR3 of the display device DD (hereinafter referred to as the "third direction"). In this embodiment, the front (or top) and back (or bottom) of each component are defined based on the direction in which the image IM is displayed. The front and back surfaces are opposite each other in the third direction DR3.

[0065] In addition, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and can be changed to different directions. Hereinafter, the first to third directions are referred to as the directions indicated by the first to third directions DR1, DR2, and DR3 respectively and are referred to with the same reference numerals.

[0066] Furthermore, the display device DD according to the present invention can sense external user input TC. User input TC includes various forms of external input, such as a part of the user's body, light, heat, or pressure. Furthermore, the display device DD can obviously sense input that comes into contact with the display device DD, as well as input that comes close to or adjacent to the display device DD.

[0067] In this embodiment, the user input TC is shown as being applied by the user's hand to the front surface FS. However, this is merely an illustrative example. As described above, the user input TC can be provided in various forms. Furthermore, the display device DD can sense the user input TC applied to the side or back of the display device DD, depending on its structure, and is not limited to a single embodiment.

[0068] The display device DD may include a window WM and an outer housing HU, which in combination define the appearance of the display device DD.

[0069] The window WM may be made of glass or plastic. The window WM may have a multi-layer or single-layer structure. For example, the window WM may have a laminated structure of multiple plastic films bonded together with an adhesive, or a laminated structure of a glass substrate and a plastic film bonded together with an adhesive. The front surface FS of the display device DD may be effectively defined by the front surface FS of the window WM.

[0070] Figure 2 yes Figure 1 An exploded perspective view of the display device DD is shown.

[0071] Reference Figure 1 as well as Figure 2 The display device DD may include a window WM, an electronic panel EP, a circuit substrate DC, an electronic module EM, and an external housing HU. The window WM and the external housing HU together define the appearance of the display device DD.

[0072] The window WM is arranged on the electronic panel EP and covers the front surface IS of the electronic panel EP. The window WM may be made of an optically transparent insulating material. For example, the window WM may be made of glass or plastic. The window WM may have a multi-layer or single-layer structure. For example, the window WM may have a laminated structure of multiple plastic films bonded together with an adhesive, or may have a laminated structure of a glass substrate and a plastic film bonded together with an adhesive.

[0073] The window WM includes a front surface FS exposed to the outside. The front surface FS of the display device DD can actually be defined by the front surface FS of the window.

[0074] The display area DA of the window WM can be an optically transparent area. The display area DA can have a shape corresponding to the active area AA of the electronic panel EP. For example, the display area DA overlaps the entire surface or at least a portion of the active area AA. The image IM displayed on the active area AA of the electronic panel EP can be visually recognized externally through the display area DA.

[0075] The bezel area BZA may be an area having a light transmittance relatively lower than that of the display area DA. The bezel area BZA defines the shape of the display area DA. The bezel area BZA may be adjacent to the display area DA and may surround the display area DA.

[0076] The frame area BZA may have a predetermined color. When the window WM is provided by a glass or plastic substrate, the frame area BZA may be a color layer printed or deposited on one side of the glass or plastic substrate. Alternatively, the frame area BZA may be formed by coloring a corresponding area of the glass or plastic substrate.

[0077] The bezel area BZA may cover the peripheral area NAA of the electronic panel EP and prevent the peripheral area NAA from being visually recognized from the outside. In addition, this is an example shown illustratively, and in some embodiments, the window WM may not include the bezel area BZA.

[0078] The electronic panel EP may display an image IM and sense a user input TC. The electronic panel EP may include a front surface IS including an active area AA and a peripheral area NAA. The active area AA may be an area activated by an electrical signal.

[0079] In this embodiment, the active area AA can be both an area for displaying the image IM and an area for sensing user input TC. The display area DA at least overlaps with the active area AA. For example, the display area DA overlaps the entire surface or at least a portion of the active area AA. Thus, the user can visually confirm the image IM through the display area DA, or can provide user input TC. However, this is merely an illustrative example; the area for displaying the image IM and the area for sensing user input TC within the active area AA can be separate, and the present invention is not limited to a particular embodiment.

[0080] The peripheral area NAA may be an area covered by the frame area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may surround the active area AA. A driving circuit or driving wiring for driving the active area AA may be arranged in the peripheral area NAA.

[0081] Various signal lines, pads PD, or electronic components that provide electrical signals to the active area AA may be arranged in the peripheral area NAA. The peripheral area NAA may be covered by the bezel area BZA and cannot be visually recognized from the outside.

[0082] In this embodiment, the electronic panel EP is assembled in a flat state with the active area AA and the peripheral area NAA facing the window WM. However, this is an illustrative example, and a portion of the peripheral area NAA in the electronic panel EP can be curved. In this case, a portion of the peripheral area NAA can face the back of the display device DD, thereby reducing the border area BZA in front of the display device DD. Alternatively, the electronic panel EP can also be assembled in a state in which a portion of the active area AA is curved. Alternatively, for the electronic panel EP according to an embodiment of the present invention, the peripheral area NAA can also be omitted.

[0083] The electronic panel EP and the window WM may be bonded to each other via a transparent adhesive member such as a pressure sensitive adhesive film (PSA), an optically clear adhesive film (OCA), or an optically clear adhesive resin (OCR).

[0084] Furthermore, an anti-reflector may be disposed between the electronic panel EP and the window WM. The anti-reflector reduces the reflectivity of external light incident from the upper side of the window WM. In one embodiment, the anti-reflector may include a phase retarder and a polarizer.

[0085] A module area MA may be defined within the active area AA of the electronic panel EP. The module area MA may be an area overlapping with the electronic module EM, described later. The electronic panel EP may receive external signals required by the electronic module EM through the module area MA, or may provide signals output by the electronic module EM to the outside. In an exemplary embodiment of the present invention, by arranging the module area MA in the active area AA rather than in the peripheral area NAA, the area of the peripheral area NAA and the border area BZA can be reduced.

[0086] The shape of the module area MA can be defined in various ways. In this embodiment, for ease of explanation, the module area MA is shown as having a circular shape. However, this is not limited to this. The module area MA can have various shapes, such as an elliptical shape, a polygonal shape, a shape including curved edges and straight edges, and is not limited to a specific embodiment.

[0087] At least a portion of the module area MA of the electronic panel EP may be surrounded by the active area AA. In this embodiment, the module area MA is separated from the peripheral area NAA. The module area MA is shown as being defined within the active area AA with all edges surrounded by the active area AA. In the coupled state of the display device DD according to this embodiment, the display area DA of the window WM may overlap with the module area MA of the electronic panel EP.

[0088] The circuit substrate DC can be connected to the electronic panel EP. The circuit substrate DC can include a flexible substrate CF and a main substrate MB. The flexible substrate CF includes an insulating film and conductive wiring attached to the insulating film. The conductive wiring is connected to the pad PD, electrically connecting the circuit substrate DC and the electronic panel EP.

[0089] In this embodiment, the flexible substrate CF can be assembled in a curved configuration. Consequently, the main substrate MB can be placed on the back of the electronic panel EP and stably accommodated within the space provided by the external housing HU. Alternatively, the flexible substrate CF can be omitted in this embodiment, in which case the main substrate MB can be directly connected to the electronic panel EP.

[0090] The main substrate MB may include signal lines and electronic components not shown. The electronic components can be connected to the signal lines and can be electrically connected to the electronic panel EP. The electronic components can generate various electrical signals (for example, a signal for generating an image IM or a signal for sensing a user's input TC) or process sensed signals. In addition, the main substrate MB can be equipped with a plurality of corresponding electrical signals for each generation and processing, but is not limited to a certain embodiment. Although not shown in the drawings, the electronic module EM can be electrically connected to the main substrate MB.

[0091] In addition, for a display device DD according to an embodiment of the present invention, the drive circuit that provides electrical signals to the active area AA can also be directly mounted on the electronic panel EP. In this case, the drive circuit can be mounted in the form of a chip, or it can be formed together with the pixel (described later). In this case, the area of the circuit substrate DC can be reduced or it can be omitted. The display device DD according to an embodiment of the present invention can include multiple embodiments and is not limited to any one embodiment.

[0092] The electronic module EM is arranged below the window WM. The electronic module EM may overlap the module area MA in planar view. The electronic module EM may receive external inputs transmitted through the module area MA or provide outputs through the module area MA. According to the present invention, the electronic module EM may be arranged to overlap the active area AA, thereby preventing an increase in the area of the peripheral area NAA and the bezel area BZA.

[0093] Figure 3 FIG. 1 is a cross-sectional view of an electronic panel EP provided in a display device according to an embodiment of the present invention.

[0094] like Figure 3 As shown, the electronic panel EP includes a display panel DP and an input sensing layer ISL. The display panel DP and the input sensing layer ISL are simply illustrated to illustrate the stacking relationship. In addition, a window WM (see FIG. 1 ) may be arranged on the input sensing layer ISL. Figure 2 ) are not shown in the figure.

[0095] like Figure 3 As shown, the display panel DP includes a base layer BL, a circuit element layer DP-CL, a light-emitting element layer DP-OLED, and an encapsulation substrate ECG. The input sensing layer ISL can be arranged on the encapsulation substrate ECG. The encapsulation substrate ECG can be an insulating and optically transparent substrate. For example, the encapsulation substrate ECG can include a glass substrate or a plastic substrate.

[0096] The input sensing layer ISL may include a first conductive layer CL1 , a first insulating layer IL1 , a second conductive layer CL2 , and a second insulating layer IL2 .

[0097] The first conductive layer CL1 is directly disposed on the package substrate ECG. In another embodiment, an insulating layer may be disposed between the package substrate ECG and the first conductive layer CL1.

[0098] The first conductive layer CL1 and the second conductive layer CL2 can each have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The conductive layer of the multi-layer structure can include at least two layers of a transparent conductive layer and a metal layer. The conductive layer of the multi-layer structure can include a metal layer containing different metals. The transparent conductive layer can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), 3,4-ethylenedioxythiophene polymer (PEDOT: Poly (3,4-ethylenedioxythiophene)), metal nanowires, and graphene. The metal layer can include molybdenum, silver, titanium, copper, aluminum, and alloys of these metals. For example, the first conductive layer CL1 and the second conductive layer CL2 can each have a three-layer metal layer structure (for example, a three-layer structure of titanium / aluminum / titanium). Relatively speaking, a metal with higher durability and lower reflectivity can be applied to the outer layer, and a metal with higher conductivity can be applied to the inner layer. In one embodiment, the first conductive layer CL1 may be a metal layer, and the second conductive layer CL2 may be a transparent conductive layer.

[0099] The first conductive layer CL1 and the second conductive layer CL2 each include a plurality of conductive patterns, each of which may include a sensing electrode and a signal line connected thereto.

[0100] The first insulating layer IL1 and the second insulating layer IL2 may each include an inorganic layer or an organic layer. In this embodiment, the first insulating layer IL1 and the second insulating layer IL2 may be inorganic layers. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In another embodiment, the second insulating layer IL2 may include an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0101] exist Figure 3 , the electronic panel EP is formed as a single substrate, and the display panel DP and the input sensing layer ISL are each a "layer" type. However, the present invention is not limited thereto. In another embodiment, the display panel DP and the input sensing layer ISL may be formed as separate substrates and then combined.

[0102] Figure 4 FIG. 4 is a plan view of a display panel DP according to an embodiment of the present invention.

[0103] like Figure 4 As shown, the display panel DP may include a driving circuit SDC, multiple signal lines (hereinafter referred to as "signal lines") SGL, multiple signal pads (hereinafter referred to as "signal pads") DP-PD, ISL-PD and multiple pixels (hereinafter referred to as "pixels") PX.

[0104] The drive circuit SDC may include a scan drive circuit. The scan drive circuit generates a plurality of scan signals (hereinafter referred to as "scan signals"), which are sequentially output to a plurality of scan lines (hereinafter referred to as "scan lines") SL described later. The scan drive circuit may also output another control signal to the drive circuit of the pixel PX.

[0105] The scan driving circuit may include a plurality of transistors formed through the same process as that of the driving circuit of the pixel PX (eg, a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process).

[0106] The signal lines SGL include scan lines SL, data lines DL, power lines PL, and control signal lines CSL. Each scan line SL is connected to a corresponding pixel PX among the plurality of pixels PX, and each data line DL is connected to a corresponding pixel PX among the plurality of pixels PX. The power lines PL are connected to the pixels PX. The control signal lines CSL can provide control signals to the scan drive circuit.

[0107] In this embodiment, the signal line SGL may further include an auxiliary line SSL. The auxiliary line SSL is connected to the input sensing layer ISL (refer to Figure 5 In one embodiment of the present invention, the auxiliary line SSL may be omitted.

[0108] The signal line SGL may include a plurality of portions arranged on different layers from each other. Figure 4 FIG. 1 shows an exemplary embodiment of a data line DL including four portions P1 to P4 and an auxiliary line SSL including two portions P10 and P20. The four portions P1 to P4 can be connected via contact holes CNT, and the two portions P10 and P20 can be connected via contact holes CNT. The first portion P10 of the auxiliary line SSL is connected to the input sensing layer ISL (see FIG. 1 ) described later via the contact hole CNT. Figure 5 ) signal line connection.

[0109] Figure 2 The illustrated pads PD may include signal pads DP-PD and ISL-PD. The signal pads DP-PD and ISL-PD may include: first-type signal pads DP-PD connected to data lines DL, power lines PL, and control signal lines CSL; and second-type signal pads ISL-PD connected to auxiliary lines SSL. The first-type signal pads DP-PD and the second-type signal pads ISL-PD are arranged adjacent to each other in a pad area NDA-PA defined as a portion of the peripheral area NAA. The stacked structures or constituent materials of the signal pads DP-PD and ISL-PD are not distinguishable from each other and may be formed through the same process.

[0110] The active area AA may be defined as an area where pixels PX are arranged. A plurality of electronic components are arranged in the active area AA. The electronic components include an organic light emitting diode equipped with each pixel PX and a pixel driving circuit connected thereto. The driving circuit SDC, the signal line SGL, the signal pads DP-PD, ISL-PD and the pixel driving circuit may be included in Figure 3 The circuit component layer DP-CL is shown.

[0111] Although not shown in the drawings, the pixel PC may include at least one transistor, at least one capacitor, and an organic light emitting diode. The pixel PX is connected to the scan line SL and the data line DL. The pixel PX receives a power supply voltage provided by the power line PL.

[0112] The signal pads DP-PD and ISL-PD of the display panel DP can be connected to Figure 2 The circuit substrate shown is DC electrically connected.

[0113] Figure 4 As shown, a portion of the display panel DP may be bent. A portion of the peripheral area NAA may be bent about a bending axis parallel to the first direction DR1. The bending axis may be defined to overlap with the second portion P2 of the data line DL and the auxiliary line SSL.

[0114] The module area MA of the display panel DP is defined within the active area AA. In an exemplary embodiment, the pixels PX may not be arranged in the module area MA of the display panel DP.

[0115] Figure 5 FIG. 4 is a plan view of an input sensing layer ISL according to an embodiment of the present invention.

[0116] Reference Figure 5 , the input sensing layer ISL is arranged at Figure 4 The input sensing layer ISL can sense the user's input TC (in Figure 1 The input sensing layer ISL may include a sensing area SA and a wiring area NSA on a plane. The sensing area SA may be defined as an area where the first sensing electrode SE1 and the second sensing electrode SE2 are arranged. In this embodiment, the wiring area NAS may be defined along the edge of the sensing area SA. The sensing area SA and the wiring area NSA may correspond to Figure 4 The active area AA and the peripheral area NAA of the display panel DP are shown.

[0117] In this embodiment, the input sensing layer ISL may be a capacitive touch sensor. One of the first sensing electrode SE1 and the second sensing electrode SE2 receives a driving signal, and the other outputs a change in capacitance between the first sensing electrode SE1 and the second sensing electrode SE2 as a sensing signal.

[0118] Each first sensing electrode SE1 has a shape extending along the first direction DR1. In addition, the first sensing electrodes SE1 may be arranged in sequence along the second direction DR2. The first sensing electrode SE1 may include a plurality of first sensing patterns SP1 and a plurality of first auxiliary patterns CP1.

[0119] Each second sensing electrode SE2 has a shape extending along the second direction DR2. In addition, the second sensing electrodes SE2 may be arranged in sequence along the first direction DR1. The second sensing electrodes SE2 may include a plurality of second sensing patterns SP2 and a plurality of second auxiliary patterns CP2.

[0120] The first sensing lines TL1-1 to TL1-a may include the same number of signal lines as the first sensing electrodes SE1. The first sensing lines TL1-1 to TL1-a may be connected to at least one of the two ends of the first sensing electrodes SE1. The second sensing lines TL2-1 to TL2-b may include the same number of signal lines as the second sensing electrodes SE2. The second sensing lines TL2-1 to TL2-b may be connected to at least one of the two ends of the second sensing electrodes SE2.

[0121] The first sensing lines TL1-1 to TL1-a may be connected to the pad areas NDA-PA (see FIG. Figure 4 ) side of the auxiliary line SSL (refer to Figure 4 The second sensing lines TL2-1 to TL2-b may be connected to the pad area NDA-PA (see FIG. Figure 4 ) on the other side of the auxiliary line SSL (refer to Figure 4 ) part.

[0122] The contact holes CNT penetrate the insulating layer (a and b are positive integers) disposed between the first and second sensing lines TL1 - 1 to TL1 - a and TL2 - 1 to TL2 - b and the auxiliary line SSL.

[0123] Figure 5 The module area MA of the input sensing layer ISL is defined within the sensing area SA. In an exemplary embodiment, the first sensing electrode SE1 and the second sensing electrode SE2 may not be arranged in the module area MA of the input sensing layer ISL.

[0124] Figure 6 is a plan view exemplarily showing the module area MA of the electronic panel EP.

[0125] Reference Figure 6 , at least a portion of the module area MA of the electronic panel EP may be surrounded by the active area AA. Figure 6 In the example shown, the module area MA is defined within the active area AA in such a way that all edges are surrounded by the active area AA.

[0126] The module area MA includes the hole area HA and the pattern area PA. The hole area HA and the electronic module EM (refer to Figure 2) overlap. On a plane, the pattern area PA may have a shape surrounding the hole area HA. Figure 6 As shown, when the hole area HA is circular, the pattern area PA may have a closed curve shape (a donut shape or a circular ring shape) continuously connected along the edge of the hole area HA. The pattern area PA may be designed in various shapes according to the shape of the hole area HA.

[0127] Preferably, the hole area HA of the electronic panel EP has a light transmittance that allows external light to be sufficiently provided to the electronic module EM. The pattern area PA of the electronic panel EP can block external light from being provided to the electronic module EM. Therefore, the hole area HA can have a light transmittance greater than that of the pattern area PA.

[0128] In one embodiment, a cover pattern CVP may be disposed in the pattern area PA. The cover pattern CVP shields the pattern area PA from light. The cover pattern CVP will be described in detail later.

[0129] Figure 7 It is along Figure 2 Cross-sectional view of I-I'.

[0130] For ease of explanation, Figure 7 FIG2 exemplarily illustrates a portion of the display panel DP and the input sensing layer ISL in the configuration of the electronic panel EP. The display panel DP may include a base layer BL, a thin film transistor TR, a light-emitting element OD, and a plurality of insulating layers 10, 20, 30, 40, and 50. The input sensing layer ISL may include a first insulating layer IL1 and a second insulating layer IL2, a plurality of first sensing patterns SP1, a plurality of first auxiliary patterns CP1, and a cover pattern CVP.

[0131] The insulating layers 10, 20, 30, 40, and 50 may be stacked sequentially along the third direction DR3. Each insulating layer 10, 20, 30, 40, and 50 may include organic and / or inorganic materials and may have a single layer or a stacked structure. In this embodiment, the insulating layers 10, 20, 30, 40, and 50 are shown as including a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, but the present invention is not limited thereto.

[0132] In this embodiment, the base layer BL may be optically transparent. For example, the base layer BL may have a visible light transmittance of about 90% or more.

[0133] The first insulating layer 10 is disposed on the base layer BL to cover the front of the base layer BL. The first insulating layer 10 may include a barrier layer and / or a buffer layer. Accordingly, the first insulating layer 10 can prevent oxygen or moisture flowing through the base layer BL from penetrating into the pixel PX, or can provide the pixel PX with an upper surface having a lower surface energy, thereby stably forming the pixel PX on the base layer BL.

[0134] In this embodiment, the first insulating layer 10 may be optically transparent. For example, the first insulating layer 10 may have a visible light transmittance of about 90% or more.

[0135] The thin film transistor TR and the light emitting element OD constitute a pixel PX. The thin film transistor TR may include a semiconductor pattern SSP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SSP is arranged on the first insulating layer 10.

[0136] The semiconductor pattern SSP includes a semiconductor substance. For example, the semiconductor pattern SSP may include a Group III element, a Group V element, a compound of a Group III element or a Group V element, or an oxide semiconductor.

[0137] The semiconductor pattern SSP may be divided into a channel area CA, an input area IA and an output area OA separated by placing the channel area CA therebetween. The channel area CA, the input area IA and the output area OA have an integrated shape connected to each other.

[0138] The channel region CA may be a region overlapping the control electrode CE in a plane. The input region IA and the output region OA have relatively higher charge mobility than the channel region CA. Charges in the semiconductor pattern SSP may move from the input region IA to the output region OA through the channel region CA.

[0139] The control electrode CE is disposed on the second insulating layer 20. The second insulating layer 20 is disposed on the first insulating layer 10 to cover the semiconductor pattern SSP. The control electrode CE may be separated from the semiconductor pattern SSP in a cross section by interposing the second insulating layer 20 therebetween.

[0140] The input electrode IE and the output electrode OE are arranged on the third insulating layer 30. The third insulating layer 30 is arranged on the second insulating layer 20 and covers the control electrode CE.

[0141] The input electrode IE penetrates the second insulating layer 20 and the third insulating layer 30 and is connected to the input area IA. The output electrode OE is separated from the input electrode IE and is connected to the output area OA. The input electrode IE and the output electrode OE can each comprise a conductive material. The input electrode IE supplies charge to the input area IA, and the output electrode OE transfers the charge transferred to the output area OA to the light-emitting element OD.

[0142] In addition, for the thin-film transistor TR according to this embodiment, the input electrode IE and the output electrode OE can also be omitted. That is, the thin-film transistor TR can also be composed only of the control electrode CE and the semiconductor pattern SSP. In this case, the input area IA and the output area OA can function as the input electrode IE and the output electrode OE, and the input electrode IE and the output electrode OE can function as connection electrodes connecting the thin-film transistor TR with other signal lines or other components. The thin-film transistor TR according to an embodiment of the present invention can be provided in various structures and is not limited to a single embodiment.

[0143] The light emitting element OD may include a first electrode E1, a second electrode E2, and a light emitting pattern EP′. The first electrode E1, the second electrode E2, and the light emitting pattern EP′ of the light emitting element OD may correspond to the light emitting element layer DP-OLED (refer to Figure 3 The first electrode E1 is disposed on the fourth insulating layer 40. The fourth insulating layer 40 is disposed on the third insulating layer 30 and covers the thin film transistor TR. The first electrode E1 is connected to the output electrode OE and is electrically connected to the thin film transistor TR.

[0144] The second electrode E2 is disposed on a fifth insulating layer 50 disposed on the fourth insulating layer 40. The fifth insulating layer 50 may include organic and / or inorganic materials and may have a single layer or a stacked structure. The second electrode E2 may have an area covering at least the entire front surface of the active area AA. Accordingly, multiple light-emitting elements OD may share a single second electrode E2. However, this is merely an illustrative example, and the second electrode E2 may also be provided in each pixel corresponding to the first electrode E1. However, this is not limited to any particular embodiment.

[0145] The fifth insulating layer 50 may define an opening that exposes at least a portion of the first electrode E1. A light-emitting pattern EP' may be disposed within the opening. The light-emitting pattern EP' may include a light-emitting material including a fluorescent material or a phosphorescent material. The light-emitting material may include an organic light-emitting material or an inorganic light-emitting material, and is not limited to any particular embodiment.

[0146] Although not shown in the accompanying drawings, a control layer may be disposed between the first electrode E1 and the second electrode E2. The control layer controls the movement of charges, thereby improving the luminous efficiency and lifespan of the light-emitting element OD. The control layer may include an electron transport material, an electron injection material, a hole transport material, or a hole input material. In one embodiment, the control layer may be disposed on the light-emitting pattern EP′. In one embodiment, the control layer may be disposed between the light-emitting pattern EP′ and the first electrode E1, or may be provided as a plurality of control layers, disposed respectively between the light-emitting pattern EP′ and the first electrode E1 and between the light-emitting pattern EP′ and the second electrode E2. However, this is not limited to any one embodiment.

[0147] The package substrate ECG is disposed on the fifth insulating layer 50. The package substrate ECG may be an insulating and optically transparent substrate, for example, a glass substrate or a plastic substrate.

[0148] The package substrate ECG may be arranged to be separated from the fifth insulating layer 50. Although not shown in the drawings, the peripheral area NAA (refer to Figure 2 ) A sealing member may also be arranged. The sealing member is arranged between the encapsulation substrate ECG and the base layer BL so that the encapsulation substrate ECG and the base layer BL are combined with a predetermined gap GP therebetween. The gap GP between the encapsulation substrate ECG and the base layer BL may be filled with air or an inert gas.

[0149] In this embodiment, an input sensing layer ISL is disposed on the display panel DP. As described above, the first sensing pattern SP1 and the first auxiliary pattern CP1 may constitute part of the input sensing layer ISL. The first sensing pattern SP1 and the first auxiliary pattern CP1, together with the first insulating layer IL1 and the second insulating layer IL2, constitute the input sensing layer ISL. Furthermore, the input sensing layer ISL may further include a cover pattern CVP.

[0150] The input sensing layer ISL may include a first insulating layer IL1 and a second insulating layer IL2 sequentially stacked. The first insulating layer IL1 and the second insulating layer IL2 may be provided to overlap the active area AA and the pattern area PA, respectively.

[0151] Each of the first insulating layer IL1 and the second insulating layer IL2 may be optically transparent. For example, each of the first insulating layer IL1 and the second insulating layer IL2 may have a visible light transmittance of approximately 90% or greater. Each of the first insulating layer IL1 and the second insulating layer IL2 may include an inorganic film, an organic film, or a stacked structure thereof.

[0152] In this embodiment, the following situation is shown: the first auxiliary pattern CP1 and the cover pattern CVP are arranged on the same layer, and are arranged on a different layer from the first sensing pattern SP1. The first sensing pattern SP1 may include a transparent conductive oxide. The first auxiliary pattern CP1 and the cover pattern CVP may each include a metal with high conductivity. The first auxiliary pattern CP1 and the cover pattern CVP may be arranged between the package substrate ECG and the first insulating layer IL1, and the first sensing pattern SP1 may pass through the first insulating layer IL1 and be connected to the first auxiliary pattern CP1. In addition, although not shown in the figure, the second auxiliary pattern CP2 (refer to Figure 5 ) may also be arranged on the same layer as the first sensing pattern SP1 and directly connected to the second sensing pattern SP2.

[0153] However, this is merely an example. Alternatively, the first auxiliary patterns CP1 and the first sensing patterns SP1 may be arranged on the same layer, while the second auxiliary patterns CP2 may be arranged on a different layer from the second sensing patterns SP2. Furthermore, the first sensing patterns SP1 and the second sensing patterns SP2 may be arranged on different layers. The input sensing layer ISL according to an embodiment of the present invention can have various structures and is not limited to a single embodiment.

[0154] The hole area HA can be connected to the electronic module EM (refer to Figure 2 ) substantially overlaps with a receiving portion that receives external input or an output portion that provides output in the electronic module EM. For example, when the electronic module EM is a camera module, the aperture area HA may be an area in the module area MA that overlaps with a lens. The aperture area HA may be an area in the module area MA that has the highest light transmittance.

[0155] The input sensing layer ISL includes a module hole MH formed in the hole area HA. The module hole MH can be formed by etching the first insulating layer IL1 and the second insulating layer IL2. By removing the first insulating layer IL1 and the second insulating layer IL2 in the hole area HA, the transmittance of the hole area HA can be improved.

[0156] Figures 8a to 8i 1 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figures 8a to 8i In the display panel DP may be Figure 7 The display panel DP shown is the same and is therefore simply illustrated. The display panel DP includes a display layer DPL and an encapsulation substrate ECG. The display layer DPL may include Figure 7 The base layer BL, the thin film transistor TR, the light emitting element OD and a plurality of insulating layers 10 , 20 , 30 , 40 and 50 are shown.

[0157] like Figure 8aAs shown, a first conductive layer CL1 is formed on the package substrate ECG. The first conductive layer CL1 can be formed by depositing a conductive material on the package substrate ECG. A photoresist pattern PR is formed on the first conductive layer CL1. The photoresist pattern PR can be formed by applying a photosensitive material to the first conductive layer CL1 and then patterning it using a photolithography process to form the photoresist pattern PR. The photoresist pattern PR can be formed in the active area AA and the pattern area PA.

[0158] Then, if Figure 8b As shown, a first etching gas ET1 is provided to form a first auxiliary pattern CP1 and a capping pattern CVP from the first conductive layer CL1. The first etching gas ET1 reacts with a portion of the first conductive layer CL1 exposed from the photoresist pattern PR to remove the exposed portion from the package substrate ECG.

[0159] Then, if Figure 8c As shown, a first insulating layer IL1 is formed on the display panel DP. The first insulating layer IL1 can be formed by covering the first auxiliary pattern CP1 and the cover pattern CVP with an insulating material. The first insulating layer IL1 can be formed by depositing an inorganic material. The first insulating layer IL1 can be formed in front of the display panel DP.

[0160] like Figure 8d As shown, a second etching gas ET2 is provided to form a plurality of contact holes CH and a first opening OP1 in the first insulating layer IL1. In one embodiment, the first opening OP1 and the contact holes CH can be formed simultaneously by the second etching gas ET2.

[0161] The contact hole CH is formed in the active area AA. The contact hole CH is formed to overlap with the first auxiliary pattern CP1 to expose a portion of the first auxiliary pattern CP1. The first opening OP1 is formed in the hole area HA. The first opening OP1 penetrates the first insulating layer IL1 to expose the package substrate ECG.

[0162] Then, if Figure 8e As shown, a second conductive layer CL2 and a photoresist pattern PR are sequentially formed on the package substrate ECG. The second conductive layer CL2 can be formed by depositing a conductive material on the first insulating layer IL1. Accordingly, the second conductive layer CL2 covers the top surface of the first insulating layer IL1, the inner surface of the contact hole CH, and the inner surface of the first opening OP1.

[0163] A photoresist pattern PR is formed on the second conductive layer CL2. The photoresist pattern PR can be formed by coating a photosensitive material on the second conductive layer CL2 and then patterning the layer using a photolithography process. The photoresist pattern PR can be formed in the active area AA and corresponding to each contact hole CH.

[0164] like Figure 8f As shown, a third etching gas ET3 is provided to form the first sensing pattern SP1 from the second conductive layer CL2. The third etching gas ET3 reacts with a portion of the second conductive layer CL2 exposed from the photoresist pattern PR to remove the exposed portion.

[0165] Then, if Figure 8g As shown, a second insulating layer IL2 and a photoresist pattern PR are sequentially formed on the package substrate ECG. The second insulating layer IL2 can be formed by covering the first sensing pattern SP1 with an insulating material. The second insulating layer IL2 can be formed by depositing an inorganic material. The second insulating layer IL2 can be formed in front of the display panel DP.

[0166] A photoresist pattern PR is formed on the second insulating layer IL2. The photoresist pattern PR can be formed by coating a photosensitive material on the second insulating layer IL2 and then patterning the layer through a photolithography process. The photoresist pattern PR is formed in the active area AA and the pattern area PA.

[0167] like Figure 8h As shown, the fourth etching gas ET4 is provided to form the second opening OP2 in the hole region HA. In one embodiment, the second opening OP2 may be formed by removing the hole region HA of the first insulating layer IL1 and the second insulating layer IL2.

[0168] Then, if Figure 8i As shown, the photoresist pattern PR is removed to form an input sensing layer ISL.

[0169] Figure 9a as well as Figure 9b It is magnified Figure 8i A cross-sectional view taken of the first area A1 shown.

[0170] Figure 8e The hole area HA in the second conductive layer CL2 can be formed by Figure 8f The etching gas ET3 is used to remove the etchant.

[0171] At this time, if Figure 9a As shown, residues CL2_R of the second conductive layer CL2 may remain on the package substrate ECG. The residues CL2_R remaining on the package substrate ECG may reduce visible light transmittance or be visually recognized as spots.

[0172] Furthermore, the residue CL2_R remaining on the upper surface of the package substrate ECG is Figure 8hIn the etching process shown, the first insulating layer IL1 and the second insulating layer IL2 in the hole area HA function as a mask on the package substrate ECG, thereby making the etching of the first insulating layer IL1 and the second insulating layer IL2 uneven, or etching the surface of the package substrate ECG without leaving any residue CL2_R.

[0173] In this case, if Figure 9b As shown in FIG. 1 , a protrusion EU is formed on the upper surface of the package substrate ECG. Such a protrusion EU may cause a change in the visible light transmittance.

[0174] Figures 10a to 10j FIG is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figures 10a to 10j In the display panel DP may be Figure 7 The display panel DP shown in FIG is the same as that shown in FIG, and is therefore simply illustrated. The display panel DP includes a display layer DPL and an encapsulation substrate ECG. The display layer DPL may include Figure 7 The base layer BL, the thin film transistor TR, the light emitting element OD and a plurality of insulating layers 10 , 20 , 30 , 40 and 50 are shown.

[0175] like Figure 10a As shown, a first conductive layer CL1 is formed on the package substrate ECG. The first conductive layer CL1 can be formed by depositing a conductive material on the package substrate ECG. A photoresist pattern PR is formed on the first conductive layer CL1. The photoresist pattern RP can be formed by applying a photosensitive material to the first conductive layer CL1 and then patterning it using a photolithography process to form the photoresist pattern PR. The photoresist pattern PR can be formed in the active area AA, the pattern area PA, and the aperture area HA.

[0176] Afterwards, if Figure 10b As shown, a first etching gas ET1 is provided to form first auxiliary patterns CP1, capping patterns CVP, and conductive patterns CPP from the first conductive layer CL1. The first auxiliary patterns CP1, capping patterns CVP, and conductive patterns CPP are spaced a predetermined distance apart along a first direction DR1.

[0177] The first etching gas ET1 reacts with a portion of the first conductive layer CL1 exposed from the photoresist pattern PR, thereby removing the exposed portion from the encapsulation substrate ECG.

[0178] Afterwards, if Figure 10c As shown, a first insulating layer IL1 is formed on the display panel DP. The first insulating layer IL1 can be formed by covering the first auxiliary pattern CP1, the cover pattern CVP, and the conductive pattern CPP with an insulating material. The first insulating layer IL1 can be formed by depositing an inorganic material. The first insulating layer IL1 can be formed in front of the display panel DP.

[0179] like Figure 10d As shown, a second etching gas ET2 is provided to form a plurality of contact holes CH in the first insulating layer IL1. The contact holes CH are formed in the active area AA. The contact holes CH are formed to overlap with the first auxiliary pattern CP1 so as to expose a portion of the first auxiliary pattern CP1.

[0180] Afterwards, if Figure 10e As shown, a second conductive layer CL2 and a photoresist pattern PR are sequentially formed on the package substrate ECG. The second conductive layer CL2 can be formed by depositing a conductive material on the first insulating layer IL1. Accordingly, the second conductive layer CL2 covers the upper surface of the first insulating layer IL1 and the inner surface of the contact hole CH.

[0181] A photoresist pattern PR is formed on the second conductive layer CL2. The photoresist pattern PR can be formed by coating a photosensitive material on the second conductive layer CL2 and then patterning the material through a photolithography process to form the photoresist pattern PR. The photoresist pattern PR can be formed in the active area AA and corresponding to each contact hole CH.

[0182] like Figure 10f As shown, the third etching gas ET3 is provided to form the first sensing pattern SP1 from the second conductive layer CL2. The third etching gas ET3 reacts with a portion of the second conductive layer CL2 exposed from the photoresist pattern PR, thereby removing the exposed portion.

[0183] Afterwards, if Figure 10g As shown, a second insulating layer IL2 and a photoresist pattern PR are sequentially formed on the package substrate ECG. The second insulating layer IL2 can be formed by covering the first sensing pattern SP1 with an inorganic substance. The second insulating layer IL2 can be formed by depositing an inorganic substance. The second insulating layer IL2 can be formed in front of the display panel DP.

[0184] A photoresist pattern PR is formed on the second insulating layer IL2. The photoresist pattern PR can be formed by coating a photosensitive material on the second insulating layer IL2 and then patterning the material through a photolithography process to form the photoresist pattern PR. The photoresist pattern PR can be formed in the active area AA and the pattern area PA.

[0185] like Figure 10h As shown, the fourth etching gas ET4 is provided to remove portions of the first insulating layer IL1 and the second insulating layer IL2 overlapping the hole area HA, thereby exposing the conductive pattern CPP in the hole area HA.

[0186] Further, if Figure 10iAs shown, a fifth etching gas ET5 is provided to remove the conductive pattern CPP in the hole area HA. Etching by the fifth etching gas ET5 can be anisotropic etching. For example, the fifth etching gas ET5 can be composed of the same material as the fourth etching gas ET4. The conductive pattern CPP in the hole area HA can be removed without removing the photoresist pattern PR used to etch the first insulating layer IL1 and the second insulating layer IL2 using the fourth etching gas ET4. Therefore, a separate photoresist pattern for removing the conductive pattern CPP is not required.

[0187] Can be borrowed Figure 10h The removal process of the first insulating layer IL1 and the second insulating layer IL2 is shown as follows: Figure 10i The module hole MH is formed by removing the conductive pattern CPP shown.

[0188] Afterwards, if Figure 10j As shown, the photoresist pattern PR is removed to form an input sensing layer ISL.

[0189] As before Figure 10e As shown, the second conductive layer CL2 is formed on the conductive pattern CPP and the first insulating layer IL1. And, the second conductive layer CL2 formed in the hole area HA of the package substrate ECG can be removed in sequence (refer to Figure 10e ), the first insulating layer IL1 (refer to Figure 10g ), the second insulating layer IL2 (refer to Figure 10g ) and the conductive pattern CPP (refer to Figure 10h ), thereby improving the transmittance of the hole area HA of the package substrate ECG. In particular, during the formation process of the input sensing layer ISL, the second conductive layer CL2 is not directly formed on the package substrate ECG, so that no residue of the second conductive layer CL2 may remain in the hole area HA.

[0190] Figures 11a to 11c is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention. Figures 11a to 11c Pictured Figure 10f Subsequent manufacturing methods.

[0191] Reference Figure 11a A photoresist pattern PR is formed on the first sensing pattern SP1. The photoresist pattern PR may be formed in the active area AA and the pattern area PA. A fourth etching gas ET4 is provided to remove the hole area HA of the first insulating layer IL1.

[0192] Afterwards, if Figure 11b As shown, the fifth etching gas ET5 is provided to remove the conductive pattern CPP. The fourth etching gas ET4 may be the same as the fifth etching gas ET5.

[0193] Afterwards, if Figure 11c As shown, the photoresist pattern PR is removed, and a second insulating layer IL2 is formed on the second conductive layer CL2. The second insulating layer IL2 can be formed by covering the first sensing pattern SP1 with an insulating material. The second insulating layer IL2 can be formed by depositing an inorganic material. The second insulating layer IL2 can be formed in front of the display panel DP.

[0194] Although Figure 10j In the hole area HA of the package substrate ECG shown in FIG, the first insulating layer IL1 and the second insulating layer IL2 are completely removed. Figure 11c The second insulating layer IL2 remains in the hole area HA of the package substrate ECG shown.

[0195] Figure 12 It is magnified Figure 11c A cross-sectional view taken of the second area BB.

[0196] like Figure 12 As shown, the upper surface of the package substrate ECG (ie, the surface in contact with the second insulating layer IL2) is smaller than that of the package substrate ECG. Figure 9a as well as Figure 9b The top surface of the package substrate ECG shown may have uniform flatness. Since the top surface of the package substrate ECG has uniform flatness, the visible light transmittance in the hole area HA may be kept constant, and no spots may be visually recognized.

[0197] Although the above description is made with reference to the preferred embodiments of the present invention, any person skilled in the art or having ordinary knowledge in the art will understand that various modifications and changes may be made to the present invention without departing from the scope of the idea and technical field of the present invention as described in the claims.

[0198] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A method for manufacturing a display device, comprising the following steps: providing a display layer divided in a plane into a hole area, a pattern area surrounding the hole area, and an active area surrounding at least a portion of the pattern area; providing a packaging substrate on the display layer; forming a conductive pattern on the packaging substrate that overlaps the hole area; forming a first insulating layer on the conductive pattern; forming a conductive layer on the first insulating layer; as well as A module hole is formed by removing a portion of the conductive layer overlapping the hole region, a portion of the first insulating layer overlapping the hole region, and the conductive pattern.

2. The method for manufacturing a display device according to claim 1 , further comprising the following steps: A second insulating layer is formed on the conductive layer and overlaps the hole region, the pattern region, and the active region respectively.

3. The method for manufacturing a display device according to claim 2, wherein The step of forming the module hole comprises the following steps: forming a photoresist pattern on the second insulating layer, overlapping the active area and the pattern area; etching the first insulating layer and the second insulating layer; etching the conductive pattern; as well as The photoresist pattern is removed.

4. The method for manufacturing a display device according to claim 3, wherein: The step of etching the first insulating layer and the second insulating layer includes the step of providing a first etching gas, The step of etching the conductive pattern includes the step of providing a second etching gas.

5. A method for manufacturing a display device, comprising the following steps: providing a display layer divided in a plane into a hole area, a pattern area surrounding the hole area, and an active area surrounding at least a portion of the pattern area; providing a packaging substrate on the display layer; forming first to third conductive patterns on the package substrate, respectively overlapping the active area, the pattern area, and the hole area; forming a first insulating layer on the first to third conductive patterns; forming a contact hole exposing a portion of the first conductive pattern; forming an electrode connected to the first conductive pattern through the contact hole; as well as A portion of the first insulating layer overlapping the hole region and the third conductive pattern are removed to form a module hole.

6. The method for manufacturing a display device according to claim 5, wherein: The first to third conductive patterns are spaced apart from each other on a plane.

7. The method for manufacturing a display device according to claim 5, wherein: The steps of forming the electrode include the following steps: forming a conductive layer filling the contact hole; forming a photoresist pattern on the conductive layer; etching the conductive layer to form the electrode; and The photoresist pattern is removed.

8. The method for manufacturing a display device according to claim 5, further comprising the following steps: A second insulating layer is formed on the electrode and overlaps the hole region, the pattern region, and the active region respectively.

9. The method for manufacturing a display device according to claim 8, wherein: The step of forming the module hole comprises the following steps: forming a photoresist pattern on the second insulating layer, overlapping the active area and the pattern area; etching the first insulating layer and the second insulating layer; etching the third conductive pattern; as well as The photoresist pattern is removed.

10. The method for manufacturing a display device according to claim 9, wherein: The step of etching the first insulating layer and the second insulating layer includes the step of providing a first etching gas, The step of etching the third conductive pattern includes the step of providing a second etching gas.

11. The method for manufacturing a display device according to claim 5, wherein: The step of forming the module hole comprises the following steps: forming a photoresist pattern on the electrode and the first insulating layer, overlapping the active area and the pattern area; etching the first insulating layer; etching the third conductive pattern; as well as The photoresist pattern is removed.

12. The method for manufacturing a display device according to claim 11, wherein: After the step of removing the photoresist pattern, the method further includes the step of forming a second insulating layer in the hole area, the pattern area and the active area.

13. The method for manufacturing a display device according to claim 5, wherein: The packaging substrate includes a glass substrate.

14. A display device comprising: Electronic modules; as well as The electronic panel is divided into a hole area overlapping with the electronic module, a pattern area surrounding the hole area, and an active area surrounding at least a portion of the pattern area. Wherein, the electronic panel includes: Display layer, displays images; a packaging substrate covering the display layer, wherein a portion overlapping with the hole region in a plane is not penetrated; and An input sensing layer is arranged on the packaging substrate, wherein the input sensing layer includes a module hole exposing the portion of the package substrate overlapping with the hole area, The input sensing layer includes a second conductive pattern on the package substrate, overlapping the pattern area and shielding the pattern area from light.

15. The display device according to claim 14, wherein A region of the package substrate overlapping the hole region has uniform flatness.

16. The display device according to claim 14, wherein The packaging substrate includes a glass substrate.

17. The display device according to claim 14, wherein The input sensing layer further includes a first conductive pattern on the package substrate and overlapping the active area.

18. The display device according to claim 17, further comprising: a first insulating layer on the first conductive pattern and the second conductive pattern that overlaps the active area and the pattern area; as well as A conductive layer is formed on the first insulating layer.

19. The display device according to claim 18, wherein: The conductive layer is electrically connected to the first conductive pattern through a contact hole penetrating the first insulating layer.

20. The display device according to claim 18, further comprising: A second insulating layer is provided on the conductive layer and overlaps the active area, the pattern area, and the hole area.

Images