Memory controller and data processing method

Abstract

A memory controller and a data processing method, the data processing method comprising: configuring a predetermined memory space to record information of data to be backed up of a memory device, wherein the information is used to indicate which logical memory spaces of the memory device are associated with data to be backed up; and updating the information according to multiple instructions received from a host device.

Description

Technical Field

[0001] The present invention relates to a data processing method, and in particular to a data processing method for recording information of data to be backed up in a storage device in real time. Background Art

[0002] Users sometimes need to back up hard disk data. When performing data backup, in order to reduce the amount of data written, it is necessary to determine which data is new and which data is old. Generally speaking, to determine the newness of data, it is necessary to parse the file system (file system) supported by the computer operating system in order to know which data is new and which data is old. However, since the hard disk capacity of today's computers has been greatly improved, for example, it has reached the level of several megabytes, therefore, parsing the file system will be a very tedious task, and because it is necessary to compare or track the update time of files one by one, a large amount of computer computing resources must be consumed. In addition, different operating systems support different file systems, and their parsing methods are also different. Therefore, different parsing methods must be designed for different file systems. Therefore, there is a compatibility issue that must be considered in the development of hard disk backup software.

[0003] To solve the above problem, the present invention provides a data processing method that can improve the execution efficiency of data backup. Summary of the invention

[0004] An object of the present invention is to provide a data processing method that can improve the execution efficiency of data backup to solve the above problems. The idea of ​​the method is to use a memory controller at the storage device end to record the information of the data to be backed up of the storage device in real time, and continuously update the information of the data to be backed up according to the access operation of the storage device. When data backup is required, by actively providing the information of the data to be backed up, the execution efficiency of data backup can be greatly improved compared with the traditional technology.

[0005] According to an embodiment of the present invention, a memory controller is coupled to a memory device, comprising a host interface and a processor. The host interface is used to receive multiple instructions from a host device. The processor is coupled to the host interface and is used to record information about data to be backed up in the memory device. The information about the data to be backed up is used to indicate which logical memory spaces of the memory device are associated with data to be backed up. The processor configures a predetermined memory space to store the information and updates the information according to the instructions.

[0006] According to another embodiment of the present invention, a data processing method includes: configuring a predetermined memory space to record information about data to be backed up in a memory device, wherein the information is used to indicate which logical memory spaces of the memory device are associated with data to be backed up; and updating the information according to multiple instructions received from a host device.

[0007] By using the information of the data to be backed up, the host device or a specific data backup software can correctly identify which logical memory spaces of the memory device are associated with data to be backed up. In this way, data backup can be performed in a simple and efficient manner, and the problems encountered in the traditional technology can be effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 4 is a block diagram of a system according to an embodiment of the present invention.

[0009] Figure 2 is a block diagram showing an example of a memory controller according to an embodiment of the present invention.

[0010] Figure 3 It is a flow chart showing a data processing method according to an embodiment of the present invention.

[0011] Figure 4 FIG. 1 is a schematic diagram showing a mapping of a memory space according to a first embodiment of the present invention.

[0012] Figure 5 FIG. 4 is a schematic diagram showing a data backup operation according to an embodiment of the present invention.

[0013] Explanation of symbols

[0014] 100: System

[0015] 110, 510: Host device

[0016] 120, 520, 530: Storage device

[0017] 121, 200: Memory controller

[0018] 122: Dynamic Random Access Memory

[0019] 123: Flash memory

[0020] 210: Host interface

[0021] 220, 230: Memory interface

[0022] 240: Processor

[0023] 250: Bus

[0024] 260: Instruction Buffer Memory

[0025] 270: Data buffer memory

[0026] 400: Determined storage space

[0027] 410: Storage unit

[0028] 450: Memory space of the memory device

[0029] 460: Logical memory space

[0030] S302, S304: Steps DETAILED DESCRIPTION

[0031] Figure 1 1 is a block diagram of a system according to an embodiment of the present invention. The system may be a data storage system, a computer system or an electronic product system. System 100 may include a host device 110 and a storage device 120. Storage device 120 may include a memory controller 121 and one or more memory devices. According to an embodiment of the present invention, storage device 120 may be a solid state drive (SSD) disposed in or connected to an electronic product. Memory controller 121 may be coupled to the one or more memory devices, wherein the memory device may be a dynamic random access memory (DRAM) 122 and a flash memory 123 as shown in the figure, and the flash memory 123 may include a plurality of flash memory modules. Memory controller 121 may access DRAM 122 and flash memory 123 through corresponding interfaces. Memory controller 121 also communicates with host device 110 through corresponding interfaces to receive multiple instructions and execute corresponding memory access operations in response to the instructions.

[0032] It should be noted that Figure 1 FIG. 1 is a simplified block diagram, in which only the components related to the present invention are shown. A person skilled in the art will appreciate that an electronic product system may include many components not shown in FIG. Figure 1 elements to implement various corresponding functions.

[0033] Figure 22 is an exemplary block diagram showing a memory controller according to an embodiment of the present invention. The memory controller 200 may be an implementation of the memory controller 121. The memory controller 200 may include multiple interfaces, such as a host interface 210, memory interfaces 220 and 230, etc., through which the memory controller 200 communicates with peripheral devices. The host interface 210 may be implemented by a controller, such as a Peripheral Component Interconnect Express (PCI Express or PCI) / Serial Advanced Technology Attachment (SATA) controller, to control communication signals transmitted between the memory controller 200 and the host device 110 through corresponding hardware interfaces. The memory controller 200 may receive multiple instructions from the host device 110 through the host interface 210. The memory interface 220 may be implemented by a DRAM controller to control communication signals transmitted between the memory controller 121 / 200 and the DRAM 122 through corresponding hardware interfaces. The memory interface 230 may be implemented by a flash memory controller to control communication signals between the memory controller 121 / 200 and the flash memory 123 via corresponding hardware interfaces.

[0034] The memory controller 200 may further include a processor 240, a bus 250, an instruction buffer memory 260, and a data buffer memory 270. The processor 240 is used to communicate with peripheral devices through the bus 250 and the aforementioned interface. The bus 250 may operate in accordance with the Open Core Protocol (OCP) to connect the host interface 210, the memory interfaces 220 and 230, the processor 240, the instruction buffer memory 260, and the data buffer memory 270 so that they can communicate and cooperate with each other. The instruction buffer memory 260 and the data buffer memory 270 are used to perform the required buffer processing, wherein the instruction buffer memory 260 and the data buffer memory 270 can be implemented by a random access memory (RAM). For example, a static random access memory (Static RAM, abbreviated as SRAM), but the present invention is not limited thereto.

[0035] It should be noted that Figure 2 FIG. 1 is a simplified block diagram, in which only the components related to the present invention are shown. A person skilled in the art will appreciate that a memory controller may include many components not shown in FIG. Figure 2 elements to implement various corresponding functions.

[0036] According to an embodiment of the present invention, the processor 240 may configure a predetermined memory space to store information of data to be backed up of a memory device (e.g., flash memory 123), and continuously update the information of data to be backed up according to the access operation of the memory device. Since the access operation of the memory device is controlled by the memory controller 121 / 200, the processor 240 may record the information of data to be backed up of the memory device in real time according to the latest access operation. For example, the processor 240 may continuously update the information of data to be backed up according to the instruction received from the host device 110.

[0037] In an embodiment of the present invention, the information of the data to be backed up is used to indicate which logical memory spaces of a memory device (e.g., flash memory 123) are associated with data to be backed up, wherein the data associated with a logical memory space may be data logically stored in the logical memory space, and the data to be backed up is data that has not been backed up by the user since the last backup operation was completed, or is data that has been updated by the user since the last backup operation was completed.

[0038] Generally speaking, the storage space of the memory device can be divided into multiple logical memory spaces by the host device 110. Each logical memory space can be addressed by a logical block address (LBA). Data logically stored in a logical memory space can actually be stored in one or more physical memory spaces of the memory device.

[0039] For example, when the user operates the host device 110 to write a file A1 into the logical storage space A, the file A1 is the data currently associated with the logical storage space A. When the user operates the host device 110 to write another file A2 into the logical storage space A to replace the original file A1, the file A2 becomes the data currently associated with the logical storage space A. That is, the file A2 is the data updated by the user.

[0040] In order to solve the problems encountered when performing data backup in the prior art, in an embodiment of the present invention, the processor 240 continuously records the information of the data to be backed up of the memory device (e.g., the flash memory 123) according to the latest access operation. Through the information of the data to be backed up, the host device 110 or a specific data backup software can correctly and quickly identify which logical memory spaces of the memory device are associated with new data (i.e., data to be backed up, or data updated by the user). In this way, when data backup needs to be performed, by actively providing the information of the data to be backed up to the host device 110 or the specific data backup software, the execution efficiency of the data backup can be greatly improved compared to the traditional technology. Among them, the specific data backup software can be software jointly developed with the memory controller 121 / 200 described in the present invention.

[0041] Figure 3 2 is a flow chart showing a data processing method according to an embodiment of the present invention. The data processing method may be executed by the memory controller 121 / 200 or the processor 240, and includes the following steps:

[0042] Step S302: Allocate a predetermined memory space to record information of data to be backed up in a memory device (e.g., flash memory 123). According to an embodiment of the present invention, the memory controller 121 / 200 may configure the predetermined memory space in the DRAM 122, the flash memory 123, or a memory device (e.g., data buffer memory 270) inside thereof. If the memory controller 121 / 200 configures the predetermined memory space in a volatile memory such as DRAM or SRAM, the data recorded in the predetermined memory space may be written into the flash memory 123 before power is turned off to preserve its content.

[0043] Step S304: Update the information of the data to be backed up according to the multiple instructions received from the host device. As described above, the processor 240 can record or update the information of the data to be backed up in real time according to the received instructions or the latest access operation.

[0044] According to the first embodiment of the present invention, the predetermined memory space may include a plurality of storage units, each of which corresponds to a logical memory space of the memory device, and the logical memory space may cover one or more consecutive logical block addresses (LBAs).

[0045] In addition, according to the first embodiment of the present invention, the information of the data to be backed up can be represented by a plurality of bits, each bit corresponds to a storage unit, and the memory controller 121 / 200 records the information of the data to be backed up by setting a value corresponding to the bit.

[0046] Figure 41 is a schematic diagram of a memory space mapping, which is used to show the correspondence between the predetermined memory space 400 for recording the information of the data to be backed up according to the first embodiment of the present invention and the memory space 450 of the memory device (e.g., the flash memory 123). According to the first embodiment of the present invention, the predetermined memory space 400 may include a plurality of storage units, such as the storage unit 410. In one embodiment of the present invention, each storage unit may be a bit, and the plurality of storage units included in the predetermined memory space 400 may form a bit map for faithfully recording the information of the data to be backed up of the memory device.

[0047] According to the first embodiment of the present invention, each storage unit or each bit may represent a continuous logical storage space in the memory space of the memory device (e.g., the flash memory 123), such as the logical storage space 460 shown in the figure, wherein the size of a continuous logical storage space 460 may be set to, for example, 4 kilo (K) bytes (B), or the size of a logical area addressed by a logical area address (LBA). According to different system requirements, the size of a logical area may be 512 bytes, 1024 bytes, or 4K bytes.

[0048] According to an embodiment of the present invention, a storage unit may correspond to multiple logical addresses, and therefore, there is a one-to-many relationship between the storage unit and the logical address. In other words, in the embodiment of the present invention, the data recorded in the given memory space 400 is compressed data, and the memory controller 121 / 200 can completely record the information of the data to be backed up corresponding to the entire memory space of the memory device (e.g., the flash memory 123) using only a relatively small memory space.

[0049] For example, assuming that the memory controller 121 / 200 uses one bit to represent a 4K-byte memory space, and assuming that the overall capacity of the memory device (e.g., the memory space 450) is 256 Gigabytes (GB), the number of bits required to completely record the information of the data to be backed up corresponding to the entire memory space of the memory device is 256GB / 4KB=64 Mega (M) bits, which is equivalent to 8MB of memory space. In other words, the memory controller 121 / 200 can completely record the information of the data to be backed up corresponding to the 256GB memory space using only 8MB of memory space.

[0050] According to an embodiment of the present invention, the information of the data to be backed up may be set to a preset value or a preset state (or, may also be referred to as an initial value or initial state) when the memory device begins to be used (for example, when the memory device is initialized by the host device 110). For example, in the first embodiment of the present invention, the memory controller 121 / 200 may initially set the value corresponding to each storage unit or each bit to 0. Therefore, the preset value of the information of the data to be backed up recorded in the given memory space 400 may be a value of all zeros. Assuming that the given memory space 400 forms a bit image map, the preset value of the bit image map may be a pattern of all zeros. Afterwards, the processor 240 may update the information of the data to be backed up according to a plurality of instructions received from the host device.

[0051] According to one embodiment of the present invention, the instruction received by the processor 240 from the host device 110 may include a write instruction. The write instruction may include a starting logical region address and a length. In response to receiving the write instruction, the processor 240 selects or determines one or more bits to be updated according to the starting logical region address and the length, and sets the value corresponding to the bit to be updated to a predetermined value different from the aforementioned initial value or preset value, wherein the predetermined value is used to represent that the data is data to be backed up (or data updated by the user). Alternatively, in another embodiment of the present invention, in response to receiving the write instruction, the processor 240 calculates the area range that needs to be marked in response to the current write operation in the predetermined memory space according to the starting logical region address and the length, and marks the area range as a predetermined state that is different from the aforementioned initial state or preset state and can represent that the data has been updated, so as to indicate that the data currently associated with the memory space corresponding to the area range in the memory device is data to be backed up.

[0052] For example, assuming that the length of the data to be written by the write instruction is 128KB, and one bit in the bit map represents 4KB of memory space, then in response to the write instruction, the number of bits to be updated is 128KB / 4KB=32 bits. The processor 240 can determine which bits in the bit map need to be updated according to the starting logical area address and the length of the data to be written, and set the values ​​corresponding to these bits to the predetermined values.

[0053] It is worth noting that according to the first embodiment of the present invention, the implementation method of updating the information of the data to be backed up according to the instruction received from the host device 110 may include at least the following two methods. Method 1: After determining which bits in the bit map or which area range in the predetermined memory space need to be updated, the processor 240 reads the content of the predetermined memory space 400 to know which value or state these bits or area ranges are currently set to, and sets the bits that are not currently set to the corresponding values ​​to the corresponding values, or marks the area that is not currently marked as the corresponding state to the corresponding state. For example, assuming that the processor 240 determines that the bits that need to be updated in response to a write instruction are bits 1 to 8 in the map, and through reading the content of the predetermined memory space 400, it is known that the values ​​currently corresponding to these bits are 11110011, where the value 0 is the default value and the value 1 represents that the corresponding data is data to be backed up, the processor 240 only needs to modify or mark the values ​​of bits 5 to 6 to 1. Method 2: After the processor 240 determines which bits in the bit map or which area range in the given memory space need to be updated, it directly sets these bits to corresponding values, or directly marks this area range as a corresponding state. Continuing with the previous example, assuming that the processor 240 determines that the bits to be updated in response to a write instruction are bits 1 to 8, it directly sets or marks the values ​​corresponding to bits 1 to 8 to 1, without caring about which values ​​bits 1 to 8 were previously set to.

[0054] According to one embodiment of the present invention, the instruction received by the processor 240 from the host device 110 may include a delete instruction. The delete instruction may include a starting logical area address and a length. In response to the receipt of the delete or modify instruction, the processor 240 selects or determines one or more bits to be updated according to the starting logical area address and the length, and sets the value corresponding to the bit to be updated to another value different from the aforementioned predetermined value, for example, setting it back to the aforementioned initial value or preset value to represent that the data has been deleted or the data is not the data to be backed up. Alternatively, in another embodiment of the present invention, in response to the receipt of the delete instruction, the processor 240 calculates the area range that needs to be marked in response to the current deletion operation in the established memory space according to the starting logical area address and the length, and marks this area range as a state that can represent that the data has been deleted or the data is not to be backed up.

[0055] It is worth noting that in one embodiment of the present invention, the processor 240 may update the information of the data to be backed up only according to the write instruction received from the host device. That is, the processor 240 will not update the information of the data to be backed up according to the delete instruction or the data delete operation of the memory device. In another embodiment, the processor 240 may update the information of the data to be backed up according to the write instruction and the delete instruction received from the host device. As described above, the processor 240 may mark the corresponding bit or area range as a value or state that may represent that the data has been deleted or the data is not to be backed up in response to the delete operation. In another embodiment, each storage unit may include multiple bits to record multiple states. For example, in response to the write instruction, the processor 240 may set or mark the corresponding storage unit or area range in the established memory space as a first state, representing that the data is data to be backed up (or, data updated by the user). In response to the delete instruction, the processor 240 may decide to restore the corresponding storage unit or area range to a preset state or mark it as a second state according to the state currently set or marked by the corresponding storage unit or the corresponding area range. For example, if the corresponding storage unit or area range is currently set or marked as the first state, it means that the current deletion operation is to delete the data that has been updated but not backed up, and the processor 240 can restore the corresponding storage unit or area range to the default state. If the corresponding storage unit or area range is currently set or marked as the default state, it means that the current deletion operation is to delete the backed up data, and the processor 240 can set or mark the corresponding storage unit or area range as the second state to indicate that the subsequent backup operation can delete the corresponding data in response to the user's current operation.

[0056] According to the second embodiment of the present invention, the predetermined memory space can store multiple records, each record includes at least a first field and a second field, the first field is used to record the starting logical area address of the data to be updated, and the second field is used to record the length of the data to be updated. For example, in the second embodiment of the present invention, in response to receiving a write instruction, the processor 240 can add a new record, and record the starting logical area address of the write instruction in the first field of the record, and record the length in the second field of the record. The processor 240 can add a corresponding record to the predetermined memory space for each write instruction in the order of the time when the write instruction is received, so as to record the starting logical area address of the write operation and the length of the write operation.

[0057] In addition, as described above, in one embodiment of the present invention, the processor 240 may update the information of the data to be backed up only according to the write instruction received from the host device. That is, the processor 240 will not update the information of the data to be backed up according to the delete instruction or the data delete operation of the memory device. In another embodiment, the processor 240 may update the information of the data to be backed up according to the write instruction and the delete instruction received from the host device. For example, each record includes a first field, a second field and a third field, the first field is used to record the starting logical area address of the data to be updated, the second field is used to record the length of the data to be updated, and the third field is used to record the update method of the data. For example, when the corresponding instruction is a write instruction, the third field can be set to a value or a state representing that the update method is "write data", and when the corresponding instruction is a delete instruction, the third field can be set to another value or another state representing that the update method is "delete data".

[0058] In the second embodiment of the present invention, it is assumed that the size of the predetermined memory space used to record the information of the data to be backed up is 32MB, and the memory size occupied by each record is 8 bytes, of which 4 bytes are used to record the information of the first field, and 4 bytes are used to record the information of the second field. In the implementation method of only recording the write instruction, the 32MB memory space can be used to store 32MB / 8B=4M records, each record corresponding to a write instruction or a write operation. If the host device 110 generally has a write length of 128KB, the amount of data to be backed up that can be recorded in the predetermined memory space is 128KB*4M=512GB, which is a considerable amount of data for general users. In other words, whether in the first embodiment of the present invention or in the second embodiment of the present invention, the memory controller 121 / 200 can use only a relatively small memory space to completely record the information of the data to be backed up corresponding to the entire memory space of the memory device (e.g., the flash memory 123). In addition, in one embodiment of the present invention, the processor 240 can also determine whether the capacity of the predetermined memory space is about to be insufficient. For example, when the remaining capacity of the predetermined memory space is lower than a predetermined critical value, the processor 240 can determine that the capacity of the predetermined memory space is about to be insufficient. When the processor 240 determines that the capacity of the predetermined memory space is about to be insufficient, it means that the amount of data to be backed up has reached a certain level. The processor 240 can further notify the host device 110 to send a reminder message to inform the user to perform data backup as soon as possible.

[0059] According to an embodiment of the present invention, the instructions received by the processor 240 from the host device 110 may also include a data backup instruction. In response to receiving the data backup instruction, the processor 240 may provide the host device 110 with the information of the currently recorded data to be backed up through the host interface 210, so that the host device 110 or the aforementioned data backup software developed jointly with the memory controller 121 / 200 can correctly and quickly identify which logical memory spaces of the memory device are associated with data that needs to be backed up for this data backup.

[0060] Figure 5 1 is a schematic diagram showing a data backup operation according to an embodiment of the present invention. When performing a data backup operation, the system may have three devices, including a host device 510, and storage devices 520 and 530, wherein the storage device 520 may be an existing storage device in the system, and the storage device 530 may be a storage device for backup. The host device 510 may perform the data backup operation by executing the aforementioned software developed together with the memory controller 121 / 200 of the present invention.

[0061] First, the host device 510 may issue a data backup command to the existing storage device 520. In response to the data backup command, the processor 240 provides the information of the data to be backed up maintained by it to the host device 510. After obtaining the information of the data to be backed up, the host device 510 may read the area of ​​the data to be backed up in the storage device 520 according to the information. For example, the host device 510 may convert the corresponding logical memory space (for example, the starting logical area address and length) according to the index value of the bit set to a predetermined value or its location (or the area range marked as a predetermined state), and access the storage device 520 to read the data stored therein. Then, the host device 510 may write the data to be backed up to the storage device 530 in sequence according to the logical memory space originally corresponding to it in the storage device 520. For example, the host device 510 may start from the first storage unit, the first bit, the first area range or the first record stored in the predetermined memory space, and perform the backup operation in sequence according to the location of the data to be backed up indicated by it. The backup operation steps of reading the data to be backed up from the storage device 520 and writing the data to the storage device 530 can be repeatedly performed until all data marked as a predetermined value or a predetermined state are copied and written to the storage device 530, or all data to be backed up (including data to be deleted) have been backed up. Afterwards, the host device 510 can issue a backup completion instruction to the storage device 520. In response to the receipt of the backup completion instruction, in a first embodiment of the present invention, the processor 240 sets the information of the data to be backed up to a preset value or a preset state (or, the aforementioned initial value or initial state), or in a second embodiment of the present invention, the processor 240 can delete or clear all data recorded in the predetermined memory space. Figure 5 In the embodiment, the information of clearing the data to be backed up is used as a representative of the above embodiments. It is worth noting that Figure 5 It shows a simplified operation flow, wherein those skilled in the art can understand that each operation shown in the figure can be completed through one or more instructions and read / write / erase operations of the memory device.

[0062] In summary, the data processing method proposed in the present invention utilizes a memory controller to continuously record information about the data to be backed up of a memory device according to the latest access operation. Through the information about the data to be backed up, a host device or a specific data backup software can correctly identify which logical memory spaces of the memory device are associated with data to be backed up, and can quickly select the data to be backed up and write it into a new storage device. In this way, when data backup is required, only the information about the data to be backed up needs to be provided to the host device or the specific data backup software, so that data backup can be performed in a simple and efficient manner, and the problem that the hard disk backup software in the traditional technology must be considered during development for compatibility with different operating systems because it needs to parse the file system supported by the computer operating system to obtain file information can be effectively avoided.

[0063] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A memory controller coupled to a memory device, comprising: a host interface for receiving a plurality of commands from a host device; as well as A processor is coupled to the host interface and is used to record information about the data to be backed up of the memory device, wherein the information is used to indicate which logical memory spaces of the memory device are associated with data to be backed up. The processor configures a predetermined memory space to store the information, and the predetermined memory space includes multiple storage units. The processor updates the information according to the multiple instructions, wherein the information is represented by multiple bits, each bit corresponding to one of the multiple storage units. The processor records the information by setting a numerical value corresponding to the multiple bits, and wherein in response to receiving a data backup instruction, the processor also provides the information to the host device through the host interface.

2. The memory controller of claim 1, wherein the command comprises a backup completion command, and in response to receiving the backup completion command, the processor sets the information to a preset value. 3 . The memory controller as claimed in claim 1 , wherein each storage unit corresponds to a logical memory space of the memory device. 4 . The memory controller as claimed in claim 3 , wherein the logical memory space covers one or more consecutive logical region addresses.

5. The memory controller of claim 1 , wherein the plurality of instructions include a write instruction, the write instruction including a starting logical region address and a length, and in response to receiving the write instruction, the processor selects one or more of the bits according to the starting logical region address and the length, and sets the value corresponding to the one or more of the plurality of bits to a predetermined value.

6. A memory controller as described in claim 1, wherein the multiple instructions include a write instruction, the write instruction includes a starting logical area address and a length, and the information stored in the given memory space includes multiple records, each record includes a first field and a second field, and in response to receiving the write instruction, the processor records the starting logical area address in the first field and records the length in the second field.

7. A data processing method, comprising: Allocate a predetermined memory space for storing information of data to be backed up of a memory device, wherein the predetermined memory space includes a plurality of storage units, the information is used to indicate which logical memory spaces of the memory device are associated with data to be backed up, and the information is represented by a plurality of bits, each bit corresponding to one of the plurality of storage units; as well as The information is updated according to a plurality of instructions received from a host device, wherein the step of updating the information according to the plurality of instructions received from the host device further comprises: Record the information by setting a value corresponding to the plurality of bits; as well as In response to receipt of a data backup command, the information is provided to the host device via a host interface.

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