Cache memory management method and management system, and information processing device

By using the first and second high-speed cache memories in the information processing device, combined with multi-threading and offline processing techniques, the response generation process was optimized, solving the problem of increased communication and processing load and achieving more efficient response generation.

CN113449220BActive Publication Date: 2026-01-13CASIO COMPUTER CO LTD
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Patent Information

Application Number
CN202110300670.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-03-25
Filing Date
2021-03-22
Publication Date
2026-01-13
Estimated Expiration
2042-01-13

AI Technical Summary

Technical Problem

Existing technologies struggle to effectively reduce communication and processing loads when workloads increase, especially during numerical processing in network services, leading to latency and inefficiency.

Method used

The information processing device is equipped with a first and a second high-speed buffer memory, which are used to store the correspondence between requests and responses and the input data and execution results of the processing, respectively. The response generation process is optimized through multi-threaded processing and offline processing technology.

Benefits of technology

By reducing communication time and local processing, the efficiency of response generation is improved, latency is reduced, and processing load is lowered.

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Abstract

The present application provides a cache management method and system for efficiently processing using a cache, and an information processing device. The information processing device, in a case where a first cache (112) does not hold a correspondence between a request and a response corresponding to the request, executes a plurality of processes for generating the response corresponding to the request; holds the response generated based on the execution results of the plurality of processes in the first cache (112) in correspondence with the request; holds the execution results of the processes in a second cache (113) in correspondence with input data of each of the plurality of processes; and transmits the response back to the request.
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Description

TECHNICAL FIELD

[0001] The present application relates to a cache memory management method, a cache memory management system, and an information processing apparatus. BACKGROUND

[0002] A cache memory is used for processing speedup. For example, by saving data or the like that has been used once as a cache, if the same data is used again thereafter, processing can be performed at high speed. For example, in a Web browser, a Web page that has been viewed once and an image used by the Web page are saved in a storage device as a cache. Thus, if the same Web page is displayed again thereafter, even if data is not acquired by communicating with a server again, the data can be read from the cache memory, so display can be speeded up.

[0003] Further, in relation to the use of a cache memory, a related technology is known in which a response is made without communicating with a server even in an offline state (for example, Japanese Patent Application Laid-Open No. 2011-164749).

[0004] However, in recent years, with the development of technology, various network services are provided, and in correspondence therewith, communication load and processing load increase. Therefore, it is desirable to provide further technology that can reduce communication load and processing load. SUMMARY

[0005] An object of the present application is to provide technology for making processing efficient using a cache memory.

[0006] An information processing method according to one aspect of the present application, in a case where a first cache memory does not have a correspondence relationship between a request and a response corresponding to the request, executes a plurality of processes for generating the response corresponding to the request; saves the response generated based on the execution results of the plurality of processes in the first cache memory in correspondence with the request; saves the execution results of the processes in a second cache memory in correspondence with input data of each of the plurality of processes; and returns the response for the request.

[0007] According to the present application, technology for making processing efficient using a cache memory can be provided.

[0008] Further features of the present application will become apparent from the following description of exemplary embodiments (with reference to the attached drawings). BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a diagram illustrating a cache memory management system according to an embodiment.

[0010] Figure 2This is a diagram illustrating the block structure of an information processing apparatus according to an embodiment.

[0011] Figure 3 This is a diagram illustrating the operation flow of an information processing apparatus performing a processing procedure in response to a request, according to an embodiment of the invention.

[0012] Figure 4A and Figure 4B This is a diagram illustrating the thread that processes the generation of a response corresponding to a request in accordance with the implementation method.

[0013] Figure 5 This is a diagram illustrating the process of generating a response.

[0014] Figure 6 This is a diagram illustrating the first cache memory.

[0015] Figure 7A and Figure 7B This is a diagram illustrating requests and responses registered in the first cache memory.

[0016] Figure 8 This is a diagram illustrating the second cache memory.

[0017] Figure 9 This is a diagram illustrating the process flow of generating a response in an embodiment.

[0018] Figure 10 This is a diagram illustrating the action flow of the sub-thread in an implementation method for generating a response.

[0019] Figure 11 It is a diagram illustrating the process flow corresponding to the input data.

[0020] Figure 12 This is a diagram illustrating the use of cache memory at different granularities in various implementation methods.

[0021] Figure 13 This is a diagram illustrating the hardware structure of a computer for implementing an information processing device according to an embodiment. Detailed Implementation

[0022] Hereinafter, several embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, corresponding elements are assigned the same reference numerals in the various drawings.

[0023] For example, if the request and the response to that request are stored as a cache, then when the same request is received again, the response stored in the cache can be read and used without performing the processing again, thus enabling high-speed processing.

[0024] Furthermore, sometimes it is possible to use a portion of the execution results of multiple processes performed to generate a response to a request for the generation of a response to another request. In this case, if the execution results of the multiple processes performed to generate the response are not cached, they cannot be used by other processes.

[0025] Therefore, in the embodiments described below, for multiple processes performed to generate a response to a request, the input data and execution results of each process are stored in a cache memory. Thus, for example, when another request is received, if the processes performed to generate a response to that other request include processes corresponding to the cached processes, the cached execution results can be used to speed up the processing.

[0026] Furthermore, as an example of a situation where the execution result of a process performed to generate a response to a request can be appropriated by other processes, one could cite a process whose execution result is always the same if the processes are identical. An example of such a process is numerical processing. Numerical processing includes, for example, processes that output the results of numerical operations, processes that plot numerical expressions graphically, processes that calculate tangents to logarithmic expressions and graphs, and processes that derive equations from groups of data points or calculate statistical values ​​such as averages or variances.

[0027] In recent years, terminals such as function calculators have been provided that perform numerical processing based on user input requests and display the results on a screen. Furthermore, services have been provided that allow terminals to access servers via web browsers, and if a numerical processing request is sent to the server, display the corresponding graph in the browser's display area as a response. However, for example, when performing numerical processing on a terminal, the processing load is high, and processing delays may occur. Furthermore, for example, when performing numerical processing via a browser or other means that a server performs the processing, the processing load is also high, resulting in delays, or delays may occur due to communication time between the terminal and the server. Therefore, there is a need to provide further technologies that can reduce the processing and communication loads of numerical processing.

[0028] Furthermore, in such algebraic processing, there is a characteristic that the result of operations on the same algebraic expression is the same. For example, even if the operations are on different algebraic expressions but a part of the expressions is the same, the result is the same for that consistent part. Therefore, even if requests are processed on different algebraic expressions, if there is a common part in the expressions, the result of one request can be used to perform the operation on another request within that part. However, if requests are simply cached in relation to responses to those requests, the cache may not be hit when different requests are received, so even if a part of the processing result can be used, caching cannot speed up the processing. An example is given below.

[0029] For example, suppose we receive y = x 2 The request to plot the expression +1 graphically. In this case, assume simply plotting y = x 2 A request to plot +1 as a graphic will cache the response accordingly, including the coordinate values ​​representing the shape of the graphic. In this case, even if a subsequent request to plot y = x is received... 2 +20 Other requests to plot as a graph, due to the relationship between y = x 2 The request for +1, which is a different graphic, did not hit the cache and therefore could not utilize the cache.

[0030] However, in y=x 2 +1 and y = x 2 In +20, x 2 The results of some operations are the same. Therefore, for example, if we represent x... 2 If the coordinate values ​​of part of the graphic's shape are saved in a cache memory, then when y = x is received later... 2 In cases where +20 is plotted as a graphic, x can also be used. 2 Partial coordinate values. Therefore, it is possible to reduce the description of y=x 2 Processing time for +20 graphics.

[0031] Furthermore, while this explanation uses numerical processing as an example, the implementation method is not limited to numerical processing. In other implementations, the method can also be applied to other processing methods such as processing strings like text or processing images. In this case, the implementation method can be applied, for example, by storing the request for processing strings or images and its response in the first cache memory 112, and storing the input data for processing strings or images and the execution results of the processing in the second cache memory 113 for each of the multiple processes executed to generate the response. The implementation method will be described in more detail below.

[0032] Figure 1 This is a diagram illustrating a cache memory management system 100 according to an embodiment. For example, in Figure 1 In this system, the cache management system 100 includes an information processing device 101 and a service providing server 102. Alternatively, the service providing server 102 may be, for example, a computer acting as a server. In other embodiments, the service providing server 102 may also be composed of multiple servers. Furthermore, in... Figure 1 In this context, the information processing device 101 may also communicate with the service provider server 102 via the browser 111 to receive services regarding numerical processing from the service provider server 102.

[0033] Information processing device 101 may be, for example, a computer such as a personal computer (PC), mobile PC, tablet computer, smartphone, or mobile phone. Information processing device 101 includes a first cache 112 that stores requests and responses corresponding to those requests, and a second cache 113 that stores input data and execution results of multiple processes performed to generate responses to requests. Furthermore, information processing device 101 may connect to service provider server 102 via network 105, such as the public telephone network or the Internet. For example, if information processing device 101 receives a request from a user via browser 111 for formula processing, such as the depiction of a formula-corresponding graphic, it sends a request to service provider server 102.

[0034] If the service provider server 102 receives a request from the information processing device 101, it refers to the third cache memory 131 to check whether a response to the request is registered in the cache memory. If a response to the request is registered in the cache memory, the service provider server 102 provides the response to the information processing device 101. On the other hand, if a response to the request is not registered in the cache memory, the service provider server 102 uses the number processing module 141 to perform multiple processes to generate a response to the request, generates a response based on the obtained calculation results, and sends it back to the information processing device 101. Furthermore, the number processing module 141 may be, for example, software that uses a computer to perform symbolic processing of numbers. An example of the number processing module 141 is a number processing system such as a CAS (Computer Algebra system).

[0035] Furthermore, the service provider server 102 registers the generated responses corresponding to the requests in the third cache memory 131. Therefore, when the same request is received subsequently, a response can be retrieved from the third cache memory 131, enabling the service provider server 102 to provide responses at high speed.

[0036] Information processing device 101, for example, can cause the browser's display area to display formulas, graphics, etc., corresponding to the request based on the received response.

[0037] However, as described above, when a request is sent to the service provider server 102 and a response corresponding to the request is obtained in the cloud, delays may occur in the depiction of graphs based on the response due to communication time between the information processing device 101 and the service provider server 102. Therefore, in this embodiment, the information processing device 101 attempts to obtain a response corresponding to the request locally. The processing performed by the information processing device 101 will be described in more detail below.

[0038] Figure 2 This is a block diagram illustrating the structure of an information processing apparatus 101 according to an embodiment. The information processing apparatus 101 includes, for example, a control unit 201, a storage unit 202, a communication unit 203, and a display unit 204. The control unit 201 can control each part of the information processing apparatus 101. In this embodiment, the control unit 201 includes a browser 111, a number processing module 212, and a processing module 213. For example, the number processing module 212 may be software that uses a computer to symbolically process numbers; in one example, it is a number processing system such as CAS. The processing module 213, for example, performs processing to control the reading and writing of information to the first cache memory 112 and the second cache memory 113. The processing module 213 includes, for example, an execution unit 231, a first storage unit 232, a second storage unit 233, and a return unit 234, and may also include other functional units. The storage unit 202 includes, for example, the first cache memory 112 and the second cache memory 113. The communication unit 203 communicates with other devices, for example, according to the instructions of the control unit 201. For example, the communication unit 203 may communicate with the service provider server 102. The display unit 204 may be a display device such as a monitor, and displays information according to the instructions of the control unit 201. Details regarding these units and the information stored in the storage unit 202 will be described later.

[0039] Figure 3 This is a diagram illustrating the operation flow of the control unit 201 of the information processing apparatus 101 in accordance with an embodiment, performing processing in response to a request. For example, if a user inputs a request via browser 111, the control unit 201 begins... Figure 3 The action flow.

[0040] In step 301 (hereafter referred to as "S", for example, S301), the control unit 201 of the information processing device 101 determines whether the environment is online. For example, if communication by the communication unit 203 is offline due to poor radio wave conditions from a base station used for connecting to the public telephone network or poor connection conditions to the Internet, the control unit 201 may determine "no" in S301, and the process proceeds to S302.

[0041] In S302, the control unit 201 determines whether offline processing is possible. For example, the control unit 201 may determine whether offline processing is possible based on whether the modules and programs required to generate a response corresponding to the request are stored in the storage unit 202. In the case where multiple processes are performed using WebAssembly to generate a response, in S302, the control unit 201 may, in one example, determine whether offline processing is possible by determining whether the browser 111 corresponds to WebAssembly. Furthermore, depending on the installation of the cache management system 100, there are also cases where the service provider server 102 is configured to handle requests for a given request. As an example, for some numerical processing, due to high processing load or the use of special modules, it may be considered to configure the service provider server 102 to handle the request. In such cases, upon receiving the given request, the control unit 201 determines the processing in S302 as "No".

[0042] If offline processing cannot be performed in S302 (S302 is "No"), the process proceeds to S304. In this case, since online connection is not possible and offline processing cannot be performed, the control unit 201 can notify an error, and this operation process ends.

[0043] On the other hand, if it is determined in S302 that offline processing can be performed (S302 is "Yes"), the process proceeds to S303. In S303, the control unit 201 performs processing to generate a response corresponding to the request. For details regarding the response generation process, please refer to... Figure 9 This will be described later. Furthermore, in S305, the control unit 201 will output a response, and the current operation will end.

[0044] Furthermore, if in S301 the environment is online and can be connected to network 105, the control unit 201 determines "yes," and the process proceeds to S306. In S306, the control unit 201 determines whether offline processing can be performed. Additionally, in S306, the control unit 201 can determine whether offline processing can be performed, for example, through the same process as in S302. As described above, if a response corresponding to a request is to be obtained online from the service provider server 102, delays may sometimes occur during processing due to communication time with the service provider server 102. Therefore, if offline processing is possible (S306 is "yes"), the process can proceed to S307 to advance offline processing.

[0045] In S307, the control unit 201 performs the process of generating a response corresponding to the request. The same process as in S303 can be performed in S307. For details regarding the response generation process, please refer to the above. Figure 9 To be described later.

[0046] In S308, the control unit 201 determines whether the response generated in response to the request contains an error. An error could be, for example, a processing crash or a timeout. If the response does not contain an error (S308 is "No"), the process proceeds to S305, and the control unit 201 outputs the obtained response.

[0047] On the other hand, if the response in S308 contains an error, for example, if an error occurred in the processing to obtain the response corresponding to the request and a correct response has not yet been obtained, then by having the service provider server 102 perform the processing to generate the response corresponding to the request, it is possible to successfully generate the response. Therefore, the control unit 201 determines "yes" in S308, and the process proceeds to S309. Furthermore, if offline processing cannot be performed in S306 (S306 is "no"), then in an online environment, the generation of the response can be delegated to the service provider server 102, so the process proceeds to S309.

[0048] In S309, the control unit 201 sends a request to the service providing server 102. If the service providing server 102 receives the request, it proceeds as described in [reference needed]. Figure 1 As exemplified, processing is performed with reference to the third cache memory 131 and / or the enable processing module 141, etc., to generate a response corresponding to the request and send it back to the information processing device 101.

[0049] In S310, the control unit 201 receives a response from the service provider server 102. In S311, the control unit 201 records the request sent to the service provider server 102 and the response received from the service provider server 102 in the first cache memory 112 accordingly. Details regarding the first cache memory 112 will be described later. Therefore, in the event that a request that might return an error is received again during offline processing, a normal response can be sent back while avoiding the possibility of errors in offline processing and communication delays. Furthermore, in S311, for example, if the request sent to the service provider server 102 includes a random function or a shuffle function whose result changes each time it is executed, the control unit 201 may not perform the registration in the first cache memory 112. Additionally, for example, in S311, if the response received by the control unit 201 from the service provider server 102 includes a response containing errors such as processing crashes or timeouts, the registration in the first cache memory 112 may also not be performed. If the processing in S311 is completed, the process proceeds to S305. In this case, in S305, the control unit 201 outputs the response received from the service provider server 102, and this operation process ends.

[0050] As mentioned above, according to Figure 3 The process flow, when a request is input, can appropriately assign whether the information processing device 101 or the service provider server 102 is responsible for generating the response to the request.

[0051] In addition, Figure 3 In the workflow, for example, if the generation of the response corresponding to the request can be performed offline, the processing can be performed offline. This reduces communication between the information processing device 101 and the service providing server 102, thus reducing delays caused by communication time.

[0052] Furthermore, in an online environment, if offline processing is not possible or an error occurs during offline processing, the control unit 201 sends a request to the service provider server 102. Thus, if a response cannot be generated during offline processing, the generation of a response corresponding to the request can be performed in the cloud. Additionally, in the above... Figure 3In the case where an error is determined in S308 during the processing, the request processing is delegated to the service providing server 102, but the implementation is not limited to this. For example, in other implementations, the processing of generating a response corresponding to the request can be performed locally in S307, and the processing in S309 can be performed in parallel to delegate the provision of the response corresponding to the request to the service providing server 102. Thus, compared to the case where an error occurs during local processing and a request is sent to the service providing server 102, the response can be received at a earlier time. Furthermore, in this case, as long as the received response is not erroneous, the request and the received response can be stored in the first cache memory accordingly.

[0053] Furthermore, since an error is notified to the user when the response cannot be generated offline in an offline environment, the user is aware that a response corresponding to the request cannot be generated.

[0054] Next, the processing of generating the response corresponding to the request in S303 and S307 will be explained. Furthermore, in this embodiment, the processing of generating the response corresponding to the request can be multithreaded using a main thread 401 installed by JavaScript and a child thread 402 installed using WebWorker.

[0055] Figure 4 is a diagram illustrating the thread for processing the generation of a response corresponding to a request in an implementation method. Figure 4A This example illustrates the scenario of generating a response using a single thread, which could be installed using JavaScript, for example. However, in this case, because the processing for generating the response and other processes, such as drawing the graphics on the browser's display area, are executed sequentially within a single thread, subsequent processing will not begin until the preceding processing is complete, potentially causing delays in drawing.

[0056] Therefore, in one embodiment, such as Figure 4B As shown, in addition to the main thread 401, at least one child thread 402 is installed to perform the processing of generating the response. Child thread 402 can be generated, for example, using the WebWorker API. Child thread 402 has its own caching mechanism and can exchange information with the main thread 401 through message events (asynchronously). Figure 4BAs shown, by multithreading, the main thread 401 enables the child thread 402 to generate responses, and other processes such as drawing can be performed without waiting for the result of the response generation process of the child thread 402. Therefore, it is possible to suppress delays in other processes such as drawing caused by the response generation process. In addition, in one embodiment, the child thread 402 may refer to the cache memory allocated to its own thread, but not to the cache memory allocated to other child threads 402. Depending on the environment, there may be cases where child threads 402 installed using WebWorker cannot refer to the cache memory. Therefore, by configuring the child thread 402 not to refer to the cache memory of other child threads 402, the implementation can be applied to such a wide range of environments.

[0057] In addition, in S303 and S307, the control unit 201 can, for example, use the API (Application Programming Interface) to call the main thread 401 installed with JavaScript to perform the processing of generating responses.

[0058] The following describes the process of generating the response executed by the main thread 401 and the child thread 402. Figure 5 This is a diagram illustrating the process of generating a response. For example, if the main thread 401 is called during the processing of S303 or S307 above... Figure 5 (1)), then the main thread 401 checks whether the response corresponding to the request is stored in the first high-speed cache memory 112. Figure 5 (2)).

[0059] Figure 6 This is a diagram illustrating the first cache memory 112. Figure 6 In the example shown, the cache key and the corresponding value are registered in the first cache memory 112. In the first cache memory 112, a request is registered in the cache key, and a response corresponding to the request is registered in the value. Alternatively, the request itself may be registered in the cache key of the first cache memory 112, but in other embodiments, for example, a value obtained by performing a prescribed process such as hash function processing on the request may also be registered.

[0060] Furthermore, Figure 7 is a diagram illustrating the correspondence between requests and responses registered in the first cache memory. Figure 7A The request is illustrated in the example. Figure 7B The example below illustrates the response corresponding to the request. Additionally, in one instance, both the request and response can be data in JSON (JavaScript Object Notation) format. Figure 7AThis example illustrates a request to depict a graphic on a browser's display screen, including the information needed in the processing required to depict the graphic. For instance, in... Figure 7A The request includes an identifier to identify the request, a graphical representation of the requested figure, and a range specification for the figure's extent. Furthermore, the request includes various settings regarding the processing of the figure. These settings may include options for specifying whether angles are measured in radians, degrees, or grades, rounding to a certain decimal place, and whether complex numbers are valid. Additionally, the request includes information specifying the drawing range of the figure. For example, in Figure 7, the maximum and minimum values ​​of the range, and the step size of the plotting points, are specified for the X and Y axes, respectively, as the drawing range.

[0061] Figure 7B This example illustrates a response that includes the information needed to depict the graphic corresponding to the request. For instance, in... Figure 7B The response includes information about the graphic and a list of coordinate points of the graphic. The information about the graphic includes, for example, the type of the graphic and information indicating whether errors occurred during the multiple processes performed to generate the response. Furthermore, the list of coordinate points of the graphic includes, for example, information about the coordinates of each point in the graphic. In the first cache memory 112, such requests and responses can be stored correspondingly.

[0062] Furthermore, in Figure 5 In (2), if the main thread 401 has a response corresponding to the request stored in the first cache memory 112, it reads the response corresponding to the request stored in the first cache memory 112 and sends the response back to the calling source browser 111. Figure 5 (3)).

[0063] On the other hand, if the response corresponding to the request is not stored in the first cache memory 112, the main thread 401 delegates the processing of the request to the processing module 213 of the child thread 402. Figure 5 (4)).

[0064] If the processing module 213 of sub-thread 402 receives a request, it executes multiple processes to generate a response corresponding to the request, while referring to the second cache memory 113 or delegating processing to the expression processing module 212. Figure 5 (5)). Furthermore, in the multiple processes used to generate the response, the processing module 213 can use the information contained in the request to perform multiple processes such as formula determination, formula type determination, graphic point calculation, etc. More details about these exemplary processes will be described later.

[0065] Furthermore, when the processing module 213 executes multiple processes for generating a response, if the execution result of a process is stored in the second cache memory 113, it uses that execution result to proceed to the next process in the multiple processes. On the other hand, if the execution result of a process is not stored in the second cache memory 113, it delegates the processing to the number processing module 212 to obtain the execution result. Additionally, when delegating processing to the number processing module 212, the processing module 213 can register a set of the input data and execution result of that process in the second cache memory 113. Figure 5 (6)).

[0066] Figure 8 This is a diagram illustrating a second cache memory 113. In the second cache memory 113, cache keys and values ​​are registered correspondingly, for example. A cache key may be input data input during each of a plurality of processes executed to generate a response. Input data may include, for example, a portion of information read from a request, the execution result of the first of the plurality of processes executed, information generated based on these, etc. Furthermore, a value may be the result of that process. Additionally, the input data of the process itself may also be registered in the cache keys of the second cache memory 113, but in other embodiments, for example, values ​​obtained by performing a predetermined process on the input data, such as a process using a hash function, may also be registered.

[0067] Next, the processing module 213 of sub-thread 402 generates a response corresponding to the request based on the execution results of multiple processes, and sends it back to the main thread 401. Figure 5 (7)). If the main thread 401 receives a response from the child thread 402, it saves the request and response accordingly in the first cache memory 112. Figure 5 (8)). Furthermore, the main thread 401 sends the response received from the child thread 402 back to the calling browser 111 as a response to the request. Figure 5 (9)), hence Figure 3 Once the processing of S303 or S307 is complete, proceed to the next process.

[0068] In addition, multiple child threads 402 can be installed to execute the response. The main thread 401 can, for example, add requests to a task queue, so that the idle child threads 402 among the multiple child threads 402 can process the requests in turn.

[0069] As above Figure 5As described in the response generation process, the first cache memory 112 stores the request and the corresponding response accordingly. On the other hand, the second cache memory 113 stores the input data of each of the multiple processes executed to generate the response corresponding to the request, along with the execution result of that process.

[0070] Furthermore, in the main thread 401, when the control unit 201 receives a request, it checks whether the request is registered in the first cache memory 112. If it is registered, it retrieves the response corresponding to the request from the first cache memory 112 and sends it back to the browser 111. Therefore, when processing the same request in the past, the processing can be accelerated by using the first cache memory 112.

[0071] Furthermore, the control unit 201, which operates as processing module 213 in sub-thread 402, checks whether a process is registered in the second cache memory 113 when executing multiple processes for generating responses corresponding to requests. If a process is registered in the second cache memory 113, the control unit 201 retrieves the result of the process from the second cache memory 113 and proceeds to the next process. Therefore, for example, if a portion of the multiple processes executed for a received request was executed in the past when processing other requests, the second cache memory 113 can be used to speed up the processing.

[0072] Furthermore, as described above, in the expression processing, the processing module 213 uses the information contained in the request to delegate multiple processes, such as expression determination, expression type determination, and graphic point calculation, to the expression processing module 212 while performing the processing. Moreover, the execution results of these multiple processes can be registered in the second cache memory 113 corresponding to the input data of these multiple processes. Hereinafter, examples of these multiple processes will be briefly described.

[0073] (1) Numerical determination and processing

[0074] In the equation determination, processing module 213, for example, determines whether the graphical form specified by the request is an equation. For example, processing module 213 receives... Figure 7A In the case of a request, the request can be read in graphical form: y = sin(x), and it can be checked whether y = sin(x) is an equation. For example, when the user inputs an equation for a graphical object, there may also be cases where the user inputs a string that cannot be graphically represented. In this case, the processing module 213 can determine that it is an error in the expression determination. Examples of strings that cannot be graphically represented include constant terms such as "3", variable terms such as "y", and errors in the notation of equations (=) or inequalities.

[0075] Furthermore, since y = sin(x) is an equation, the result of the above numerical determination is that... Figure 8 The first segment of the second cache memory 113 records the input data: y = sin(x) and the "equation" that serves as its result.

[0076] (2) Determination and processing of numerical expression type

[0077] In determining the type of the expression, processing module 213 determines which type of graph the form "y = sin(x)" belongs to, for example, the orthogonal coordinate system type y = f(x) or x = f(y), the polar coordinate system type r = f(θ), etc. If the left side of the graph specified by the request is y and the right side is an expression that does not contain independent variables other than x, it is determined to be the orthogonal coordinate system type y = f(x). Furthermore, if the left side of the graph is x and the right side is an expression that does not contain independent variables other than y, it is determined to be the orthogonal coordinate system type x = f(y). Moreover, if the left side is r and the right side is an expression that does not contain independent variables other than θ, it is determined to be the polar coordinate system type r = f(θ).

[0078] Furthermore, here y = sin(x) is of the type y = f(x) in an orthogonal coordinate system, so the result of the above determination of the expression type is that... Figure 8 The second segment of the second cache memory 113 records the input data: y = sin(x) and the "y = f(x) type" as its determination result.

[0079] For example, as described above, processing module 213 can determine the type of graph. Furthermore, the input data and execution results of processes 1 to 3 described in the above formula type determination are registered in... Figure 8 The record is in the second segment of the second cache memory 113.

[0080] (3) Graphic point calculation and processing

[0081] In the calculation of graphic points, processing module 213 calculates the coordinate values ​​of graphic points contained within the depicted area, based on the requested graphic form. For example, in Figure 7A The request specifies the graphical form: y = sin(x), and specifies the range of the graph as Xmin: -7.5, Xmax: 7.5, Xstep: 0.1, Ymin: -7.5, Ymax: 7.5, Ystep: 0.1. The control unit 201 can calculate the coordinates of graphical points within the specified range during graphical point calculation. Figure 8The third entry of the second cache memory 113 contains records corresponding to the calculation of graphic points. These records include, as input data, the graphic form y = sin(x), its depicted range, and as values, the coordinates of each point as the result of the processing.

[0082] For example, as shown in (1) to (3) above, the control unit 201 can execute multiple processes for generating a response corresponding to a request, and register the execution result of the process in the second cache memory 113 corresponding to the input data of the process. Furthermore, the multiple processes for generating the response described above are illustrative, and the implementation is not limited to them. For example, according to the implementation, some of the multiple processes described above may not be executed, or further processes may be executed separately.

[0083] Next, the action flow for the response generation and processing described above will be explained below.

[0084] Figure 9 This is a diagram illustrating the operation flow of the response generation process executed by the control unit 201, which is the main thread 401, in the relevant implementation. For example, if proceeding to S303 or S307, the control unit 201 can send a response via an API, etc. Figure 9 The process is called and executed.

[0085] In S901, the control unit 201, which operates as the main thread 401, generates a cache key for retrieving data from the first cache memory 112. For example, if a past request is registered in the cache key of the first cache memory 112, the control unit 201 can use the request as the cache key. Furthermore, if a value obtained by performing a predetermined process such as hash function processing is registered in the cache key of the first cache memory 112, the control unit 201 can perform the same processing on the request to generate a cache key.

[0086] In S902, the control unit 201 uses the generated cache key to search the first cache memory 112 and determines whether a record corresponding to the request is registered in the first cache memory 112. If no record corresponding to the request is registered in the first cache memory 112 (S902 is "No"), the process proceeds to S906. On the other hand, if a record corresponding to the request is registered in the first cache memory 112 (S902 is "Yes"), the process proceeds to S903.

[0087] In S903, the control unit 201 determines whether the request is an NG request that meets the specified conditions. An NG request could be, for example, a request whose response changes each time it is executed. This is because, for example, if the response changes each time it is executed, even if the same request is registered in the first cache memory 112, the content of the registered response and the response to this request may differ, and the cached value cannot be reused. Furthermore, examples of requests whose results change each time they are executed include requests involving random functions, shuffling functions, etc.

[0088] If the request in S903 is an NG request that does not meet the specified conditions (S903 is "No"), the process proceeds to S904. In S904, the control unit 201 retrieves the response corresponding to the request from the first cache memory 112, and in S905, it sends back the processing response of the calling source in S303 or S307, and this operation process ends.

[0089] On the other hand, if the request in S903 is NG (S903 is "Yes"), the process proceeds to S906. In S906, the control unit 201 delegates the execution of the request to the sub-thread 402. For example, the control unit 201 can register the requested task in the task queue, causing the sub-thread 402 to execute the processing corresponding to the request.

[0090] In S907, the control unit 201 receives a response from the sub-thread 402. In S908, the control unit 201 determines whether the response is an NG response that meets the specified conditions. An NG response that meets the specified conditions could be, for example, an error response indicating that a correct response to the request has not been generated. Error responses include, for example, processing crashes, timeout errors, etc. If the response is an NG response ("Yes" in S908), the process proceeds to S905, where the control unit 201 can send the response determined to be an NG response back to the processing of the calling source in S303 or S307. Alternatively, if an NG response is sent back in S307, it can be determined to be an error in S308, and a request can be sent to the service provider server 102 in the processing of S309. Thus, the service provider server 102 can handle the processing, increasing the likelihood of obtaining a correct response to the request.

[0091] On the other hand, if the response in S908 is not an NG response (S908 is "No"), the process proceeds to S909. In S909, the control unit 201 registers the request and response correspondingly in the first cache memory 112, the process proceeds to S905, and the response is sent back to the processing of the calling source in S303 or S307, and this operation process ends.

[0092] Based on the above,Figure 9 In the main thread 401, if the control unit 201 has a response corresponding to the request registered in the first high-speed cache memory 112, it can send back the response. Therefore, it is possible to send back the response to the request at high speed.

[0093] In addition, according to Figure 9 In the main thread 401, when the control unit 201 generates a response corresponding to the request from the sub-thread 402, it saves the response received from the sub-thread 402 to the first cache memory 112. Therefore, when the same request is received again, it can be processed quickly using the response stored in the first cache memory 112.

[0094] In addition, during the processing of S909, if the request is an NG request including a random function, a shuffling function, etc., the control unit 201 may not store the request and response in the first cache memory 112.

[0095] Next, the process of generating a response corresponding to the request, performed by the control unit 201 as a sub-thread 402, will be described. Figure 10 This is a diagram illustrating the action flow of the process performed to generate a response corresponding to a request in accordance with an embodiment. In sub-thread 402, control unit 201 may, for example, begin if a task is assigned from a task queue that has registered tasks corresponding to the request. Figure 10 The action flow.

[0096] In S1001, the control unit 201, which is the action of sub-thread 402, generates input data to be used in processing based on the request of the assigned task. In one example, the control unit 201 may extract a portion of the information contained in the request (e.g., a graph) as input data.

[0097] In S1002, the control unit 201 processes the input data. Furthermore, the processing in S1002 to S1004 is repetitive. In S1002, the control unit 201 can sequentially execute a series of multiple processes for generating a response to a request, proceeding to the next process each time a process is repeated. For example, if it is numerical processing, the series of multiple processes may include numerical determination, numerical type determination, graphic point calculation, etc. In S1003, the control unit 201 determines whether the series of multiple processes for generating a response to a request has been completed. If the series of multiple processes for generating a response to a request has not been completed (S1003 is "No"), the process proceeds to S1004.

[0098] In S1004, the control unit 201 generates the next input data. For example, the control unit 201 may read other information from the request or generate the next input data using the execution result of the process in S1002. If the next input data is generated, the flow returns to S1002, and the control unit 201 can use the generated next input data to execute the next process in a series of multiple processes for generating a response.

[0099] Furthermore, if all the multiple processes in S1003 used to generate the response corresponding to the request are completed (S1003 is "Yes"), the process proceeds to S1005.

[0100] In S1005, the control unit 201 can generate a response based on the execution results of a series of multiple processes, append the generated response to the queue of registered processing results, and send the response back to the main thread 401.

[0101] Next, refer to Figure 11 The processing performed in S1002 is explained. Figure 11 This is a diagram illustrating the workflow of the processing corresponding to the input data performed in S1002. For example, if the processing proceeds to S1002, the control unit 201, which operates as sub-thread 402, can begin. Figure 11 The action flow.

[0102] In S1101, the control unit 201, which operates as sub-thread 402, generates a cache key for retrieving data from the second cache memory 113 based on the input data. For example, if past input data is already registered in the cache key of the second cache memory 113, the control unit 201 can use the input data as the cache key as is. Furthermore, if, for example, a value obtained by performing a predetermined process such as hash function processing is registered in the cache key of the second cache memory 113, the control unit 201 can perform the same processing on the input data to generate a cache key.

[0103] In S1102, the control unit 201 uses the generated cache key to search the second cache memory 113 and determines whether a record corresponding to the input data is registered in the second cache memory 113. If a record corresponding to the input data is registered in the second cache memory 113 (S1102 is "yes"), the process proceeds to S1103.

[0104] In S1103, the control unit 201 determines whether the input data specifies an NG process that satisfies the first condition. The input data specifying an NG process could be, for example, input data specifying a process whose result changes each time it is executed. This is because, for example, if the execution result changes each time the process is executed, even if a record corresponding to the same input data is registered in the second cache memory 113, the execution result of the same process may not be the same in the next execution, and the cached value cannot be reused. Furthermore, as examples of input data specifying a process whose result changes each time it is executed, input data specifying processes including random functions, shuffling functions, etc., can be given.

[0105] If the input data in S1103 does not specify NG processing that satisfies the first condition (S1103 is "No"), the process proceeds to S1104. In S1104, the control unit 201 retrieves the calculation result corresponding to the input data from the second cache memory 113, and in S1105, the calculation result is sent back to the processing of the calling source in S1002, and this operation process ends.

[0106] On the other hand, if no record corresponding to the input data is registered in the second cache memory 113 in S1102 (S1102 is "No"), and if the input data specifies NG processing in S1103 (S1103 is "Yes"), the process proceeds to S1106. In this case, since the execution result of the processing cannot be obtained from the second cache memory 113, in S1106, the control unit 201 delegates the processing corresponding to the input data to the numerical processing module 212. In addition, in the case of NG processing, by delegating the processing to the numerical processing module 212 in S1106, it is possible to avoid the situation where the execution result of the processing registered in the second cache memory 113 is used even though it is not allowed. Furthermore, the processing delegated to the numerical processing module 212 in S1106 can be determined based on the input data and the timing of which of the multiple processes in a series of processes for generating a response to the request was called. Figure 11 The processing methods differ. The processing delegated to the numerical processing module 212 can be, for example, numerical determination, numerical type determination, graphical point calculation, etc.

[0107] In S1107, the control unit 201 receives the execution result of the processing entrusted by the slave expression processing module 212. In S1108, the control unit 201 determines whether the execution result of the processing is an NG execution result that satisfies the second condition. An NG execution result that satisfies the second condition is, for example, a result that includes an error indicating that the calculation result of the input data was unsuccessful. Errors include, for example, processing crashes, timeout errors, etc. If the execution result of the processing is an NG execution result (S1108 is "yes"), in S1105, the NG execution result can be sent back to the processing of the calling source S1002. Thus, it is possible to avoid registering the execution result of the processing in the second cache memory 113 even though the execution result cannot be misappropriated in other processes.

[0108] On the other hand, if the execution result processed in S1108 is not an NG execution result (S1108 is "No"), the process proceeds to S1109. In S1109, the control unit 201 registers the input data and the processing execution result correspondingly in the second cache memory 113, the process proceeds to S1105, the processing execution result is sent back to the processing of the calling source S1002, and this operation process ends. In addition, in S1109, if the input data is NG processing including random functions, shuffling functions, etc., the control unit 201 may choose not to save the input data and execution result in the second cache memory 113.

[0109] Based on the above Figure 10 and Figure 11 In the operation flow, within sub-thread 402, control unit 201 executes a series of multiple processes to generate a response corresponding to the request. Furthermore, when executing the series of multiple processes, if the execution result of the process is registered in the second high-speed cache memory 113, the control unit 201 utilizes the execution result, thus enabling high-speed execution of the process.

[0110] On the other hand, if the execution result of a series of multiple processes is not registered in the second cache memory 113 during execution, the control unit 201 delegates processing to the number processing module 212, which saves the input data of the process and the execution result of the process into the second cache memory 113 accordingly. Therefore, when the same process is executed later, the execution result of the process stored in the second cache memory 113 can be used to execute the process at high speed.

[0111] Furthermore, according to the embodiments described above, data of different granularities are registered in the first cache memory 112 and the second cache memory 113. For example, in the above embodiments, the granularity of the information registered in the first cache memory 112 is larger than the granularity of the information registered in the second cache memory 113.

[0112] As described above, requests and responses are registered correspondingly in the first cache memory 112. Therefore, when an input request is registered in the first cache memory 112, the response can be read from the first cache memory 112 and sent back immediately. However, in this case, if the input request does not completely match the request registered in the first cache memory 112, processing cannot be accelerated.

[0113] On the other hand, there are cases, such as numerical processing, where a portion of the execution results of multiple processes performed to generate a response to a request can be appropriated in a process used to generate a response to another request. In this case, as described in the above embodiment, by registering the input data of each process and the execution result of that process in the second cache memory 113 respectively, the execution results can be appropriated in the process used to generate a response to another request. As a result, the processing for obtaining a response to a request can be accelerated, or the processing load can be reduced.

[0114] Figure 12 This diagram illustrates the use of cache memory at different granularities in various implementation methods. For example, in the information processing apparatus 101, it is assumed that the control unit 201 performs the process of drawing a graph corresponding to a number on the display screen of the display unit 204. Furthermore, it is assumed that the control unit 201 receives a request for y = sin(x) + a, in the range of 0 ≤ a ≤ 10, and continuously draws the corresponding graph while gradually increasing the value of a by 1 each time.

[0115] In this case, the control unit 201 first sets a = 0, executes a series of multiple processes to generate a graph of y = sin(x), and displays the graph on the display screen based on the obtained response. Furthermore, the control unit 201 records the request for y = sin(x) and the response including the coordinate values ​​of each point of the graph in the first cache memory 112. Moreover, in the embodiment, the execution results of the processes are recorded in the second cache memory 113 corresponding to the input data of the multiple processes executed in generating the requested graph of y = sin(x). For example, the control unit 201 can use y = sin(x), which is a part of the expression y = sin(x) + a, as input data, and record the coordinate values ​​of each point of the graph in the second cache memory 113.

[0116] In this case, for example, if we then generate a graph of y = sin(x) + 1 with a = 1, the first cache memory 112 only stores the response corresponding to the request for y = sin(x). Since this is different from y = sin(x) + 1, we cannot obtain information from the first cache memory 112 that can be used to generate the graph. However, the second cache memory 113 stores the coordinate values ​​of each point of the graph, with y = sin(x) as input data. Therefore, when the control unit 201 generates a graph in response to the request for y = sin(x) + 1, it can read the coordinate values ​​of the graph from the second cache memory 113 regarding sin(x), which is part of the expression y = sin(x) + 1. Therefore, processing can be performed at a much faster speed compared to performing all the calculations. Similarly, when plotting the graph of y = sin(x) + a in the range of a = 2 to 10, the coordinate values ​​of the graph of y = sin(x) can be read from the second cache memory 113, which can reduce the processing load and perform processing at high speed.

[0117] Furthermore, when the control unit 201 draws a graph of y = sin(x) + 10 after setting a = 10, and then draws a graph of y = sin(x) again, since the corresponding response is registered in the first cache memory 112, the calculation can be performed even using the numerical processing module 212. Therefore, it is possible to further reduce the processing load and increase the processing speed.

[0118] Furthermore, this example illustrates the use of information from the second cache memory 113 in a case where a portion of the numerical expression is common; however, examples of the effects that the second cache memory 113 can bring are not limited to this. For example, suppose a request is received to depict graphics with different depiction ranges indicated by the same numerical expression. In this case, since the numerical expression is the same, determination results such as numerical expression determination and numerical expression type determination can be obtained from the second cache memory 113, thereby reducing the processing load and increasing the processing speed.

[0119] As described above, for example, in cases like numerical processing where the execution result is always the same if the processing is the same, if one of the multiple processes executed to generate a response to a request is the same as one of the second or more processes executed to generate a response to another request, then the execution result of the previously performed process can be reused in the subsequent process. In this case, according to the implementation, not only is the response corresponding to the request cached, but also the input data of the multiple processes executed to generate the response and the execution results of the processes are cached accordingly, thus achieving a reduction in processing load and a speedup of processing.

[0120] Furthermore, in the above-described embodiment, the first cache memory 112 and the second cache memory 113 are stored in the information processing device 101, so the reference to the cache memory from other devices may be limited. On the other hand, the third cache memory 131 of the service providing server 102 can be shared among multiple information processing devices 101 connected to the services provided by the service providing server 102 and multiple accounts registered in the services. Therefore, in the third cache memory 131, when responding to requests from multiple information processing devices 101 and accounts, a wide variety of requests and responses can be cached, which can improve the hit rate.

[0121] The above embodiments are illustrative, but are not limited to these. For example, the above operation flow is illustrative, and the implementation is not limited to this. Where possible, the operation flow may be executed by changing the order of processing, may include more processes, or may omit some processes.

[0122] Furthermore, the above-described embodiments describe an example where the information processing device 101 calls the main thread 401 and sub-thread 402 from the browser 111, utilizing cache memories with different granularities. However, the embodiments are not limited to this. For example, in other embodiments, the first cache memory 112 and the second cache memory 113 may be integrated into a single cache memory. For example, as described above... Figure 4A As shown, when the main thread 401 performs all the processing for the request, the control unit 201 may also register the input data of the processing and the information of the processing execution result registered in the second cache memory 113 in the above embodiment to the first cache memory 112.

[0123] Furthermore, in other embodiments, the control unit 201 may also perform a process to synchronize information between the first cache memory 112 and the second cache memory 113. For example, the control unit 201 may also perform a process to register records registered in the first cache memory 112 to the second cache memory 113, and also a process to register records registered in the second cache memory 113 to the first cache memory 112. Thus, for example, the first cache memory 112 can also refer to the input data and calculation results of multiple processes for generating a response corresponding to a request. Furthermore, for example, the second cache memory 113 can also refer to the request and the response corresponding to the request. Moreover, by configuring the cache memory in this way, processing speed can be achieved according to the installation. For example, in the above embodiment, when the main thread 401 also executes the processing executed by the sub-thread 402, since the execution results of multiple processes for generating a response can be obtained from the first cache memory 112 of the main thread 401, the processing in the main thread 401 can be executed at high speed.

[0124] Furthermore, in the above embodiment, an example was described where each sub-thread 402 has a second cache memory 113. In this case, since each sub-thread 402 stores different data in the second cache memory 113, there is a possibility that data registered in the second cache memory 113 of other sub-threads 402 cannot be used. However, the embodiment is not limited to this. For example, in other embodiments, the control unit 201 may also perform processing to register data newly registered in a certain second cache memory 113 of a certain sub-thread 402 into the second cache memory 113 of other sub-threads 402, and to synchronize the contents of the second cache memory 113 among the sub-threads 402. Alternatively, the embodiment may be configured such that multiple sub-threads 402 refer to a single shared second cache memory 113.

[0125] Furthermore, in the above-described embodiment, an example of the information processing device 101 performing processing via the browser 111 was described. Therefore, the installation method may be limited by the specifications of JavaScript and WebWorkers associated with the browser 111. However, the embodiment is not limited to processing via the browser 111. For example, in other embodiments, the browser 111 may not be used. For example, the embodiment may also be installed in the information processing device 101 to perform applications such as drawing graphics corresponding to numbers. In this case, the control unit 201 may also register the registration contents of the first cache memory 112 and the second cache memory 113 into a single cache memory and manage and perform processing.

[0126] Furthermore, in the above-described embodiments, in Figure 9 If the request hits the first cache memory 112 and is not an NG request, the processing is terminated without delegating the request to the sub-thread 402. However, in other embodiments, the processing of the request may be delegated to the sub-thread 402 even if the request hits the first cache memory 112 and is not an NG request. For example, when there are few requests and the processing capacity of the control unit 201 is sufficient, by having the sub-thread 402 perform the processing in this way, the input data and execution results of the processing can be stored in the second cache memory 113.

[0127] Furthermore, in the above-described embodiment, during the processing in S1002, the control unit 201 operates, for example, as the execution unit 231. Additionally, during the processing in S909, the control unit 201 operates, for example, as the first storage unit 232. During the processing in S1109, the control unit 201 operates, for example, as the second storage unit 233. During the processing in S905, the control unit 201 operates, for example, as the feedback unit 234.

[0128] Figure 13 This is a diagram illustrating the hardware structure of a computer 1300 used to implement the information processing apparatus 101 of the relevant embodiments. Figure 13 The hardware structure for implementing the information processing device 101 includes, for example, a processor 1301, a memory 1302, a storage device 1303, a reading device 1304, a communication interface 1306, an input / output interface 1307, an input device 1311, and a display device 1312. Furthermore, the processor 1301, memory 1302, storage device 1303, reading device 1304, communication interface 1306, and input / output interface 1307 are interconnected, for example, via a bus 1308.

[0129] The processor 1301 can be a single processor, a multi-processor, or a multi-core processor. For example, the processor 1301 can read and execute programs, functioning as the control unit 201, browser 111, number processing module 212, main thread 401, and sub-thread 402 (processing module 213) in the above-described embodiment. Furthermore, the processor 1301 can execute programs, such as a cache management program describing the order of the above-described operation flow, using the memory 1302, functioning as the execution unit 231, first storage unit 232, second storage unit 233, and return unit 234.

[0130] The memory 1302 is, for example, a semiconductor memory, and may also include RAM and ROM regions. The storage device 1303 is, for example, a semiconductor memory or external storage device such as a hard disk or flash memory. RAM is short for Random Access Memory. ROM is short for Read Only Memory.

[0131] The reading device 1304 accesses the removable storage medium 1305 according to the instructions of the processor 1301. The removable storage medium 1305 may be, for example, a semiconductor device, a medium that inputs and outputs information via magnetic action, or a medium that inputs and outputs information via optical action. Furthermore, a semiconductor device may be, for example, a USB (Universal Serial Bus) memory. Additionally, a medium that inputs and outputs information via magnetic action may be, for example, a magnetic disk. A medium that inputs and outputs information via optical action may be, for example, a CD-ROM, DVD, or Blu-ray Disc (Blu-ray is a registered trademark). CD is short for Compact Disc. DVD is short for Digital Versatile Disk.

[0132] Storage unit 202 includes, for example, a memory 1302, a storage device 1303, and a removable storage medium 1305. For example, a first cache memory 112 and a second cache memory 113 are stored in the storage device 1303.

[0133] Communication interface 1306 communicates with other devices according to the instructions of processor 1301. In one example, communication interface 1306 can send and receive data with service provider server 102 via network 105 through wired or wireless communication. Communication interface 1306 is an example of the communication unit 203 described above.

[0134] The input / output interface 1307 may be an interface between a device that performs input and output. For example, the input / output interface 1307 may be connected to an input device 1311, such as a keyboard, mouse, touch panel, etc., that receives instructions from a user. Furthermore, the input / output interface 1307 may be connected to a display device 1312. The display device 1312 may be a device for displaying information, such as a monitor or projector. For example, it may be... Figure 12 The display screen is shown on the display device 1312, which is connected to the input / output interface 1307. The display device 1312 is an example of the display unit 204 described above. The input / output interface 1307 can also be connected to other output devices, such as sound devices like speakers and printing devices like printers.

[0135] The various programs related to the implementation method are provided to the information processing device 101 in the following form, for example.

[0136] (1) Pre-installed in storage device 1303.

[0137] (2) Provided via removable storage medium 1305.

[0138] (3) Provided from the program server or other server 1330 via network 105.

[0139] Additionally, server 1330 may have in one instance Figure 13 The hardware structure of the computer 1300.

[0140] Additionally, it is used to implement references Figure 13 The hardware structure of the computer 1300 in the described information processing apparatus 101 is illustrative, and the implementation is not limited to this. For example, a part of the above structure may be deleted, and new structures may be added. Furthermore, in other embodiments, for example, some or all of the functions of the control unit 201 may be implemented as hardware such as FPGA, SoC, ASIC, and PLD. FPGA stands for Field Programmable Gate Array. SoC stands for System-on-a-chip. ASIC stands for Application Specific Integrated Circuit. PLD stands for Programmable Logic Device.

[0141] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0142] While the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is given the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

[0143] This invention claims priority based on Japanese Patent Application No. 2020-053621, filed on March 25, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A cache memory management method characterized by comprising: in a case where a correspondence relation between a first request and a first response corresponding to the first request is not held in a first cache memory, executing a plurality of processes for generating the first response corresponding to the first request; holding input data of each of the plurality of processes and an execution result of the process corresponding to the input data together in either one of the first cache memory and a second cache memory; holding the first response generated based on the execution result of the plurality of processes in the first cache memory in correspondence with the first request; for the first request, returning the first response; in a case where a correspondence relation between a second request and a second response corresponding to the second request is held in the first cache memory, returning the second response read out from the first cache memory; in a case where the correspondence relation between the second request and the second response corresponding to the second request is not held in the first cache memory, executing a plurality of processes for generating the second response corresponding to the second request; even in a case where a correspondence relation between input data of a second process of the plurality of processes for generating the second response corresponding to the second request and an execution result of the process corresponding to the input data of the second process is held in the either one of the cache memories, not acquiring the execution result of the second process from the either one of the cache memories in a case where the input data of the second process specifies a process satisfying a first condition, the first condition is a condition that the execution result of the process corresponding to the input data of the second process changes every time the process is executed.

2. The cache memory management method according to claim 1, characterized by comprising: in a case where a correspondence relation between input data of a first process of the plurality of processes for generating the second response corresponding to the second request and an execution result of the process corresponding to the input data of the first process is held in the either one of the cache memories, acquiring the execution result of the first process from the either one of the cache memories.

3. The cache memory management method according to claim 1, characterized in that the second request is a request related to a mathematical expression process.

4. The cache memory management method according to claim 3, characterized in that in a case where the execution result of the second process is not acquired from the either one of the cache memories, the second process is executed using a mathematical expression process module, and the second response is generated based on a calculation result obtained.

5. The cache memory management method according to claim 1, characterized in that in the process held in the either one of the cache memories, in a case where a process whose execution result satisfies a second condition is executed, the input data and the execution result of the process are not held in the either one of the cache memories. The second condition is a condition in which an execution result of the processing corresponding to the input data of the processing is a result including an error, and the error indicates a state in which an operation result for the input data of the processing is not successfully obtained.

6. The cache memory management method according to Claim 1, wherein the plurality of processes for generating the first response are executed by one of the plurality of threads; the one thread saves the execution result of the processing in the certain one of the cache memories allocated to the one thread in correspondence with the input data of each of the plurality of processes.

7. The cache memory management method according to Claim 6, wherein the one thread does not refer to the cache memory allocated to another thread of the plurality of threads.

8. The cache memory management method according to Claim 1, wherein in a case where the first request and the first response corresponding to the first request are saved in the certain one of the cache memories in correspondence with each other, the first response corresponding to the first request is obtained from the first cache memory.

9. The cache memory management method according to Claim 1, wherein the first request is a request related to numerical formula processing.

10. A cache memory management system, comprising: an information processing apparatus; and a server, wherein the information processing apparatus performs the following processing: in a case where a first request and a first response corresponding to the first request are not saved in a first cache memory in correspondence with each other, a plurality of processes for generating the first response corresponding to the first request are executed; input data of each of the plurality of processes and an execution result of the processing are saved in a certain one of the first cache memory and a second cache memory in correspondence with each other; the first response generated on the basis of the execution result of the plurality of processes is saved in the first cache memory in correspondence with the first request; the first response is returned with respect to the first request; in a case where a second request and a second response corresponding to the second request are saved in the first cache memory in correspondence with each other, the second response read out from the first cache memory is returned; in a case where the second request and the second response corresponding to the second request are not saved in the first cache memory in correspondence with each other, a plurality of processes for generating the second response corresponding to the second request are executed; even in a case where input data of a second process of the plurality of processes for generating the second response corresponding to the second request and an execution result of the processing corresponding to the input data of the second process are saved in the certain one of the cache memories in correspondence with each other, the execution result of the second process is not obtained from the certain one of the cache memories in a case where the input data of the second process specifies processing satisfying a first condition. ​ ​ ​ ​ ​ ​ ​ ​ ​ The first condition is a condition in which an execution result of processing corresponding to the second input data changes each time the processing is executed.

11. The cache management system according to Claim 10, wherein The information processing apparatus performs the following processing: In a case where an error occurs in the plurality of processes for generating the first response corresponding to the first request, the first request is transmitted to the server; The first response corresponding to the first request is received from the server.

12. The cache management system according to Claim 10, wherein The information processing apparatus performs the following processing: In response to the first request being received, the plurality of processes for generating the first response corresponding to the first request are executed, and the first request is transmitted to the server; The first response corresponding to the first request is received from the server.

13. The cache management system according to Claim 11, wherein The information processing apparatus saves the first response received from the server in the first cache.

14. The cache management system according to Claim 11, wherein The server saves the first response generated based on an execution result of the plurality of processes corresponding to the first request in a third cache.

15. The cache management system according to Claim 14, wherein In the third cache, a third response generated in accordance with an execution result of a plurality of processes corresponding to a third request from another computer is saved in correspondence with the third request; The server, in a case where the first request is received from the information processing apparatus, notifies the information processing apparatus of the third response as the first response for the first request when the first request coincides with the third request.

16. The cache management system according to Claim 10, wherein The first request is a request related to numerical formula processing.

17. An information processing apparatus comprising: at least one processor; The processor performs the following processing: In a case where a correspondence relationship between a first request and a first response corresponding to the first request is not saved in a first cache, a plurality of processes for generating the first response corresponding to the first request are executed; The first response generated based on an execution result of the plurality of processes is saved in the first cache in correspondence with the first request; Input data of each of the plurality of processes and an execution result of the process are saved together in one of the first cache and a second cache in correspondence with the process; The first response is sent back for the first request; In a case where the first cache stores a correspondence between the second request and the second response corresponding to the second request, the second response read from the first cache is returned; In a case where the first cache does not store the correspondence between the second request and the second response corresponding to the second request, a plurality of processes for generating the second response corresponding to the second request are executed; Even in a case where the certain cache stores a correspondence between input data of a second process of the plurality of processes for generating the second response corresponding to the second request and an execution result of a process corresponding to the input data of the second process, the execution result of the second process is not acquired from the certain cache in a case where the input data of the second process specifies a process satisfying a first condition, The first condition is a condition under which the execution result of the process corresponding to the input data of the second process changes every time the process is executed.

18. The information processing apparatus according to claim 17, wherein The first request is a request related to a numerical formula process.

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