Method for processing fin field effect transistor devices
By forming the trench and recessed substrate separately in the process steps, and independently controlling the trench depth and fin structure height, the control problem in the manufacturing of fin field-effect transistor devices in the prior art has been solved, and high-precision and high-efficiency fin field-effect transistor manufacturing has been achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
- Filing Date
- 2021-03-24
- Publication Date
- 2026-06-09
AI Technical Summary
Existing technologies struggle to independently control the critical dimensions of the fin structure height and dielectric isolation height in fin field-effect transistor devices, leading to limitations in manufacturing processes.
By forming trenches and recessing the substrate in two separate process steps, the trench depth and fin structure height are independently controlled. The inner wall of the trench is protected with a filler material, and the fin structure is formed by an etching process.
This technology enables high-precision and high-efficiency manufacturing of fin field-effect transistor devices, reduces the impact of micro-loads and fin loads within cells, and improves the critical size control of trench and fin structures.
Smart Images
Figure CN113451213B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a method for processing fin field-effect transistor devices, particularly fork-plate devices, and also to a fin field-effect transistor device that can be obtained by the above method. Background Technology
[0002] A FinFET is a metal-oxide-semiconductor field-effect transistor (MOSFET) with a fin-shaped channel between the source and drain terminals. The gate is thus placed on two or three sides of the fin-shaped channel, and preferably around the channel. Compared to conventional planar MOSFETs such as CMOS, FinFETs allow for faster switching timing and higher current density.
[0003] A forksheet (FSH) device is a special type of fin field-effect transistor where the fin channel comprises multiple vertically stacked nanosheets. The fin channel of a forksheet device also includes pMOS and nMOS sides separated by a dielectric barrier at the center of the fin. By using this forksheet design, the switching timing of the fin field-effect transistor can be increased while reducing power consumption.
[0004] However, manufacturing fin field-effect transistor (FET) devices and fork-type devices is challenging. In particular, current manufacturing processes do not allow for independent control of critical dimensions such as the height of the fin structure and the height of the dielectric isolation within the fin structure. This results in significant limitations in the design of fin field-effect transistors and fork-type devices. Summary of the Invention
[0005] Therefore, the object of this disclosure is to provide an improved method for processing fin field-effect transistor devices, particularly fork-plate devices, and to provide an improved fin field-effect transistor device that can be obtained by the above method. In particular, the disadvantages described above should be avoided.
[0006] According to a first aspect, this disclosure relates to a method for processing fin field-effect transistor devices, particularly fork-type devices, wherein the method includes:
[0007] - Provide a base;
[0008] - A trench is formed in the substrate, wherein the trench extends along a first direction;
[0009] - Fill the trench with filler material;
[0010] - The base is partially recessed to form a fin structure, wherein the fin structure includes a filled groove, a first segment of the base on a first side of the filled groove, and a second segment of the base on a second side of the filled groove.
[0011] - A gate structure is formed on and around the fin structure.
[0012] This enables the efficient and highly process-controlled processing of fin field-effect transistor devices.
[0013] In particular, by forming the trenches and recessing the substrate in two separate and independent process steps, the depth of the trenches and the height of the fin structure including the trenches can be controlled independently of each other. Conversely, forming the trenches and fin structure simultaneously will make the trench depth dependent on the fin height.
[0014] Furthermore, by forming trenches and recessing the substrate in two separate and independent process steps, the effects of micro-load and intra-cell fin load, i.e., local variations in etching rate, can be reduced. These local variations are caused, for example, by differences in trench width and fin-to-fin distance when trenches and fin structures are formed simultaneously. By eliminating these effects, straighter trench wall profiles and better critical dimension control of fin structures and trenches can be achieved.
[0015] The grooves filled before the fin structure is formed offer an additional advantage: the inner walls of the grooves are protected by the filling material when the fin structure is formed.
[0016] Fin field-effect transistor devices can be nanosheet devices, especially nanosheet FETs, or fork-plate devices, especially fork-plate FETs (FSH FETs).
[0017] This fin structure can form the channel of a fin field-effect transistor. Preferably, the fin structure is arranged between the source and drain terminals of the fin field-effect transistor.
[0018] In one implementation, the method further includes:
[0019] A p-doped region is formed on or in a first segment of the substrate and / or an n-doped region is formed on or in a second segment of the substrate, preferably after the fin structure is formed.
[0020] This enables the efficient processing of fin field-effect transistors with both p-gate and n-gate.
[0021] Alternatively, an n-doped region may be formed on or in the first segment and / or a p-doped region may be formed on or in the second segment.
[0022] Preferably, the fin structure forms a channel, wherein a first section defines the p-gate contact of the channel and a second section defines the n-gate contact of the channel, or vice versa. Specifically, the fin field-effect transistor device is a multi-gate device, wherein the gate structure of the fin field-effect transistor includes a p-gate and an n-gate.
[0023] In one embodiment, preferably, the p-doped and / or n-doped regions are formed by means of an epitaxial growth process during the epitaxial formation of the source and drain terminals.
[0024] This achieves the following advantages: preferably, the first and second segments can be doped efficiently during the formation of the source and drain.
[0025] For example, p-doped regions can be formed by depositing SiGe:B (boron-doped SiGe) and Ga, and n-doped regions can be formed by depositing SiP (phosphorus-doped silicon) and As, preferably deposited on the first and second segments of the fin structure, respectively.
[0026] In one embodiment, the step of forming a trench in the substrate includes:
[0027] A grating structure is formed on a substrate, wherein the grating structure includes a pair of masks extending along a first direction, wherein the pair of masks are arranged at a distance from each other; and
[0028] The substrate is etched into the area between the pairs of masks to form trenches.
[0029] This enables the formation of trenches with high precision and efficiency.
[0030] Specifically, the grating structure includes a hard mask on the substrate.
[0031] Etching between pairs of masks can include wet etching processes and / or dry etching processes, such as reactive ion etching processes.
[0032] In one embodiment, the step of forming trenches in the substrate further includes:
[0033] After forming the grating structure, a sacrificial structure is formed on the substrate and around the grating structure, wherein the sacrificial structure includes at least one material layer; and
[0034] Selectively remove the sacrificial structure in the region between pairs of masks.
[0035] This enables the formation of trenches with high precision and efficiency.
[0036] In one embodiment, the spacer layer is formed at least partially around the pair of masks, particularly on the facing sidewalls of each of the pair of masks.
[0037] This enables the formation of trenches with high precision and efficiency. In particular, the spacer layer enhances critical dimension (CD) control of the trenches; for example, by applying the spacer layer to the facing sidewalls of the masks, the diameter of the trenches formed in the substrate between the masks can be further reduced. Preferably, the facing sidewalls refer to the inner sidewalls of the mask on the trench-forming side of each mask.
[0038] In one implementation, a spacer layer is formed in the region between pairs of masks before the sacrificial structure is formed or after the sacrificial structure is selectively removed.
[0039] This enables the formation of trenches with high precision and efficiency. In particular, forming the spacer layer before or after the selective removal of the sacrificial structure provides further critical dimension (CD) control over the trenches and / or fin structures.
[0040] In one embodiment, the fin structure is formed by recessing, in particular etching, the substrate at a certain distance from each side of the filled trench.
[0041] This allows for the efficient formation of fin structures. Etching can include wet etching or dry etching processes.
[0042] In one implementation, the distance from each side of the filled trench is defined by the width of the mask on the corresponding side of the trench.
[0043] This enables the formation of fin structures with high precision and efficiency.
[0044] Preferably, the fin structure is completely self-aligned to the mask, which can form a hard mask grating. The mask enables critical dimension (CD) control of the fin structure.
[0045] In one embodiment, the difference between the depth of the groove and the height of the fin structure is less than 10%, particularly less than 5%, more particularly less than 2%, or wherein the depth of the groove substantially corresponds to the height of the fin structure.
[0046] This enables the processing of fin field-effect transistor devices with high control over design parameters. In particular, by forming trenches and recessing the substrate in two separate and independent process steps, the depth of the trenches and the height of the fin structure can be independently adjusted, for example, made substantially the same.
[0047] In one implementation, the depth of the trench is greater than or equal to the height of the fin structure.
[0048] This enables the processing of fin field-effect transistor devices with high control over design parameters. In particular, it prevents localized variations in the etch rate that occur when both trenches and fins are formed simultaneously. These localized variations are caused, for example, by differences between the trench width and the fin-to-fin distance, and typically result in trench depths that are less than the fin height.
[0049] In another embodiment, the depth of the groove is less than the height of the fin structure. Preferably, the groove depth and the fin height can be controlled independently of each other.
[0050] In one embodiment, the filler material includes a dielectric material, particularly silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride oxynitride (SiOCN), silicon carbonitride (SiCN), silicon dioxide (SiO2), silicon carbonitride (SiCO), or silicon oxynitride (SiON).
[0051] Preferably, the filled trenches form a dielectric isolation barrier for the fin structure.
[0052] In one implementation, the trench is filled using a plasma-enhanced atomic layer deposition (PEALD) process.
[0053] This enables the trenches to be filled efficiently using advanced processing control.
[0054] Alternatively, the trenches can be filled with low-temperature (LT) SiN deposition and / or flowable chemical vapor deposition (FCVD) of SiC.
[0055] In one embodiment, the substrate comprises a nanosheet structure of alternating nanolayers of two different semiconductor materials, particularly Si and SiGe, wherein the trenches penetrate the nanosheet structure.
[0056] This enables the efficient processing of fin structures, such as forked structures, which include alternating nanolayers. In particular, when the substrate is partially recessed to form the fin structure, the first and second segments of the substrate on opposite sides of the fin structure each comprise nanosheet structures.
[0057] According to the second aspect, this disclosure relates to a fin field-effect transistor device, particularly a fork-type device, which can be obtained by the method according to the first aspect of this disclosure, particularly wherein the difference between the depth of the trench and the height of the fin structure is less than 10%, particularly less than 5%, more particularly less than 2%, or wherein the depth of the trench substantially corresponds to the height of the fin structure.
[0058] This enables the efficient processing and high process control of fin field-effect transistor devices.
[0059] The fin field-effect transistor device fabricated using the method of the first aspect demonstrates a clear "fingerprint" of the method. By forming trenches and recessing the substrate in two separate and independent process steps, the depth of the trenches and the height of the fin structure including the trenches can be controlled independently of each other; in particular, the trench depth can be greater than or substantially equal to the fin height. Conversely, forming the trenches and fin structure simultaneously in a bonding process step, such as an etching step, will cause the trench depth to depend on the fin height, where, for example, due to the so-called micro-loading effect, the trench depth will typically be less than the fin height. Attached Figure Description
[0060] The invention will now be described in conjunction with the accompanying drawings.
[0061] Figures 1a to 1i The steps of a method for processing a fin field-effect transistor device according to an embodiment are shown; and
[0062] Figures 2a to 2j The steps of a method for processing a fin field-effect transistor device according to an embodiment are shown. Detailed Implementation
[0063] Figures 1a to 1i The steps of a method for processing a fin field-effect transistor device according to an embodiment are shown. In particular, the main steps for forming the fin structure of the fork-shaped device are shown.
[0064] like Figure 1a As shown, the method includes providing a substrate 21.
[0065] The substrate 21 may include, for example, a base structure 1 made of Si, and a nanosheet structure of alternating nanolayers 2 and 3 disposed on the base structure 1. The alternating nanolayers may include a Si layer 2 and a SiGe layer 3; for example, when disposed between two Si layers 2, the Si layer 2 has a thickness of 10 nm, and the SiGe layer 3 has a thickness of 7 nm. The SiGe layer 3 may form the top layer of the substrate 21 and may have a relatively large thickness, for example, 30 nm. The SiGe layer 3 may include 30% germanium (Ge).
[0066] like Figure 1a As shown, the method further includes forming a grating structure on a substrate 21, wherein the grating structure includes a pair of masks 23 extending along a first direction, specifically along the x-direction. The pairs of masks 23 are arranged such that they are spaced a first distance from each other. The x-direction is perpendicular to the z-direction, which is aligned with the direction of layer fabrication, and the x-direction is also perpendicular to the y-direction, as indicated by the schematic coordinate system. The x-direction extends to... Figures 1a to 1i Within the plane.
[0067] exist Figure 1aIn an exemplary embodiment, two pairs of masks 23 on a substrate 21 are shown, wherein the location where the fin structure is formed in each pair of masks 23 is defined. For clarity, the method will be described below with reference to one of the pairs of masks 23 and the fin structure generated by means of the pairs of masks 23; obviously, this also applies to the second pair.
[0068] Preferably, each of the pairs of masks 23 includes a bottom layer 4, an intermediate layer 5, and a top layer 6. The bottom layer 4 may be made of SiO2, the intermediate layer 5 may be made of Si3N4 (silicon nitride), and the top layer 6 may be made of SiC, SiCO, or SiO2.
[0069] Specifically, the grating structure forms a hard mask (HM) on the substrate 21. The grating structure can be formed by depositing layers 4, 5, and 6 on the substrate 21 and then photolithographically structuring the layers 4, 5, and 6.
[0070] like Figure 1b As shown, the method further includes forming a spacer layer 7 on the substrate 21 and around the pair of masks 23. In particular, the spacer layer 7 is also formed on the facing sidewalls of the pair of masks 23.
[0071] The spacer layer can be formed by a deposition process such as plasma-enhanced atomic layer deposition (PEALD) and can include Si3N4 and / or SiO2.
[0072] like Figure 1c As shown, the method further includes forming a sacrificial structure on the substrate 21 and on and around the grating structure. The sacrificial structure includes at least one material layer 8, 9, 10.
[0073] exist Figure 1c In this structure, the sacrificial structure comprises three material layers 8, 9, and 10: a spin-coated carbon (SoC) layer 8, a spin-coated glass (SoG) layer 9, and a photoresist (PR) layer 10. The PR layer 10 can be opened in the region above the paired masks 23, specifically by means of a photolithographic mask to selectively illuminate the PR layer 10, followed by development and removal steps.
[0074] like Figure 1d As shown, the method also includes selective removal, i.e., opening the sacrificial structure, particularly opening the SoC layer 8 and SoG layer 9 in the region between the pairs of masks 23.
[0075] Selective removal can be achieved by etching the SoC layer 8 and SoG layer 9 below the opening of PR layer 8. Specifically, SoC layer 8 and SoG layer 9 are etched using a dry etching step, which selectively removes the SoC and SoG materials while leaving most of PR layer 9 intact.
[0076] like Figure 1e As shown, the method further includes forming a trench 25 in the substrate 21, wherein the trench extends along the x-direction.
[0077] The trench 25 can be formed by etching into the substrate 21 in the region between pairs of masks 23, for example by an isotropic etching process such as reactive ion etching. For example, the trench 25 has a width of 8 nm.
[0078] like Figure 1f As shown, the method also includes filling the groove 25 with filling material 11.
[0079] The filling material 11 can be a dielectric material that forms a dielectric isolation barrier for the fin structure.
[0080] Trench 25 can be filled using a plasma-enhanced atomic layer deposition (PEALD) process. Alternatively, trench 25 can be filled by low-temperature (LT) SiN deposition and / or flowable chemical vapor deposition (FCVD) of SiC.
[0081] Grooves 25 filled before the formation of the fin structure (reference) Figure 1i It provides an additional advantage: when the base is recessed to form a fin structure, the inner wall of the groove 25 is protected by the filling material 11.
[0082] like Figure 1g As shown, the method also includes recessing the trench filler material. The filler material can be recessed by etching back or by chemical mechanical polishing (CMP).
[0083] Preferably, the method further includes removing residual portions of the sacrificial structure, such as Figure 1h As shown. In particular, the removal of the sacrificial structure includes the stripping of SoC layer 8.
[0084] like Figure 1i As shown, the method includes partially recessing the base 21 to form a fin structure 27.
[0085] The fin structure 27 may include a filled groove 25, a first segment of the base on a first side of the filled groove 25, and a second segment of the base on a second side of the filled groove 25.
[0086] The fin structure 27 can be formed by recessing the substrate at a distance from each side of the filled trench 25, specifically defined by the width of the respective mask 23 in the pair of masks 23, and preferably by the thickness of the spacer layer 7 surrounding the mask 23. The fin structure can be self-aligned to the mask 23, which can form a hard mask grating. The mask can enhance the critical dimension (CD) control of the fin structure 27.
[0087] Specifically, the substrate can be recessed to form the fin structure 27 by means of appropriate dry or wet etching processes, particularly isotropic etching back processes. During or after the recess, excess filler material 11 protruding from the paired masks 23 can be removed.
[0088] Forming and filling the trench 25 prior to forming the fin structure 27 allows for control over the design of the trench 25, particularly its depth, independently of the height of the fin structure 27. For example, the difference between the depth of the trench 25 and the height of the fin structure 27 can be set to less than 10%, 5%, 2%, or even 1%. Specifically, the corresponding process steps can be adjusted so that the height of the recessed fin structure 27 substantially corresponds to the depth of the trench 25. The depth of the trench 25 can also be set to be greater than the height of the fin structure 27, allowing the filled trench below the fin structure 27 to extend further into the substrate 21. Conversely, when the trench 25 and the fin structure 27 are formed simultaneously, the depth of the trench 25 is typically less than the fin height, particularly due to local variations in the etching rate. These local variations are caused, for example, by differences between the trench width and the fin-to-fin distance. This limitation can be overcome by forming the trench and fin structures in separate steps.
[0089] After the fin structure 27 is formed, p-doped regions can be formed on the fin, particularly on or within the first segment of the substrate 21. Similarly, n-doped regions can be formed on the fin, particularly on or within the second segment of the substrate 21.
[0090] Preferably, during the epitaxial formation of the source and drain terminals, p-doped and / or n-doped regions can be formed using an epitaxial growth process. For example, p-doped regions can be formed by depositing SiGe:B (boron-doped SiGe) and Ga, while n-doped regions can be formed by depositing SiP (phosphorus-doped silicon) and As.
[0091] Preferably, in another step, the method includes forming a gate structure on and around the fin structure 27.
[0092] The gate structure may include a p-gate in contact with the p-doped region of the fin structure 27 and an n-gate in contact with the n-doped region of the fin structure 27.
[0093] Figures 2a to 2j The steps of a method for processing a fin field-effect transistor device according to another embodiment are shown.
[0094] Figures 2a to 2j The method shown is the same as Figures 1a to 1i The main difference in the methods shown lies in the order in which the spacer layer 7 and the sacrificial structure are applied.
[0095] like Figure 2aAs shown, the method includes providing a substrate 21, which includes, for example, a base structure 1 made of Si and a nanosheet structure of alternating nanolayers 2, 3 disposed on the base structure 1. The substrate 21 includes a grating structure. In particular, Figure 2a The substrate 21 and grating structure shown are... Figure 1a The substrate 21 shown is the same as the grating structure.
[0096] like Figure 2b As shown, the method includes forming a sacrificial structure on the substrate 21 and directly on and around the grating structure. The sacrificial structure may also include three material layers 8, 9, and 10, wherein the PR layer 10 may be opened in a region above the paired masks 23.
[0097] The sacrificial structure may also include an amorphous silicon (a-Si) layer. In particular, the a-Si layer may replace the SoC layer 8.
[0098] The method also includes selectively removing the sacrificial structure, particularly the SoC layer 8 and SoG layer 9 in the region between the paired masks 23, such as Figure 2c As shown.
[0099] exist Figure 2d In the subsequent steps shown, spacer layers 12 are formed on the remaining sacrificial structure, the pairs of masks 23, and the substrate between the pairs of masks 23. In particular, spacer layers 7 are also formed on the facing sidewalls of the masks 23.
[0100] The spacer layer 12 can be a SiO2 or Si3N4 layer. In particular, the formation of the spacer layer 12 includes the formation of a low-temperature oxide.
[0101] like Figure 2e As shown, the method also includes selectively removing the spacer layer 12, for example, by etching. In particular, the spacer layer 12 remains intact only at the facing sidewalls of the mask 23 and / or at the facing sidewalls of the sacrificial structure on top of the mask.
[0102] The remaining spacer layer 12 on the facing sidewalls of mask 23 can facilitate the formation of grooves 25 between masks having a critical size, for example, a diameter smaller than the distance between masks 23. In other words, the remaining spacer layer 12 allows for a reduction in the gap between the pairs of masks 23, and thus a reduction in the width of the grooves 25 formed between the pairs of masks 23.
[0103] like Figures 2f to 2g As shown, the method further includes forming a groove 25 and filling the groove 25 with a filling material, preferably using a material similar to that used above for... Figures 1e to 1f The same process as described above.
[0104] like Figure 2h As shown, the method also includes recessing the trench filling material 11. The filling material can be recessed by an isotropic dry etching process.
[0105] like Figures 2i to 2j As shown, the method further includes removing the residue of the sacrificial structure and partially recessing the substrate 21 to form the fin structure 27, preferably utilizing the method described above. Figures 1h to 1i The same process as described above.
[0106] Preferably, in another step, the method includes forming a gate structure on and around the fin structure 27.
[0107] In this method, such as Figures 2a to 2j As shown, the formation of the groove 25 is also separate from the formation of the fin structure 27. Therefore, the depth of the groove can be controlled independently of the height of the fin structure 27. In particular, the depth of the groove 25 can be greater than or substantially equal to the height of the fin structure 27.
[0108] When using the same grating structure as the starting point Figures 1a to 1i The method steps shown may result in the obtained fin structure 27 being related to Figures 2a to 2j The method steps shown have different critical dimensions, particularly different widths. The critical dimension of each fin structure 27 depends on the critical dimensions of the corresponding pair of masks 23, particularly the width (distance in the y-direction) of each mask 23, and on the spacer layers 7 on the sidewalls of the masks 23, which increases the effective width of the masks 23. Figures 1a to 1i In the method shown, spacer layer 7 is arranged on the facing and away sidewalls of mask 23 (see reference). Figure 1i ), among which, in Figures 2a to 2j In the method shown, the spacer layer 12 is arranged only on the facing sidewall of the mask 23 (see reference). Figure 2j Therefore, through Figures 1a to 1i The width of the fin structure 27 formed by the method shown in the y-direction is equal to the width of the fin structure 27 formed by the method shown in the y-direction. Figures 2a to 2j The method shown increases the width of the fin structure by twice the thickness of the spacer layer 7. The spacer layers 7 and 12 on the facing sidewalls of mask 23 reduce the effective distance of the mask and thus reduce the diameter of the trench 25 in the y-direction. Therefore, forming the spacer layers 7 and 12 before or after the selective removal of the sacrificial structure provides further critical dimension (CD) control over the trench 25 and / or the fin structure 27.
[0109] use Figures 1a to 1i or Figures 2a to 2jThe fin structure 27 formed by the method shown can be the channel of a fin field-effect transistor device. In particular, the fin field-effect transistor device is a fork-plate (FSH) device. The method may include additional steps, such as forming source and drain terminals connected through the fin structure or forming connections to the gate structure.
[0110] The substrate 21 can be a wafer, particularly a Si wafer including a nanosheet structure.
[0111] All features of all embodiments described, illustrated and / or claimed herein can be combined with each other.
Claims
1. A method for processing forksheet devices, characterized in that, The method includes: A substrate (21) is provided, wherein the substrate (21) comprises a nanosheet structure of alternating nanolayers (2, 3) of two different semiconductor materials; A trench (25) is formed in the substrate (21), wherein the trench (25) extends along a first direction and wherein the trench (25) passes through the nanosheet structure; The groove (25) is filled with filling material (11); The substrate (21) is partially recessed to form a fin structure (27), wherein the fin structure (27) includes a filled trench (25), a first segment of the substrate (21) on a first side of the filled trench (25), and a second segment of the substrate (21) on a second side of the filled trench (25), wherein the first segment and the second segment of the substrate (21) form opposite sides of the fin structure (27) and each includes a portion of the nanosheet structure, and wherein the filled trench forms a dielectric isolation barrier for the fin structure (27); and A gate structure is formed on and around the fin structure (27).
2. The method as described in claim 1, characterized in that, The method further includes: A p-doped region is formed on or in the first segment of the substrate (21); and An n-doped region is formed on or in the second segment of the substrate (21).
3. The method as described in claim 2, characterized in that, The p-doped region and / or the n-doped region are formed by means of an epitaxial growth process.
4. The method as described in any one of the preceding claims, characterized in that, The step of forming the trench (25) in the substrate (21) includes: A grating structure is formed on the substrate, wherein the grating structure includes a pair of masks (23) extending along the first direction, wherein the pair of masks (23) are arranged at a distance from each other; and The substrate (21) is etched into the region between the pairs of masks (23) to form the trench (25).
5. The method as described in claim 4, characterized in that, The step of forming the trench (25) in the substrate (21) further includes: After forming the grating structure, a sacrificial structure is formed on the substrate and around the grating structure, wherein the sacrificial structure includes at least one material layer (8, 9, 10); and The sacrificial structure is selectively removed in the region between the pairs of masks (23).
6. The method as described in claim 5, characterized in that, Spacer layers (7, 12) are formed at least partially around the pairs of masks (23).
7. The method as described in claim 6, characterized in that, The spacer layer (7, 12) is formed in the region between the pairs of masks (23) before the sacrificial structure is formed or after the sacrificial structure is selectively removed.
8. The method as described in claim 4, characterized in that, The fin structure (27) is formed by recessing the base (21) at a certain distance from each side of the filled groove (25).
9. The method as described in claim 8, characterized in that, The distance from each side of the filled trench (25) is defined by the width of the mask (23) on the corresponding side of the trench (25).
10. The method as described in claim 1, characterized in that, The difference between the depth of the groove (25) and the height of the fin structure (27) is less than 10%, or the depth of the groove (25) substantially corresponds to the height of the fin structure (27).
11. The method as described in claim 1, characterized in that, The depth of the groove (25) is greater than or equal to the height of the fin structure (27).
12. The method as described in claim 1, characterized in that, The filler material (11) includes a dielectric material.
13. The method as described in claim 1, characterized in that, The trench (25) is filled using a plasma-enhanced atomic layer deposition (PEALD) process.
14. A forksheet device, which can be obtained by the method according to any one of the preceding claims.