Semiconductor device

Abstract

Provided is a semiconductor device having a transistor that achieves both high field-effect mobility and high reliability. This semiconductor device includes a first insulating layer, a first layer and a second layer provided apart from each other on the first insulating layer, a semiconductor layer located on the first insulating layer, the first layer, and the second layer and having indium and oxygen, a second insulating layer on the semiconductor layer, a first conductive layer located on the second insulating layer, a third insulating layer located on the semiconductor layer and the first conductive layer and having silicon and nitrogen, a second conductive layer, and a third conductive layer. The semiconductor layer has a first region overlapping with the first layer, a second region overlapping with the second layer, and a third region positioned between the first region and the second region. The first conductive layer overlaps with the third region. The second conductive layer is in contact with the first region at a first opening of the third insulating layer. The third conductive layer is in contact with the second region at a second opening of the third insulating layer.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a display device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, there has been a growing demand for high-resolution display devices. Devices requiring high-resolution displays include those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), all of which are being actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electroluminescence) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using organic EL elements.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Examples of oxide semiconductors applicable to transistors include indium oxide and indium gallium zinc oxide. Non-patent document 1 discloses a thin-film transistor using polycrystalline indium hydrogenate formed by low-temperature solid-phase crystallization.

[0008] International Publication No. 2016 / 038508

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022)

[0010] One aspect of the present invention aims to provide a semiconductor device having a transistor with high field-effect mobility. Alternatively, it aims to provide a semiconductor device having a transistor with high on-current. Alternatively, it aims to provide a semiconductor device having a transistor of a very small size. Alternatively, it aims to provide a semiconductor device having a transistor with a short channel length. Alternatively, it aims to provide a semiconductor device having a transistor with good electrical characteristics. Alternatively, it aims to provide a semiconductor device having a highly reliable transistor. Alternatively, it aims to provide a semiconductor device that operates at high speed. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device with low wiring resistance. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a highly reliable display device. Alternatively, it aims to provide a high-definition display device. Alternatively, it aims to provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, it aims to provide a method for manufacturing a highly productive transistor, semiconductor device, or display device. Alternatively, it aims to provide a novel semiconductor layer, transistor, semiconductor device, display device, or method for manufacturing the same.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the Future includes a first insulating layer, a first layer and a second layer provided separately on the first insulating layer, semiconductor layers on the first insulating layer, on the first layer and on the second layer, a second insulating layer on the semiconductor layer, a first conductive layer on the second insulating layer, a third insulating layer on the semiconductor layer and on the first conductive layer, a second conductive layer, and a third conductive layer, wherein the semiconductor layer includes a first region overlapping with the first layer, a second region overlapping with the second layer, and a third region located between the first region and the second region. The semiconductor device comprises a first conductive layer overlapping with a third region, a third insulating layer having a first opening overlapping with the first region and a second opening overlapping with the second region, a second conductive layer having a region located within the first opening and contacting the upper surface of the first region, a third conductive layer having a region located within the second opening and contacting the upper surface of the second region, a third insulating layer having silicon and nitrogen, and a semiconductor layer having indium and oxygen.

[0013] In the above embodiment, it is preferable that the first conductive layer has a region that overlaps with one or both of the first and second layers.

[0014] In the above embodiment, it is preferable that there is a fourth conductive layer, the first insulating layer is located on the fourth conductive layer, the fourth conductive layer overlaps with the first conductive layer, and the fourth conductive layer has a region that overlaps with one or both of the first and second layers.

[0015] In the above embodiment, the first conductive layer has a layer made of the first material, and the second conductive layer and the third conductive layer each have a layer made of the second material, and it is preferable that the second material is different from the first material.

[0016] In the above embodiment, it is preferable that the first material is copper or an alloy containing copper, and the second material is a metal having one or more selected from molybdenum, aluminum, titanium, tungsten, tantalum, and manganese, or a metal alloy having one or more selected from molybdenum, aluminum, titanium, tungsten, tantalum, and manganese.

[0017] In the above embodiment, it is preferable that the first material is copper or a copper-containing alloy, and the second material is a metal oxide or a metal nitride.

[0018] Furthermore, in the above embodiment, it is preferable that the thickness of the region of the third insulating layer that overlaps with the first conductive layer is greater than the thickness of the region of the second insulating layer that overlaps with the first conductive layer.

[0019] Alternatively, one aspect of the present invention comprises a first insulating layer, a first layer and a second layer provided separately on the first insulating layer, semiconductor layers on the first insulating layer, on the first layer and on the second layer, a second insulating layer on the semiconductor layer, a first conductive layer on the second insulating layer, a third insulating layer on the semiconductor layer and on the first conductive layer, a second conductive layer, and a third conductive layer, wherein the semiconductor layer comprises a first region overlapping with the first layer, a second region overlapping with the second layer, and a third region located between the first region and the second region. The semiconductor device comprises a first conductive layer overlapping with a third region, a third insulating layer having a first opening reaching the first layer and a second opening reaching the second layer, a second conductive layer having a region located within the first opening and contacting the upper surface of the first layer, a third conductive layer having a region located within the second opening and contacting the upper surface of the second layer, a third insulating layer having silicon and nitrogen, and a semiconductor layer having indium and oxygen.

[0020] Furthermore, in the above embodiment, it is preferable that the first opening and the second opening do not overlap with the semiconductor layer.

[0021] One aspect of the present invention can provide a semiconductor device having a transistor with high field-effect mobility. Or, a semiconductor device having a transistor with a large on-current. Or, a semiconductor device having a transistor of a very small size. Or, a semiconductor device having a transistor with a short channel length. Or, a semiconductor device having a transistor with good electrical characteristics. Or, a semiconductor device having a highly reliable transistor. Or, a semiconductor device that operates at high speed. Or, a semiconductor device with a small footprint. Or, a semiconductor device with low wiring resistance. Or, a semiconductor device or display device with low power consumption. Or, a highly reliable display device. Or, a high-definition display device. Or, a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Or, a highly productive method for manufacturing a transistor, semiconductor device, or display device. Or, a novel semiconductor layer, transistor, semiconductor device, display device, or method for manufacturing the same.

[0022] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0023] Figures 1A, 1B, and 1C are cross-sectional views showing an example of a semiconductor device. Figure 2A is a top view showing an example of a semiconductor device. Figures 2B, 2C, 2D, and 2E are cross-sectional views showing an example of a semiconductor device. Figures 3A and 3B are cross-sectional views showing an example of a semiconductor device. Figure 4A is a top view showing an example of a semiconductor device. Figures 4B and 4C are cross-sectional views showing an example of a semiconductor device. Figure 5A is a top view showing an example of a semiconductor device. Figures 5B and 5C are cross-sectional views showing an example of a semiconductor device. Figure 6A is a top view showing an example of a semiconductor device. Figures 6B and 6C are cross-sectional views showing an example of a semiconductor device. Figure 7A is a top view showing an example of a semiconductor device. Figures 7B and 7C are cross-sectional views showing an example of a semiconductor device. Figure 8A is a top view showing an example of a semiconductor device. Figures 8B and 8C are cross-sectional views showing an example of a semiconductor device. Figure 9A is a top view showing an example of a semiconductor device. Figures 9B and 9C are cross-sectional views showing an example of a semiconductor device. Figure 10A is a top view showing an example of a semiconductor device. Figures 10B and 10C are cross-sectional views showing an example of a semiconductor device. Figures 11A, 11B, 11C, 11D, 11E, and 11F are cross-sectional views showing an example of a semiconductor device. Figure 12A is a top view showing an example of a semiconductor device. Figures 12B and 12C are cross-sectional views showing an example of a semiconductor device. Figures 13A, 13B, 13C, 13D, 13E, and 13F are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 14A, 14B, 14C, and 14D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 15A, 15B, 15C, and 15D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 16A is a top view showing an example of a semiconductor device. Figures 16B, 16C, and 16D are cross-sectional views showing an example of a semiconductor device. Figure 17A is a top view showing an example of a semiconductor device. Figures 17B and 17C are cross-sectional views showing an example of a semiconductor device. Figures 18A and 18B are cross-sectional views showing an example of a semiconductor device. Figure 19A is a top view showing an example of a semiconductor device. Figures 19B and 19C are cross-sectional views showing an example of a semiconductor device. Figure 20 is a perspective view showing an example of a display device. Figures 21A and 21B are cross-sectional views showing an example of a display device.Figure 22 is a cross-sectional view showing an example of a display device. Figure 23 is a cross-sectional view showing an example of a display device. Figures 24A, 24B, and 24C are cross-sectional views showing an example of a display device. Figures 25A and 25B are cross-sectional views showing an example of a display device. Figures 26A, 26B, 26C, and 26D are diagrams showing an example of an electronic device. Figures 27A, 27B, 27C, 27D, 27E, and 27F are diagrams showing an example of an electronic device. Figures 28A, 28B, 28C, 28D, 28E, 28F, and 28G are diagrams showing an example of an electronic device. Figure 29 is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figures 30A and 30B are cross-sectional TEM images of a transistor according to an embodiment. Figure 31A is a top view showing an example of a semiconductor device. Figures 31B and 31C are cross-sectional views showing an example of a semiconductor device. Figure 32 is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 33 shows the Id-Vg characteristics of the transistor according to the embodiment. Figures 34A and 34B are cross-sectional TEM images of the transistor according to the embodiment. Figures 35A and 35B are cross-sectional TEM images of the transistor according to the embodiment. Figure 36 shows the Id-Vg characteristics of the transistor according to the embodiment.

[0024] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0025] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for parts that are identical or have similar functions, and repeated explanations are omitted. In addition, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0026] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0027] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0028] In this specification and the drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements that have been given an identifying numeral, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0029] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0030] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0031] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0032] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" can be used interchangeably. The names of the gate and back gate of a transistor can be appropriately rephrased as needed, such as gate electrode and back gate electrode. The gate can also be called the top gate or front gate. The back gate can also be called the bottom gate.

[0033] In this specification, "connection" includes, as an example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0034] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0035] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0036] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0037] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and to the state in a p-channel transistor where it is less than or equal to the threshold voltage.

[0038] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0039] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0040] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0041] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, it may also be said that the "matching or roughly matching top shapes" apply. Furthermore, when the top shapes match or roughly match, it can also be said that the "edges match or roughly match," or "the edges are aligned or roughly aligned."

[0042] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as the taper angle.

[0043] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0044] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0045] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0046] In this specification, a structure in which different light-emitting layers are created using light-emitting devices with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

[0047] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0048] In this specification, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element includes a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other as a common electrode.

[0049] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to return to its original shape.

[0050] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, used after repeated deformation, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by an average adult's hand without requiring excessive force. Furthermore, flexibility can be quantified as the deformation of an object in response to an external force using a testing machine capable of measuring stress-strain (tensile testing machine, compression testing machine, etc.).

[0051] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that are not flexible (which can be called rigid parts).

[0052] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0053] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the same will be described with reference to Figures 1A to 17C. The semiconductor device according to one aspect of the present invention can be suitably used, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0054] <Configuration Example 1> A transistor applicable to a semiconductor device, which is one aspect of the present invention, will be described. A schematic cross-sectional view of the transistor 10 is shown in Figure 1A.

[0055] The transistor 10 is provided on an insulating surface. For example, the transistor 10 can be provided on a substrate (not shown) having an insulating surface. Alternatively, an insulating film can be provided on a substrate (not shown), and the transistor 10 can be provided on the insulating film.

[0056] The transistor 10 has a semiconductor layer 18, an insulating layer 16, an insulating layer 15, a conductive layer 14, and a conductive layer 13. The conductive layer 13, insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14 are stacked in this order.

[0057] An insulating layer 16 is provided on a semiconductor layer 18, and a conductive layer 14 is provided on the insulating layer 16. The conductive layer 14 has a region that overlaps with the semiconductor layer 18 via the insulating layer 16. In the transistor 10, the conductive layer 14 functions as a first gate electrode, and the insulating layer 16 functions as a first gate insulating layer. The conductive layer 14 located above the semiconductor layer 18 can be called the top gate electrode, and the insulating layer 16 can be called the top gate insulating layer.

[0058] An insulating layer 15 is provided on the conductive layer 13, and a semiconductor layer 18 is provided on the insulating layer 15. The conductive layer 13 has a region that overlaps with the semiconductor layer 18 via the insulating layer 15. In the transistor 10, the conductive layer 13 functions as a second gate electrode, and the insulating layer 15 functions as a second gate insulating layer. The conductive layer 13 located below the semiconductor layer 18 can be called the bottom gate electrode, and the insulating layer 15 can be called the bottom gate insulating layer. Furthermore, the conductive layer 13 has a region that overlaps with the conductive layer 14 via the insulating layer 15, the semiconductor layer 18, and the insulating layer 16.

[0059] Figure 1A shows a configuration in which the width of the conductive layer 14 and the width of the conductive layer 13 are the same, but the present invention is not limited to this. The width of the conductive layer 14 and the width of the conductive layer 13 can be different. Also, Figure 1A shows a configuration in which the edge of the conductive layer 14 is in contact with the upper surface of the insulating layer 16, that is, the insulating layer 16 has a region that protrudes beyond the edge of the conductive layer 14. The present invention is not limited to this, and the edges of the insulating layer 16 and the conductive layer 14 can be the same or approximately the same.

[0060] In the semiconductor layer 18, the region overlapping with at least one of the conductive layer 14 and the conductive layer 13 functions as a channel-forming region. For the sake of simplicity, the region of the semiconductor layer 18 that overlaps with the conductive layer 14 is sometimes referred to as the channel-forming region, but a region that does not overlap with the conductive layer 14 but overlaps with the conductive layer 13 can also function as a channel-forming region.

[0061] Transistor 10 has gate electrodes (a first gate electrode and a second gate electrode) on both sides of the channel formation region, and can be described as a dual-gate type transistor. Note that one of the first and second gate electrodes may be referred to as the top gate electrode or front gate electrode (sometimes simply as the gate electrode), and the other as the bottom gate electrode or back gate electrode.

[0062] By providing a back gate electrode, the on-current of the transistor can be increased. Furthermore, by providing a back gate electrode, the potential on the back gate electrode side (also called the back channel side) of the semiconductor layer 18 is fixed, improving the saturation in the Id-Vd characteristic. Additionally, by fixing the potential on the back channel side of the semiconductor layer 18, the threshold voltage shift can be suppressed. Therefore, a transistor with a small drain current (hereinafter also referred to as cutoff current) when the gate voltage (Vg) is 0V can be created, resulting in a semiconductor device with low power consumption.

[0063] In this specification, the term "high saturation" may be used to describe a transistor where the change in current in the saturation region of the Id-Vd characteristic is small.

[0064] The semiconductor material used for the semiconductor layer 18 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities as dopants.

[0065] The crystallinity of the semiconductor material used in the semiconductor layer 18 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0066] For example, silicon can be used for the semiconductor layer 18. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speed. Transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed. Note that transistors using silicon for the channel formation region are sometimes referred to as Si transistors, and transistors using LTPS for the channel formation region are sometimes referred to as LTPS transistors.

[0067] The semiconductor layer 18 preferably has a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties. The band gap of the metal oxide in the semiconductor layer 18 is preferably 2.0 eV or more, and more preferably 2.5 eV or more. Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably small off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, the power consumption of semiconductor devices can be reduced by applying OS transistors. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0068] The metal oxide preferably contains at least indium. For example, indium oxide (also written as indium oxide) can be suitably used for the semiconductor layer 18.

[0069] The semiconductor layer 18 is preferably crystalline. Using a crystalline oxide semiconductor for the semiconductor layer 18 is preferable because it suppresses the degradation of transistor characteristics. The semiconductor layer 18 is preferably highly crystalline, and preferably polycrystalline or monocrystalline. A polycrystalline indium oxide film is preferably used as the semiconductor layer 18, and a monocrystalline indium oxide film is more preferably used.

[0070] Single-crystal films are particularly preferred because they do not have grain boundaries, thus suppressing carrier scattering at grain boundaries and enabling transistors with high field-effect mobility. Compared to microcrystalline and amorphous films, polycrystalline films can reduce carrier scattering and enable transistors with high field-effect mobility. When a polycrystalline film is used for the semiconductor layer 18, it is preferable that the grain size of the crystal grains contained in the semiconductor layer 18 is large. By using a polycrystalline film with large grain size, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, thus enabling transistors with high field-effect mobility. Furthermore, it is preferable that there are few crystal grain boundaries in the channel formation region that intersect with the direction of drain current flow (also known as the channel length direction). Note that even with a polycrystalline film, if there are no crystal grain boundaries in the channel formation region, the same effects as a single-crystal film can be achieved.

[0071] The transistor 10A shown in Figure 1B differs from transistor 10 mainly in that it does not have a conductive layer 13. Transistor 10A has a semiconductor layer 18, an insulating layer 16, an insulating layer 15, and a conductive layer 14. The insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14 are stacked in this order. In transistor 10A, the conductive layer 14 functions as a gate electrode, and the insulating layer 16 functions as a gate insulating layer. By not providing a conductive layer 13, the manufacturing process can be simplified and productivity can be increased. Transistor 10A can be described as a single-gate type transistor. Transistor 10A can also be described as a top-gate type transistor.

[0072] It is preferable to use a material that is difficult for substances to permeate in one or more of the layers constituting the insulating layer 15. This layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to suppress the diffusion of impurities contained below the transistor 10A (for example, the substrate) into the transistor 10A.

[0073] The barrier film can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, and a silicon nitride oxide. Typically, the barrier film can be made from one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide.

[0074] Figure 1B shows a configuration in which an insulating layer 15 is provided, but the present invention is not limited to this. A configuration without an insulating layer 15 is also possible. By omitting the insulating layer 15, the process can be simplified and productivity can be increased.

[0075] Furthermore, transistor 10A and transistor 10 can be mounted on the same substrate by sharing some of the manufacturing processes. In that case, by also providing an insulating layer 15 to transistor 10A, the processes other than the formation of the conductive layer 13 can be shared, thereby increasing productivity.

[0076] The transistor 10B shown in Figure 1C differs from transistor 10 mainly in that it does not have a conductive layer 14. Transistor 10B has a semiconductor layer 18, an insulating layer 16, an insulating layer 15, and a conductive layer 13. The conductive layer 13, insulating layer 15, semiconductor layer 18, and insulating layer 16 are stacked in this order. In transistor 10B, the conductive layer 13 functions as a gate electrode, and the insulating layer 15 functions as a gate insulating layer. By not providing a conductive layer 14, the manufacturing process can be simplified and productivity can be increased. Transistor 10B can be described as a single-gate type transistor. Transistor 10B can also be described as a bottom-gate type transistor.

[0077] The insulating layer 16 functions as a protective layer. Furthermore, one or more layers constituting the insulating layer 16 may be provided with a layer that functions as a barrier film. By providing a layer that functions as a barrier film, the diffusion of impurities contained in the layer above the transistor 10B into the transistor 10B can be suppressed. For details on the barrier film, please refer to the previous description.

[0078] Figure 1C shows a configuration in which an insulating layer 16 is provided, but the present invention is not limited to this. A configuration without an insulating layer 16 is also possible. By omitting the insulating layer 16, the process can be simplified and productivity can be increased.

[0079] Furthermore, transistor 10B and transistor 10 can be mounted on the same substrate by sharing some of the manufacturing processes. In this case, by providing an insulating layer 16 to transistor 10B as well, the processes other than the formation of the conductive layer 14 can be shared, thereby increasing productivity. Also, transistor 10B, transistor 10A, and transistor 10 can be mounted on the same substrate by sharing some of the manufacturing processes.

[0080] The semiconductor layer 18 can be a single layer or a stacked structure of two or more layers.

[0081] <Configuration Example 1-1> A semiconductor device that is one aspect of the present invention will be described in more detail.

[0082] Figure 2A shows a top view (also called a plan view) of a semiconductor device 20 according to one aspect of the present invention. Figure 2B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 2A, and Figure 2C shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2. Note that in Figure 2A, some components of the semiconductor device 20 (such as the gate insulating layer) are omitted. In subsequent drawings, as in Figure 2A, some components of the top view of the semiconductor device will also be omitted.

[0083] The semiconductor device 20 has a transistor 100. The transistor 100 has a conductive layer 103 on a substrate 102, an insulating layer 105 on the conductive layer 103, a semiconductor layer 108 on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108, and a conductive layer 104 on the insulating layer 106.

[0084] The semiconductor device 20 also has layers 121a and 121b on the insulating layer 105. The semiconductor layer 108 has a region located on layer 121a and a region located on layer 121b. It is preferable that the semiconductor layer 108 is in contact with the upper surface of the insulating layer 105, the upper surface of layer 121a, and the upper surface of layer 121b, respectively.

[0085] The insulating layer 106 has a region that is in contact with the upper surface of the semiconductor layer 108. The conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. In the transistor 100, the conductive layer 104 functions as a first gate electrode, and the insulating layer 106 functions as a first gate insulating layer.

[0086] The conductive layer 103 has a region that overlaps with the semiconductor layer 108 via the insulating layer 105. The conductive layer 103 functions as a second gate electrode, and the insulating layer 105 functions as a second gate insulating layer. Furthermore, the conductive layer 103 has a region that overlaps with the conductive layer 104 via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106.

[0087] In the semiconductor layer 108, a channel formation region is formed in a region that overlaps with at least one of the conductive layer 104 and the conductive layer 103.

[0088] The transistor 100 has gate electrodes (a first gate electrode and a second gate electrode) on both sides of the channel formation region, and can be described as a dual-gate type transistor.

[0089] The conductive layer 103, insulating layer 105, semiconductor layer 108, insulating layer 106, and conductive layer 104 correspond to the conductive layer 13, insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14 shown in Figure 1A, etc. For details on the conductive layer 103, insulating layer 105, semiconductor layer 108, insulating layer 106, and conductive layer 104, refer to the descriptions relating to the conductive layer 13, insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14.

[0090] An insulating layer 195 is provided on the conductive layer 104 and the insulating layer 106, and an insulating layer 218 is provided on the insulating layer 195. The insulating layer 195 and the insulating layer 218 each function as protective layers for the transistor 100. It is also possible to omit the insulating layer 218.

[0091] The insulating layer 195 has openings 147a and 147b that reach the semiconductor layer 108. A conductive layer 112a is provided so as to cover opening 147a. A conductive layer 112b is provided so as to cover opening 147b. An insulating layer 218 is provided on the conductive layer 112a, conductive layer 112b and insulating layer 195. As shown in Figures 2D and 2E, it is also possible to configure the openings 147a and 147b to penetrate the semiconductor layer 108 and reach layers 121a and 121b. By using the configuration shown in Figures 2D and 2E, even when the thickness of the semiconductor layer 108 is reduced, for example, layers 121a and 121b can be used to suitably reduce the resistance between the semiconductor layer 108 and the conductive layers 112a and 112b.

[0092] Transistor 100 can be described as a TGSA (Top Gate Self-Aligned) type transistor. In a TGSA type transistor, the physical distance between conductive layers 112a and 112b, which function as one and the other source and drain electrodes, and conductive layer 104, which functions as the gate electrode, can be increased, thereby reducing the parasitic capacitance between them.

[0093] The conductive layers 104, 103, 112a, and 112b can be made of the same material. Alternatively, at least one of them can be made of a different material.

[0094] Here, for example, copper or a copper-containing alloy is used as the conductive layer 104. Copper and copper-containing alloys have extremely low resistance, and by using them as the conductive layer 104, the operating speed of the semiconductor device can be increased when the conductive layer 104 is used as wiring. In addition, power consumption may be reduced.

[0095] Furthermore, when copper is used for the conductive layer 104, it is preferable to have a laminated structure for the conductive layer 104, with conductive layers that are resistant to oxidation placed above and below the copper layer. For example, a structure can be formed in which a copper layer is sandwiched between layers made of titanium. Figures 18A and 18B show an example in Figures 2B and 2C in which the conductive layer 104 is a three-layer laminated structure consisting of conductive layer 104a, conductive layer 104b on conductive layer 104a, and conductive layer 104c on conductive layer 104b. Here, for example, copper can be used for conductive layer 104b, and materials that are resistant to oxidation can be used for conductive layer 104a and conductive layer 104c. It is preferable that the sides of conductive layer 104a, conductive layer 104b, and conductive layer 104c are tapered. This can improve the coverage of the layer provided on top of them. The taper angles of each conductive layer may be different from each other. For example, the taper angles can be made different depending on the etching conditions. The taper angle is, for example, greater than 0 degrees and less than 90 degrees.

[0096] When the conductive layer 104 has a laminated structure, it is preferable that the thickness of the copper layer (for example, the conductive layer 104b in Figures 18A and 18B) is 30% or more, with the total thickness of the conductive layer 104 being 100%. This allows for a suitable reduction in the electrical resistance of the conductive layer 104.

[0097] Furthermore, in one embodiment of the present invention, the semiconductor device may also use different materials for the conductive layer 112a and conductive layer 112b from the material used for the conductive layer 104.

[0098] As an example, a configuration in which materials other than copper are used for conductive layers 112a and 112b will be described. For example, a metal or metal alloy having one or more selected from molybdenum, aluminum, titanium, tungsten, tantalum, and manganese can be used for conductive layers 112a and 112b.

[0099] Alternatively, for example, metal oxides or metal nitrides can be used as conductive layers 112a and 112b.

[0100] When the conductive layer 112a and conductive layer 112b are in a laminated structure, for example, the thickness of the layer using the above material can be 30% or more of the total thickness, with the total thickness being 100%.

[0101] Figures 2A and 2B show the width Lg of the gate electrode.

[0102] Furthermore, in a TGSA-type transistor, if the resistance of the source and drain regions in the semiconductor layer 108 is not sufficiently reduced, the resistance between the conductive layer 112a and the channel formation region, and between the conductive layer 112b and the channel formation region will increase, causing a decrease in the on-current of the transistor 100. In particular, when the thickness of the semiconductor layer 108 is thin, it may be difficult to reduce the resistance of the source and drain regions.

[0103] In particular, when a metal oxide is used as the semiconductor layer, thinning the semiconductor layer 108 can result in a highly reliable transistor with good test results in GBT (Gate Bias Temperature) stress tests, where an electric field is applied to the gate and the transistor is held at a high temperature. Specifically, for example, excellent results can be obtained in PBTS (Positive Bias Temperature Stress) tests, where a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and the transistor is held at a high temperature, and in NBTIS (Negative Bias Temperature Illumination Stress) tests, where light is irradiated and a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature, which is preferable.

[0104] The thickness of the semiconductor layer 108 is preferably, for example, 1 nm to 30 nm, more preferably 2 nm to 30 nm, more preferably 2 nm to 20 nm, more preferably 4 nm to 20 nm, and more preferably 4 nm to 10 nm.

[0105] In one embodiment of the present invention, a semiconductor device can realize a transistor that is highly reliable and has high driving capability.

[0106] In one embodiment of the present invention, by providing layers 121a and 121b, the resistance of the source region and drain region of the transistor can be reduced, thereby realizing a transistor with excellent characteristics.

[0107] Preferably, the region where semiconductor layer 108 and layer 121a are stacked, and the region where semiconductor layer 108 and layer 121b are stacked, have lower resistance than the channel formation region of semiconductor layer 108.

[0108] A conductive layer can be used as layer 121a and layer 121b.

[0109] Furthermore, materials that can be used as semiconductor layer 108 can also be applied to layers 121a and 121b. For example, indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), aluminum zinc oxide (Al-Zn oxide, AZO) Other materials that can be used include indium aluminum zinc oxide (also written as In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.

[0110] Furthermore, increasing the thickness of layers 121a and 121b is preferable because it can reduce the electrical resistance of the layers. In particular, when using materials that can be used as semiconductor layers 108 for layers 121a and 121b, it is preferable to increase the thickness of layers 121a and 121b. For example, it is preferable that the thickness of layers 121a and 121b be greater than that of semiconductor layer 108.

[0111] When using metal oxides containing indium as layers 121a and 121b, their thickness is preferably, for example, 20 nm or more.

[0112] It is preferable that layers 121a and 121b are provided in contact with the lower surface of the semiconductor layer 108. When the semiconductor layer 108 is in contact with layers 121a and 121b, the resistance of the semiconductor layer 108 may be reduced in the contacted region. Furthermore, by using highly conductive materials for layers 121a and 121b, they can function as electrodes or wiring. This makes it possible to reduce resistance between the semiconductor layer of the transistor and the source electrode, and between the semiconductor layer and the drain electrode.

[0113] For example, materials having a metal and oxygen can be used as layers 121a and 121b. For example, conductive metal oxides (also called oxide conductors (OC)) can be used as layers 121a and 121b. When a metal oxide is used as the semiconductor layer 108, using oxide conductors as layers 121a and 121b allows for the formation of a good junction between the semiconductor layer 108 and layer 121a (or layer 121b), thereby reducing contact resistance. Examples of oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), gallium-doped zinc oxide, and In-Ga-Zn oxide.

[0114] Furthermore, for layers 121a and 121b, for example, materials having one or more metals, materials having one or more metals and nitrogen, etc., can be used. For layers 121a and 121b, for example, metals, metal alloys, and metal nitrides can be used. Examples of metals include chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium. Examples of metal nitrides include tantalum nitride and titanium nitride.

[0115] Layers 121a and 121b can function as nuclei or seeds to enhance the crystallinity of the semiconductor layer 108. In such cases, layers 121a and 121b can also be called seed layers, seed crystals, or crystal nuclei. For example, when a metal oxide is used as the semiconductor layer 108, using metal oxides as layers 121a and 121b can sometimes enhance the crystallinity of the semiconductor layer 108.

[0116] When a metal oxide having a cubic crystal structure is used as the semiconductor layer 108, for example, by using metal oxides having a cubic crystal structure as layers 121a and 121b, they can be suitably made to function as seed crystals. Alternatively, materials having a hexagonal or trigonal crystal structure can be used as layers 121a and 121b. Examples of metal oxides having a cubic crystal structure include indium oxide and indium tin oxide. Examples of metal oxides having a hexagonal crystal structure include zinc oxide, indium gallium oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium gallium zinc oxide, or indium tin zinc oxide.

[0117] Furthermore, metal oxides that readily adopt a CAAC (c-axis aligned crystal) structure can be used as layers 121a and 121b. By forming indium oxide on a metal oxide having a CAAC structure, indium oxide with a crystal orientation <111> oriented perpendicular to the surface being formed can be formed as the semiconductor layer 108. Examples of metal oxides that readily adopt a CAAC structure include indium gallium zinc oxide and indium tin zinc oxide.

[0118] Furthermore, layers 121a and 121b can each be a laminated structure of two or more layers. The materials described above can be applied to each layer.

[0119] When layers 121a and 121b form a laminated structure, the uppermost layer of the laminated structure is a layer that can come into contact with the semiconductor layer 108. Therefore, it is preferable to use, for example, a metal oxide as the uppermost layer of the laminated structure.

[0120] As an example of the case where the layers 121a and 121b have a two-layer stacked structure, a metal, an alloy of a metal, or a metal nitride can be used for the lower layer, and a metal oxide can be used for the upper layer.

[0121] The semiconductor device according to one aspect of the present invention has layers 121a and 121b provided so as to contact the lower layer of the semiconductor layer 108, so that a low-resistance region functioning as a source region and a drain region can be formed in the semiconductor layer 108 without introducing impurities into the semiconductor layer 108 using an ion implantation method or the like.

[0122] Further, when a metal oxide is used as the semiconductor layer 108, the metal oxide may function as a low-resistance region because the metal oxide has a defect in which hydrogen enters an oxygen deficiency (hereinafter sometimes referred to as V Ｏ H). Therefore, the source region and the drain region of the semiconductor layer 108 may have a high concentration of V Ｏ H. Further, by supplying hydrogen to the regions that become the source region and the drain region in the semiconductor layer 108, an oxygen deficiency (V Ｏ ) occurs, and V Ｏ H occurs by entering the oxygen deficiency (V Ｏ ), so that the electrical resistance of the region can be efficiently reduced. On the other hand, in the channel formation region, it is preferable that the concentration of oxygen deficiency (V Ｏ ) and V Ｏ H is low. By reducing the concentration of V Ｏ and V Ｏ H in the channel formation region, the electrical characteristics of the transistor can be stabilized and the reliability can be improved. The semiconductor device according to one aspect of the present invention can selectively reduce the resistance of a region by providing the layers 121a and 121b so as to overlap with the region that is desired to function as the source region and the drain region in the semiconductor layer 108 of the transistor.

[0123] By providing layers 121a and 121b in contact with the semiconductor layer 108, oxygen vacancies may occur in the semiconductor layer 108 in the regions in contact with these conductive layers. The regions where oxygen vacancies occur can sometimes function as source and drain regions. For example, as mentioned earlier, hydrogen can enter the oxygen vacancies to create V Ｏ This generates H, which allows for a favorable reduction in the resistance of the semiconductor layer 108.

[0124] The insulating layer 195 can be provided in contact with the semiconductor layer 108. The region of the semiconductor layer 108 in contact with the insulating layer 195, and the region near it, may function as a low-resistance region. In particular, hydrogen supplied from the insulating layer 195 enters the oxygen vacancy created by the contact between layers 121a and 121b, thus V Ｏ This generates H, which allows for a favorable reduction in the resistance of the semiconductor layer 108.

[0125] For example, it is preferable to use an insulating layer 195 that has the function of supplying hydrogen. An insulating layer that has the function of supplying hydrogen is, for example, an insulating layer that contains hydrogen that is desorbed by heating. It is also preferable that the insulating layer 195 has barrier properties against moisture. Insulating layers containing nitrogen, such as silicon nitride, silicon nitride oxide, and silicon oxynitride, can function as insulating layers with barrier properties against moisture and can therefore be suitably used as the insulating layer 195.

[0126] A layer containing nitrogen and silicon can be used as the insulating layer 195. Alternatively, a layer containing nitrogen, oxygen, and silicon can be used as the insulating layer 195.

[0127] Silicon nitride, silicon nitride oxide, silicon oxide nitride, and the like can be used as the insulating layer 195.

[0128] The insulating layer 195 can function as an interlayer insulating layer. By increasing the thickness of the insulating layer 195, for example, parasitic capacitance between the conductive layer 104 and the conductive layer, electrodes, wiring, etc. formed on the insulating layer 195 can be reduced. Preferably, the thickness of the region of the insulating layer 195 that overlaps with the conductive layer 104 is greater than the thickness of the region of the insulating layer 106 that overlaps with the conductive layer 104. Figure 3A shows a thickness T195 as an example of the thickness of the region of the insulating layer 195 that overlaps with the conductive layer 104, and a thickness T106 as an example of the thickness of the region of the insulating layer 106 that overlaps with the conductive layer 104.

[0129] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0130] The hydrogen concentration of the insulating layer 195 can be measured, for example, using secondary ion mass spectrometry (SIMS). The hydrogen concentration of the insulating layer 195 is 2.0 × 10⁻⁶. ２０ atoms / cm ３ Preferably, it is 5.0 × 10 ２０ atoms / cm ３ It is more preferable that the above conditions are met.

[0131] Furthermore, while it is preferable that hydrogen is supplied to the source and drain regions of the semiconductor layer 108, it is preferable that the hydrogen concentration in the channel formation region be reduced compared to the source and drain regions. The hydrogen concentration of the insulating layer 195 is 1.0 × 10⁻⁶. ２２ atoms / cm ３ By setting it to less than 2.0 × 10⁻¹⁰, for example, hydrogen can be suitably supplied to the source and drain regions, and the switching characteristics of the transistor can be improved. The hydrogen concentration of the insulating layer 195 is 2.0 × 10⁻¹⁰. ２０ atoms / cm ３ The above 1.0 x 10 ２２ atoms / cm ３ Less than 5.0 × 10 ２０ atoms / cm ３ The above 1.0 x 10 ２２atoms / cm ３ Less than 5.0 × 10 ２０ atoms / cm ３ The above 5.0 x 10 ２１ atoms / cm ３ Less than is even preferable.

[0132] An insulating layer that has the function of supplying hydrogen can be formed, for example, using plasma CVD. SiH is used as the deposition gas. ４ and NH ３ By using this, it is possible to form silicon nitride containing hydrogen in the film. ４ and NH ３ In addition to N ２ You can also use this.

[0133] In addition to the gas mentioned above, N ２ By using O, it is possible to form silicon nitride oxide or silicon oxynitride oxide containing hydrogen in the film. ４ NH ３ and N ２ By using O to form silicon nitride or silicon oxynitride, for example, an insulating layer having the above hydrogen concentration can be formed. ４ NH ３ and N ２ In addition to O, N ２ You can also use this.

[0134] The semiconductor layer 108 has a region 108P that overlaps with layer 121a, a region 108Q that overlaps with layer 121b, and a region 108i sandwiched between regions 108P and 108Q. Regions 108P and 108Q can function as one or the other of a source region and a drain region, respectively. In the semiconductor layer 108, a channel formation region is formed in the region that overlaps with at least one of the conductive layer 104 and the conductive layer 103. Region 108i overlaps with the conductive layer 104 that functions as a gate and can function as a channel formation region. Region 108i also overlaps with the conductive layer 103 that functions as a second gate.

[0135] Layers 121a and 121b are provided spaced apart. In the semiconductor layer 108, at least a portion of the region between the region overlapping with layer 121a and the region overlapping with layer 121b can function as a channel formation region.

[0136] Furthermore, layers 121a and 121b may have regions that overlap with the conductive layer 104, as shown in Figure 2B, etc. Also, layers 121a and 121b may have regions that overlap with the conductive layer 103, as shown in Figure 2B, etc.

[0137] In the configuration shown in Figure 2B, etc., region 108P and region 108Q each have a region that overlaps with the conductive layer 104. The regions in regions 108P and 108Q that overlap with the conductive layer 104 may function, for example, as channel-forming regions. Also, if the resistance of the region is low, the region may function as either a source region or a drain region. Furthermore, if the resistance of the region is lower than that of the channel-forming region, the region can function, for example, as a buffer region for mitigating the drain electric field.

[0138] Furthermore, the region where the conductive layer 103 and layer 121a overlap, and the region where the conductive layer 103 and layer 121b overlap, can each function as a buffer region for mitigating the drain electric field.

[0139] Furthermore, in the manufacturing process of a transistor according to one embodiment of the present invention, it is preferable to form the insulating layer 195 such that it has a region in contact with the semiconductor layer 108. It is also preferable that the insulating layer 195 has a function of releasing hydrogen. This allows hydrogen from the insulating layer 195 to diffuse into the region of the semiconductor layer 108 that is in contact with the insulating layer 195. As a result, the resistance of that region can be reduced. In addition, by performing heat treatment after forming the insulating layer 195, the diffusion of hydrogen into the semiconductor layer 108 and the reduction in resistance due to the entry of hydrogen into the semiconductor layer 108 may be promoted.

[0140] Furthermore, plasma-based methods such as plasma CVD and sputtering can be used to deposit the insulating layer 195, and these methods may have the effect of plasma treatment on the semiconductor layer 108. Therefore, by depositing the insulating layer 195 using these methods, it may be possible to introduce impurities into the semiconductor layer 108 through plasma treatment. By introducing these impurities, a low-resistance region can be provided in the semiconductor layer 108.

[0141] In the configuration example shown in Figure 2B, etc., the insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 106, the upper and side surfaces of the conductive layer 104, and the upper surface of the insulating layer 105.

[0142] The insulating layer 195 has regions in contact with region 108P and region 108Q. The insulating layer 195 also has an opening 147a reaching region 108P and an opening 147b reaching region 108Q. A conductive layer 112a is provided so as to cover the opening 147a. At the opening 147a, the conductive layer 112a is in contact with region 108P and connected to region 108P. A conductive layer 112b is provided so as to cover the opening 147b. At the opening 147b, the conductive layer 112b is in contact with region 108Q and connected to region 108Q.

[0143] Figure 2B and others show a configuration in which the edge of the insulating layer 106 is located outside the edge of the conductive layer 104. Therefore, the semiconductor layer 108 has a region covered by both the conductive layer 104 and the insulating layer 106, and a region located outside of that region that is not covered by the conductive layer 104 but is covered by the insulating layer 106.

[0144] In Figure 2B, etc., the region in region 108P that is in contact with the insulating layer 195 is shown as region 108P1, and the region inside that region that is covered by the insulating layer 106 is shown as region 108P2. Similarly, in region 108Q, the region in contact with the insulating layer 195 is shown as region 108Q1, and the region inside that region that is covered by the insulating layer 106 is shown as region 108Q2. The insulating layer 195 has an opening, and conductive layers 112a and 112b are provided to fill this opening.

[0145] In Figure 2B and other figures, the region in contact with the conductive layer 112a is also shown as region 108P1, and the region in contact with the conductive layer 112b is also shown as region 108Q1. In these regions, for example, after the insulating layer 195 is provided on the region, the insulating layer 195 is removed when forming the openings 147a and 147b.

[0146] Since regions 108P2 and 108Q2 are not in contact with the insulating layer 195, their hydrogen concentration may be lower than that of regions 108P1 and 108Q1. Therefore, regions 108P2 and 108Q2 may have higher resistance than regions 108P1 and 108Q1.

[0147] Figures 3A and 3B show enlarged views of Figure 2B. Figure 3A is an enlarged view including regions 108P1 and 108P2, and Figure 3B is an enlarged view including regions 108Q1 and 108Q2. In region 108P2, the region overlapping with the conductive layer 104 is designated as region 108P2_2, and the region outside of it is designated as region 108P2_1. Similarly, in region 108Q2, the region overlapping with the conductive layer 104 is designated as region 108Q2_2, and the region outside of it is designated as region 108Q2_1.

[0148] In the semiconductor layer 108, it is preferable that the resistance of the semiconductor layer 108 is low in the region outside the area that overlaps with the conductive layer 104. If the resistance is high, it will lead to a decrease in the on-current of the transistor. In addition, the resistance value of the semiconductor layer 108 may change in steps in the region outside the area that overlaps with the conductive layer 104. For example, the impurity concentration may increase in steps or in a continuous gradient as it moves away from the region close to the channel formation region. This may reduce the gate electric field near the edge of the conductive layer 104 that functions as a gate, and improve the reliability of the transistor.

[0149] Preferably, the semiconductor layer 108 has a lower surface in contact with layer 121a and an upper surface in contact with the insulating layer 195, and has a region sandwiched between layer 121a and the insulating layer 195. Similarly, preferably, the semiconductor layer 108 has a lower surface in contact with layer 121b and an upper surface in contact with the insulating layer 195, and has a region sandwiched between layer 121b and the insulating layer 195. The upper surface of the semiconductor layer 108 may also be in contact with one or both of the conductive layers 112a and 112b instead of the insulating layer 195. In such a region, the V by layer 121a or layer 121b Ｏ The combined contribution of the hydrogen from the insulating layer 195 allows for a lower resistance value. Furthermore, if an oxygen vacancy occurs when layer 121a or layer 121b comes into contact with the semiconductor layer 108, hydrogen supplied from the insulating layer 195 enters the oxygen vacancy, thus reducing the resistance value. Ｏ H is generated, and the resistance value can be suitably reduced.

[0150] Furthermore, in the semiconductor layer 108, in regions where only layer 121a (or layer 121b) and the insulating layer 195 are in contact, the resistance may be higher compared to regions where both are in contact. Such regions may function as buffer regions that mitigate the drain electric field.

[0151] Figure 3A shows the overlapping width L1a of conductive layer 104 and layer 121a. Figure 3B shows the overlapping width L1b of conductive layer 104 and layer 121b. By increasing the widths L1a and L1b, the area that functions as a buffer region can be made larger, thereby improving the reliability of the transistor. Also, the widths L1a and L1b may be different values, and the difference in these values ​​depends, for example, on the positional accuracy of the mask in the photolithography process.

[0152] As described above, in one aspect of the present invention, the semiconductor device has layers 121a and 121b in contact with the semiconductor layer 108 of the transistor, thereby reducing the resistance of the semiconductor layer 108 without introducing impurities. In the transistor manufacturing process of one aspect of the present invention, the transistor can be manufactured without using ion implantation or other methods for introducing impurities, thus enabling the production of transistors at a low cost. Furthermore, in the transistor manufacturing process of one aspect of the present invention, the transistor can be manufactured without using methods that make it difficult to scale up equipment such as ion implantation, so it can be easily applied to production processes using large substrates.

[0153] Furthermore, as described above, in one embodiment of the present invention, by providing an insulating layer 195 in contact with the semiconductor layer 108 of the transistor, impurities can be introduced into the semiconductor layer 108 by utilizing the diffusion of impurities from the insulating layer 195. Introducing impurities using this method is more productive and preferable compared to introducing impurities using methods such as ion implantation.

[0154] Furthermore, when forming a low-resistance region in the semiconductor layer 108, impurities may be introduced using methods such as ion implantation. For example, by providing layers 121a and 121b in contact with the semiconductor layer 108 and further introducing impurities, it may be possible to more effectively control the resistance of the semiconductor layer 108.

[0155] By using the conductive layer 104, which functions as a gate electrode, as a mask and supplying impurities to the semiconductor layer 108, regions that function as a source region and a drain region can be formed in a self-aligned manner. Alternatively, the insulating layer 106, which functions as a gate insulating layer, can be used as a mask. In regions that do not overlap with either the conductive layer 104 or the insulating layer 106, for example, the impurity concentration will be higher than in regions that overlap with the insulating layer 106 but not with the conductive layer 104. A higher impurity concentration allows for lower electrical resistance.

[0156] By introducing impurities, regions containing impurities can be created in the semiconductor layer 108, thereby lowering the electrical resistance of those regions. For example, regions 108P1 and 108Q1 can be configured to contain impurities. Regions 108P2_1 and 108Q2_1 can also be configured to contain impurities. The impurity concentrations in regions 108P and 108Q are higher than the impurity concentrations in the channel-forming region (for example, region 108i in Figure 2B). Furthermore, in regions 108P2_1 and 108Q2_1, for example, the impurity concentrations are higher than in region 108i and lower than in regions 108P and 108Q. The elements contained in the impurities (hereinafter also referred to as the first element) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the first element.

[0157] For supplying impurities, methods such as plasma treatment or treatment utilizing thermal diffusion by heating can be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As a device for generating plasma, for example, a dry etching device, an ashing device, a plasma CVD device, or a high-density plasma CVD device can be used.

[0158] When hydrogen is used as the first element, by performing plasma processing in an atmosphere containing a hydrogen-containing gas using a plasma CVD apparatus, hydrogen can be supplied to regions of the semiconductor layer 108 that do not overlap with the conductive layer 104. This makes it possible to form regions 108P and 108Q containing impurities. Furthermore, by using a plasma CVD apparatus for supplying impurities and depositing the insulating layer 195, the supply of impurities and the deposition of the insulating layer 195 can be performed continuously within the apparatus, thereby increasing productivity. Moreover, productivity can be further increased by performing the supply of impurities and the deposition of the insulating layer 195 continuously in the same processing chamber within the apparatus.

[0159] The method of supplying impurities is not limited to this, and for example, ion implantation can be suitably used. Ion implantation allows for highly precise control of the concentration profile in the depth direction by controlling the ion acceleration energy and dose amount. Furthermore, by using an ion implantation method that ionizes the source gas and supplies the ions by mass separation, it is possible to supply ions of a specific mass, thereby increasing the purity of the supplied impurities. Alternatively, productivity can be increased by using an ion implantation method that supplies ions without mass separation. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that the method of supplying ions by mass separation is sometimes called ion implantation, and the method of supplying ions without mass separation is sometimes called ion doping.

[0160] When an element that readily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 108 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V) exist in the semiconductor layer 108. Ｏ ) occurs. If an element that becomes stable when bonded with oxygen is used as the first element, the first element in the semiconductor layer 108 exists stably in an oxidized state, so it is less likely to desorb due to heat applied during the semiconductor device manufacturing process, and the electrical resistance of regions 108P and 108Q can be kept low. For this reason, it is preferable to use an element as the first element in which its oxide can exist as a solid at least at the temperature during the manufacturing process. Boron and phosphorus, or both, can be suitably used as the first element.

[0161] When boron is used as the first element, boron contained in regions 108P and 108Q can exist in a state bonded with oxygen. This is evident in X-ray photoelectron spectroscopy (XPS, or ESCA) analysis, B ２ O ３ This can be confirmed by observing spectral peaks caused by bonding. Furthermore, in XPS analysis, spectral peaks caused by the element boron in its elemental state may not be observed, or their intensity may be extremely low, almost at background levels.

[0162] In supplying impurities, it is preferable to adjust the supply conditions so that the concentration of impurities is highest on the surface of the semiconductor layer 108, or in a region close to the surface.

[0163] The raw material used to supply impurities can, for example, be a gas containing the first element. When supplying boron, typically B ２ H ６ Gas, or BF ３ One or more gases can be used. Also, when supplying phosphorus, typically pH ３ Gases can be used. Alternatively, gases obtained by diluting these source gases with noble gases can also be used.

[0164] For example, CH4 is used as a raw material for supplying impurities. ４ , N ２ NH ３ , AlH ３ AlCl ３ SiH ４ Si ２ H ６ F ２ HF, H ２ , (C ５ H ５ ) ２ Mg and noble gases can be used. The raw materials are not limited to gases; solids or liquids can also be heated and vaporized for use.

[0165] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the semiconductor layer 108. Note that impurities may also be supplied to regions of the insulating layer 105 that do not overlap with the conductive layer 104, resulting in those regions containing impurities.

[0166] As shown in Figure 2B and other figures, it is preferable that the sides of the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 each have a tapered shape. This improves the coverage of the layers provided on the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 (for example, the insulating layer 195), and suppresses the occurrence of defects such as stepped breaks or porosity in these layers.

[0167] Furthermore, for example, because the conductive layer 104 has a tapered shape, the thickness of the conductive layer 104 becomes thinner, especially near the edges. In regions where the thickness of the conductive layer 104 is thin, the masking effect in introducing impurities is weakened. Therefore, although the impurity concentration in the region of the semiconductor layer 108 that overlaps with the conductive layer 104 is lower than in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104, impurities may still be introduced. The region in which impurities have been introduced is a region that overlaps with the conductive layer 104 and may function as a buffer region that mitigates the drain electric field.

[0168] Furthermore, for example, because the insulating layer 106 has a tapered shape, the thickness of the insulating layer 106 may become thinner, especially near the edges, and the impurity concentration may become higher.

[0169] The conductive layer 103 preferably has a region that protrudes from the edge of the conductive layer 104. This enhances the effect of making it difficult for electric fields generated outside the transistor to act on the channel formation region (also known as the electric field shielding effect).

[0170] The conductive layer 103 can be configured to be connected to either the conductive layer 112a or the conductive layer 112b. For example, by providing openings in the insulating layer 195 and the insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 112a so as to cover these openings, the conductive layer 103 and the conductive layer 112a can be in contact. By connecting the conductive layer 112a and the conductive layer 103, the source electrode and the drain electrode and the back gate electrode can be brought to the same potential. For example, when the conductive layer 112a functions as the source electrode, a shift in the threshold voltage of the transistor 100 can be suppressed. Furthermore, the reliability of the transistor 100 can be improved.

[0171] The conductive layer 103 can be configured to be connected to the conductive layer 104. For example, by providing openings in the insulating layer 106 and the insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 104 so as to cover the openings, the conductive layer 103 and the conductive layer 104 can be in contact. By connecting the gate electrode and the back gate electrode, the back gate electrode and the gate electrode can be brought to the same potential, and the on-current of the transistor 100 can be increased.

[0172] <Configuration Example 1-2> Figures 4A to 4C show configuration examples different from those shown in Figures 2A to 2C. Figure 4A is a top view of a semiconductor device 20A, which is one embodiment of the present invention. Figure 4B is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 4A, and Figure 4C is a cross-sectional view of the section along the dashed-dotted line B1-B2.

[0173] The semiconductor device 20A has a transistor 100A. Transistor 100A differs from transistor 100 shown in Figure 2A, etc., mainly in that it does not have a conductive layer 103. By not providing the conductive layer 103, the manufacturing process can be simplified and productivity can be increased. In transistor 100A, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. Transistor 100A can be described as a single-gate type transistor. Transistor 100A can also be described as a top-gate type transistor.

[0174] <Configuration Example 1-3> Different configuration examples from those shown in Figures 2A to 2C are shown in Figures 5A to 5C. Figure 5A is a top view of a semiconductor device 20B, which is one embodiment of the present invention. Figure 5B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 5A, and Figure 5C is a cross-sectional view of the section along the dashed line B1-B2.

[0175] The semiconductor device 20B has a transistor 100B. Transistor 100B differs mainly from transistor 100 shown in Figure 2A, etc., in that it does not have a conductive layer 104. By not providing the conductive layer 104, the manufacturing process can be simplified and productivity can be increased. In transistor 100B, the conductive layer 103 functions as a gate electrode, and the insulating layer 105 functions as a gate insulating layer. Transistor 100B can be described as a single-gate type transistor. Transistor 100B can also be described as a bottom-gate type transistor. Note that in transistor 100B, the insulating layer 106 does not necessarily have to function as a gate insulating layer of the transistor. Furthermore, by providing the insulating layer 106, it is possible to configure the device so that the insulating layer 195 does not come into contact with the channel formation region of the semiconductor layer 108. For example, if a layer that has the function of supplying hydrogen is used as the insulating layer 195, the insulating layer 106 can function as a layer that blocks the supply of hydrogen to the channel formation region. Therefore, in transistor 100B, it is preferable that the insulating layer 106 has a hydrogen blocking function. Furthermore, increasing the thickness of the insulating layer 106 can enhance the blocking function. For example, in transistor 100B, the insulating layer 106 can be 5 nm or more, or 10 nm or more, or 20 nm or more.

[0176] <Modification 1-1> Figures 6A and 6B show modified versions of Figures 2A and 2B. Figure 6A is a top view of a semiconductor device 20, which is one embodiment of the present invention. Figure 6B is a cross-sectional view of the cross-section along the dashed line A1-A2 shown in Figure 6A. Figure 6B shows a configuration in which the edge of the insulating layer 106 coincides with, or roughly coincides with, the edge of the conductive layer 104. More specifically, the edge of the upper surface of the insulating layer 106 coincides with the edge of the lower surface of the conductive layer 104. For example, by forming the conductive layer 104 and the insulating layer 106 using the same mask, and using a condition during formation in which the edge of the formed layer does not recede inward compared to the edge of the mask, the configurations shown in Figures 6A and 6B can be produced. On the other hand, for example, by using a condition in which the edge of the conductive layer 104 recedes further than the mask during formation, configurations like those in Figures 2A to 2C may be formed.

[0177] Figures 6A and 6B also show examples of configurations in which the edges of semiconductor layer 108 and layer 121a, and the edges of semiconductor layer 108 and layer 121b are aligned. Such configurations can be fabricated, for example, by removing the region that overlaps with region 108i in the conductive film that will become layers 121a and 121b, and then forming layers 121a and 121b using a mask for forming the semiconductor layer 108.

[0178] Figure 6C shows a modified example of Figure 6B. As shown in Figure 6C, the semiconductor layer 108 can also be configured to cover the edges of layer 121a and layer 121b. This configuration increases the contact area between the semiconductor layer 108 and layer 121a, and between the semiconductor layer 108 and layer 121b.

[0179] <Modification 1-2> Figures 7A to 7C show modifications of Figures 2A to 2C. Figure 7A is a top view of a semiconductor device 20 according to one embodiment of the present invention, Figure 7B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 7A, and Figure 7C is a cross-sectional view of the section along the dashed line B1-B2 shown in Figure 7A.

[0180] The configuration shown in Figures 7A to 7C differs from that in Figures 2A to 2C mainly in that the conductive layer 104 and layer 121a, and the conductive layer 104 and layer 121b, do not overlap with each other. Therefore, the semiconductor layer 108 has a region 108S located between region 108i and region 108P, which does not overlap with either the conductive layer 104 or layer 121a, and a region 108T located between region 108i and region 108Q, which does not overlap with either the conductive layer 104 or layer 121b. These regions can function as buffer regions. Also, as shown in Figures 7A to 7C, the upper surfaces of region 108S and region 108T do not come into contact with the insulating layer 195, so regions 108S and 108T are regions where hydrogen does not easily diffuse.

[0181] Furthermore, Figures 31A to 31C show modified examples of Figures 2A to 2C, and differ from Figures 7A to 7C in the width of the conductive layer 104 in the channel length direction. Figure 31A is a top view of a semiconductor device 20 according to one embodiment of the present invention, Figure 31B is a cross-sectional view of the cross-section along the dashed line A1-A2 shown in Figure 31A, and Figure 31C is a cross-sectional view of the cross-section along the dashed line B1-B2 shown in Figure 31A.

[0182] In the configuration shown in Figures 31A to 31C, the edge of the conductive layer 104 on the layer 121a side and the edge of layer 121a roughly overlap in a plan view. Also, the edge of the conductive layer 104 on the layer 121b side and the edge of layer 121b roughly overlap in a plan view. Regions 108P2 and Q2 of the semiconductor layer 108 overlap with the conductive layer 103 but do not overlap with the conductive layer 104.

[0183] <Modification 1-3> Figures 8A to 8C show modifications of Figures 2A to 2C. Figure 8A is a top view of a semiconductor device 20 according to one embodiment of the present invention, Figure 8B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 8A, and Figure 8C is a cross-sectional view of the section along the dashed line B1-B2 shown in Figure 8A. The configuration shown in Figures 8A to 8C differs from Figures 2A to 2C in that the edges of the conductive layer 104 and the insulating layer 106 are generally aligned, and in the semiconductor layer 108, the upper surface is in contact with the insulating layer 195 in the region outside the region 108i that overlaps with the conductive layer 104, forming a region where hydrogen can easily diffuse. The region outside region 108i has regions 108P1, 108Q1, 108U, and 108V. Regions 108P1 and Q1 are regions that overlap with layers 121a and 121b. Furthermore, region 108U is a region whose upper surface is in contact with the insulating layer 195 and does not overlap with layer 121a, and the contribution of layer 121a to reducing resistance is smaller than that of region 108P1. Similarly, region 108V is a region whose upper surface is in contact with the insulating layer 195 and does not overlap with layer 121b, and the contribution of layer 121b to reducing resistance is smaller than that of region 108Q1. Therefore, the resistance value of region 108U is higher than, for example, region 108P1 and lower than region 108i. Also, the resistance value of region 108V is higher than, for example, region 108Q1 and lower than region 108i.

[0184] Furthermore, as shown in Figures 19A to 19C, layers 121a and 121b can be configured so that they do not overlap with any of the conductive layer 104, conductive layer 103, or insulating layer 106.

[0185] <Modification 1-4> Figures 9A and 9B show configuration examples different from those shown in Figures 2A and 2B. Figure 9A is a top view of a semiconductor device 20C, which is one embodiment of the present invention. Figure 9B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 9A, and Figure 9C is a cross-sectional view of the section along the dashed line B1-B2 shown in Figure 9A.

[0186] The semiconductor device 20C has a transistor 100C. Transistor 100C differs from transistor 100 shown in Figure 2A, etc., in that conductive layers 112a and 112b are formed in the same process as conductive layer 104.

[0187] The insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 108. Conductive layers 112a and 112b are provided so as to cover a portion of opening 147a and a portion of opening 147b. Conductive layer 112a has a region that contacts the semiconductor layer 108 at opening 147a, and conductive layer 112b has a region that contacts the semiconductor layer 108 at opening 147b.

[0188] In region 108P1 of the semiconductor layer 108, the region in contact with the conductive layer 112a can function as either a source region or a drain region. In region 108Q1, the region in contact with the conductive layer 112b can function as either a source region or a drain region.

[0189] <Modification 1-5> Figures 10A to 10C show modifications of Figures 2A to 2C. Figure 10A is a top view of a semiconductor device 20 according to one embodiment of the present invention, Figure 10B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 10A, and Figure 10C is a cross-sectional view of the section along the dashed line B1-B2 shown in Figure 10A. The configuration shown in Figures 10A to 10C differs from Figures 2A to 2C mainly in that the insulating layer 106 covers the upper surface of the semiconductor layer 108 and the insulating layer 195 does not come into contact with the semiconductor layer 108, and that the openings 147a and 147b, through which the conductive layers 112a and 112b are provided, are provided in both the insulating layer 195 and the insulating layer 106.

[0190] The semiconductor layer 108 has a region 108P that is in contact with layer 121a and a region 108Q that is in contact with layer 121b. Region 108P has a region 108P3 whose upper surface is in contact with the insulating layer 106 or the conductive layer 112a provided within the opening 147a of the insulating layer 106 and does not overlap with the conductive layer 104, and a region 108P2 that overlaps with the conductive layer 104. Region 108Q has a region 108Q3 whose upper surface is in contact with the insulating layer 106 or the conductive layer 112b provided within the opening 147b of the insulating layer 106 and does not overlap with the conductive layer 104, and a region 108Q2 that overlaps with the conductive layer 104. Since regions 108P3 and 108Q3 do not come into contact with the insulating layer 195 during the semiconductor device manufacturing process, their resistance values ​​may be higher than those of regions 108P1 and Q1 shown in Figure 2B, etc. Therefore, it is more preferable to further reduce the resistance by introducing impurities into these regions using ion implantation or the like, with the conductive layer 104 acting as a mask.

[0191] <Modification 1-6> Figures 16A to 16C show modified versions of Figures 2A to 2C. Figure 16A is a top view of a semiconductor device 20 according to one embodiment of the present invention, Figure 16B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 16A, Figure 16C is a cross-sectional view of the section along the dashed line B1-B2 shown in Figure 16A, and Figure 16D is a cross-sectional view of the section along the dashed line B3-B4 shown in Figure 16A. The configurations shown in Figures 16A to 16C differ from Figures 2A to 2C mainly in that they do not have conductive layers 112a and 112b. In the configurations shown in Figures 16A to 16C, layers 121a and 121b can be used as wiring by stretching them. Figures 16A and 16D show an example in which the extended region of layer 121b is connected to the conductive layer 112c embedded in the opening 147c provided in the insulating layer 195. Layers 121a and 121b can also be extended so as to overlap with other adjacent semiconductor elements, such as transistors, diodes, etc.

[0192] <Modification 1-7> Figures 17A to 17C show modifications of Figures 2A to 2C. Figure 17A is a top view of a semiconductor device 20 according to one embodiment of the present invention, Figure 17B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 17A, and Figure 17C is a cross-sectional view of the section along the dashed line B1-B2 shown in Figure 17A. The configuration shown in Figures 17A to 17C differs from Figures 2A to 2C in that the top surface of layer 121a and the top surface of layer 121b each have regions not covered by the semiconductor layer 108, and conductive layers 112a and 112b are provided in contact with these regions not covered by the semiconductor layer 108. Furthermore, when conductive layers are used as layers 121a and 121b, contact resistance can be reduced by configuring the conductive layers of layer 121a and conductive layer 112a, and layer 121b and conductive layer 112b to be in contact with each other.

[0193] The materials that can be used for each component will be explained.

[0194] [Insulating layer 106, insulating layer 105] It is preferable that insulating layer 106 and insulating layer 105 each have one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0195] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0196] The insulating layer 106 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 106 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 106. Specifically, it is preferable that the region of the insulating layer 106 that is in contact with the channel-forming region of the semiconductor layer 108 contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 106 that is in contact with the channel-forming region of the semiconductor layer 108. The same applies to the insulating layer 105. For example, it is preferable that the insulating layer 106 and the insulating layer 105 each contain silicon and oxygen, respectively. Silicon oxide or silicon oxiditride can be suitably used for the insulating layer 106 and the insulating layer 105, respectively.

[0197] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxiditrides having aluminum and hafnium, oxides having silicon and hafnium, oxiditrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0198] In Figure 2B and other figures, the insulating layer 106 and insulating layer 105 are shown as single-layer structures, but the present invention is not limited to this. One or both of the insulating layer 106 and insulating layer 105 can be made into a laminated structure of two or more layers. When one or both of the insulating layer 106 and insulating layer 105 are made into a laminated structure, the insulating layer on the semiconductor layer 108 side preferably has an oxide or oxidizride. The insulating layer on the semiconductor layer 108 side can preferably be made of one or more of silicon oxide, silicon oxidizride, or aluminum oxide.

[0199] A barrier layer can be provided on one or more of the layers constituting the insulating layer 106. This suppresses the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106. Furthermore, it suppresses the diffusion of oxygen contained in the semiconductor layer 108 into the conductive layer 104 side via the insulating layer 106. This prevents oxygen deficiencies (V) in the semiconductor layer 108. Ｏ This can suppress the formation of ) and prevent oxidation of the conductive layer 104 by oxygen contained in the semiconductor layer 108, thereby preventing an increase in the electrical resistance of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be obtained. One or more oxides and oxidized nitrides can be used as the barrier film of the insulating layer 106, for example, aluminum oxide can be suitably used. Similarly, it is preferable to provide a layer that functions as a barrier film in one or more of the layers constituting the insulating layer 105. One or more nitrides and nitride oxides can be used as the barrier film of the insulating layer 105, for example, silicon nitride can be suitably used.

[0200] The insulating layer 106 can be, for example, a laminated structure of a silicon oxidizide film and a silicon nitride film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of a silicon oxidizide film and an aluminum oxide film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon oxidizide film on the aluminum oxide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film. Here, an example is shown in which the insulating layer 106 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 106 can also have a laminated structure of three or more layers.

[0201] When the insulating layer 105 has a two-layer structure, a layer that functions as a barrier film can be used as the first layer on the side in contact with the conductive layer 103. Furthermore, an oxide or oxidized nitride can be used as the second layer on the side in contact with the semiconductor layer 108. Typically, silicon nitride can be preferably used for the first layer and silicon oxidized nitride for the second layer. Here, an example is shown in which the insulating layer 105 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 105 can also have a laminated structure of three or more layers.

[0202] [Conductive layer 112a, conductive layer 112b, conductive layer 103, conductive layer 104] Conductive layers 112a, 112b, 103, and 104 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for conductive layers 112a, 112b, 103, and 104 include, for example, one or more of copper, chromium, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys comprising one or more of the aforementioned metals. Conductive layers 112a, 112b, 103, and 104 can preferably be conductive materials with low electrical resistivity that contain one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred because they are easy to mass-produce.

[0203] Conductive layers 112a, 112b, 103, and 104 can each be made of a conductive metal oxide (also called an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0204] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0205] The conductive layers 112a, 112b, 103, and 104 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0206] Conductive layers 112a, 112b, 103, and 104 can each be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0207] Conductive layers 112a, 112b, 103, and 104 can each be made of a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). Using a Cu-X alloy film allows for processing by wet etching, thus reducing manufacturing costs.

[0208] Note that conductive layers 112a, 112b, 103, and 104 can be made of the same material. Alternatively, at least one of them can be made of a different material.

[0209] It is preferable that the conductive layer 103 is made of a material that can withstand heat-inducing processes after the formation of the conductive layer 103 (for example, heat treatment in the formation of the semiconductor layer 108). It is preferable that the conductive layer 103 is made of a high-melting-point material that provides both heat resistance and conductivity. As a high-melting-point material, for example, tungsten and molybdenum, or both, can be suitably used.

[0210] The conductive layer 104 may also have a laminated structure. For example, the conductive layer 104 can have a two-layer structure. The conductive layer used as the upper layer preferably uses a conductive material with low electrical resistivity, and preferably contains one or more of copper, aluminum, gold, and silver. In particular, it is preferable to contain one or more of copper or aluminum. This makes it possible to make the electrical resistance of the conductive layer 104 extremely low. Furthermore, it is preferable to use a conductive material with lower electrical resistivity for the conductive layer used as the upper layer compared to the conductive layer used as the lower layer. Also, it is preferable that the thickness of the upper conductive layer is greater than the thickness of the lower conductive layer.

[0211] The conductive layer used in the lower layer (the conductive layer closer to the insulating layer 106) can be made of a different material than the conductive layer in the upper layer. Since the conductive layer in the lower layer is provided in contact with the insulating layer 106, it is preferable to use a conductive material that is resistant to oxidation, or a conductive material that maintains low electrical resistance even if oxidized. This prevents the conductive layer 104 from being oxidized by the oxygen contained in the insulating layer 106, which would increase the electrical resistance of the conductive layer 104. As materials that are resistant to oxidation that can be used in the conductive layer 104, it is preferable to use one or more of titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, and nitrides containing tantalum and aluminum.

[0212] Furthermore, the lower conductive layer can suppress the diffusion of metal components (e.g., copper) contained in the upper conductive layer into the semiconductor layer 108 via the insulating layer 106. This makes it possible to create a highly reliable transistor.

[0213] Furthermore, the conductive layer 104 can also be made into a laminated structure of three or more layers.

[0214] If the conductive layer 104 has a three-layer structure, it can be configured by sandwiching a material with low electrical resistivity between conductive materials that are resistant to oxidation. For example, a layer made of copper or aluminum can be sandwiched between layers made of titanium.

[0215] [Insulating layer 195, insulating layer 218] The insulating layer 195 preferably has one or more inorganic insulating layers. The inorganic insulating layers can be made from the materials listed for insulating layer 106 and insulating layer 105.

[0216] As the insulating layer 218, either an inorganic insulating layer or an organic insulating layer, or both, can be used. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105. Examples of materials that can be used for the organic insulating layer include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The organic insulating layer functions as a planarizing layer that reduces irregularities caused by the transistor.

[0217] It is preferable to provide a layer that functions as a barrier film on one or both of the insulating layer 195 and the insulating layer 218. This suppresses the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside, and suppresses a shift in the threshold voltage. Therefore, a highly reliable semiconductor device can be made. Furthermore, if impurities can diffuse into the semiconductor layer 108 via the conductive layer 112a and the conductive layer 112b, it is preferable to provide a layer that functions as a barrier film on the insulating layer 218. The barrier film can be described in the above description. The insulating layer 195 and the insulating layer 218 can preferably be one or more of, for example, silicon nitride, silicon oxide nitride, and aluminum oxide. When an aluminum oxide film is used as the barrier film, it is preferable because it has extremely high barrier properties even when thin.

[0218] The insulating layer 195 and the insulating layer 218 can each be a single-layer structure or a laminated structure.

[0219] The insulating layer 218 can have a laminated structure. Preferably, one or more of the laminated layers function as barrier films. This enhances the effect of suppressing the diffusion of impurities into the transistor from the outside. For example, the insulating layer 218 can have a laminated structure of an aluminum oxide layer and a silicon nitride layer located on top of it. In this case, silicon nitride oxide can be suitably used for the insulating layer 195. The aluminum oxide film can be formed using the sputtering method, and the silicon nitride film and silicon nitride oxide film can be formed using the plasma CVD method, respectively. However, the sputtering method has lower coverage than the plasma CVD method. Therefore, by making the insulating layer 218 a laminated structure of an insulating layer formed using the sputtering method and an insulating layer formed using the plasma CVD method, the barrier properties of the insulating layer 218 can be further enhanced. Similarly, the insulating layer 195 can also have a laminated structure.

[0220] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatments. For example, single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates made of silicon or silicon carbide can be used as the substrate 102. In addition, a substrate on which semiconductor elements are provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0221] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0222] [Semiconductor Layer] A semiconductor layer applicable to one embodiment of the present invention will be described.

[0223] The semiconductor layer preferably has a metal oxide that exhibits semiconductor properties. The band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or higher, and more preferably 2.5 eV or higher.

[0224] A semiconductor layer can be formed by depositing a metal oxide film and processing the metal oxide film into island-like structures. It is preferable to perform a heat treatment to crystallize the metal oxide film after depositing it or after processing it into island-like structures. By performing the heat treatment, the grain size of the crystals contained in the semiconductor layer can be increased, and the crystallinity of the semiconductor layer can be improved. Furthermore, the heat treatment can reduce defects in the semiconductor layer. In addition, the heat treatment can remove impurities contained in the semiconductor layer or adsorbed on its surface. Examples of impurities contained in the semiconductor layer include those caused by the metal oxide film deposition gas (e.g., hydrogen gas, oxygen gas, and argon gas). Examples of impurities adsorbed on the surface of the semiconductor layer include hydrogen and water.

[0225] The metal oxide film is preferably deposited by sputtering using a metal target or a metal oxide target. For example, it can be deposited using magnetron sputtering. In addition, an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used during film deposition.

[0226] Here, by varying the deposition conditions for the metal oxide film, the film quality of the metal oxide film (later the semiconductor layer) can be varied. Examples of film quality include conductivity, band gap, defect amount, impurity concentration, and crystallinity. Examples of deposition conditions include power density, pressure, gas type, gas flow rate, substrate temperature, and the distance between the sputtering target and the substrate (also called T-S distance or TS distance). When varying the deposition conditions, one or more of the following can be varied: power density, pressure, gas type, gas flow rate, substrate temperature, and T-S distance.

[0227] Examples of power supplies used in sputtering equipment include DC (Direct Current) power supplies, RF (Radio Frequency) power supplies, and AC (Alternating Current) power supplies. A pulsed DC power supply, which applies a pulsed voltage to the target, can also be used. Furthermore, magnetron sputtering, which utilizes the magnetic field of a magnet, offers a high deposition rate, thus increasing productivity.

[0228] Alternatively, metal oxide films are preferably deposited using atomic layer deposition (ALD). Since the ALD method allows for easy control of the deposition rate, thin films can be deposited with high yield. Therefore, the ALD method is particularly suitable when the metal oxide film is thin.

[0229] Alternatively, chemical vapor deposition (CVD) can be used instead of sputtering or ALD.

[0230] It is preferable to use conditions that result in low crystallinity of the metal oxide film when forming the metal oxide film. By performing a heat treatment after forming a metal oxide film with low crystallinity to induce crystallization, the grain size can be increased. If the number of grains contained in the metal oxide film is large at the time of film formation, the grain size of the grains after heat treatment may become small. Therefore, it is preferable that the number of grains contained in the metal oxide film is small at the time of film formation, and that the metal oxide film has low crystallinity.

[0231] When forming a metal oxide film, a gas containing hydrogen (for example, H) ２ or H ２It is preferable to use O). This reduces the number of crystal grains generated during the formation of the metal oxide film, resulting in a metal oxide film with low crystallinity. Hydrogen gas and argon gas can be suitably used as the film-forming gas for the metal oxide film. The ratio of the hydrogen gas flow rate to the total film-forming gas when forming the metal oxide film (hereinafter also referred to as the hydrogen flow rate ratio) is preferably higher than 0% and 20% or less, more preferably higher than 0% and 15% or less, and even more preferably higher than 0% and 10% or less. However, the hydrogen flow rate ratio in the formation of the metal oxide film is not limited to the above range.

[0232] By using oxygen gas as the deposition gas for metal oxide films, oxygen vacancies (V) can be created in the metal oxide film. Ｏ This can suppress the occurrence of ( ). Furthermore, by using oxygen gas as the deposition gas for the metal oxide film, the amount of oxygen contained in the metal oxide film can be increased, which can promote crystallization during subsequent heat treatment. In addition, oxygen can be supplied to the insulating layer 15 during the deposition of the metal oxide film.

[0233] For example, oxygen gas and argon gas can be suitably used as the film-forming gas for metal oxide films. The ratio of the flow rate of oxygen gas to the total film-forming gas when forming a metal oxide film (hereinafter also referred to as the oxygen flow rate ratio) is preferably higher than 0% and 10% or less, more preferably higher than 0% and 7% or less, and even more preferably higher than 0% and 5% or less. By setting the oxygen flow rate ratio within the above range, the crystallinity of the metal oxide film can be reduced, and oxygen vacancies and V in the semiconductor layer can be reduced. Ｏ H can be reduced.

[0234] A mixture of hydrogen gas, oxygen gas, and an inert gas can also be used as the film-forming gas for metal oxide films.

[0235] When forming a metal oxide film, a low substrate temperature is preferable. For example, it is preferable to form the metal oxide film without heating the substrate. This reduces the number of crystal grains generated during the formation of the metal oxide film, resulting in a metal oxide film with low crystallinity. The substrate temperature during metal oxide film formation is preferably between room temperature and 150°C, more preferably between room temperature and 100°C, more preferably between room temperature and 80°C, and more preferably between room temperature and 50°C. In particular, it is preferable to form the metal oxide film at room temperature or without heating the substrate. Note that the substrate temperature during metal oxide film formation is not limited to the above range.

[0236] When using the ALD method for depositing metal oxide films, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0237] Metal oxide films can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0238] For example, when forming an indium oxide film, an indium-containing precursor can be used. Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0239] Examples of oxidizing agents include ozone, oxygen, hydrogen peroxide, and water.

[0240] It is preferable to use a high temperature for the heat treatment after depositing a metal oxide film or after processing the metal oxide film into island shapes. By increasing the heat treatment temperature, the crystallinity of the semiconductor layer can be improved. In the semiconductor layer, regions with low crystallinity (e.g., amorphous regions) may exist between crystal grains. In particular, if regions with low crystallinity exist in the channel formation region, there is a risk that the field-effect mobility of the transistor will be reduced due to carrier scattering. By increasing the heat treatment temperature, the grain size of the crystal grains increases, and the regions with low crystallinity between crystal grains can be reduced. This makes it possible to create a transistor with high field-effect mobility. In addition, by increasing the heat treatment temperature, the grain size of the crystal grains contained in the semiconductor layer may increase. By increasing the heat treatment temperature, defects in the semiconductor layer can be further reduced. Furthermore, impurities contained in the semiconductor layer or adsorbed on the surface can be efficiently removed by the heat treatment.

[0241] The temperature for the heat treatment is preferably 100°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 670°C or lower, more preferably 300°C or higher and 670°C or lower, more preferably 350°C or higher and 670°C or lower, more preferably 400°C or higher and 670°C or lower, and more preferably 450°C or higher and 670°C or lower. It is preferable that the temperature of the substrate during the heat treatment falls within the above temperature range. However, the temperature of the substrate during the heat treatment is not limited to the above range.

[0242] The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing or oxygen-containing atmosphere. It is preferable to carry out the heat treatment in an oxygen-containing atmosphere. Performing the heat treatment in an oxygen-containing atmosphere may enhance effects such as defect reduction and increased grain size. CDA can be suitably used as the atmosphere for the heat treatment. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the semiconductor layer as much as possible.

[0243] The apparatus used for the heat treatment is not particularly limited, and for example, an apparatus that heats by heat conduction or thermal radiation from a heating element can be used. For example, an oven or a rapid thermal annealing (RTA) apparatus can be used for the heat treatment. As an RTA apparatus, an LRTA (Lamp RTA) apparatus that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp can be used. Examples of such lamps include halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Alternatively, as an RTA apparatus, a GRTA (Gas RTA) apparatus that heats the workpiece using high-temperature gas can be used. By using an RTA apparatus, the heat treatment time can be shortened. The treatment time is preferably 1 minute or more and 10 minutes or less, more preferably 3 minutes or more and 10 minutes or less, and more preferably 5 minutes or more and 10 minutes or less. Furthermore, when using an RTA device to achieve a short heating time, the heating temperature can be set above the strain point of the substrate. This further reduces the heating time. Typically, a GRTA device can be used to perform a heating treatment at 650°C for 6 minutes.

[0244] The grain size of the crystal grains contained in the semiconductor layer is preferably 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferable, there is no particular upper limit on the grain size. Note that the grain size of the crystal grains is not limited to the above range.

[0245] The crystallinity of a semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0246] The grain size of crystal grains contained in a semiconductor layer can be analyzed, for example, by TEM, scanning transmission electron microscopy (STEM), or electron backscatter diffraction (EBSD or EBSP). Alternatively, a combination of these methods can be used for analysis. For example, the average grain size of multiple crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be defined as, for example, the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter of a circle.

[0247] In this specification, a grain boundary refers to, for example, the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two grains in a TEM image, if the crystal orientations of those two grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same grain.

[0248] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axis is defined.

[0249] The cubic crystal structure of indium oxide belongs to space group Ia-3 (space group number 206).

[0250] The grain size of the crystals can also be confirmed, for example, using an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating irregularities on the surface of the semiconductor layer using etchants with different etching rates depending on the crystal plane or crystallinity, the crystal grains can be more easily observed with an optical microscope or a scanning electron microscope (SEM). When an indium oxide film is used as the semiconductor layer, the crystal grains of indium oxide can be more easily observed by using an etchant containing an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid.

[0251] It is preferable that the concentration of impurities in the channel-forming region be low. It is also preferable that the channel-forming region be of high purity. In the channel-forming region, impurities can act as carrier scattering sources and thus can be a factor in reducing field-effect mobility. Furthermore, impurities can also be a factor in inhibiting crystal growth.

[0252] Impurities in the indium oxide film include gallium, zinc, boron, aluminum, and silicon. In the channel-forming region, the concentration of each of these impurities is preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less. Elements that may be contained in the indium oxide film include, for example, carbon and hydrogen. Carbon and hydrogen are elements that may be contained in the film-forming gas (e.g., precursor) of the indium oxide film, and may be present in the indium oxide film in greater quantities than the aforementioned impurities. ppm is an abbreviation for "parts per million," and 1 ppm is 1 × 10⁻⁶. −６ That is the case.

[0253] For analyzing the concentration of impurities in a semiconductor layer, for example, SIMS or XPS can be used. When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. However, in areas with low concentrations, quantitative analysis may be difficult or the concentration may fall below the detection limit.

[0254] The concentrations of gallium, zinc, boron, aluminum, and silicon in the channel-forming region are, respectively, 1 × 10⁻⁶. ２０ atoms / cm ３ The following is preferable, and moreover, 5 × 10 １９ atoms / cm ３ The following is preferable, and moreover, 3 × 10 １９ atoms / cm ３ The following are preferable, and moreover, 1 × 10 １９ atoms / cm ３ The following is preferable, and moreover, 3 × 10 １８ atoms / cm ３ The following are preferable, and moreover, 1 × 10 １８ atoms / cm ３ The following are preferable.

[0255] The hydrogen concentration in the channel formation region is 5.0 × 10⁻⁶. ２１ atoms / cm ３The following is preferable. Also, by having a region where the channel formation region has a hydrogen concentration of 5.0 × 10 ２０ atoms / cm ３ or more, for example, the carrier concentration of the semiconductor layer can be increased. For example, when the semiconductor layer has a stacked structure, it can be configured to have a layer with a hydrogen concentration of 5.0 × 10 ２０ atoms / cm ３ or more.

[0256] By using an indium oxide film with large crystal grain size and low impurity concentration in a transistor, the field-effect mobility of the transistor can be 50 cm ２ / (V·s) or more, further 100 cm ２ / (V·s) or more, further 150 cm ２ / (V·s) or more, further 200 cm ２ / (V·s) or more, further 250 cm ２ / (V·s) or more.

[0257] The metal oxides that can be used in semiconductor layers will be described in detail. The metal oxide preferably contains at least indium. Indium oxide can be suitably used as the metal oxide. Alternatively, for example, gallium oxide or zinc oxide can be used as the metal oxide. Alternatively, the metal oxide preferably contains one or both of indium and zinc. Alternatively, the metal oxide preferably has one or more elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy with oxygen, for example, a metallic or metalloid element with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have high bonding energy with oxygen and their ionic radii are similar to those of indium or zinc. Furthermore, tin is more preferred because its tetravalent state can increase carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may include metalloid elements.

[0258] The semiconductor layer is, for example, indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), aluminum zinc oxide (Al-Zn oxide, Other suitable materials include indium aluminum zinc oxide (also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.

[0259] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0260] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0261] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a high on-current can be realized.

[0262] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0263] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and its reliability can be improved.

[0264] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be obtained. Furthermore, oxygen vacancies (V) can be added to the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed, Ｏ This suppresses carrier generation caused by (), thereby preventing a shift in the transistor's threshold voltage. As a result, the drain current (hereinafter also referred to as the cutoff current) that flows when the gate voltage (Vg) is 0V can be reduced, making it possible to create a normally-off transistor. Furthermore, it is possible to create a transistor with a small off-current. In addition, fluctuations in the transistor's electrical characteristics are suppressed, improving reliability.

[0265] The composition of the metal oxide applied to the semiconductor layer affects the electrical characteristics and reliability of the transistor. Therefore, by varying the metal oxide composition according to the required electrical characteristics and reliability of the transistor, it is possible to create a semiconductor device that achieves both excellent electrical characteristics and high reliability.

[0266] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably not less than the atomic ratio of element M. Examples of the atomic ratios of the metal elements in such an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. The vicinity of the composition includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-current or field-effect mobility of the transistor can be increased.

[0267] The atomic ratio of In in the In-M-Zn oxide can also be less than the atomic ratio of element M. Examples of the atomic ratios of the metal elements in such an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions in the vicinity thereof. By increasing the proportion of the number of atoms of M in the metal oxide, the generation of oxygen vacancies (V Ｏ ) can be suppressed.

[0268] When element M has a plurality of elements, the sum of these atomic ratios can be used as the atomic ratio of element M.

[0269] By using a material with a high indium content in the semiconductor layer, the on-current or field-effect mobility of the transistor can be increased. Furthermore, by having element M, oxygen vacancies (V ＯThe generation of ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical properties. For example, it is preferable to use metal oxides of In:M:Zn = 40:1:10 and nearby elements. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides of In:Sn:Zn = 40:1:10 and nearby elements can be suitably used. Alternatively, metal oxides of In:Al:Zn = 40:1:10 and nearby elements can be suitably used.

[0270] A metal oxide that does not contain element M can be applied to the semiconductor layer. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0271] For analyzing the composition of semiconductor layers, for example, energy-dispersive X-ray spectroscopy (EDX), XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained from the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained from the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, or it may be difficult to quantify the content of element M, or it may fall below the detection limit.

[0272] Furthermore, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% compared to that of the sputtering target.

[0273] It is preferable to use a crystalline metal oxide for the semiconductor layer. Examples of crystalline metal oxide structures include CAAC structure, polycrystalline structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer can be reduced, enabling the realization of a highly reliable semiconductor device.

[0274] It is preferable to use CAAC-OS or nc-OS for the semiconductor layer.

[0275] CAAC-OS has multiple layered crystals. The c-axis of these crystals is oriented in the direction normal to the surface to be formed. Preferably, the semiconductor layer has layered crystals that are parallel or approximately parallel to the surface to be formed. For example, preferably, the semiconductor layer has layered crystals that are parallel or approximately parallel to the upper surface of the insulating layer 15. With this configuration, the layered crystals of the semiconductor layer are formed parallel or approximately parallel to the channel length direction of the transistor, making it possible to create a transistor with a large on-current.

[0276] When a metal oxide is used in the semiconductor layer, the V of the channel formation region Ｏ It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V). Ｏ It is important to repair ). Ｏ By using a metal oxide with sufficiently reduced impurities such as H in the channel formation region, a transistor with stable electrical characteristics can be made. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. Ｏ The process of repairing this is sometimes referred to as oxygenation treatment.

[0277] OS transistors exhibit minimal fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton beams, and neutron beams).

[0278] The semiconductor layer may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0279] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel formation region in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0280] <Configuration Example 2> As shown in the following configuration example, the semiconductor layer 18 can be in a stacked structure.

[0281] The transistor 10C shown in Figure 11A is an example of a structure in which the semiconductor layer 18 has a three-layer structure in the configuration shown in Figure 1A, consisting of semiconductor layer 18a, semiconductor layer 18b on semiconductor layer 18a, and semiconductor layer 18c on semiconductor layer 18b. An enlarged view of the semiconductor layer 18 and its vicinity shown in Figure 11A is shown in Figure 11B. Semiconductor layer 18b is in contact with and sandwiched between semiconductor layers 18a and 18c. The semiconductor layers 18a, 18b, and 18c can each be made from the materials listed for semiconductor layer 18.

[0282] The semiconductor layers 18a, 18b, and 18c can use the same material for each other. This allows for the use of common equipment for depositing the semiconductor layers 18a, 18b, and 18c, thereby reducing the manufacturing cost of semiconductor devices. Alternatively, different materials can be used for at least one of the semiconductor layers 18a, 18b, and 18c. This broadens the range of materials that can be selected for the semiconductor layers 18a, 18b, and 18c.

[0283] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0284] In some cases, the boundaries between semiconductor layer 18a and semiconductor layer 18b, and between semiconductor layer 18b and semiconductor layer 18c, cannot be clearly identified. Therefore, in Figure 11A and other figures, these boundaries are shown with dashed lines.

[0285] Preferably, the conductivity of semiconductor layer 18b is higher than that of either semiconductor layer 18a or semiconductor layer 18c. This ensures that the main current path in transistor 10 is through semiconductor layer 18b. On the other hand, in semiconductor layer 18, it is preferable that semiconductor layer 18a, which is in contact with the second gate insulating layer, and semiconductor layer 18c, which is in contact with the first gate insulating layer, are both denser and have fewer defects than semiconductor layer 18b.

[0286] Trap levels caused by impurities or defects may form at the interface between the insulating layer 16, which functions as the first gate insulating layer, and the semiconductor layer 18, and at the interface between the insulating layer 15, which functions as the second gate insulating layer, and the semiconductor layer 18, and at the interface at the interface at the interface at the interface. Furthermore, when the insulating layer 16 is deposited, damage may be inflicted on the interface between the insulating layer 16 and the semiconductor layer 18, causing trap levels to form at the interface between the insulating layer 16 and the semiconductor layer 18, and at the interface

[0287] Here, when a high potential is applied to the conductive layer 14, which functions as the first gate electrode, trap levels may be formed at and near the interface between the insulating layer 16 and the semiconductor layer 18. Similarly, when a high potential is applied to the conductive layer 13, which functions as the second gate electrode, trap levels may be formed at and near the interface between the insulating layer 15 and the semiconductor layer 18. If electrons are trapped in these trap levels, the threshold voltage of the transistor may shift to the positive side, potentially reducing reliability. By providing a semiconductor layer 18c with few defects in contact with the insulating layer 16, the formation of trap levels at and near the interface between the insulating layer 16 and the semiconductor layer 18 can be suppressed. Similarly, by providing a semiconductor layer 18a with few defects in contact with the insulating layer 15, the formation of trap levels at and near the interface between the insulating layer 15 and the semiconductor layer 18 can be suppressed. This makes it possible to create a highly reliable transistor.

[0288] In this way, by sandwiching a highly conductive semiconductor layer 18b between semiconductor layers 18a and 18c, which have few defects, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0289] Preferably, the film density of semiconductor layer 18a and semiconductor layer 18c is higher than the film density of semiconductor layer 18b. This reduces defects in semiconductor layer 18a and semiconductor layer 18c. Furthermore, by providing a semiconductor layer 18c with a high film density on semiconductor layer 18b, damage to semiconductor layer 18b during the deposition of the insulating layer 16 can be suppressed. For example, the film density can be evaluated using Rutherford backscattering spectrum (RBS) or X-ray reflectivity (XRR). It is also possible to configure semiconductor layer 18a and semiconductor layer 18c to have the same film density as semiconductor layer 18b, or to have a lower film density than semiconductor layer 18b.

[0290] When the semiconductor layer 18 has a three-layer structure consisting of semiconductor layer 18a, semiconductor layer 18b, and semiconductor layer 18c, the metal oxide films are formed in the following order: a first metal oxide film which will become semiconductor layer 18a, a second metal oxide film which will become semiconductor layer 18b, and a third metal oxide film which will become semiconductor layer 18c.

[0291] The first, second, and third metal oxide films can be deposited using methods such as sputtering, ALD, and chemical vapor deposition (CVD), respectively. The first, second, and third metal oxide films can be deposited using the same method, or they can be deposited using different methods. In the following, magnetron sputtering may be used as an example to explain the deposition methods for the first, second, and third metal oxide films.

[0292] The power densities under the deposition conditions for the first and third metal oxide films are preferably higher than the power densities under the deposition conditions for the second metal oxide film. By increasing the power density, dense semiconductor layers 18a and 18c with few defects can be obtained.

[0293] Furthermore, it is preferable that the pressure in the first and third film deposition conditions is lower than the pressure in the second film deposition condition. By lowering the pressure, it is possible to obtain dense semiconductor layers 18a and 18c with few defects.

[0294] In Figure 11B, the thicknesses T18a of semiconductor layer 18a, T18b of semiconductor layer 18b, and T18c of semiconductor layer 18c are indicated by solid arrows. Thicknesses T18a, T18b, and T18c are the thicknesses of each layer in the region of semiconductor layer 18 that overlaps with the conductive layer 14 in a cross-sectional view. Note that thicknesses T18a, T18b, and T18c can be controlled by the processing time (also referred to as deposition time) during the deposition of semiconductor layers 18a, 18b, and 18c, respectively.

[0295] A thickness T18b is preferably thick. A thickness T18b is preferably thicker than either thickness T18a or thickness T18c. By increasing the thickness T18b of the semiconductor layer 18b, which is the main current path, a transistor with a large on-current can be made. However, if the thickness T18b is too thick, oxygen vacancies (V) in the semiconductor layer 18b may occur. Ｏ ) and V Ｏ An increase in the amount of H can cause a shift in the transistor's threshold voltage, potentially leading to a larger cutoff current. The thickness T18b is preferably 1 nm to 30 nm, more preferably 2 nm to 30 nm, more preferably 2 nm to 20 nm, more preferably 4 nm to 20 nm, and more preferably 4 nm to 10 nm. By setting the thickness T18b within the above range, a transistor with a large on-current can be made. Furthermore, by suppressing the shift in the threshold voltage, the cutoff current can be reduced, resulting in a normally-off transistor. Note that the thickness T18b is not limited to the above range.

[0296] It is preferable that thicknesses T18a and T18c are each thinner than thickness T18b. Furthermore, thicknesses T18a and T18c are preferably 0.5 nm to 10 nm, more preferably 0.5 nm to 6 nm, more preferably 0.5 nm to 4 nm, more preferably 0.5 nm to 3 nm, and more preferably 1 nm to 3 nm. If thickness T18c is too thick, the physical distance between the conductive layer 14, which functions as the first gate electrode, and the semiconductor layer 18b becomes longer, which may result in a decrease in field-effect mobility. On the other hand, if thickness T18c is too thin, the physical distance between the trap levels at the interface and near the interface of the insulating layer 16 and the semiconductor layer 18b, and the semiconductor layer 18b, which is the main current path, becomes shorter, which may result in a decrease in field-effect mobility. In addition, reliability may decrease. The same applies to thickness T18a. By setting the thicknesses T18a and T18c within the aforementioned ranges, a transistor with high field-effect mobility and high reliability can be obtained. Note that the thicknesses T18a and T18c are not limited to the aforementioned ranges.

[0297] The thicknesses T18a and T18c can be the same or different.

[0298] In some cases, the boundaries between semiconductor layer 18a and semiconductor layer 18b, and between semiconductor layer 18b and semiconductor layer 18c, cannot be clearly identified, making it impossible to measure the thicknesses T18a, T18b, and T18c.

[0299] Figures 11C to 11F illustrate configuration examples that differ in some aspects from Figure 11A. Note that in the following, explanations of parts that overlap with Figures 1A to 1C and Figure 11A may be omitted. Furthermore, in the drawings shown below, parts having the same function as those in Figures 1A to 1C and Figure 11A may use the same hatching pattern and may not be labeled with reference numerals.

[0300] Figure 11C shows a schematic cross-sectional view of a transistor 10D that can be applied to a semiconductor device according to one aspect of the present invention.

[0301] Transistor 10D differs from transistor 10C mainly in that it does not have a conductive layer 13.

[0302] If the conductive layer 13 is not provided, the semiconductor layer 18a can be omitted, as shown in the transistor 10E in Figure 11D. The semiconductor layer 18 has a two-layer structure consisting of semiconductor layer 18b and semiconductor layer 18c. For details on semiconductor layer 18b and semiconductor layer 18c, please refer to the previous description. By omitting the semiconductor layer 18a, the process can be simplified and productivity can be increased.

[0303] Figure 11E shows a schematic cross-sectional view of a transistor 10F that can be applied to a semiconductor device according to one aspect of the present invention.

[0304] The transistor 10F differs from the transistor 10C mainly in that it does not have a conductive layer 14.

[0305] By providing a semiconductor layer 18a between the insulating layer 15, which functions as a gate insulating layer, and the semiconductor layer 18b, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0306] If the conductive layer 14 is not provided, the semiconductor layer 18c can be omitted, as shown in the transistor 10G in Figure 11F. The semiconductor layer 18 has a two-layer structure consisting of semiconductor layer 18a and semiconductor layer 18b. The semiconductor layers 18a and 18b can be described in the previous section. By omitting the semiconductor layer 18c, the process can be simplified and productivity can be increased. However, if the semiconductor layer 18 is damaged when the insulating layer 16 is formed, it is preferable to provide the semiconductor layer 18c as shown in Figure 11E. This can suppress damage to the semiconductor layer 18b, resulting in a transistor with high field-effect mobility.

[0307] <Configuration Example 2-1> Figures 12A to 12C show an example in which the semiconductor layer 108 has a three-layer stacked structure in the configuration shown in Figures 2A to 2C. Figure 12A shows a top view of a semiconductor device 20 including a transistor 100. Figure 12B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 12A, and Figure 2C shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2. As shown in Figures 12B and 12C, the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108a, semiconductor layer 108b on semiconductor layer 108a, and semiconductor layer 108c on semiconductor layer 108b. Semiconductor layer 108b is in contact with and sandwiched between semiconductor layers 108a and 108c. For semiconductor layers 108a, 108b, and 108c, refer to the description relating to semiconductor layers 18a, 18b, and 18c.

[0308] The conductivity of semiconductor layer 108b is preferably higher than that of either semiconductor layer 108a or semiconductor layer 108c. This ensures that the main current path in transistor 10 is semiconductor layer 108b. On the other hand, it is preferable that semiconductor layer 108a and semiconductor layer 108c are denser and have fewer defects than semiconductor layer 108b. By sandwiching semiconductor layer 108b between semiconductor layers 108a and 108c, a transistor 100 can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device 20 can be made that achieves both high-speed operation and high reliability. For the film thickness of semiconductor layers 108a, 108b, and 108c, refer to the descriptions relating to thickness T18a, thickness T18b, and thickness T18c, respectively.

[0309] By providing a semiconductor layer 108c between the insulating layer 106, which functions as a gate insulating layer, and the semiconductor layer 108b, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0310] Furthermore, if the conductive layer 103 is not provided in the transistor, the semiconductor layer 108a can be omitted. By omitting the semiconductor layer 108a, the process can be simplified and productivity can be increased.

[0311] <Example of Manufacturing Method> A method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Note that explanations of the materials and formation methods of each element may be omitted if they have already been described.

[0312] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal-organic chemical vapor deposition (MOCVD).

[0313] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0314] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by deposition methods using shielding masks such as metal masks.

[0315] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0316] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of the light source. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0317] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0318] Here, an example of a method for manufacturing the semiconductor device 20 shown in Figures 2A to 2C will be explained using Figures 13A to 15D. Figures 13A, 13C, 13E, 14A, 14C, 15A, and 15C correspond to the cross-sectional views between the dashed lines A1 and A2 shown in Figure 2B, respectively. Also, Figures 13B, 13D, 13F, 14B, 14D, 15B, and 15D correspond to the cross-sectional views between the dashed lines B1 and B2 shown in Figure 2C, respectively.

[0319] First, a conductive film is formed on the substrate 102, and the conductive film is processed to form a conductive layer 103. Sputtering is preferably used to form the conductive film.

[0320] Next, an insulating layer 105 is formed on the conductive layer 103 and the substrate 102. The insulating layer 105 can preferably be formed using sputtering or plasma CVD.

[0321] Next, a film 121f is formed on the insulating layer 105 (Figures 13A and 13B). Sputtering or plasma CVD can be suitably used to form the film 121f.

[0322] Next, layers 121a and 121b are formed by removing a portion of the film 121f (Figures 13C and 13D). At this time, at least a portion of the region of film 121f that overlaps with the conductive layer 103 is removed. Furthermore, a portion of film 121f is removed so that the region 108i of the semiconductor layer 108 and the conductive layer 104 that are later formed have regions that do not overlap with either layer 121a or layer 121b.

[0323] Next, a semiconductor film that will become the semiconductor layer 108 is formed. This semiconductor film is provided in contact with the upper surface of layer 121a, the upper surface of layer 121b, and the upper surface of the insulating layer 105.

[0324] Before forming the semiconductor film, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 105, and a treatment to supply oxygen into the insulating layer 105. For example, a heat treatment can be performed in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Oxygen can be supplied to the insulating layer 105 by plasma treatment in an atmosphere containing an oxidizing gas such as 0). Plasma treatment containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 105 while supplying oxygen. After such treatment, it is preferable to continuously form a metal oxide film without exposing the surface of the insulating layer 105 to the atmosphere.

[0325] Next, the semiconductor film that will become the semiconductor layer 108 is processed into an island shape to form the semiconductor layer 108 (Figures 13C and 13D).

[0326] The semiconductor layer 108 can be suitably formed using a wet etching method. In this case, a portion of the insulating layer 105 in areas that do not overlap with the semiconductor layer 108 may be etched and become thinner.

[0327] Next, a heat treatment is performed. The semiconductor layer 108 may crystallize during the heat treatment.

[0328] The temperature for the heat treatment is preferably 100°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 670°C or lower, more preferably 300°C or higher and 670°C or lower, more preferably 350°C or higher and 670°C or lower, more preferably 400°C or higher and 670°C or lower, and more preferably 450°C or higher and 670°C or lower. It is preferable that the temperature of the substrate during the heat treatment falls within the above temperature range. However, the temperature of the substrate during the heat treatment is not limited to the above range.

[0329] The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing or oxygen-containing atmosphere. It is preferable to carry out the heat treatment in an oxygen-containing atmosphere. Performing the heat treatment in an oxygen-containing atmosphere may enhance effects such as defect reduction and increased grain size. CDA can be suitably used as the atmosphere for the heat treatment. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a very low content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the semiconductor layer 18 as much as possible.

[0330] The apparatus used for the heat treatment is not particularly limited, and for example, an apparatus that heats by heat conduction or thermal radiation from a heating element can be used. For example, an oven or a rapid thermal annealing (RTA) apparatus can be used for the heat treatment. As an RTA apparatus, an LRTA (Lamp RTA) apparatus that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp can be used. Examples of such lamps include halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Alternatively, as an RTA apparatus, a GRTA (Gas RTA) apparatus that heats the workpiece using high-temperature gas can be used. By using an RTA apparatus, the heat treatment time can be shortened. The treatment time is preferably 1 minute or more and 10 minutes or less, more preferably 3 minutes or more and 10 minutes or less, and more preferably 5 minutes or more and 10 minutes or less. Furthermore, when using an RTA device to achieve a short heating time, the heating temperature can be set above the strain point of the substrate. This further reduces the heating time. Typically, a GRTA device can be used to perform a heating treatment at 650°C for 6 minutes.

[0331] Heat treatment can also be used to supply oxygen to the semiconductor layer 108, which is formed from the insulating layer 105, or to the semiconductor layer 108.

[0332] Note that heat treatment is not performed at this stage, and can be combined with heat treatment performed in a later step. In addition, a heat treatment in a later step (for example, a film formation step) may also serve as this heat treatment.

[0333] After the formation of the semiconductor film that will become the semiconductor layer 108, the contact between layers 121a and 121b reduces the resistance of the contacted region. Alternatively, the contact between layers 121a and 121b is reduced by applying a heat treatment after contact. Note that this heat treatment can be combined with a heat treatment performed in a later step.

[0334] In Figures 13C and 13D, the regions in semiconductor layer 108 that overlap with layers 121a and 121b are shown as region 108Pf and region 108Qf, respectively, and the region between region 108Pf and region 108Qf is shown as region 108i. Region 108Pf is a region whose resistance has been reduced by, for example, layer 121a, and region 108Qf is a region whose resistance has been reduced by, for example, layer 121b.

[0335] Next, an insulating film 106f is formed to cover the semiconductor layer 108 and the insulating layer 105, forming the insulating layer 106. For forming the insulating film 106f, methods such as PECVD, sputtering, or ALD can be suitably used.

[0336] When an oxide semiconductor is used for the semiconductor layer 108, it is preferable that the insulating layer 106 functions as a barrier film that suppresses the diffusion of oxygen. By having the function of the insulating layer 106 that suppresses the diffusion of oxygen, the detachment of oxygen from the semiconductor layer 108 is suppressed, and oxygen vacancies (V) are formed in the semiconductor layer 108. Ｏ This suppresses the increase of ). Furthermore, the diffusion of oxygen from the semiconductor layer 108 to the conductive layer 104 via the insulating layer 106 is suppressed, thereby suppressing oxidation of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be made.

[0337] By increasing the temperature during film formation of the insulating film 106f, a gate insulating layer with fewer defects can be obtained. However, if the temperature during film formation of the insulating film 106f is high, oxygen will be desorbed from the semiconductor layer 108, resulting in oxygen vacancies and V in the semiconductor layer 108. Ｏ In some cases, the H content may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature during the deposition of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0338] Before depositing the insulating film 106f, the surface of the semiconductor layer 108 can be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. This reduces impurities at the interface between the semiconductor layer 108 and the insulating layer 106, enabling the realization of a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating film 106f. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the deposition of the insulating film 106f are performed continuously without exposure to the atmosphere.

[0339] After the insulating film 106f is formed, oxygen can be supplied to the insulating film 106f. As a method of supplying oxygen, for example, ion implantation or plasma treatment can be used. As the plasma treatment, a device that turns oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that turn gas into plasma using high-frequency power include a PECVD device, a plasma etching device, and a plasma ashing device. Plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: carbon monoxide and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0340] Next, it is preferable to deposit a film 139 on the insulating film 106f (Figures 13E and 13F). Sputtering is preferably used to deposit the film 139. By depositing the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f.

[0341] The conductivity of the film 139 is not a concern. As the film 139, at least one of an insulating film, a semiconductor film, and a conductive film can be used. As the film 139, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used.

[0342] As the film 139, it is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108.

[0343] When forming the film 139, the higher the oxygen flow ratio of the film-forming gas introduced into the processing chamber of the film-forming apparatus or the oxygen partial pressure in the processing chamber, the more the amount of oxygen supplied into the insulating film 106f can be increased. The oxygen flow ratio or the oxygen partial pressure is preferably, for example, 50% or more and 100% or less, more preferably, 60% or more and 100% or less, more preferably, 70% or more and 100% or less, more preferably, 80% or more and 100% or less, more preferably, 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% and make the oxygen partial pressure as close to 100% as possible.

[0344] Thus, by forming the film 139 by sputtering in an oxygen-containing atmosphere, it is possible to supply oxygen to the insulating film 106f and prevent oxygen from desorbing from the insulating film 106f when forming the film 139. As a result, a large amount of oxygen can be confined in the insulating film 106f. Then, by subsequent heat treatment, a large amount of oxygen can be supplied to the semiconductor layer 108. As a result, oxygen deficiency and V Ｏ H can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.

[0345] After forming the film 139, it is preferable to perform a heat treatment. By performing a heat treatment after forming the film 139, oxygen can be effectively supplied from the film 139 to the insulating film 106f.

[0346] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 106f as much as possible. The heat treatment can be carried out using an oven, RTA device, etc.

[0347] After the film 139 is formed, or after the aforementioned heat treatment, oxygen can be supplied to the insulating film 106f via the film 139. For example, ion implantation or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0348] Next, the film 139 is removed. Removing the film 139 exposes the insulating film 106f. There are no particular limitations on the method for removing the film 139, but a wet etching method can be preferably used. By using a wet etching method, etching of the insulating film 106f during the removal of the film 139 can be suppressed. This prevents the thickness of the insulating film 106f from becoming thinner, and the thickness of the insulating layer 106 can be made uniform.

[0349] The process of supplying oxygen to the insulating film 106f is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 106f by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 106f, and then oxygen can be supplied to the insulating film 106f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0350] Next, a conductive film 104f, which will become the conductive layer 104, is formed on the insulating film 106f. The conductive film 104f can be formed by, for example, sputtering, thermal CVD (including MOCVD), or ALD.

[0351] Next, a mask 192 is formed on the conductive film 104f (Figures 14A and 14B). For example, a resist mask can be used as the mask 192.

[0352] Next, the conductive film 104f and the insulating film 106f are processed using the mask 192 to form the conductive layer 104 and the insulating layer 106. After that, the mask 192 is removed (Figures 14C and 14D). For example, a wet etching method can be suitably used to form the conductive layer 104. For example, a dry etching method can be suitably used to form the insulating layer 106.

[0353] For example, when highly conductive copper is used as the conductive film 104f, the conductive layer 104 can be formed using a wet etching method.

[0354] The conductive layer 104 and the insulating layer 106 can be formed, for example, using the same resist mask. A resist mask can be formed on the conductive film 104f, and the conductive film 104f and the insulating film 106f can be processed using the resist mask as a mask. By using the same resist mask for forming the conductive layer 104 and the insulating layer 106, productivity can be increased. In the example shown in this manufacturing method, a wet etching method with isotropic etching is used for forming the conductive layer 104, and a dry etching method with anisotropic etching is used for forming the insulating layer 106, so that the edge of the conductive layer 104 is located inside the edge of the insulating layer 106. It is also possible to make the edges of the conductive layer 104 and the insulating layer 106 coincide or roughly coincide.

[0355] While it is preferable to reduce the resistance of the semiconductor layer in the regions that function as source and drain regions of the semiconductor layer 108, providing an insulating layer 106 on these regions may increase the resistance of the semiconductor layer due to the reduction of oxygen vacancies. Furthermore, providing an insulating layer 106 that functions as a barrier film on these regions may make it difficult for hydrogen from the subsequently formed insulating layer 195 to diffuse, making it difficult to reduce the resistance of the source and drain regions of the semiconductor layer 108. Therefore, it is preferable not to provide an insulating layer 106 on at least a portion of the regions that function as source and drain regions on the semiconductor layer 108.

[0356] Next, an insulating film 195f is formed to cover the conductive layer 104, the insulating layer 106, and the semiconductor layer 108, forming an insulating layer 195 (Figures 15A and 15B). The PECVD method can be suitably used to form the insulating film 195f. Here, in the region 108Pf shown in Figures 14C and 14D, regions 108P1 and 108P2 are formed as shown in Figures 15A and 15B. In the region 108Qf, regions 108Q1 and 108Q2 are formed as shown in Figures 15A and 15B. These regions are formed, for example, after the insulating film 195f is formed, or after the insulating film 195f is formed and then heat-treated. Regions 108P1 and 108Q1 are regions where resistance can be reduced by introducing impurities diffused from the insulating film 195f. It is preferable that regions 108P1 and 108Q1 have lower resistance than regions 108P2 and Q2.

[0357] For example, by performing plasma processing in an atmosphere containing a gas that functions as an impurity using a PECVD apparatus, the first element can be supplied to a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Furthermore, by using a PECVD apparatus for supplying impurities and for forming the insulating film 195f, the supply of impurities and the formation of the insulating layer 195 can be performed continuously within the apparatus, thereby increasing productivity.

[0358] A gas containing a first element can be used to deposit the insulating film 195f. For example, when hydrogen is used as the first element, the insulating film 195f can be deposited using a gas containing hydrogen (e.g., ammonia gas and hydrogen gas). This allows the supply of impurities and the deposition of the insulating film 195f to be carried out continuously within the apparatus, thereby increasing productivity. For example, when silicon oxynitride is used for the insulating film 195f, it is preferable to use a mixed gas of a silicon-containing depositing gas, an oxidizing gas, and a hydrogen-containing gas. When silicon nitride is used as the insulating film 195f, it is preferable to use a mixed gas of a silicon-containing depositing gas, nitrogen gas, an oxidizing gas, and a hydrogen-containing gas. As the silicon-containing depositing gas, for example, one or more of silane, disilane, trisilane, and silane fluoride can be used. As the oxidizing gas, a gas containing oxygen can be suitably used. As the oxidizing gas, for example, oxygen (O) ２ ), ozone (O ３ ), nitrous oxide (N ２ O), nitric oxide (NO) and nitrogen dioxide (NO) ２ One or more of the following can be used: Typically, when silicon oxidiznitride is used for the insulating film 195f, silane gas, nitrous oxide (N) ２ A mixture of gas (O) and ammonia gas can be used. When silicon nitride oxide is used for the insulating film 195f, silane gas, nitrogen gas, and nitrous oxide (N) can be used. ２ A mixture of gas O and ammonia gas can be used.

[0359] If the deposition temperature of the insulating film 195f is too high, impurities diffused from the insulating film 195f may diffuse into the peripheral area of ​​the semiconductor layer 108, including the channel formation region. Furthermore, the electrical resistance of regions 108P and 108Q may increase. Therefore, it is preferable to determine the deposition temperature of the insulating film 195f considering the diffusion of impurities.

[0360] The deposition temperature for the insulating film 195f is preferably, for example, 150°C to 400°C, more preferably 200°C to 350°C, more preferably 250°C to 350°C, and more preferably 250°C to 300°C. By depositing the insulating film 195f at a low temperature, a transistor with good electrical characteristics can be obtained even with a short channel length.

[0361] After forming the insulating film 195f, a heat treatment can be performed. This heat treatment may cause hydrogen to diffuse into regions 108P1 and 108Q1, or the diffused hydrogen to enter oxygen vacancies, potentially lowering the electrical resistance. A detailed explanation of the heat treatment is omitted as it can be found in the previous description. Note that if the heat treatment temperature is too high (for example, above 500°C), impurities may diffuse into the channel formation region, potentially leading to a decrease in the electrical characteristics and reliability of the transistor.

[0362] Note that this heat treatment is not required. Furthermore, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Also, if there is a heat treatment in a later step (e.g., a film formation process), this heat treatment may be combined with that step.

[0363] Next, a portion of the insulating film 195f is removed to form openings 147a and 147b that reach the semiconductor layer 108 (Figures 15C and 15D). This forms the insulating layer 195. For example, a dry etching method can be suitably used to form openings 147a and 147b.

[0364] Next, conductive layers 112a and 112b are formed to cover openings 147a and 147b.

[0365] Next, an insulating layer 218 is formed on the insulating layer 195, the conductive layer 112a, and the conductive layer 112b. The PECVD method can be suitably used to form the insulating layer 218.

[0366] By following the above steps, the semiconductor device 20 shown in Figures 2A to 2C can be manufactured.

[0367] The configuration examples shown in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0368] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0369] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0370] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0371] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0372] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0373] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８cm −３ It is within the following range. By sufficiently reducing the carrier concentration, it can be expected that the value of the hole mobility can be increased to about 270 cm ２ / (V·s).

[0374] Indium oxide can contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, copper, etc. By substituting these elements for indium, the carrier concentration can be lowered. In addition, nitrogen, phosphorus, arsenic, antimony, etc. can be mentioned. By substituting these elements for oxygen, the carrier concentration can be lowered.

[0375] On the other hand, by increasing the carrier concentration, the electrical resistance can be lowered. For example, the range of the carrier concentration suitable for the source region and drain region of a transistor, or a resistor, or a transparent conductive film is such that the value of the carrier concentration is 1×10 ２０ cm −３ It includes the range, for example 1×10 １９ cm −３ or more, 1×10 ２２ cm −３ or less. By sufficiently increasing the carrier concentration, it can be expected that the resistivity can be reduced to 1×10 −４ Ω·cm or less.

[0376] Indium oxide can contain an element that increases the carrier concentration. For example, it is preferable to contain an element common to the source electrode and drain electrode of a transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, boron, etc. In particular, it is more preferable to use an element whose oxide has conductivity or semiconductor properties.

[0377] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0378] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0379] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0380] The crystallinity of indium oxide can be analyzed, for example, by XRD, TEM, or electron diffraction. Alternatively, a combination of these methods may be used for analysis.

[0381] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0382] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0383] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0384] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0385] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0386] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0387] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0388] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0389] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0390] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0391] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0392] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0393] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0394] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0395] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0396] (Embodiment 3) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 20 to 25.

[0397] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0398] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0399] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a flexible printed circuit board (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an integrated circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0400] The display device of this embodiment may also function as a touch panel. For example, the display device can be fitted with various detection elements (also called sensor elements) that can detect the proximity or contact of an object to be detected, such as a finger.

[0401] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0402] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0403] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0404] <Example of Display Device Configuration 1> Figure 20 shows a perspective view of the display device 50A.

[0405] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 20, substrate 152 is shown with a dashed line.

[0406] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Figure 20 shows an example in which the IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 20 can also be described as a display module having the display device 50A, an IC, and an FPC.

[0407] The connection portion 140 is provided on the outside of the display unit 162. The connection portion 140 can be provided along one or more sides of the display unit 162. There can be one or more connection portions 140. Figure 20 shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit 162. The connection portion 140 connects the common electrode of the display element to the conductive layer, and can supply potential to the common electrode.

[0408] The circuit section 164 includes, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 can be configured to include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0409] The circuit section 164 can utilize various circuits, including shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexer circuits, and logic circuits. The circuit section 164 can also utilize transistors and capacitive elements. The transistors in the circuit section 164 can be formed using the same process as the transistors in the pixel circuit.

[0410] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. These signals and power are input to the conductive layer 165 from the outside via the FPC 172, or from the IC 173.

[0411] Figure 20 shows an example where IC 173 is mounted on the substrate 151 using the COG method. IC 173 can be an IC having, for example, one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can also be configured without an IC. Furthermore, the IC can be mounted on the FPC using the COF method or the like.

[0412] A semiconductor device according to one aspect of the present invention can be applied, for example, to one or both of the display unit 162 and the circuit unit 164 of a display device 50A. Oxide semiconductors (OS) can preferably be used in the channel formation region of the transistors in the display device. By using OS transistors, a display device with low power consumption can be made. Furthermore, the semiconductor device according to one aspect of the present invention can be used in both the display unit 162 and the circuit unit 164, that is, all of the transistors in the display device can be OS transistors. By making all of the transistors in the display device OS transistors in this way, the manufacturing cost can be kept low.

[0413] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0414] The display unit 162 is the area in the display device 50A that displays images, and has a plurality of pixels 201 arranged periodically. Figure 20 shows a magnified view of one pixel 201.

[0415] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0416] The pixel 201 shown in Figure 20 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. The number of sub-pixels that a single pixel has is not particularly limited.

[0417] Each sub-pixel 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0418] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. Other display elements can also be used, such as shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type elements. Furthermore, QLEDs (Quantum-dot LEDs) using a light source and color conversion technology with quantum dot materials can be used.

[0419] Examples of quantum dot materials used in the color conversion layer include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of elements belonging to Groups 4 to 14 and Group 16 elements, compounds of Group 2 elements and Group 16 elements, compounds of Group 13 elements and Group 15 elements, compounds of Group 13 elements and Group 17 elements, compounds of Group 14 elements and Group 15 elements, compounds of Group 11 elements and Group 17 elements, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0420] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, telluride Indium sulfide, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, gallium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tungsten oxide Examples include carbon dioxide, titanium dioxide, zirconium dioxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, compounds of selenium, zinc, and cadmium, compounds of indium, arsenic, and phosphorus, compounds of cadmium, selenium, and sulfur, compounds of cadmium, selenium, and tellurium, compounds of indium, gallium, and arsenic, compounds of indium, gallium, and selenium, compounds of indium, selenium, and sulfur, compounds of copper, indium, and sulfur, and combinations thereof. In addition, so-called alloy-type quantum dots, whose composition is expressed in any ratio, can be used.

[0421] Examples of quantum dot structures include core-type, core-shell-type, and core-multishell-type structures. Furthermore, because quantum dots have a high proportion of surface atoms, they are highly reactive and prone to aggregation. Therefore, to prevent aggregation and improve dispersibility in the dispersion medium, it is preferable that a protective agent is attached to the surface of the quantum dots, or that protective groups are provided. This can also reduce reactivity and improve electrical stability.

[0422] As the size of a quantum dot decreases, its band gap increases, so its size is adjusted appropriately to obtain light of a desired wavelength. As the size decreases, the emission of quantum dots shifts towards the blue side, that is, towards higher energy, so by changing the size of the quantum dots, the emission wavelength can be adjusted across the ultraviolet, visible, and infrared spectral wavelength ranges. The size (diameter) of a quantum dot is, for example, 0.5 nm to 20 nm, preferably 1 nm to 10 nm. Furthermore, the narrower the size distribution of quantum dots, the narrower the emission spectrum becomes, and the better the color purity of the emission can be obtained. The shape of the quantum dots is not particularly limited and may be spherical, rod-shaped, disc-shaped, or other shapes. A quantum rod, which is a rod-shaped quantum dot, has the function of exhibiting directional light.

[0423] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0424] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and Guest Host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0425] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0426] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0427] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0428] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0429] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0430] One embodiment of the present invention is a semiconductor device having a transistor with a high on-current. A suitable material for the channel formation region of the transistor can be an oxide semiconductor (OS), resulting in a transistor with a low off-current. This semiconductor device can be suitably used in either or both of the display unit 162 and the circuit unit 164. Furthermore, this semiconductor device can be used in both the display unit 162 and the circuit unit 164, meaning all transistors in the display device can be OS transistors. By using OS transistors for all transistors in the display device in this way, manufacturing costs can be kept low.

[0431] Figure 21A shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the end section.

[0432] The display device 50A shown in Figure 21A has transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0433] The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0434] The display device 50A is a top-emission type. In the top-emission type, transistors and the like can be placed overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0435] Transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. Transistor 205D is provided in the circuit section 164, while transistors 205R, 205G, and 205B are provided in the display section 162. These transistors can be manufactured using the same process. Note that transistors with different structures can also be used for transistors 205D, 205R, 205G, and 205B.

[0436] This embodiment shows an example in which OS transistors are used for transistors 205D, 205R, 205G, and 205B. Transistors according to one aspect of the present invention can be used for transistors 205D, 205R, 205G, and 205B. In other words, the display device 50A has transistors according to one aspect of the present invention in both the display unit 162 and the circuit unit 164. By using transistors according to one aspect of the present invention in the display unit 162, the pixel size can be reduced and higher resolution can be achieved. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced and the bezel can be narrowed. For details on transistors according to one aspect of the present invention, refer to the description in the previous embodiment.

[0437] Figure 21A shows an example configuration in which transistors 205D, 205R, 205G, and 205B are replaced with transistor 100 as shown in Figure 2B. By using TGSA type transistors, the parasitic capacitance between the source electrode, drain electrode, and gate electrode can be reduced. Therefore, the degradation of display quality caused by parasitic capacitance can be suppressed.

[0438] Transistors 205D, 205R, 205G, and 205B each have a conductive layer 104 functioning as a first gate, a conductive layer 103 functioning as a second gate electrode, an insulating layer 106 functioning as a first gate insulating layer, a second gate insulating layer 105, conductive layers 112a and 112b functioning as source and drain electrodes, and a semiconductor layer 108 having a metal oxide. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0439] Furthermore, the transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures.

[0440] The display device of this embodiment may have, for example, one or more of planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be top-gate or bottom-gate types. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0441] The display device of this embodiment may also have Si transistors.

[0442] To increase the luminescence brightness of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the light-emitting element.

[0443] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thereby allowing control of the current flowing to the light-emitting element. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0444] In terms of the saturation of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, OS transistors can stabilize the luminescence brightness of a light-emitting element because the change in source-drain current is small even when the source-drain voltage is changed.

[0445] The transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 may all be the same or there may be two or more different structures. Similarly, the structures of the multiple transistors in the display unit 162 may all be the same or there may be two or more different structures.

[0446] All of the transistors in the display unit 162 may be OS transistors, all of the transistors in the display unit 162 may be Si transistors, or some of the transistors in the display unit 162 may be OS transistors and the rest may be Si transistors.

[0447] For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for transistors that function as switches to control conduction and non-conduction between wires, and an LTPS transistor is used for transistors that control current.

[0448] For example, one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. One of the source and drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

[0449] On the other hand, the other transistor in the display unit 162 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and one of the source and drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly low (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image.

[0450] An insulating layer 218 is provided so as to cover transistors 205D, 205R, 205G, and 205B. As mentioned above, the insulating layer 218 can be an inorganic insulating layer, an organic insulating layer, or both. Preferably, the insulating layer 218 has an organic insulating layer that functions as a planarizing layer. Alternatively, the insulating layer 218 can have a laminated structure of an organic insulating layer and an inorganic insulating layer. Preferably, the outermost layer of the insulating layer 218 functions as an etching protection layer. An inorganic insulating layer can be suitably used as the etching protection layer. This makes it possible to suppress the formation of recesses in the insulating layer 218 when processing the pixel electrodes 111R, 111G, and 111B. Alternatively, recesses may be provided in the insulating layer 218 when processing the pixel electrodes 111R, 111G, and 111B. Note that the pixel electrodes 111R, 111G, and 111B are sometimes collectively referred to as the pixel electrode 111.

[0451] A light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B are provided on the insulating layer 218.

[0452] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 218, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Figure 21A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0453] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 218, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Figure 21A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0454] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 218, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Figure 21A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0455] In Figure 21A, EL layers 113R, 113G, and 113B are all shown to be the same thickness, but this is not the only option. The thicknesses of EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the thickness of EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each is intensified. This makes it possible to realize a microcavity structure and improve the color purity of the light emitted from each light-emitting element.

[0456] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R at an opening provided in the insulating layer 218. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0457] The ends of the pixel electrodes 111R, 111G, and 111B are covered by an insulating layer 237. The insulating layer 237 functions as a partition. The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both inorganic insulating materials and / or organic insulating materials. For example, the insulating layer 237 can be made of a material that can be used for the insulating layer 218. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. In addition, the insulating layer 237 electrically insulates adjacent light-emitting elements from each other.

[0458] The insulating layer 237 is provided at least on the display unit 162. The insulating layer 237 may be provided not only on the display unit 162, but also on the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may extend to the end of the display device 50A.

[0459] The common electrode 115 is a continuous film provided in common to the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The common electrode 115, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed by the same process as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B.

[0460] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0461] A conductive film that transmits visible light may also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0462] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, other examples of such materials include aluminum-containing alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-magnesium alloys and silver-containing alloys such as silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0463] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0464] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the electrical resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable.

[0465] The EL layers 113R, 113G, and 113B are each provided in an island-like manner. In Figure 21A, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 21A, but this is not the only case. In other words, adjacent EL layers may not overlap and may be separated from each other. Furthermore, in a display device, there may be both areas where adjacent EL layers overlap and areas where adjacent EL layers do not overlap and are separated.

[0466] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0467] Examples of luminescent materials include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0468] Examples of quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Furthermore, quantum dot materials containing elemental groups of Group 2 and Group 16, Group 13 and Group 15, Group 13 and Group 17, Group 11 and Group 17, or Group 14 and Group 15 can be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0469] The light-emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more of the organic compounds may be substances with high hole transport properties (hole transport material) and / or substances with high electron transport properties (electron transport material). Alternatively, one or more of the organic compounds may be bipolar substances (substances with high electron and hole transport properties) or TADF materials.

[0470] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0471] The EL layer may have, in addition to the light-emitting layer, one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may contain either or both a bipolar material and a TADF material.

[0472] The light-emitting element can be made of either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0473] The light-emitting element may be a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. The tandem structure is a configuration in which multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be made. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same brightness, thus improving reliability. The tandem structure can also be called a stack structure.

[0474] In Figure 21A, when using a tandem light-emitting element, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0475] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded together via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 21A, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided in a frame shape so as not to overlap with the light-emitting elements. Furthermore, the space may be filled with a resin different from the adhesive layer 142 provided in a frame shape.

[0476] The protective layer 131 is provided at least on the display section 162, and preferably so as to cover the entire display section 162. It is preferable that the protective layer 131 covers not only the display section 162, but also the connection section 140 and the circuit section 164. Furthermore, it is preferable that the protective layer 131 extends to the end of the display device 50A. On the other hand, in the connection section 197, there is a portion where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 166.

[0477] By providing a protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved.

[0478] The protective layer 131 can be a single layer or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

[0479] The presence of an inorganic film in the protective layer 131 prevents oxidation of the common electrode 115 and suppresses the intrusion of impurities (such as moisture and oxygen) into the light-emitting element, thereby suppressing degradation of the light-emitting element and improving the reliability of the display device.

[0480] The protective layer 131 preferably has one or more inorganic insulating layers. The protective layer 131 can be made of the same material that can be used for the insulating layer 106 and the insulating layer 105. In particular, the protective layer 131 preferably uses a nitride or nitride oxide, and more preferably uses a nitride.

[0481] The protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO. The inorganic film is preferably highly resistive, and more specifically, it is preferably more resistive than the common electrode 115. The inorganic film may further contain nitrogen.

[0482] When the light emitted from a light-emitting element is extracted via a protective layer 131, it is preferable that the protective layer 131 has high transmittance to visible light. For example, ITO, IGZO, and aluminum oxide are preferred because they are inorganic materials with high transmittance to visible light.

[0483] As the protective layer 131, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using such a laminated structure, it is possible to suppress the penetration of impurities (water, oxygen, etc.) into the EL layer.

[0484] Furthermore, the protective layer 131 may have an organic layer. For example, the protective layer 131 may have both an organic layer and an inorganic layer. Examples of organic layers that can be used in the protective layer 131 include organic insulating layers that can be used in the insulating layer 218.

[0485] A connection portion 197 is provided in the region of substrate 151 where substrate 152 does not overlap. At the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. Figure 21A shows an example in which the conductive layer 165 is formed by processing the same conductive film as conductive layers 112a and 112b. The conductive layer 166 is shown as an example in which it is formed by processing the same conductive film as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. The connection portion between conductive layer 165 and conductive layer 166 can be configured similarly to the connection portion between pixel electrode 111 and conductive layer 112b. Specifically, Figure 21A shows an example in which an opening is provided in the insulating layer 218, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 at this opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection part 197 and the FPC 172 to be connected via the connection layer 242.

[0486] The display device 50A is of the top-emission type. The light emitted by the light-emitting element is emitted towards the substrate 152. It is preferable to use a material with high transmittance to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0487] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in connection portions 140, and in circuit portions 164, etc.

[0488] A colored layer, such as a color filter, may be provided on the surface of the substrate 152 facing the substrate 151, or on the protective layer 131. By placing a color filter on top of the light-emitting element, the color purity of the light emitted from the pixel can be increased.

[0489] A colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. One or more of the following can be used for each colored layer: metal materials, resin materials, pigments, and dyes. The colored layers are formed at the desired positions using methods such as printing, inkjet printing, and photolithography etching.

[0490] Various optical components can be placed on the outside of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. In addition, surface protection layers such as an antistatic film to suppress the adhesion of dust, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and a shock-absorbing layer may be placed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ Providing a protective layer (where x is a real number greater than 0) is preferable as it can suppress surface contamination and scratching. Alternatively, DLC (diamond-like carbon), aluminum oxide, polyester-based materials, or polycarbonate-based materials may be used as the surface protective layer. It is preferable to use a material with high transmittance to visible light for the surface protective layer. Furthermore, it is preferable to use a material with high hardness for the surface protective layer.

[0491] The substrates 151 and 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc., respectively. The substrate on the side that extracts light from the light-emitting element should be made of a material that transmits the light. If flexible materials are used for substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. In addition, a polarizing plate may be used as at least one of substrates 151 and 152.

[0492] As substrates 151 and 152, various materials can be used, such as polyester resins like polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 may be made of glass of a thickness sufficient to provide flexibility.

[0493] Furthermore, when a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy for the substrate of the display device. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence). Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0494] Various types of curing adhesives can be used as the adhesive layer 142, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0495] As the connecting layer 242, an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), etc., can be used.

[0496] <Example of Display Device Configuration 2> Figure 21B shows an example of a cross-section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). The configuration shown in Figure 21B can be combined with the configuration of the region including the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 218 of the display unit 162, the connection unit 140, and the end portion shown in Figure 21A. Note that in the following description of the display device, parts that are the same as those described in the previously described display device may be omitted.

[0497] The display device 50B shown in Figure 21B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light, etc.

[0498] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0499] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0500] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0501] The light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 115. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0502] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 21B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0503] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers can be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration can be obtained in which the entire light-emitting element emits white light. Furthermore, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers combine to create a configuration in which the entire light-emitting element emits white light.

[0504] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0505] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, a light-emitting unit that emits red light, and a light-emitting unit that emits blue light in that order. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. In addition, other layers may be provided between the two light-emitting layers.

[0506] Furthermore, by applying a microcavity structure, a light-emitting element that normally emits white light may also emit light of specific wavelengths, such as red, green, or blue, with increased intensity.

[0507] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 21B emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. The color conversion layer can be described in the above description. Specifically, the various quantum dot materials described above can be used for the color conversion layer. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. Some of the light emitted by a light-emitting element may pass through without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via a colored layer, the color of light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light exhibited by the subpixel.

[0508] <Example of Display Device Configuration 3> The display device 50C shown in Figure 22 differs from the display device 50A in that it has a conductive layer 234p, a conductive layer 234a, a conductive layer 234b, and an insulating layer 239.

[0509] An insulating layer 239 is provided on the conductive layer 234p, conductive layer 234a, conductive layer 234b, and insulating layer 218, and light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 239. The insulating layer 239 can be made from the same materials as those used for the insulating layer 218.

[0510] The conductive layer 234p is provided so as to cover the opening provided in the insulating layer 218. The conductive layer 234p is connected to the conductive layer 112b of the transistor 205R at the opening.

[0511] The pixel electrode 111R is provided so as to cover an opening in the insulating layer 239. The pixel electrode 111R is in contact with the conductive layer 234p at the opening and is connected to the conductive layer 234p. In other words, the pixel electrode 111R is connected to the conductive layer 112b via the conductive layer 234p. The same applies to the pixel electrode 111G and the pixel electrode 111B.

[0512] The conductive layer 234a is provided so as to cover the opening provided in the insulating layer 218. The conductive layer 234a is in contact with the conductive layer 165 at the opening and is connected to the conductive layer 165.

[0513] The conductive layer 166 is provided so as to cover the opening provided in the insulating layer 239. The conductive layer 166 is in contact with the conductive layer 234a at the opening and is connected to the conductive layer 234a. In other words, the conductive layer 166 is connected to the conductive layer 165 via the conductive layer 234a.

[0514] Figure 22 shows a configuration in which the circuit section 164 has a conductive layer 234b. Alternatively, the conductive layer 234b can be connected to the transistor 205D.

[0515] The conductive layers 234p, 234a, and 234b can be formed by processing the same conductive film. Furthermore, each of the conductive layers 234p, 234a, and 234b functions as wiring. The conductive layers 234p, 234a, and 234b are provided on different layers from the conductive layers 112a, 112b, 104, and 103. Therefore, since wiring can be arranged on each layer, the degree of layout flexibility is increased, and the circuit's occupied area can be reduced.

[0516] The conductive layers 234p, 234a, and 234b can be made from the materials listed for conductive layers 112a, 112b, and 104. The conductive layers 234p, 234a, and 234b can be formed in the same process. For example, the conductive layers 234p, 234a, and 234b can be formed by depositing a conductive film and then processing the conductive film.

[0517] <Example of Display Device Configuration 4> The display device 50D shown in Figure 23 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0518] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0519] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. Figure 23 shows an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153. In addition, a colored layer 132R, a colored layer 132G, and a colored layer 132B are provided on the insulating layer 195, and an insulating layer 218 is provided on the colored layer 132R, a colored layer 132G, and a colored layer 132B.

[0520] The light-emitting element 130R, which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0521] The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0522] The light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.

[0523] The pixel electrodes 111R, 111G, and 111B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission type display device, a metal with low electrical resistivity can be used for the common electrode 115, thereby suppressing voltage drops caused by the electrical resistance of the common electrode 115 and achieving high display quality.

[0524] A transistor according to one aspect of the present invention can be miniaturized and have a smaller occupied area, which allows for an increase in the aperture ratio of pixels or a reduction in the size of pixels in a display device with a bottom emission structure.

[0525] <Example of Display Device Configuration 5> The display device 50E shown in Figure 24A differs from the display device 50A mainly in that it has a light-receiving element 130S. Also, in Figure 24A, transistors below the insulating layer 218 (for example, transistor 205R, transistor 205G, and the transistor connected to the light-receiving element 130S) are omitted. The transistors such as transistor 205R and transistor 205G can be configured as shown in Figure 21A.

[0526] The display device 50E has a light-emitting element and a light-receiving element in each pixel. In the display device 50E, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element.

[0527] In a display device 50E having light-emitting and light-receiving elements in its pixels, the pixels have a light-receiving function, allowing for the detection of contact or proximity of an object while displaying an image. Therefore, the display unit 162 has, in addition to an image display function, one or both of an imaging function and a sensing function. For example, the display device 50E can not only display an image using all of its subpixels, but some subpixels can also emit light as a light source, some other subpixels can perform light detection, and the remaining subpixels can display an image.

[0528] Therefore, it is not necessary to provide a light receiving unit and a light source separately from the display device 50E, and the number of components in the electronic device can be reduced. For example, there is no need to separately provide a biometric authentication device or a capacitive touch panel for scrolling, etc., which are provided in the electronic device. Therefore, by using the display device 50E, it is possible to provide an electronic device with reduced manufacturing costs.

[0529] When a light-receiving element is used as an image sensor, the display device 50E can capture an image using the light-receiving element. For example, the image sensor can be used to capture images for personal authentication, such as fingerprints, palm prints, irises, pulse patterns (including vein patterns and arterial patterns), or faces.

[0530] The light-receiving element can be used in touch sensors (also called direct touch sensors) or non-contact sensors (also called hover sensors, hover touch sensors, or touchless sensors). Touch sensors can detect an object (such as a finger, hand, or pen) by making direct contact between the display device and the object. Non-contact sensors, on the other hand, can detect an object even if the object does not come into contact with the display device.

[0531] The light-receiving element 130S has a pixel electrode 111S on an insulating layer 218, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50E.

[0532] The pixel electrode 111S is connected to a conductive layer (for example, a conductive layer that functions as one of the source electrode and drain electrode) of a transistor located beneath the insulating layer 218 at an opening provided in the insulating layer 218.

[0533] The ends of the pixel electrodes 111S are covered by an insulating layer 237.

[0534] The common electrode 115 is a continuous film provided in common to the light-receiving element 130S, the light-emitting element 130R (not shown), the light-emitting element 130G, and the light-emitting element 130B. The common electrode 115, which is shared by the light-emitting element and the light-receiving element, is connected to the conductive layer 123 provided at the connection portion 140.

[0535] The functional layer 113S has at least an active layer (also called a photoelectric conversion layer). The active layer contains a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), and the manufacturing equipment can be shared.

[0536] The functional layer 113S may further include layers other than the active layer, such as a material with high hole transport properties, a material with high electron transport properties, or a bipolar material. Furthermore, it may also further include layers containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material. For example, the functional layer 113S can be made from materials that can be used in the above-described light-emitting devices.

[0537] The photodetector can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the photodetector can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0538] The display device 50E shown in Figures 24B and 24C has a layer 353 with a light-receiving element, a circuit layer 355, and a layer 357 with an light-emitting element between the substrate 151 and the substrate 152.

[0539] Layer 353 has, for example, a light-receiving element 130S. Layer 357 has, for example, light-emitting elements 130R, 130G, and 130B.

[0540] The circuit layer 355 includes a circuit for driving a light-receiving element and a circuit for driving a light-emitting element. The circuit layer 355 includes, for example, a transistor 205R, a transistor 205G, a transistor connected to the light-receiving element, etc. In addition, the circuit layer 355 may be provided with one or more of the following: switches, capacitors, resistors, wiring, and terminals.

[0541] Figure 24B shows an example of using the light-receiving element 130S as a touch sensor. As shown in Figure 24B, the light emitted by the light-emitting element in layer 357 is reflected by the finger 352 that is in contact with the display device 50E, and the light-receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has come into contact with the display device 50E.

[0542] Figure 24C shows an example of using the light-receiving element 130S as a non-contact sensor. As shown in Figure 24C, the light emitted by the light-emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50E, and the light-receiving element in layer 353 detects the reflected light.

[0543] <Example of Display Device Configuration 6> The display device 50F shown in Figure 25A is an example of a display device to which an MML (metal maskless) structure is applied. In other words, the display device 50F has a light-emitting element manufactured without using a fine metal mask.

[0544] In a display device using an MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by depositing a light-emitting layer onto one surface and then processing it using lithography. Therefore, it is possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and displays high quality. For example, if the display device is composed of three types of light-emitting elements, such as a blue light-emitting element, a green light-emitting element, and a red light-emitting element, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0545] Because MML (Multilayer Molded) devices can be manufactured without using a metal mask, they can exceed the resolution limits imposed by the precision required for metal mask alignment. Furthermore, when manufacturing devices without a metal mask, the equipment and cleaning processes associated with metal mask manufacturing are eliminated. Additionally, since the lithography process can utilize equipment common to or similar to that used for transistor manufacturing, there is no need to introduce special equipment for manufacturing MML devices. Thus, MML structures allow for lower manufacturing costs, making them suitable for mass production of devices.

[0546] In a display device to which an MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement. Therefore, a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) can be realized using a so-called stripe arrangement in which the R, G, and B subpixels are each arranged in one direction.

[0547] By providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0548] By employing a film deposition process using an area mask and a processing process using a resist mask, light-emitting elements can be fabricated using a relatively simple process.

[0549] Note that the laminated structure from substrate 151 to insulating layer 218, and the laminated structure from protective layer 131 to substrate 152 are the same as those of the display device 50A, so their explanation is omitted.

[0550] In Figure 25A, light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 218.

[0551] The light-emitting element 130R includes a conductive layer 124R on an insulating layer 218, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in Figure 25A emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0552] The light-emitting element 130G includes a conductive layer 124G on an insulating layer 218, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in Figure 25A emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0553] The light-emitting element 130B includes a conductive layer 124B on an insulating layer 218, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in Figure 25A emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be called the pixel electrode.

[0554] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by multiple light-emitting elements is referred to as the common layer 114. In this specification, the common layer 114 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc. Furthermore, light-emitting elements manufactured without using a metal mask do not need to have a common layer, and all layers constituting the EL layer may be formed in an island-like manner.

[0555] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0556] Note that in Figure 25A, layers 133R, 133G, and 133B are all shown to be the same thickness, but this is not the only option. The thicknesses of layers 133R, 133G, and 133B may be different.

[0557] The conductive layer 124R is connected to the conductive layer 112b of transistor 205R at an opening provided in the insulating layer 218. Similarly, the conductive layer 124G is connected to the conductive layer 112b of transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of transistor 205B.

[0558] The conductive layer 124R, conductive layer 124G, and conductive layer 124B are formed to cover the openings provided in the insulating layer 218. Layer 128 is embedded in the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B, respectively.

[0559] Layer 128 has the function of flattening the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B, which are connected to conductive layers 124R, 124G, and 124B, are provided on conductive layers 124R, 124G, and 124B and on layer 128. Therefore, regions overlapping with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixels. It is preferable to use conductive layers that function as reflective electrodes for conductive layers 124R and 126R.

[0560] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material, and especially preferable that it be formed using an organic insulating material. For example, an organic insulating material that can be used for the insulating layer 237 described above can be applied to layer 128.

[0561] Figure 25A shows an example in which the upper surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0562] The height of the top surface of layer 128 and the height of the top surface of conductive layer 124R may be the same, approximately the same, or different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0563] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or it may cover the side surface of the end of the conductive layer 124R. Preferably, the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape. Specifically, it is preferable that the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0564] Detailed explanations of conductive layers 124G, 126G, and conductive layers 124B, 126B are omitted because they are the same as conductive layers 124R, 126R.

[0565] The top and sides of the conductive layer 126R are covered by layer 133R. Similarly, the top and sides of the conductive layer 126G are covered by layer 133G, and the top and sides of the conductive layer 126B are covered by layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixels.

[0566] The upper surfaces and sides of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.

[0567] In Figure 25A, the insulating layer 237 shown in Figure 21A, etc., is not provided between the conductive layer 126R and layer 133R. Similarly, the insulating layer 237 is not provided between the conductive layer 126G and layer 133G, and between the conductive layer 126B and layer 133B. In other words, the display device 50F does not have an insulating layer (also called a partition, bank, spacer, etc.) that is in contact with the pixel electrodes and covers the upper edges of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0568] As described above, layers 133R, 133G, and 133B each have an emissive layer. Preferably, layers 133R, 133G, and 133B each have one or both of a carrier transport layer (electron transport layer or hole transport layer) and a carrier block layer (hole block layer or electron block layer) on the emissive layer. When the surfaces of layers 133R, 133G, and 133B are exposed to the atmosphere during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the emissive layer prevents the emissive layer from being exposed to the atmosphere because it does not have the emissive layer exposed to the outermost surface. This reduces the damage the emissive layer receives and improves the reliability of the light-emitting element.

[0569] The common layer 114 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.

[0570] Each side of layer 133R, layer 133G, and layer 133B is covered by the insulating layer 125. The insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B via the insulating layer 125.

[0571] The sides (and even a portion of the top surface) of layers 133R, 133G, and 133B are covered by at least one of the insulating layers 125 and 127. This prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrode and the sides of layers 133R, 133G, and 133B, thereby suppressing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0572] Preferably, the insulating layer 125 has regions that are in contact with the respective sides of layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0573] The insulating layer 127 is provided on the insulating layer 125 so as to fill any recesses in the insulating layer 125. Preferably, the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.

[0574] By providing insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, thereby reducing the large height differences and irregularities on the formed surface of layers (e.g., carrier injection layers and common electrodes) on the island-shaped layers, making it flatter. Consequently, the coverage of the carrier injection layers and common electrodes can be improved.

[0575] The common layer 114 and the common electrode 115 are provided on layers 133R, 133G, 133B, insulating layer 125, and insulating layer 127. Before the insulating layer 125 and insulating layer 127 are provided, a step difference occurs due to the region where the pixel electrode and island-shaped EL layer are provided and the region where the pixel electrode and island-shaped EL layer are not provided (the region between light-emitting elements). In one embodiment of the present invention, the presence of the insulating layer 125 and insulating layer 127 can flatten this step difference and improve the coverage of the common layer 114 and the common electrode 115. Therefore, connection failures due to step breaks can be suppressed. In addition, it is possible to suppress the local thinning of the common electrode 115 due to the step difference and the resulting increase in electrical resistance.

[0576] The upper surface of the insulating layer 127 preferably has a highly flat shape. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a convex curved shape with a large radius of curvature.

[0577] The insulating layer 125 can be a single-layer structure or a laminated structure of two or more layers. Preferably, the insulating layer 125 has one or more inorganic insulating layers. The insulating layer 125 can be made of the same material that can be used for the insulating layer 106 and insulating layer 105. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer during the formation of the insulating layer 127. In particular, by applying an inorganic insulating film such as an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 with fewer pinholes and excellent function in protecting the EL layer can be formed. Alternatively, the insulating layer 125 may be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 may be a laminated structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0578] Preferably, the insulating layer 125 functions as a barrier insulating layer against at least one of water and oxygen. Preferably, the insulating layer 125 has the function of suppressing the diffusion of at least one of water and oxygen. Furthermore, preferably, the insulating layer 125 has the function of capturing or fixing (getting) at least one of water and oxygen.

[0579] The insulating layer 125 functions as a barrier insulating layer, thereby suppressing the intrusion of impurities (typically at least one of water and oxygen) that could diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and, furthermore, a highly reliable display device.

[0580] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the large height differences and irregularities in the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface forming the common electrode 115.

[0581] As the insulating layer 127, an insulating layer having an organic material can be suitably used. Preferably, a photosensitive resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin is preferred. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0582] As the insulating layer 127, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins may be used. Alternatively, as the insulating layer 127, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used. Furthermore, a photoresist may be used as the photosensitive resin. Either a positive-type or negative-type material may be used as the photosensitive resin.

[0583] The insulating layer 127 may be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element, the insulating layer 127 can suppress light leakage (stray light) from the light-emitting element to adjacent light-emitting elements through the insulating layer 127. This improves the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0584] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). In particular, it is preferable to use a resin material obtained by laminating or mixing two or more color filter materials, as this can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, it is possible to create a black or near-black resin layer.

[0585] <Example of Display Device Configuration 7> Figure 25B shows an example of a cross-section of the display unit 162 of the display device 50G. The display device 50G differs from the display device 50F in that a coloring layer (such as a color filter) is provided for each sub-pixel of each color. The configuration shown in Figure 25B can be combined with the configuration shown in Figure 25A, which includes the region containing the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 218 of the display unit 162, the connection unit 140, and the end.

[0586] The display device 50G shown in Figure 25B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R, a colored layer 132G, and a colored layer 132B, etc.

[0587] The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50G via the colored layer 132R. Similarly, the light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50G via the colored layer 132G. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50G via the colored layer 132B.

[0588] Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed using the same material and the same process. Furthermore, these three layers 133 are spaced apart from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0589] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 25B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0590] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 25B emit blue light. In this case, layer 133 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. Moreover, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. By extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0591] Furthermore, while Figure 25A shows a top-emission type display device, a bottom-emission type display device can also be used.

[0592] Furthermore, in Figure 25A, a light-receiving element can be provided on the insulating layer 218. The light-emitting element and the light-receiving element can use a common electrode 115 in common. The light-receiving element can also have the same configuration as the light-emitting element; for example, it can function as a light-receiving element by replacing the EL layer 113 of the light-emitting element with a functional layer.

[0593] Furthermore, a display device according to one embodiment of the present invention may be a display device using liquid crystal elements. In addition, VA mode, FFS mode, etc., can be used as the driving mode for the liquid crystal.

[0594] This embodiment can be combined with other embodiments as appropriate.

[0595] (Embodiment 4) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 26 to 28.

[0596] The electronic device of this embodiment has a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made high-definition and high-resolution. Therefore, it can be used in the display units of various electronic devices.

[0597] A semiconductor device according to one aspect of the present invention can also be applied to components other than the display unit of an electronic device. For example, using a semiconductor device according to one aspect of the present invention in the control unit of an electronic device is preferable because it enables lower power consumption.

[0598] Examples of electronic devices include television sets, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0599] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0600] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher ...

Claims

The first insulating layer, A first layer and a second layer are provided spaced apart on the first insulating layer, A semiconductor layer on the first insulating layer, on the first layer and on the second layer, A second insulating layer on the semiconductor layer, The first conductive layer on the second insulating layer, A third insulating layer on the semiconductor layer and the first conductive layer, A second conductive layer, It has a third conductive layer, The semiconductor layer has a first region overlapping with the first layer, a second region overlapping with the second layer, and a third region located between the first region and the second region. The first conductive layer overlaps with the third region, The third insulating layer has a first opening that overlaps with the first region and a second opening that overlaps with the second region. The second conductive layer has a region located within the first opening, The second conductive layer is in contact with the upper surface of the first region. The third conductive layer has a region located within the second opening, The third conductive layer is in contact with the upper surface of the second region. The third insulating layer comprises silicon and nitrogen, The semiconductor device comprises a semiconductor layer containing indium and oxygen. 　 In claim 1, A semiconductor device wherein the first conductive layer has a region that overlaps with one or both of the first and second layers. 　 In claim 1, It has a fourth conductive layer, The first insulating layer is located on the fourth conductive layer, The fourth conductive layer overlaps with the first conductive layer, A semiconductor device wherein the fourth conductive layer has a region that overlaps with one or both of the first and second layers. 　 In claim 1, The first conductive layer has a layer made of the first material, The second conductive layer and the third conductive layer each have layers made of the second material. A semiconductor device wherein the second material is a different material from the first material. 　 In claim 4, The first material is copper or a copper-containing alloy. The second material is a metal having one or more selected from molybdenum, aluminum, titanium, tungsten, tantalum, and manganese, or a metal alloy having one or more selected from molybdenum, aluminum, titanium, tungsten, tantalum, and manganese, in a semiconductor device. 　 In claim 4, The first material is copper or a copper-containing alloy. The semiconductor device wherein the second material is a metal oxide or metal nitride. 　 In claim 1, In the third insulating layer, the thickness of the region overlapping with the first conductive layer is: A semiconductor device wherein the second insulating layer is thicker than the thickness of the region that overlaps with the first conductive layer. 　 The first insulating layer, A first layer and a second layer are provided spaced apart on the first insulating layer, A semiconductor layer on the first insulating layer, on the first layer and on the second layer, A second insulating layer on the semiconductor layer, The first conductive layer on the second insulating layer, A third insulating layer on the semiconductor layer and the first conductive layer, A second conductive layer, It has a third conductive layer, The semiconductor layer has a first region overlapping with the first layer, a second region overlapping with the second layer, and a third region located between the first region and the second region. The first conductive layer overlaps with the third region, The third insulating layer has a first opening that reaches the first layer and a second opening that reaches the second layer, The second conductive layer has a region located within the first opening, The second conductive layer is in contact with the upper surface of the first layer, The third conductive layer has a region located within the second opening, The third conductive layer is in contact with the upper surface of the second layer. The third insulating layer comprises silicon and nitrogen, The semiconductor device comprises a semiconductor layer containing indium and oxygen. 　 In claim 8, The first and second openings are, respectively, not overlapping with the semiconductor layer, in a semiconductor device.

Images