Method for topography detection of multilayer nested traps

Abstract

The present application relates to the technical field of semiconductor device manufacturing, in particular to a kind of topography detection method of multilayer nested well, comprising: one of the first doped well and third doped well is used as collector region, the other is used as emitter region, and the second doped well is used as base region, to obtain a pseudo-BJT structure;The thickness of the second doped well meets the size requirement of base region;Respectively, voltage is applied to the first doped well, the second doped well and the third doped well, so that the collector junction of pseudo-BJT structure is reverse biased, and the emitter junction is zero biased;Test the leakage current between the first doped well and the third doped well;Based on the leakage current tested, the topography state of the second doped well is obtained.In the present application, the multilayer nested well is used as the pseudo-BJT structure for leakage current detection, which can accurately detect the topography anomaly of the doped well according to the size of the leakage current, and the topography of the entire doped well can be determined whether there is an anomaly through one test, and the test is more convenient.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a method for detecting the morphology of multilayer nested wells. Background Technology

[0002] In CMOS integrated circuit devices, ion implantation (doping) is mainly used to modify the electrical properties of the device. The general process flow is to first define the doping region using photolithography, then perform ion implantation, and finally anneal. The post-lithography photoresist performance (PR), ion implantation parameters, and annealing parameters are all crucial. Among these, poor post-lithography CD (critical dimension), OVL shift (overlay shift), and PR Profile (photoresist morphology) can affect ion distribution, thus impacting device electrical performance. Therefore, it is necessary to inspect the well morphology; however, existing inspection methods cannot accurately detect all well morphology anomalies, resulting in defective products still being produced. Summary of the Invention

[0003] One of the objectives of this invention is to provide a convenient and highly accurate method for detecting the morphology of multi-layer nested traps, thereby improving the efficiency and accuracy of detection.

[0004] To achieve the above objectives, the present invention provides a method for morphology detection of a multilayer nested well, wherein the multilayer nested well includes a first doped well and a third doped well having a first doping type, and a second doped well having a second doping type and forming an isolation between the first doped well and the third doped well; the morphology detection method includes the following steps: By using one of the first and third doped wells as the collector region and the other as the emitter region, and using the second doped well as the base region, a pseudo-BJT (bipolar junction transistor) structure is obtained; the thickness of the second doped well meets the size requirements of the base region. Voltages are applied to the first doped well, the second doped well, and the third doped well, respectively, so that the collector junction of the pseudo-BJT structure is reverse biased and the emitter junction is zero biased. Test the leakage current between the first doped well and the third doped well; Based on the measured leakage current, the morphology of the second doped well was obtained.

[0005] Furthermore, in the step of applying voltages to the first doped well, the second doped well, and the third doped well respectively, so that the collector junction of the pseudo-BJT structure is reverse biased and the emitter junction is zero biased: the voltage difference between the collector region and the emitter region of the pseudo-BJT structure is 1.2 to 1.3 times the maximum value of the pre-designed device operating voltage.

[0006] Furthermore, the first doping type is N-doped, the second doping type is P-doped, the collector region of the pseudo-BJT structure is connected to a positive voltage, the base region is grounded, and the emitter region is connected to zero voltage or a negative voltage.

[0007] Furthermore, the first doping type is P-doped, the second doping type is N-doped, and the collector region of the pseudo-BJT structure is connected to a negative voltage, while the base region and emitter region are connected to a positive voltage.

[0008] Furthermore, the first doped well is provided with a plurality of first metal contacts, which are connected as a whole by a first wire; the second doped well is provided with a plurality of second metal contacts, which are connected as a whole by a second wire; and the third doped well is provided with a plurality of third metal contacts, which are connected as a whole by a third wire.

[0009] Furthermore, the first, second, and third conductors are covered with a passivation layer, and the passivation layer has a first contact hole for leading out the first conductor, a second contact hole for leading out the second conductor, and a third contact hole for leading out the third conductor. During testing, the voltage signal that needs to be connected to the first doped well is connected to the first contact hole through the first test line, the voltage signal that needs to be connected to the second doped well is connected to the second contact hole through the second test line, and the voltage signal that needs to be connected to the third doped well is connected to the third contact hole through the third test line. After the test, the first test line is disconnected from the first contact hole, the second test line is disconnected from the second contact hole, and the third test line is disconnected from the third contact hole.

[0010] Furthermore, the third doped well includes a plurality of interconnected shape units, each shape unit having at least one third metal contact, a plurality of second metal contacts being provided in the second doped well surrounding each shape unit, a plurality of first metal contacts being spaced apart along the length of the first doped well, and at least one first metal contact being provided in the first doped well corresponding to each shape unit.

[0011] Furthermore, the shape unit is cross-shaped, including a central part located in the middle of the shape unit, a first strip-shaped part and a second strip-shaped part located on both sides of the central part along a first direction, and a third strip-shaped part and a fourth strip-shaped part located on both sides of the central part along a second direction.

[0012] Furthermore, the width of the second doped well is 0.25 to 2.5 μm, the width of the first stripe, the second stripe, the third stripe and the fourth stripe are 6 to 10 times the width of the second doped well, and the width of the first stripe, the second stripe, the third stripe and the fourth stripe are 7 to 11 times the width of the second doped well.

[0013] Furthermore, the width of the second doped well is 1 / 20 to 1 / 10 of the narrowest part of the first doped well, which is 0.25 to 2.5 μm.

[0014] In summary, the morphology detection method for multi-layer nested traps in this application has the following unexpected technical effects: (i) The three-layer nested well is used as a pseudo BJT structure for leakage current detection. Since the magnitude of the leakage current is directly related to the thickness of the base region 520, the pseudo BJT structure is made to enter the punch-through state by forming a voltage difference of 1.2 to 1.3 times the maximum value of the pre-designed device operating voltage between the collector region 530 and the emitter region 510 of the pseudo BJT structure. The morphological abnormality of the doped well can be accurately detected according to the magnitude of the leakage current.

[0015] (ii) By treating the first doped well 100, the second doped well 200 and the third doped well 300 as a whole to form the collector region 530, the base region 520 and the emitter region 510 of the pseudo BJT structure, the morphology of the entire doped well can be determined by a single test. This greatly reduces the workload of testing compared to testing the sheet resistance of each shape unit individually, making the test more convenient. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the existing sheet resistance testing method.

[0017] Figure 2 A process flow diagram of a method for topography detection of multi-layer nested traps is shown.

[0018] Figure 3 Leakage current I C With voltage difference V CE A diagram illustrating the changes.

[0019] Figure 4 This is a schematic diagram of a three-layer nested trap structure.

[0020] Figure 5 This is a structural diagram of a cross-shaped unit.

[0021] Figure 6 A schematic diagram of a structure in which wires are connected to a three-layer nested trap and a voltage is applied.

[0022] Figure 7 for Figure 6 A cross-sectional view along the direction perpendicular to the x-axis.

[0023] Figure 8 The equivalent structure for testing the structure.

[0024] Figure 9 This is a schematic cross-sectional view of a second doped well with an unusual morphology.

[0025] Figure 10 This is a schematic diagram of the test connection for a traditional BJT device.

[0026] Figure 11 This is a cross-sectional schematic diagram of a five-layer nested trap.

[0027] The diagrams in the instruction manual are labeled as follows: First doped well 100; first metal contact 101; first wire 102; second doped well 200; second metal contact 201; second wire 202; third doped well 300; third metal contact 301; third wire 302; center portion 310; first strip portion 311; second strip portion 312; third strip portion 313; fourth strip portion 314; emitter region 510; base region 520; emitter junction 521; collector junction 522; collector region 530; first layer doped well 610, second layer doped well 620, third layer doped well 630, fourth layer doped well 640 and fifth layer doped well 650. Detailed Implementation

[0028] The following disclosure provides various embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where other components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations.

[0029] Furthermore, spatial relation terms such as "below," "under," "below," "above," and "above" may be used herein to readily describe the relationship between one element or component and another element (or component) or component (or component) as shown in the figure. In addition to the orientations shown in the figure, spatial relation terms will encompass various different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and will be interpreted accordingly through the spatial relation descriptors used herein.

[0030] Although the numerical ranges and parameter settings presented in this invention are approximations, the numerical settings in specific instances are reported as precisely as possible. Any numerical value, however, inherently contains certain inevitable errors arising from the standard deviation found in the respective test measurements. Similarly, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable average standard error that can be conceived by one of ordinary skill in the art. Except in instances of operation / work, or unless expressly stated otherwise, all numerical ranges, totals, values, and percentages, such as those for material quantities, durations, temperatures, operating conditions, amounts, and other similarities disclosed herein, should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise stated, the numerical parameter settings set forth in this invention and the appended claims are approximations that can be changed upon request. At a minimum, each numerical parameter should be interpreted based on the number of significant figures reported and the application of ordinary rounding techniques. A range herein may be expressed as from one endpoint to another or between two endpoints. All scopes disclosed herein include endpoints unless otherwise stated.

[0031] The following embodiments illustrate preferred embodiments of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

[0032] CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuits are the cornerstone of the modern digital world. Almost all chips used today (such as CPUs, memory, mobile phone processors, and various controllers) are based on CMOS technology. However, the continuous miniaturization of its process nodes (such as 7nm, 5nm, and 3nm) is not merely a proportional reduction in geometric dimensions, but rather an approach to a series of fundamental physical limits. This necessitates disruptive improvements at every stage of semiconductor process technology, introducing entirely new materials and complex integration schemes to maintain and enhance device performance.

[0033] In the fabrication of CMOS integrated circuits, the steps related to wells are the most critical and complex part of the entire process, playing a decisive role in the final performance of the device (such as withstand voltage, on-resistance, and threshold voltage). They define the respective regions of NMOS and PMOS transistors and determine whether all subsequent devices can function properly.

[0034] In the fabrication of doped wells, the first step is to define the doped well region using photolithography. The specific process generally follows: First, a layer of photoresist is spin-coated onto the wafer surface, and then exposed using a well region mask. The pattern on the mask determines which areas are transparent (allowing light to pass through) and which are opaque. The exposed (or unexposed, depending on the type of photoresist) areas are then dissolved, exposing the silicon substrate and opening the window for ion implantation. Ion implantation (i.e., bombardment with high-energy ions) then achieves chemical doping. The difference in ion blocking ability between the photoresist and silicon is the basis of selectivity. Implanted ions form an amorphous layer in silicon, following the LSS theoretical distribution (approximately Gaussian distribution vertically, with lateral scattering). The dosage determines the carrier concentration, and the energy determines the junction depth. Finally, annealing is performed, using a high-temperature process to achieve structural repair and electrical activation. Rapid thermal annealing can achieve high activation rates in an extremely short time (milliseconds) while suppressing impurity diffusion.

[0035] PR Performance refers to the overall performance of photoresist throughout the entire photolithography process. It encompasses key characteristics such as CD (Content Delivery), OVL (On-Version Variation), and PR Profile. In chip manufacturing, photoresist acts as a temporary, nanoscale template. Its performance directly determines the quality of the resulting pattern, which in turn directly determines the precision of subsequent ion implantation and etching, ultimately determining the electrical performance of each transistor. Therefore, monitoring these parameters is of paramount importance on semiconductor production lines.

[0036] Critical dimension (CD) refers to the width or spacing of the finest and most critical pattern lines on a chip; that is, the dimensions that have the greatest impact on device performance and are the most difficult to manufacture. It directly determines the device's process node and basic performance. Deviations in CD directly lead to changes in the effective channel length of transistors, resulting in a series of electrical failures such as threshold voltage drift, changes in drive current, and increased leakage current. Taking source-drain injection after gate sidewall formation as an example, the CD (i.e., injection window spacing) in this step is directly equal to the effective gate length. If the CD is too large, it will lead to a reduction in the injection region spacing. After annealing, the lateral diffusion of impurities will further shorten the effective channel length, exacerbating the short-channel effect, causing Vth roll-off, and a surge in leakage current. Therefore, controlling CD is the primary goal of photolithography.

[0037] OVL (Overlay Level) refers to the alignment error between the current lithography layer and the existing pattern of the previous layer (or several previous layers). Chip manufacturing typically requires dozens of lithography layers, and each layer's pattern must be precisely aligned with the layer below it, much like the different color plates in a color magazine must be aligned. In lightly doped drain implantation, precise alignment between the implanted region and the gate edge is required. If OVL shift occurs, it will cause asymmetry in the overlap between the implanted region and the gate. Excessive overlap on one side increases gate-drain leakage, while insufficient overlap on the other side increases external series resistance, and in severe cases, the device will fail completely. OVL error is one of the direct causes of short circuits or open circuits. For example, if the metal wires connecting the source and drain of a transistor are misaligned with the contact holes on the lower layer, it will cause a sharp increase in contact resistance or even complete loss of continuity, leading to direct chip failure.

[0038] Photoresist profile (PR profile) refers to the three-dimensional geometry of the photoresist pattern left on the silicon wafer after exposure and development. Key considerations include sidewall tilt angle, resist thickness, and top profile. Non-vertical sidewalls can create a shadowing effect during implantation. Especially in high-angle halo implantation, the tilt angle is used to create non-uniform doping below the channel to suppress short-channel effects. If the top of the PR profile collapses or the bottom has feet, it will completely change the ion incident angle, causing the halo implantation position to deviate from the design and lose its Vth control function. Uneven resist thickness or defects can lead to changes in local blocking ability, potentially causing unplanned penetration doping and introducing parasitic leakage paths. Additionally, the flatness of the top, and the presence of dome-like or collapsed edges, are also crucial parameters. The photoresist morphology serves as a template for subsequent processes (such as ion implantation and etching). A poor PR profile can cause shadowing effects during ion implantation, blurring the boundaries of doped regions; and during etching, the pattern may be incorrectly transferred to lower layers, leading to uncontrolled CD (cutoff and etching).

[0039] In existing technologies, after photolithography, critical dimensions and overlay accuracy are inspected on the manufacturing line using metrology equipment. However, due to capacity and cost limitations, this inspection is a sampling inspection rather than a full inspection. Therefore, some wafers or batches may not be measured. If these unsampled wafers happen to have CD (Cut-out) or OVL (Out-of-Vehicle) anomalies, the system will not be able to detect them.

[0040] Furthermore, as the analysis above shows, the final morphology of the well is affected not only by the implantation energy but also by the sidewall shape of the photoresist. If the sidewalls of the photoresist are not perpendicular (e.g., they are tilted or undercut), the implanted ions will be scattered, ultimately causing the junction surface (PN junction interface) of the well to tilt as well. Although scanning electron microscopes (SEMs) are available on the production line to visualize the patterns, it is difficult to accurately quantify the 3D information of the photoresist, such as sidewall angles and bottom shapes. This invisible anomaly directly affects the electrical performance of the device.

[0041] Although the final electrical test (CP test) is 100% accurate, the most commonly used existing electrical testing method is the sheet resistance method, which still has the problem of missing values ​​when detecting well morphology. Sheet resistance describes the resistance of a square thin film from one side to the opposite side, and its calculation formula is as follows: Rs=ρ / t (Equation 1) In equation (1), Rs represents sheet resistance; ρ represents the resistivity of the material (inversely proportional to the doping concentration); and t represents the thickness of the thin film (i.e., the junction depth of the trap).

[0042] Please see Figure 1 Measure the doped well in the active region AA ( Figure 1 When measuring the sheet resistance of an N-well (NW) junction, the test point can be led out of the doped well through the existing contact holes CT of the STI (Shallow Tunneling Inductor) and the metal contact M1 connected to the contact holes via shallow trenches near the top and sides of the doped well, thus allowing for sheet resistance measurement. Sheet resistance is a comprehensive reflection of doping concentration and junction depth. Although its morphology cannot be directly observed like under a microscope, it can reflect the electrical quality of the morphology through numerical changes.

[0043] For example, sheet resistance can reflect the average doping concentration. If the junction depth (well depth) t is fixed, a smaller sheet resistance indicates a smaller resistivity ρ, meaning a higher doping concentration and better conductivity. Sheet resistance can also reflect the junction depth (well depth). If the doping concentration ρ is fixed, a smaller sheet resistance indicates a deeper junction depth t. Furthermore, sheet resistance can be used for process monitoring. In ion implantation, the dosage is fixed. If the sheet resistance measured after annealing is too high, it usually means the junction depth is too shallow (t is too small), i.e., the annealing temperature or time is insufficient, and impurities have not diffused sufficiently. Or it may indicate a low activation rate (ρ is too large), i.e., annealing failed to effectively repair lattice damage, and impurity atoms did not occupy lattice sites to become effective charge carriers.

[0044] Therefore, in CMOS fabrication processes, the sheet resistance acts as a thermometer for the well morphology. By monitoring this value, engineers can quickly determine whether ions are bombarded too shallowly, whether annealing is sufficient, or whether impurities are activated, thereby indirectly controlling whether the longitudinal morphology (depth and concentration distribution) of the well meets the requirements.

[0045] However, if an anomaly occurs in the ion implantation region of the doped well (such as junction tilt or uneven concentration), existing sheet resistance testing may not be able to detect it effectively, thus determining that the doped well is normal. This can lead to the chip with hidden defects being packaged and shipped, and the problem may only be exposed when the customer uses it, potentially causing significant losses.

[0046] In summary, existing quality control systems have significant gaps, which could allow manufacturing defects to penetrate all inspection lines and reach the customer. Therefore, there is an urgent need to improve existing inspection methods. Since electrical testing involves 100% inspection, it is necessary to adopt a more accurate electrical testing method than testing sheet resistance.

[0047] Please see Figure 2 , Figure 2 A process flow diagram of a method for morphology detection of multi-layer nested wells is shown. In the illustrated embodiment, the multi-layer nested well is a three-layer nested well; however, the multi-layer nested well can also have more than three layers. The following description uses a three-layer nested well as an example. The multi-layer nested well includes a first doped well 100 and a third doped well 300 having a first doping type, and a second doped well 200 having a second doping type and forming an isolation between the first doped well 100 and the third doped well 300. The morphology detection method of the multi-layer nested well includes the following steps: S100. One of the first doped well 100 and the third doped well 300 is used as the collector region 530 and the other as the emitter region 510. The second doped well 200 is used as the base region 520 to obtain a pseudo BJT structure.

[0048] In specific implementation, the first doped well 100 can be selected as the collector region 530, and the third doped well 300 can be selected as the emitter region 510. Alternatively, the third doped well 300 can be selected as the collector region 530, and the first doped well 100 can be selected as the emitter region 510.

[0049] Both the first doped well 100 and the third doped well 300 are formed by ion implantation of a first doping type, while the second doped well 200 is formed by ion implantation of a second doping type. For example, when the first doped well 100 and the third doped well 300 are N-wells formed by implantation of pentavalent elements (e.g., phosphorus, arsenic, etc.), the second doped well 200 is a P-well formed by implantation of trivalent elements (e.g., boron); when the first doped well 100 and the third doped well 300 are P-wells formed by implantation of trivalent elements, the second doped well 200 is an N-well formed by implantation of pentavalent elements. Since the doping concentrations of the first doped well 100 and the third doped well 300 are generally different, the doped well with the higher doping concentration can be selected as the emitter region 510, and the doped well with the lower doping concentration can be selected as the collector region 530, in accordance with the common practice of transistor configuration. Of course, the doped well with a low doping concentration can be selected as the emitter region 510 and the doped well with a high doping concentration can be selected as the collector region 530 in the first doped well 100 and the third doped well 300, and the test can still be carried out normally.

[0050] The thickness of the second doped well 200 meets the size requirements of the base region 520, and the width of the second doped well 200 is generally 1 / 20 to 1 / 10 of the narrowest part of the first doped well 100. Under normal circumstances, the second doped well 200 is a doped well with uniform thickness throughout. The size of the base region 520 of the transistor is one of the core parameters that determines its performance, and it has a significant inverse relationship with both avalanche breakdown voltage and leakage current. First, the base region 520 is the transport channel for charge carriers (electrons or holes). The wider the base region 520, the longer the distance that charge carriers need to travel from the emitter to the collector, increasing the probability of collisions and scattering in the path, thus weakening the avalanche multiplication effect; therefore, a higher voltage is required to trigger breakdown. Second, the base region 520 is the recombination region for minority carriers. The wider the base region 520, the longer the minority carriers stay in the base region 520, and the higher the probability of recombination with majority carriers. This leads to a decrease in current gain, requiring a larger base current to maintain the same collector current, resulting in increased leakage current. Therefore, if the base region 520 is too thin, the device will break down even with a small voltage, easily damaging it during testing. Conversely, if the base region 520 is too thick, a very high voltage is required to achieve breakdown, making testing difficult at excessively high voltages.

[0051] S200: Voltages are applied to the first doped well 100, the second doped well 200, and the third doped well 300, respectively, causing the collector junction 522 (i.e., the PN junction between the collector region 530 and the base region 520) of the pseudo-BJT structure to be reverse biased and the emitter junction 521 (i.e., the PN junction between the emitter region 510 and the base region 520) to be zero biased. For example, when the first doped well 100 and the third doped well 300 are N-wells and the second doped well 200 is a P-well, the collector region 530 of the pseudo-BJT structure is connected to a high voltage (generally a positive voltage), the base region 520 is grounded, and the emitter region 510 is connected to a low voltage (generally zero voltage or a negative voltage), thereby causing the collector junction 522 of the pseudo-BJT structure to be reverse biased and the emitter junction 521 to be zero biased. When the first doped well 100 and the third doped well 300 are P-wells and the second doped well 200 is an N-well, the collector region 530 of the pseudo-BJT structure is connected to a low voltage (generally a negative voltage), and the base region 520 and the emitter region 510 are connected to a high voltage (generally a positive voltage), thereby making the collector junction 522 of the pseudo-BJT structure reverse biased and the emitter junction 521 zero biased.

[0052] When voltages are applied to the first doped well 100, the second doped well 200, and the third doped well 300, the voltage difference between the collector region 530 and the emitter region 510 of the pseudo-BJT structure (i.e., the voltage difference between the first doped well 100 and the third doped well 300) is generally 1.2 to 1.3 times the maximum value of the pre-designed operating voltage of the device (i.e., the CMOS integrated circuit device), preferably 1.25 times. When the CMOS integrated circuit device is a low-voltage device, the voltage difference between the first doped well 100 and the third doped well 300 is also low because its designed operating voltage is low. When the CMOS integrated circuit device is a medium-voltage device, the voltage difference between the first doped well 100 and the third doped well 300 is also significantly higher because its designed operating voltage is significantly higher than that of the low-voltage device. When the CMOS integrated circuit device is a high-voltage device, the voltage difference between the first doped well 100 and the third doped well 300 is also higher because its designed operating voltage is high. For example, when the CMOS integrated circuit device is a high-voltage device and its designed maximum operating voltage is 60V, the voltage difference between the first doped well 100 and the third doped well 300 can be 75V (i.e., 1.25 times 60V).

[0053] The first doped well 100, the second doped well 200, and the third doped well 300 are typically provided with multiple metal contacts, and the metal contacts within the same doped well are connected as a whole by wires. Specifically, the first doped well 100 is provided with multiple first metal contacts 101, which are connected as a whole (i.e., an equipotential body) by first wires 102. The second doped well 200 is provided with multiple second metal contacts 201, which are connected as a whole by second wires 202. The third doped well 300 is provided with multiple third metal contacts 301, which are connected as a whole by third wires 302. During testing, voltages can then be applied to the first doped well 100, the second doped well 200, and the third doped well 300 respectively through the first wires 102, the second wires 202, and the third wires 302.

[0054] S300: Test the leakage current between the first doped well 100 and the third doped well 300. The first conductor 102, the second conductor 202, and the third conductor 302 are generally covered with a passivation layer. The passivation layer has a first contact hole for leading out the first conductor 102, a second contact hole for leading out the second conductor 202, and a third contact hole for leading out the third conductor 203 (not shown in the figure). The passivation layer and contact holes are conventional structures of semiconductor devices and will not be described in detail here. During testing, the voltage signal to be connected to the first doped well 100 is connected to the first contact hole through the first test line, the voltage signal to be connected to the second doped well 200 is connected to the second contact hole through the second test line, and the voltage signal to be connected to the third doped well 300 is connected to the third contact hole through the third test line. This allows the application of corresponding voltages to the first doped well 100, the second doped well 200, and the third doped well 300, respectively, and the testing of the leakage current between the first doped well 100 and the third doped well 300. After the test is completed, disconnect the first test lead from the first contact hole, disconnect the second test lead from the second contact hole, and disconnect the third test lead from the third contact hole to restore the structure of the device.

[0055] Please see Figure 3 Voltages are applied to the first doped well 100 and the third doped well 300 respectively, causing the collector junction 522 of the pseudo-BJT structure to be reverse biased and the emitter junction 521 to be zero biased. The voltage difference between the first doped well 100 and the third doped well 300 (i.e., the voltage difference between the collector region 530 and the emitter region 510 of the pseudo-BJT structure) is V. CE The base region punch-through voltage V is less than that of the pseudo-BJT structure. PT At that time, as the voltage difference V between the first doped well 100 and the third doped well 300... CEAs the voltage increases, the reverse bias voltage of the collector junction 522 in the pseudo-BJT structure increases, causing the depletion layer of the collector junction 522 to extend towards the base region 520, thus compressing and narrowing the effective width of the base region 520. During this process, the leakage current between the first doped well 100 and the third doped well 300 (i.e., the leakage current between the collector region 530 and the emitter region 510 of the pseudo-BJT structure) I... C Very small (much smaller than about 10) -6 μA), and current I C The value remains almost unchanged.

[0056] S400. Based on the tested leakage current, the morphology of the second doped well is obtained. If the leakage current is greater than a preset current threshold, the morphology of the second doped well 200 is determined to be abnormal; otherwise, the morphology of the second doped well 200 is determined to be normal. The current threshold can be determined according to the actual parameters of the device; for example, the current threshold can be approximately 10. -6 μA. The principle of determining the morphology of the doped well based on the current threshold is as follows: When the voltage difference V between the first doped well 100 and the third doped well 300 CE Increase the base region punch-through voltage V to 520V in the pseudo-BJT structure PT At this time, the depletion layer of the collector junction 522 and the depletion layer of the emitter junction 521 of the pseudo-BJT structure meet at the base region 520, and the base region 520 is completely pinched off. At this point, the pseudo-BJT structure operates in the punch-through state, and a low-resistance direct conductive channel is formed between the collector region 530 and the emitter region 510 of the pseudo-BJT structure. The leakage current I between the first doped well 100 and the third doped well 300... C The current increases significantly, and the leakage current I between the first doped well 100 and the third doped well 300 is also increased. C It will change with the voltage difference V between the first doped well 100 and the third doped well 300 CE The increase is linear (potentially greater than approximately 10) with increasing [variable name]. -6 This is a non-destructive breakdown, but it can cause device failure. (μA).

[0057] When the voltage difference V between the first doped well 100 and the third doped well 300 CE Increase the avalanche breakdown voltage V of the pseudo-BJT structure B At this time, the electric field strength within the depletion layer of the collector junction 522 in the pseudo-BJT structure is extremely high. Charge carriers are accelerated and collide with the crystal lattice, generating new electron-hole pairs, leading to a chain reaction (avalanche multiplication). At this point, the pseudo-BJT structure operates in a breakdown state, with a leakage current I between the first doped well 100 and the third doped well 300. C Increased dramatically (far greater than about 10) -6 (μA), usually accompanied by heat generation, which may cause permanent damage to the device.

[0058] When a voltage difference V is applied between the first doped well 100 and the third doped well 300 CE When the voltage is 1.2 to 1.3 times the pre-designed maximum operating voltage of the device, the pseudo-BJT structure will inevitably operate in either the punch-through or breakdown state. If the pseudo-BJT structure operates in the early stages of the punch-through state, the leakage current I between the first doped well 100 and the third doped well 300 will be... C The increase will be small, still less than about 10. -6 μA indicates that the second doped well 200 meets the operating requirements and its morphology is normal. If the pseudo-BJT structure operates in the latter part of the punch-through state, the leakage current I between the first doped well 100 and the third doped well 300 will be... C The increase is significant, exceeding approximately 10. -6 At this point, although the device has not failed, it still indicates that the second doped well 200 has a defect and its morphology is abnormal. If the pseudo-BJT structure is operating in a breakdown state, the leakage current I between the first doped well 100 and the third doped well 300 will be... C It is already much greater than about 10 -6 The μA value further illustrates that the second doped well 200 has obvious defects and its morphology is abnormal.

[0059] For a three-layer nested well, its morphology mainly includes the morphology at the connection between the first doped well 100 and the second doped well 200, as well as the morphology at the connection between the second doped well 200 and the third doped well 300. Therefore, if the morphology of the second doped well 200 is determined to be normal by detection, it means that the morphology at the connection between the first doped well 100 and the second doped well 200, as well as the morphology at the connection between the second doped well 200 and the third doped well 300, are all normal.

[0060] The following is a specific example to illustrate this: Please see Figure 4 To avoid making the graphics too complex, Figure 4 Only one side of the first metal contact 101 is shown. In the three-layer nested wells, the outer first doped well 100 is rectangular, and the inner third doped well 300 includes multiple interconnected shape units. A ring of second doped wells 200, matching the outer contour of the third doped well 300, is formed around it. The first doped well 100 and the third doped well 300 are N-wells formed by pentavalent element implantation, and the second doped well 200 is a P-well formed by trivalent element implantation. Of course, in other embodiments, the first doped well 100 and the third doped well 300 can also be P-wells formed by trivalent element implantation, and the second doped well 200 can also be an N-well formed by pentavalent element implantation.

[0061] The width of the second doped well 200 is 1 / 20 to 1 / 10 of the narrowest dimension of the first doped well 100 (since the first doped well 100 is rectangular, its narrowest dimension is the width of the rectangle), preferably 1 / 20 of the width of the first doped well 100. In this embodiment, the width of the second doped well 200 includes its width Xi in the x-axis direction and its width Yi in the y-axis direction, where Xi = Yi.

[0062] Please see Figure 5 In this embodiment, the shape unit may be cross-shaped, including a central portion 310 located in the middle of the shape unit, and extending along the first direction (i.e., Figure 4 and 5 The first strip portion 311 and the second strip portion 312 located on both sides of the center portion 310 (in the y-axis direction) and along the second direction (i.e. Figure 4 and 5 The third stripe portion 313 and the fourth stripe portion 314 are located on both sides of the center portion 310 (in the x-axis direction). Correspondingly, the second doped well 200 forms a first "U"-shaped portion around the first stripe portion 311 of each shape unit, a second "U"-shaped portion around the second stripe portion 312 of each shape unit, a third "U"-shaped portion around the third stripe portion 313 of the leftmost shape unit, and a fourth "U"-shaped portion around the fourth stripe portion 314 of the rightmost shape unit. Of course, the shape unit can also adopt other shapes.

[0063] Each of the three shape units of the third doped well 300 is provided with at least one third metal contact 301, preferably one third metal contact 301 in each shape unit. A plurality of second metal contacts 201 are provided in the second doped well 200 surrounding each shape unit, preferably two second metal contacts 201 in the second doped well 200 surrounding each shape unit, the two second metal contacts 201 being respectively disposed on the first "U"-shaped portion and the second "U"-shaped portion corresponding to the shape unit. Along its length direction in the first doped well 100 (… Figure 4 and 5 Multiple first metal contacts 101 are spaced apart along the x-axis direction in the pattern formed by the second doped well 200. The first metal contacts 101 can be arranged along the length direction on both sides of the pattern formed by the second doped well 200.

[0064] The width d2 of the first stripe portion 311, the second stripe portion 312, the third stripe portion 313, and the fourth stripe portion 314 is 6 to 10 times the width d1 of the second doped well 200, preferably 8 times. The width d3 of the first stripe portion 311, the second stripe portion 312, the third stripe portion 313, and the fourth stripe portion 314 is 7 to 11 times the width d1 of the second doped well 200, preferably 9 times.

[0065] In this embodiment, the width d1 of the second doped well 200 is 0.25 μm to 2.5 μm, the width d2 of the first stripe portion 311, the second stripe portion 312, the third stripe portion 313 and the fourth stripe portion 314 is 2 μm to 20 μm, and the width d3 of the first stripe portion 311, the second stripe portion 312, the third stripe portion 313 and the fourth stripe portion 314 is 2.25 μm to 22.5 μm. Correspondingly, the width Xa of the first and second U-shaped portions is 2.5μm to 25μm, the length Ya of the first and second U-shaped portions is 2.25μm to 22.5μm, the width Yb of the third and fourth U-shaped portions is 2.5μm to 25μm, the length Xb of the third and fourth U-shaped portions is 2.25μm to 22.5μm, and the distance Xc between two adjacent first or second U-shaped portions is 4.5μm to 45μm.

[0066] Please see Figure 6 To avoid making the graphics too complex, Figure 6 Only one side of the first metal contact 101 is shown. Since the first doped well 100 and the third doped well 300 are N-wells, and the second doped well 200 is a P-well, the pseudo-BJT structure is an NPN transistor. In this case, each of the first metal contacts 101 in the first doped well 100 is connected via a first lead and serves as the emitter of the pseudo-BJT structure, connected to a low level L. Each of the second metal contacts 201 in the second doped well 200 is connected via a second lead and serves as the base of the pseudo-BJT structure, grounded to GND. Each of the third metal contacts 301 in the third doped well 300 is connected via a third lead and serves as the collector of the pseudo-BJT structure, connected to a high level H. Alternatively, each of the first metal contacts 101 in the first doped well 100 can be connected by a first lead and used as the collector of the pseudo-BJT structure connected to a high level H. Each of the third metal contacts 301 in the third doped well 300 can be connected by a third lead and used as the emitter of the pseudo-BJT structure connected to a low level L. Each of the second metal contacts 201 in the second doped well 200 can be connected by a second lead and used as the base of the pseudo-BJT structure grounded to GND, remaining unchanged.

[0067] Please see Figure 7 , Figure 7 for Figure 6 A cross-sectional view along the vertical x-axis shows a pseudo-BJT test structure formed by connecting the first doped well 100 to a low-level voltage (L), the second doped well 200 to ground (GND), and the third doped well 300 to a high-level voltage (H). Please refer to [link to relevant documentation]. Figure 8 This is the equivalent structure for the test structure. After setting the voltage difference between the high level H and the low level L to 1.2 to 1.3 times the pre-designed maximum operating voltage of the device, the leakage current between the first doped well 100 and the third doped well 300 is tested. If the morphology of the second doped well 200 is normal and its thickness is uniform throughout, the measured leakage current will be less than approximately 10. -6 μA, thus the morphology of the second doped well 200 can be determined to be normal based on the leakage current value obtained from the test.

[0068] Please see Figure 9 If the morphology of the second doped well 200 is abnormal, the thickness of the region of the second doped well 200 with the abnormality will be reduced, resulting in a reduction in the electrical thickness of the base region 520 of the pseudo-BJT structure. Based on previous analysis, the punch-through voltage VPT of the base region 520 when the pseudo-BJT structure enters the punch-through state and the avalanche breakdown voltage Va when it enters the breakdown state are... B Both will decrease, thus creating the same voltage difference V between the first doped well 100 and the third doped well 300. CE At that time, the leakage current of the abnormal pseudo-BJT structure in the second doped well 200 is even greater, exceeding approximately 10. -6 μA, thus enabling accurate detection of morphological anomalies in the second doped well 200.

[0069] according to Figure 6 The structure shown has at least one third metal contact 301 in each shape unit of the third doped well 300, at least two third metal contacts 301 in each shape unit of the second doped well 200, and at least one first metal contact 101 in each shape unit of the first doped well 100. This ensures the uniformity of the test, and the morphology of the second doped well 200 can be determined by a single test. Compared with testing the sheet resistance of each shape unit, this greatly reduces the workload of the test and makes the test more convenient.

[0070] Please see Figure 10 , Figure 10This is a schematic diagram of the test connections for traditional BJT devices. Traditional BJT devices include Deep N-Well (DNW), P-Well (PWELL), N-Well (NWELL), High Voltage P-type (HVP), High Voltage N-type (HVN), Contact (CT), Shallow Trench Isolation (STI), Emitter, Collector, and Base. (Comparison) Figure 9 and Figure 7 As can be seen, its structure is completely different from the multi-layer nested well in this application. Therefore, the pseudo-BJT structure formed by the multi-layer nested well structure in this application is not completely the same as the traditional BJT device in terms of structure. However, the pseudo-BJT structure in this application defines the emitter region 510, the base region 520 and the collector region 530 in the same way as the traditional BJT device, thus obtaining a similar electrical structure.

[0071] For nested wells with more than three layers, each doped well whose thickness meets the size requirement of the base region 520 can be designated as a second doped well 200. Each second doped well 200 and its adjacent doped wells on the inner and outer sides are grouped into a group of doped wells, with each group forming a three-layer nested well. Since the above testing method can only apply voltage to three adjacent nested wells at a time, when the number of nested wells is more than three, they can be grouped into groups of three for testing. A thinner doped well can be designated as a second doped well 200, its outer doped well as a first doped well 100, and its inner doped well as a third doped well 300, thus forming a group. It should be noted that the same doped well can be divided into two groups of doped wells.

[0072] Please see Figure 11As an example of a five-layer nested well, it includes a first-layer doped well 610, a second-layer doped well 620, a third-layer doped well 630, a fourth-layer doped well 640, and a fifth-layer doped well 650 nested from the outside to the inside. If the second-layer doped well 620 and the fourth-layer doped well 640 both meet the thickness requirements of the second doped well 200, the first-layer doped well 610, the second-layer doped well 620, and the third-layer doped well 630 can be divided into a first group of doped wells, and the third-layer doped well 630, the fourth-layer doped well 640, and the fifth-layer doped well 650 can be divided into a second group of doped wells. In the first group of doped wells, the first doped well 610 is the first doped well 100, the second doped well 620 is the second doped well 200, and the third doped well 630 is the third doped well 300; in the second group of doped wells, the third doped well 630 is the first doped well 100, the fourth doped well 640 is the second doped well 200, and the fifth doped well 650 is the third doped well 300.

[0073] Next, a three-layer nested well morphology detection method can be used to detect whether the morphology of the second doped well 200 in each group of doped wells is normal. Specifically, the first doped well 100 and the third doped well 300 in each group of doped wells are used as the collector region 530 and the emitter region 510, respectively, and the second doped well 200 in each group of doped wells is used as the base region 520, resulting in a pseudo-BJT structure. Then, voltages are applied to the first doped well 100, the second doped well 200, and the third doped well 300, respectively, so that the collector junction 522 of the pseudo-BJT structure is reverse biased and the emitter junction 521 is zero biased. Finally, the leakage current between the first doped well 100 and the third doped well 300 is tested; if the leakage current is greater than a preset current threshold, the morphology of the second doped well 200 in that group of doped wells is considered abnormal; otherwise, the morphology of the second doped well 200 is considered normal.

[0074] For a five-layer nested well, if the second doped well 200 (i.e., the second doped well 620 and the fourth doped well 640) in the first group of doped wells and the second group of doped wells are both normal, it means that the morphology at the connection between the first doped well 610 and the second doped well 620, the connection between the second doped well 620 and the third doped well 630, the connection between the third doped well 630 and the fourth doped well 640, and the connection between the fourth doped well 640 and the fifth doped well 650 are all normal, thus completing the morphology detection of the five-layer nested well.

[0075] In summary, the morphology detection method for multi-layer nested traps in this application has the following unexpected technical effects: (i) The three-layer nested well is used as a pseudo BJT structure for leakage current detection. Since the magnitude of the leakage current is directly related to the thickness of the base region 520, the pseudo BJT structure is made to enter the punch-through state by forming a voltage difference of 1.2 to 1.3 times the maximum value of the pre-designed device operating voltage between the collector region 530 and the emitter region 510 of the pseudo BJT structure. The morphological abnormality of the doped well can be accurately detected according to the magnitude of the leakage current.

[0076] (ii) By treating the first doped well 100, the second doped well 200 and the third doped well 300 as a whole to form the collector region 530, the base region 520 and the emitter region 510 of the pseudo BJT structure, the morphology of the entire doped well can be determined by a single test. This greatly reduces the workload of testing compared to testing the sheet resistance of each shape unit individually, making the test more convenient.

[0077] (iii) For nested traps with more than three layers, the measurement can be performed by dividing them into multiple three-layer nested traps using the grouping method, which has a wide range of applications.

Claims

1. A method for detecting the morphology of a multi-layer nested trap, characterized in that, The multilayer nested well includes a first doped well and a third doped well having a first doping type, and a second doped well having a second doping type formed between the first doped well and the third doped well for isolation; the morphology detection method includes the following steps: By using one of the first and third doped wells as the collector region and the other as the emitter region, and using the second doped well as the base region, a pseudo-BJT structure is obtained; the thickness of the second doped well meets the size requirements of the base region. Voltages are applied to the first doped well, the second doped well, and the third doped well, respectively, so that the collector junction of the pseudo-BJT structure is reverse biased and the emitter junction is zero biased. Test the leakage current between the first doped well and the third doped well; Based on the measured leakage current, the morphology of the second doped well was obtained.

2. The morphology detection method for multi-layer nested traps according to claim 1, characterized in that, In the step of applying voltages to the first doped well, the second doped well, and the third doped well respectively, so that the collector junction of the pseudo-BJT structure is reverse biased and the emitter junction is zero biased: the voltage difference between the collector region and the emitter region of the pseudo-BJT structure is 1.2 to 1.3 times the maximum value of the pre-designed device operating voltage.

3. The morphology detection method for multi-layer nested traps according to claim 1, characterized in that: The first doping type is N-doped, the second doping type is P-doped, and the collector region of the pseudo-BJT structure is connected to a positive voltage, the base region is grounded, and the emitter region is connected to zero voltage or a negative voltage.

4. The morphology detection method for multi-layer nested traps according to claim 1, characterized in that: The first doping type is P-doped, the second doping type is N-doped, and the collector region of the pseudo-BJT structure is connected to a negative voltage, while the base region and emitter region are connected to a positive voltage.

5. The morphology detection method for multi-layer nested traps according to claim 1, characterized in that: The first doped well is provided with a plurality of first metal contacts, which are connected into a whole by a first wire; the second doped well is provided with a plurality of second metal contacts, which are connected into a whole by a second wire; the third doped well is provided with a plurality of third metal contacts, which are connected into a whole by a third wire.

6. The morphology detection method for multi-layer nested traps according to claim 5, characterized in that: The first, second, and third conductors are covered with a passivation layer. The passivation layer has a first contact hole for leading out the first conductor, a second contact hole for leading out the second conductor, and a third contact hole for leading out the third conductor. During testing, the voltage signal that needs to be connected to the first doped well is connected to the first contact hole through the first test line, the voltage signal that needs to be connected to the second doped well is connected to the second contact hole through the second test line, and the voltage signal that needs to be connected to the third doped well is connected to the third contact hole through the third test line. After the test, the first test line is disconnected from the first contact hole, the second test line is disconnected from the second contact hole, and the third test line is disconnected from the third contact hole.

7. The morphology detection method for multi-layer nested traps according to claim 5, characterized in that: The third doped well includes a plurality of interconnected shape units, each shape unit having at least one third metal contact, a plurality of second metal contacts being provided in the second doped well surrounding each shape unit, a plurality of first metal contacts being spaced apart along the length of the first doped well, and at least one first metal contact being provided in the first doped well corresponding to each shape unit.

8. The morphology detection method for multi-layer nested traps according to claim 7, characterized in that: The shape unit is cross-shaped, including a central part located in the middle of the shape unit, a first strip-shaped part and a second strip-shaped part located on both sides of the central part along a first direction, and a third strip-shaped part and a fourth strip-shaped part located on both sides of the central part along a second direction.

9. The morphology detection method for multi-layer nested traps according to claim 8, characterized in that: The width of the second doped well is 0.25 to 2.5 μm, and the widths of the first, second, third, and fourth stripes are 6 to 10 times the width of the second doped well, and the widths of the first, second, third, and fourth stripes are 7 to 11 times the width of the second doped well.

10. The morphology detection method for multi-layer nested traps according to any one of claims 1 to 9, characterized in that: The width of the second doped well is 1 / 20 to 1 / 10 of the narrowest part of the first doped well, and is 0.25 to 2.5 μm.

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