Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate including a chip region and an edge region; an integrated circuit element on the chip region; an interlayer insulating layer covering the integrated circuit element; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first conductive pattern and a second conductive pattern on the interconnection structure, the first conductive pattern and the second conductive pattern being electrically connected to the interconnection structure; a first passivation layer covering the first conductive pattern and the second conductive pattern and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and between the first conductive pattern and the second conductive pattern, the second passivation layer has a bottom surface positioned at a vertical level lower than a vertical level of a top surface of the first conductive pattern.

Description

[0001] Korean Patent Application Nos. 10-2020-0037779, filed on March 27, 2020, and 10-2020-0156359, filed on November 20, 2020, both entitled "Semiconductor Device" are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0002] Embodiments relate to a semiconductor device. BACKGROUND

[0003] A semiconductor package can include a semiconductor chip configured to store a large amount of data and process a large amount of stored data in a short time. The semiconductor chip can include an internal integrated circuit for storing or processing data and a chip pad for exchanging data with an external device. SUMMARY

[0004] Embodiments can be implemented by providing a semiconductor device including a substrate including a chip region and an edge region around the chip region, an integrated circuit element on the chip region, an interlayer insulating layer covering the integrated circuit element, an interconnection structure having an internal interconnection line on the interlayer insulating layer, the interconnection structure having a side surface on the edge region, a first conductive pattern and a second conductive pattern on the interconnection structure, the first conductive pattern and the second conductive pattern being electrically connected to the internal interconnection line, a first passivation layer covering the first conductive pattern and the second conductive pattern and the side surface of the interconnection structure, and a second passivation layer on the first passivation layer, wherein the second passivation layer includes a second insulating material, the first passivation layer includes a first insulating material, and the second insulating material of the second passivation layer is different from the first insulating material of the first passivation layer, a bottom surface of the second passivation layer is positioned at a vertical level lower than a vertical level of a top surface of the first conductive pattern in a region between the first conductive pattern and the second conductive pattern.

[0005] Embodiments can be implemented by providing a semiconductor device including a substrate, an integrated circuit element on the substrate, an interlayer insulating layer covering the integrated circuit element, an interconnection structure on the interlayer insulating layer, the interconnection structure including an internal interconnection line connected to the integrated circuit element, a conductive pattern on the interconnection structure, the conductive pattern being electrically connected to the internal interconnection line, a first passivation layer covering a side surface of the interconnection structure and the conductive pattern, and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material, the first passivation layer includes the insulating material, and the insulating material of the second passivation layer is different from the insulating material of the first passivation layer, a thickness of the first passivation layer is smaller than a thickness of the second passivation layer in a region between the conductive patterns, and the thickness of the first passivation layer is greater than the thickness of the second passivation layer in a region on a top surface of each of the conductive patterns.

[0006] An embodiment can be implemented by providing a semiconductor device including a substrate including a chip region and an edge region around the chip region; an integrated circuit element on the chip region of the substrate; an interlayer insulating layer covering the integrated circuit element; an interconnection structure on the interlayer insulating layer, the interconnection structure having a side surface on the edge region of the substrate; a conductive pattern on a top surface of the interconnection structure, the conductive pattern electrically connected to an internal interconnection line in the interconnection structure; a protective layer covering the conductive pattern; and a passivation layer on the protective layer, the passivation layer having an opening partially exposing a top surface of the conductive pattern, wherein the passivation layer includes a first passivation layer on the protective layer and covering at least a portion of the side surface of the interconnection structure, a second passivation layer on the first passivation layer and including an insulating material different from that of the first passivation layer, and a third passivation layer on the second passivation layer and including an insulating material different from that of the first passivation layer and that of the second passivation layer, wherein a thickness of the conductive pattern is greater than a thickness of each of the first passivation layer to the third passivation layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a substrate on which a semiconductor device according to an embodiment is integrated.

[0009] Figure 2 is an enlarged plan view of a portion AA of Figure 1

[0010] Figures 3 to 6 is a sectional view taken along line I-I' of a stage in a method of manufacturing a semiconductor device according to an embodiment. Figure 2

[0011] Figures 7A to 7C is an enlarged sectional view of a portion BB of Figure 6

[0012] Figures 8 to 11 is a sectional view taken along line I-I' of a stage in a method of manufacturing a semiconductor device according to an embodiment. Figure 2

[0013] Figure 12A and Figure 12B is an enlarged sectional view of a portion CC of Figure 11

[0014] Figure 13A and Figure 13B ​​​​​is a cross-sectional view of a portion CC of the semiconductor device according to an embodiment. Figure 11 is a cross-sectional view of a portion CC of the semiconductor device according to an embodiment.

[0015] Figure 14 and Figure 15 is a cross-sectional view of the semiconductor device according to an embodiment taken along line I-I' of Figure 2

[0016] Figure 16 is a plan view of a semiconductor chip separated from the semiconductor device according to an embodiment.

[0017] Figure 17 is a cross-sectional view of a semiconductor package including the semiconductor chip according to an embodiment.

[0018] Figure 18 is a cross-sectional view of a portion CC of the semiconductor device according to an embodiment. Figure 2

[0019] Figure 19 is a cross-sectional view of a semiconductor package including the semiconductor chip according to an embodiment. DETAILED DESCRIPTION

[0020] Figure 1 is a semiconductor substrate on which the semiconductor device is integrated according to an embodiment. Figure 2 is an enlarged plan view of a portion AA of Figure 1

[0021] Referring to Figure 1 and Figure 2 , the substrate 100 can include chip regions 10 on which semiconductor integrated circuits are formed, and scribe line regions 20 between the chip regions 10.

[0022] The substrate 100 can include a semiconductor material (e.g., silicon), an insulating material (e.g., glass), or a semiconductor layer covered with an insulating material. In one embodiment, the substrate 100 can be a silicon wafer.

[0023] The chip regions 10 can be two-dimensionally arranged along a first direction D1 and a second direction D2 perpendicular to each other. Each of the chip regions 10 can be surrounded or encircled by the scribe line regions 20.

[0024] The scribe line regions 20 can be located between the chip regions 10 and can extend in the first direction D1 and the second direction D2. The scribe line regions 20 can include cutting regions 22 to be cut by a sawing machine or a dicing machine, and edge regions 24 located between the cutting regions 22 and the chip regions 10. The edge regions 24 can surround the chip regions 10, respectively.

[0025] ​​​In one embodiment, a semiconductor memory device (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), a NAND flash, or a resistive random access memory (RRAM)) can be located on the chip region 10 of the substrate 100. In one embodiment, a micro electro mechanical system (MEMS) device, an optoelectronic device, or a processor (e.g., a CPU or a DSP) can be located on the chip region 10 of the substrate 100. In one embodiment, a standard cell including a semiconductor element such as an OR gate or an AND gate can be located on the chip region 10 of the substrate 100.

[0026] The conductive pattern 150 can be located in or on the chip region 10 of the substrate 100. The conductive pattern can be a chip pad for inputting or outputting data or signals to or from an integrated circuit. The conductive pattern 150 can also be referred to as a chip pad 150. Some of the chip pads 150 can be located on the boundary of each chip region 10. Other chip pads 150 among the chip pads 150 can be located on the central portion of the chip region 10.

[0027] Figures 3 to 6 is a cross-sectional view taken along the line I-I' of Figure 2 according to an embodiment of a method of manufacturing a semiconductor device. Figures 7A to 7C is an enlarged cross-sectional view corresponding to a portion BB of Figure 6 according to an embodiment of a method of manufacturing a semiconductor device. Figures 8 to 11 is a cross-sectional view taken along the line I-I' of Figure 2 according to an embodiment of a method of manufacturing a semiconductor device. Figure 12A and Figure 12B are enlarged cross-sectional views showing a portion CC of Figure 11 according to an embodiment of a method of manufacturing a semiconductor device.

[0028] Referring to Figure 2 and Figure 3 , the substrate 100 can include chip regions 10 and a scribe region 20. The scribe region 20 can include a cut region 22 at a central portion thereof and an edge region 24 located between the cut region 22 and the chip region 10. The scribe region 20 can extend in a first direction D1 and a second direction D2.

[0029] The integrated circuit element 101 can be located on the chip region 10 of the substrate 100. The integrated circuit element 101 can include a memory cell array in which a switching element and a data storage element are disposed, and a logic region in which a MOS FET, a capacitor, and a resistor are disposed. The integrated circuit element 101 can be covered with the interlayer insulating layer 103, for example, the interlayer insulating layer 103 can completely cover the top surface of the substrate 100. The interlayer insulating layer 103 can include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The lower interconnection line 105a can be located in the interlayer insulating layer 103. The lower interconnection line 105a can be located on the chip region 10 and can be connected to the integrated circuit element 101. The dummy lower interconnection line 105b can be located in the interlayer insulating layer 103. The dummy lower interconnection line 105b can be located in the edge region 24 and can be electrically disconnected or isolated from the integrated circuit element 101. The lower interconnection line 105a and the dummy lower interconnection line 105b can be formed of or include a metal material (e.g., W, Ti, Ta, TiN, WN, or TaN). As used herein, the term "or" is not an exclusive term, for example, "A or B" will include A, B, or both A and B.

[0030] The interconnection structure 110 can be formed on the interlayer insulating layer 103. The interconnection structure 110 can include a lower insulating layer 112 and an internal interconnection line 114 located in the lower insulating layer 112.

[0031] A lower insulating layer 112 can be formed on the interlayer insulating layer 103 to completely cover the top surface of the substrate 100. The lower insulating layer 112 can include a plurality of stacked insulating layers. In one embodiment, the lower insulating layer 112 can be formed of or can include a low-k dielectric material having a lower dielectric constant than silicon oxide. The lower insulating layer 112 can have a dielectric constant of about 1.0 to 3.0, and can include an organic material, an inorganic material, or an organic-inorganic hybrid material. In one embodiment, the lower insulating layer 112 can be porous or non-porous. The lower insulating layer 112 can be formed of or can include an impurity-doped silicon oxide material or a low-k organic polymer. The impurity-doped oxide material can include, for example, fluorine-doped oxide (FSG), carbon-doped oxide, silicon oxide, hydrogen silsesquioxane (HSQ, SiO:H), methyl silsesquioxane (MSQ, SiO:CH3), or a-SiOC (SiOC:H). The low-k organic polymer can include, for example, polyallyl ether resin, cyclic fluorine resin, siloxane copolymer, fluorinated polyallyl ether resin, polyperfluorostyrene, polytetrafluorostyrene resin, fluorinated polyimide resin, polyfluorinated naphthalene, metal silicide resin, etc. In one embodiment, the lower insulating layer 112 can include at least two insulating layers vertically stacked and a barrier layer between the insulating layers. In one embodiment, the barrier layer can be formed of or can include an insulating material such as SiN, SiON, SiC, SiCN, SiOCH, SiOC, or SiOF.

[0032] In one embodiment, an uppermost layer (e.g., a layer farthest from the substrate 100) of the insulating layers constituting the lower insulating layer 112 can be formed of or can include a material different from that of the other insulating layers. The uppermost insulating layer of the lower insulating layer 112 can be formed of or can include, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0033] Internal interconnect lines 114 can be formed in the lower insulating layer 112 on the chip region 10. The internal interconnect lines 114 on the chip region 10 can be electrically connected to the integrated circuit elements 101. The internal interconnect lines 114 can include metal lines extending parallel to the top surface of the substrate 100 and metal vias penetrating the lower insulating layer 112 vertically and connecting metal lines at different levels to each other. The metal lines and the metal vias can be formed of or include a first metal material, e.g., W, Al, Ti, Ta, Co, or Cu. In one embodiment, the metal lines and the metal vias can be formed of or include copper (Cu). The metal lines and the metal vias can further include a barrier metal layer which can be formed of a metal nitride, e.g., TiN, WN, TaN, or TaSiN.

[0034] The in-die pads 124 can be located on the top surface of the lower insulating layer 112, e.g., the surface facing away from the substrate 100. The in-die pads 124 can be located on the chip region 10 and can be electrically connected to the internal interconnect lines 114 of the interconnect structure 110. The in-die pads 124 can be electrically connected to the integrated circuit elements 101 through the internal interconnect lines 114. The in-die pads 124 can be data pads for transmitting or receiving data signals, command / address pads for transmitting or receiving command / address signals, power pads for applying a ground voltage or a power supply voltage, or test pads for testing the integrated circuit elements 101. The in-die pads 124 can be formed of or include a second metal material different from the first metal material. The in-die pads 124 can be formed of or include, e.g., W, Al, Ti, Ta, Co, or Cu. In one embodiment, the in-die pads 124 can be formed of or include aluminum (Al). The in-die pads 124 can further include a barrier metal layer which can be formed of a metal nitride, e.g., TiN, WN, TaN, or TaSiN.

[0035] The dam structure 116 can be formed on the edge region 24 of the substrate 100. The dam structure 116 can enclose each chip region 10 when viewed in a plan view. The dam structure 116 can have a ring shape or a closed loop shape when viewed in a plan view. At least a portion of the dam structure 116 can be formed using or during the process of forming the internal interconnect lines 114 on the chip region 10. The dam structure 116 can include dummy metal lines extending in the lower insulating layer 112 and parallel to the top surface of the substrate 100 and dummy metal vias penetrating a portion of the lower insulating layer 112 vertically and connecting dummy metal lines at different levels.

[0036] Dummy inner chip pads 128 can be located on the top surface of the lower insulating layer 112. The dummy inner chip pads 128 can be located on the edge region 24 and can be connected to the dam structure 116. The dummy inner chip pads 128 can surround each chip region 10 when viewed in a plan view.

[0037] An upper insulating layer 130 can be formed to completely cover the top surface of the substrate 100. The upper insulating layer 130 can be formed on the uppermost layer of the lower insulating layer 112 and can cover the inner chip pads 124 and the dummy inner chip pads 128. In one embodiment, the upper insulating layer 130 can be formed of or include an insulating material having a mechanical durability higher than that of the lower insulating layer 112. In one embodiment, the upper insulating layer 130 can be formed of or include an insulating material having a dielectric constant higher than that of the lower insulating layer 112. The upper insulating layer 130 can include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The upper insulating layer 130 can be formed of or include, for example, silicon nitride (SiN), silicon oxynitride (SiON), SiCN, high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), O3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG) material, Tonen silazane (TOSZ), or a combination thereof.

[0038] In one embodiment, the upper insulating layer 130 can include a plurality of insulating layers. In one embodiment, the upper insulating layer 130 can include a first upper insulating layer 132, a second upper insulating layer 134, and a third upper insulating layer 136 that can be sequentially stacked on the lower insulating layer 112. The second upper insulating layer 134 can be formed of an insulating material, can have an etch selectivity with respect to the first upper insulating layer 132 and the third upper insulating layer 136, and can be thinner than the first upper insulating layer 132 and the third upper insulating layer 136. The first upper insulating layer 132 and the third upper insulating layer 136 can be formed of different insulating materials from each other. In one embodiment, the first upper insulating layer 132 can be a high-density plasma (HDP) oxide layer, the second upper insulating layer 134 can be a silicon nitride layer, and the third upper insulating layer 136 can be a tetraethyl orthosilicate (TEOS) layer.

[0039] Referring to Figure 2 and Figure 4A conductive pattern 150 can be formed on the interconnect structure 110. The formation of the conductive pattern 150 can include forming a metal layer to cover the interconnect structure 110 and patterning the metal layer to form the conductive pattern 150, the conductive pattern 150 being electrically connected to the internal interconnect lines 114 in the interconnect structure 110.

[0040] The conductive patterns 150 can be spaced apart from each other in a direction parallel to the top surface of the substrate 100 (e.g., laterally). In one embodiment, some of the conductive patterns 150 can be pads for electrically connecting the integrated circuit elements 101 to an outside (e.g., of a device). Other conductive patterns 150 of the conductive patterns 150 can be interconnect lines to electrically connect the pads to each other or to the internal interconnect lines 114. The conductive patterns 150 can be formed of or include a first metal material (e.g., W, Al, Ti, Ta, Co, or Cu). The conductive patterns 150 can be formed of or include copper (Cu), for example.

[0041] An upper via 126 can be formed to connect the conductive pattern 150 to the in-die pad 124. The upper via 126 can be formed before the conductive pattern 150 is formed. The upper via 126 can be formed to penetrate the first upper insulating layer 132, the second upper insulating layer 134, and the third upper insulating layer 136. A width of the upper via 126 can decrease as a distance from the in-die pad 124 decreases (e.g., the upper via 126 can have a shape that tapers downward). The upper via 126 can be formed of or include the same material as the material of the conductive pattern 150.

[0042] Referring to Figure 2 and Figure 5 A protective layer 162 can be formed on the interconnect structure 110 and the conductive pattern 150, and a trench 164 can be formed on the dicing region 22 of the substrate 100.

[0043] The protective layer 162 can cover a top surface of the interconnect structure 110, and can cover side surfaces and a top surface of the conductive pattern 150. A thickness of the protective layer 162 can be smaller than a thickness of the conductive pattern 150. The thickness of the protective layer 162 can be in a range of 0.1 times to 0.3 times the thickness of the conductive pattern 150. The protective layer 162 can be formed of or include silicon oxide. In one embodiment, the protective layer 162 can be a PE-TEOS layer.

[0044] The trench 164 can be formed by removing a portion of the lower insulating layer 112, a portion of the upper insulating layer 130, and a portion of the protective layer 162. In one embodiment, the formation of the trench 164 can include forming an etching mask on the protective layer 162 to expose the dicing region 22 and performing an etching process using the etching mask. The trench 164 can be formed to expose at least a portion of the top surface of the interlayer insulating layer 103. As a result of forming the trench 164, the lower insulating layer 112 and the upper insulating layer 130 can have side surfaces 100s and 130s formed on the edge region 24. The side surface 100s of the lower insulating layer 112 and the side surface 130s of the upper insulating layer 130 can be inclined at an angle with respect to the top surface of the base 100 (e.g., the trench 164 can have a shape tapered downward). The trench 164 can be formed along the dicing region 22 and can extend in the first direction D1 and the second direction D2 to enclose the chip region 10. The width of the trench 164 can decrease as the distance from the top surface of the base 100 decreases.

[0045] Referring to Figure 2 and Figure 6 The first passivation layer 172 can be formed to cover the conductive pattern 150. The protective layer 162 can be located between the first passivation layer 172 and the conductive pattern 150. The first passivation layer 172 can cover the top surface of the protective layer 162 on the chip region 10 and can have a non-constant (e.g., variable) thickness. The thickness of the protective layer 162 can be smaller than the thickness of the first passivation layer 172. In one embodiment, a portion of the first passivation layer 172 on the side surface of the conductive pattern 150 can be thinner than the rest of the first passivation layer 172. In one embodiment, on the chip region 10, the first passivation layer 172 can have a top surface (e.g., a surface facing away from the base 100), and a portion of the top surface can be positioned at a vertical level lower than the vertical level of the top surface of each conductive pattern 150 (e.g., positioned at a vertical level closer to the base 100 than the top surface of each conductive pattern 150). On the dicing region 22, the first passivation layer 172 can cover a portion of the top surface of the interlayer insulating layer 103 (e.g., a portion of the interlayer insulating layer 103 exposed at the bottom of the trench 164) and the inner side surface of the trench 164.

[0046] In one embodiment, referring to Figure 7AA first deposition process can be performed to form a preliminary passivation layer 171 on the protective layer 162. The first deposition process can be performed using a high-density plasma chemical vapor deposition (HDP-CVD) method. The preliminary passivation layer 171 can be formed to cover the protective layer 162 on the first conductive pattern 150a and the second conductive pattern 150b. The preliminary passivation layer 171 can have inner side surfaces 171s protruding between the first conductive pattern 150a and the second conductive pattern 150b and toward each other. The distance between the inner side surfaces 171s of the preliminary passivation layer 171 can increase as the distance from the top surface of the upper insulating layer 130 decreases (e.g., the gap between the inner side surfaces 171s of the preliminary passivation layer 171 can have a substantially trapezoidal shape). In one embodiment, the inner side surfaces 171s of the preliminary passivation layer 171 can be connected to each other, and in this case, a void can be formed in the preliminary passivation layer 171.

[0047] Next, referring to FIG. 1C, Figure 7B An etching process can be performed on the preliminary passivation layer 171 to remove a portion of the preliminary passivation layer 171. During the etching process, the inner side surfaces 171s protruding toward each other can be partially removed. During the etching process, the maximum distance between the inner side surfaces 171s can increase. The etching process can be performed in such a way that the distance between the inner side surfaces 171s of the preliminary passivation layer 171 can decrease as the distance from the upper insulating layer 130 decreases. The preliminary passivation layer 171 on the side surfaces of the first conductive pattern 150a and the second conductive pattern 150b can be thinner than the preliminary passivation layer 171 on the top surfaces of the first conductive pattern 150a and the second conductive pattern 150b and between the first conductive pattern 150a and the second conductive pattern 150b (e.g., the portion of the preliminary passivation layer 171 on the protective layer 162 between the first conductive pattern 150a and the second conductive pattern 150b and directly on the upper insulating layer 130).

[0048] Next, referring to FIG. 1D, Figure 7C A second deposition process can be performed to increase the thickness of the preliminary passivation layer 171, thereby forming a first passivation layer 172. The second deposition process can be performed using a high-density plasma chemical vapor deposition (HDP-CVD) method.

[0049] Referring to FIG. 1E, Figure 2 and Figure 8A second passivation layer 182 can be formed on the first passivation layer 172. The second passivation layer 182 can be formed to sufficiently or completely cover the top surface of the first passivation layer 172. On the chip region 10, the first passivation layer 172 can fill at least a portion of the space between two adjacent conductive patterns 150. On the scribe line region 20, the second passivation layer 182 can fill a portion of the trench 164. The second passivation layer 182 can be an oxide layer, and can be formed by performing a deposition process using tetraethyl orthosilicate (TEOS) as a source material.

[0050] Referring to Figure 2 and Figure 9 A third passivation layer 192 can be formed to cover the second passivation layer 182. Before forming the third passivation layer 192, the top surface of the second passivation layer 182 can be planarized. The planarization of the top surface of the second passivation layer 182 can be performed using a chemical mechanical polishing (CMP) process. Next, the third passivation layer 192 can be formed by performing a deposition process on the planarized top surface of the second passivation layer 182. The third passivation layer 192 can fill a portion of the trench 164 on the scribe line region 20. The third passivation layer 192 can include a silicon nitride layer or a silicon oxynitride layer.

[0051] Referring to Figure 2 and Figure 10 An opening OP can be formed to expose the top surface 150t of at least one of the conductive patterns 150. The opening OP can have a width that increases as a distance from the conductive pattern 150 increases. The formation of the opening OP can include forming a mask pattern on the third passivation layer 192, and etching the first passivation layer to the third passivation layers 172, 182, and 192 anisotropically using the mask pattern as an etching mask. The portion of the conductive pattern 150 exposed by the opening OP can be a pad portion for connecting the integrated circuit element 101 to an external device. The opening OP can have a rectangular shape, a circular shape, or a polygonal shape. In the case where the opening OP has a rectangular shape, the pad portion of the semiconductor device can have a rectangular shape as shown in FIG. 1B. Figure 2

[0052] Referring to Figure 2 and Figure 11 ​A sawing process can be performed on the cut regions 22 of the scribe regions 20 to separate the chip regions 10 from each other. At least a portion of the cut regions 22 can be removed by the sawing process. As a result of the sawing process, the substrate 100 can be divided into a plurality of semiconductor chips separated from each other. Each semiconductor chip can have a chip region 10 and an edge region 24 around the chip region 10. In one embodiment, a portion of the cut regions 22 can be left or remain near the edge regions 24. The lower insulating layer 112 and the upper insulating layer 130 located on the scribe regions 20 can be partially removed before the sawing process, and can help prevent the substrate 100 from being incompletely cut or help prevent the thin film from being torn or cracked toward the chip region during the sawing process of the substrate 100.

[0053] In one embodiment, referring to Figure 11 and Figure 12A , the conductive pattern 150 can include a first conductive pattern 150a and a second conductive pattern 150b spaced apart from each other in a direction parallel to the top surface of the substrate 100. The first conductive pattern 150a can be a pad portion of which a top surface is partially exposed by the opening OP, and the second conductive pattern 150b can be an interconnection line positioned at the same vertical level as the pad portion. The protective layer 162 can cover the conductive patterns 150a and 150b, and the protective layer 162 can have a constant thickness. Unlike the thickness of the protective layer 162, the thickness t1 of the first passivation layer 172 and the thickness t2 of the second passivation layer 182 (e.g., in a vertical direction) can not be constant. In one embodiment, at a position on the top surface of the first conductive pattern 150a and the top surface of the second conductive pattern 150b, the thickness t1 of the first passivation layer 172 can be greater than the thickness t2 of the second passivation layer 182. In one embodiment, at a position between the first conductive pattern 150a and the second conductive pattern 150b, the thickness t1 of the first passivation layer 172 can be less than the thickness t2 of the second passivation layer 182. The first conductive pattern 150a and the second conductive pattern 150b can have a thickness t3 (e.g., in a vertical direction) that is greater than the thickness t1 of the first passivation layer 172 and greater than the thickness t2 of the second passivation layer 182 (e.g., greater than the thickness t2 of the second passivation layer 182 at a position on the top surface of the second conductive pattern 150b), and on the top surface of the first conductive pattern 150a, the thickness t3 of the first conductive pattern 150a can be 1.1 times to 1.9 times the thickness t1 of the first passivation layer 172. The thickness of the third passivation layer 192 can be less than the thickness t1 of the first passivation layer 172 and less than the thickness t2 of the second passivation layer 182.

[0054] The second passivation layer 182 can have a bottom surface 182b. A portion of the bottom surface 182b of the second passivation layer 182 located between the first conductive pattern 150a and the second conductive pattern 150b can be at a vertical level lower than a vertical level of the top surface of the first conductive pattern 150a and the top surface of the second conductive pattern 150b (e.g., closer to the substrate 100 than the top surface of the first conductive pattern 150a and the top surface of the second conductive pattern 150b).

[0055] Referring to Figure 11 and Figure 12B , the first conductive pattern 150a and the second conductive pattern 150b can have inner side surfaces 150s facing each other (e.g., facing). The inner side surfaces 150s of the conductive patterns 150a and 150b can be inclined at an angle with respect to the top surface of the substrate 100. The inner side surfaces 150s of the conductive patterns 150a and 150b can form a first angle θ1 with respect to the top surface of the substrate 100. The first passivation layer 172 can have inner side surfaces 172s between the conductive patterns 150a and 150b. The inner side surfaces 172s of the first passivation layer 172 can form a second angle θ2 with respect to the top surface of the substrate 100. In one embodiment, the second angle θ2 can be smaller than the first angle θ1.

[0056] Hereinafter, a semiconductor device according to various embodiments will be described. For a brief description, previously described elements can be identified by the same reference numerals without overlapping descriptions thereof. Figures 2 to 12B

[0057] Figure 13A and Figure 13B are enlarged cross-sectional views corresponding to a portion CC of Figure 11 of the semiconductor device according to an embodiment.

[0058] Referring to Figure 13A , on the top surface 150t of the first conductive pattern 150a and the top surface 150t of the second conductive pattern 150b, the thickness t2 of the second passivation layer 182 can be greater than the thickness t1 of the first passivation layer 172.

[0059] Referring to Figure 13B , the inner side surfaces 172s of the first passivation layer 172 can contact each other. In one embodiment, a lowermost surface 182b of the second passivation layer 182 (e.g., a portion of the second passivation layer 182 closest to the substrate 100) can be located between the first conductive pattern 150a and the second conductive pattern 150b, and can have a sharp shape (e.g., can become a point).

[0060] Figure 14 and Figure 15 are enlarged cross-sectional views of a portion of the semiconductor device according to an embodiment, along​Figure 2 a cross-sectional view taken along line I-I' of FIG. 1.

[0061] Referring to Figure 14 On the top surface of the conductive pattern 150, the first passivation layer 172 can be in contact (e.g., direct contact) with the third passivation layer 192. In one embodiment, the planarization process described with reference to Figure 9 to expose the top surface of the first passivation layer 172. The second passivation layer 182 can not be exposed to the opening OP.

[0062] Referring to Figure 15 The top surface 103t of the interlayer insulating layer 103 can be lower (e.g., closer to the substrate 100) on the scribe region 22 than on the chip region 10 and the edge region 24. In one embodiment, the lowermost surface 172b of the first passivation layer 172 on the scribe region 22 can be located at a vertical level lower than a vertical level of the uppermost surface (e.g., 103t) of the interlayer insulating layer 103.

[0063] Figure 16 is a plan view of a semiconductor chip separated from a semiconductor device according to an embodiment. Figure 17 is a cross-sectional view of a semiconductor package including a semiconductor chip according to an embodiment.

[0064] Referring to Figure 16 The semiconductor chip 200 that has been singulated on the substrate 100 by a sawing process can include the chip region 10 and the edge region 24 around the chip region 10. A portion of the scribe region 22 can remain near or around the edge region 24. The scribe region 22 can surround the edge region 24, and in this case, the scribe region 22 and the edge region 24 can constitute the scribe line region 20. The conductive pattern 150 can be located in or on the outer edge region of the chip region 10. The dam structure 116 can be located on the edge region 24 to surround the chip region 10.

[0065] Referring to Figure 17 The semiconductor package 1000 can include the semiconductor chip 200, the package substrate 500, the external bonding terminal 550, and the molding layer 570. In one embodiment, the semiconductor chip 200 manufactured by the aforementioned manufacturing method can be mounted on the package substrate 500.

[0066] The semiconductor chip 200 can include the chip pad 150 exposed by the passivation layer 153. The passivation layer 153 can include the first to third passivation layers 172, 182, and 192 described above. The chip pad 150 can include a data pad for inputting or outputting a data signal, a command / address pad for inputting or outputting a command signal and an address signal, or a ground pad and a power pad to which a ground voltage and a power voltage can be applied, respectively.

[0067] In one embodiment, the package substrate 500 may be a printed circuit board, a flexible substrate, or a strip substrate. In one embodiment, the package substrate 500 may include a flexible printed circuit board or a rigid printed circuit board, or a combination thereof, in which internal interconnects are provided.

[0068] The package substrate 500 may have a top surface and a bottom surface facing each other, and may include a bonding pad 510 and an outer bonding pad 520. The bonding pad 510 may be located on the top surface of the package substrate 500, and the outer bonding pad 520 may be located on the bottom surface of the package substrate 500. The bonding pad 510 and the outer bonding pad 520 may be connected to each other via internal interconnects. The semiconductor chip 200 may be located on a central region of the top surface of the package substrate 500, and the adhesive layer 515 may be located between the semiconductor chip 200 and the package substrate 500.

[0069] Bonding pad 510 can be connected to chip pad 150 of semiconductor chip 200 via wiring W. External bonding pad 520 can be connected to bonding pad 510 via internal interconnect ICL.

[0070] The molding layer 570 may be located on the top surface of the package substrate 500 to cover the semiconductor chip 200. The molding layer 570 may include an epoxy molding compound.

[0071] External bonding terminal 550 can be attached to external bonding pad 520 on the bottom surface of package substrate 500. Semiconductor package 1000 can be connected to external electronic devices through external bonding terminal 550.

[0072] Figure 18 The semiconductor device according to the embodiment and Figure 2 The sectional view corresponding to line I-I'. Figure 19 This is a cross-sectional view of a semiconductor package including a semiconductor chip according to an embodiment. For brevity, previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0073] Reference Figure 18According to an embodiment, the semiconductor chip can include a through interconnection structure 210 and a lower pad 222. The through interconnection structure 210 can penetrate the substrate 100 and the interlayer insulating layer 103, and can be connected to the internal interconnection line 114. The through interconnection structure 210 can include a conductive layer 212 and a via insulating layer 214. The conductive layer 212 can be formed of or include a metal material (e.g., W, Al, Ti, Ta, Co, or Cu). The via insulating layer 214 can be located between the conductive layer 212 and the substrate 100 and between the conductive layer 212 and the interlayer insulating layer 103. The via insulating layer 214 can be formed of or include, for example, silicon oxide. The lower pad 222 can be electrically connected to the internal interconnection line 114 through the conductive layer 212 of the through interconnection structure 210. The side surface of the lower pad 222 can be covered by a lower passivation layer 224, which can be disposed to cover the bottom surface 100b of the substrate 100.

[0074] Referring to Figure 19 According to an embodiment, the semiconductor package can be a high bandwidth memory (HBM) package. The semiconductor package 1000 can include semiconductor chips 200, a processing chip 300, a mediator 400, and a package substrate 500.

[0075] The semiconductor chips 200, which can be manufactured by the aforementioned method, can be mounted on the package substrate 500. The semiconductor chips 200 can include memory chips and / or logic chips. In one embodiment, the lowermost one of the semiconductor chips 200 can be a logic chip. The logic chip can be, for example, a microprocessor, an analog device, or a digital signal processor. Except for the lowermost semiconductor chip 200, the semiconductor chips 200 can be memory chips. In one embodiment, the memory chips can include volatile memory chips (e.g., dynamic random access memory (DRAM) chips and static random access memory (SRAM) chips) or non-volatile memory chips (e.g., phase change random access memory (PRAM) chips, magnetoresistive random access memory (MRAM) chips, ferroelectric random access memory (FeRAM) chips, or resistive random access memory (RRAM) chips).

[0076] The semiconductor chips 200 can include pads 200P on their top and bottom surfaces. The pads 200P can be Figure 18One of the under pads 222 and the chip pads 150 shown in FIG. 1. In one embodiment, the pads on the top surface of the semiconductor chip 200 can be the under pads 222, and the pads on the bottom surface of the semiconductor chip 200 can be the chip pads 150. In one embodiment, the pads on the top surface of the semiconductor chip 200 can be the chip pads 150, and the pads on the bottom surface of the semiconductor chip 200 can be the under pads 222. The semiconductor chip 200 can be electrically connected to the interposer 400 through the bonding terminals 202.

[0077] The interposer 400 can be located between the semiconductor chip 200 and the package substrate 500. The interposer 400 can include pads 400P on its top and bottom surfaces. The interposer 400 can electrically connect the processing chip 300 and the semiconductor chip 200 to the package substrate 500 through the bonding terminals 402 and 302. The processing chip 300 can be, for example, a microprocessor unit (MPU) or a graphics processor unit (GPU).

[0078] The external bonding terminals 550 can be attached to the external bonding pads 500P on the bottom surface of the package substrate 500. The semiconductor package 1000 can be connected to an external electronic device through the external bonding terminals 550.

[0079] By summarizing and reviewing, as the electronic industry develops, semiconductor devices can have high integration density and high operating speed. A semiconductor chip can include a redistribution layer that connects to chip pads and is used to change the position of pads placed at a specific location in the semiconductor chip.

[0080] According to an embodiment, a passivation layer that covers the uppermost metal lines and pads on a chip region of a semiconductor chip can have a multi-layer structure and can prevent cracks or process failures from occurring in the semiconductor chip and can increase the mechanical durability of the semiconductor chip.

[0081] One or more embodiments can provide a semiconductor device including a redistribution pad.

[0082] One or more embodiments can provide a semiconductor device including a plurality of stacked passivation layers.

[0083] Example embodiments have been disclosed and, although a particular terminology is employed, it is understood that the examples are used in a generic and descriptive sense and not for purposes of limitation. In some instances, features, attributes and / or benefits of the disclosed examples can be utilized to mutual advantage with reference to other examples. In some instances, the described features, benefits and / or elements of the examples can be used alone or in combination with other features, benefits and / or elements of other examples. Thus, the scope of the disclosure should be construed in view of the appended claims and the full breadth of the patent is pointed out with each element which follows the word “means” being set forth in independent claim form.

Claims

1. A semiconductor device comprising: a substrate including a chip region and a peripheral region around the chip region; an integrated circuit element on the chip region; an interlayer insulating layer covering the integrated circuit element; an interconnect structure having internal interconnect lines on the interlayer insulating layer, the interconnect structure having a side surface on the peripheral region; a first conductive pattern and a second conductive pattern on the interconnect structure, the first conductive pattern and the second conductive pattern electrically connected to the internal interconnect lines; a first passivation layer covering the first conductive pattern and the second conductive pattern and the side surface of the interconnect structure; and a second passivation layer on the first passivation layer, wherein: the second passivation layer includes a second insulating material, the first passivation layer includes a first insulating material, and the second insulating material of the second passivation layer is different from the first insulating material of the first passivation layer, the second passivation layer has a bottom surface positioned at a vertical level lower than a vertical level of a top surface of the first conductive pattern in a region between the first conductive pattern and the second conductive pattern, a portion of the first passivation layer on a side surface of each of the first conductive pattern and the second conductive pattern is thinner than a remaining portion of the first passivation layer, a thickness of the first passivation layer is smaller than a thickness of the second passivation layer in the region between the first conductive pattern and the second conductive pattern, and a thickness of the first passivation layer is greater than a thickness of the second passivation layer in a region on a top surface of each of the first conductive pattern and the second conductive pattern, and each of the first passivation layer and the second passivation layer has an opening exposing a portion of the top surface of the first conductive pattern, the first conductive pattern is a pad portion whose top surface is partially exposed by the opening, the second conductive pattern is an interconnect line positioned at a same vertical level as the pad portion, and the second conductive pattern is completely covered by each of the first passivation layer and the second passivation layer. A thickness of the first passivation layer is smaller than a thickness of the first conductive pattern on the top surface of the first conductive pattern.

2. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 2, wherein: a thickness of the first conductive pattern ranges from 1.1 times to 1.9 times a thickness of the first passivation layer on the top surface of the first conductive pattern.

4. The semiconductor device according to claim 1, wherein: the first passivation layer has an inner side surface between the first conductive pattern and the second conductive pattern, and an inclination angle of the inner side surface is smaller than an inclination angle of a side surface of the first conductive pattern facing the second conductive pattern.

5. The semiconductor device according to claim 1, further comprising a protective layer between the first passivation layer and the first conductive pattern and the second conductive pattern, a thickness of the protective layer is smaller than a thickness of the first passivation layer. wherein, 6. The semiconductor device according to claim 1, further comprising a third passivation layer on the second passivation layer, a thickness of the third passivation layer is smaller than a thickness of the first passivation layer and smaller than a thickness of the second passivation layer. wherein a top surface of the second passivation layer is in contact with a bottom surface of the third passivation layer.

7. The semiconductor device according to claim 6, wherein ​ 8. The semiconductor device according to any one of claims 1 to 7, further comprising a through-substrate interconnection structure that penetrates the substrate and the interlayer insulating layer, the through-substrate interconnection structure being connected to the internal interconnection line.

9. The semiconductor device according to any one of claims 1 to 7, wherein: the first passivation layer includes a high-density plasma oxide layer, and the second passivation layer includes a tetraethyl orthosilicate layer.

10. A semiconductor device comprising: a substrate; an integrated circuit element on the substrate; an interlayer insulating layer covering the integrated circuit element; an interconnection structure on the interlayer insulating layer, the interconnection structure including an internal interconnection line connected to the integrated circuit element; a conductive pattern on the interconnection structure, the conductive pattern being electrically connected to the internal interconnection line; a first passivation layer covering side surfaces of the interconnection structure and the conductive pattern; and a second passivation layer on the first passivation layer, wherein: the second passivation layer includes an insulating material, the first passivation layer includes an insulating material, and the insulating material of the second passivation layer is different from the insulating material of the first passivation layer, a thickness of the first passivation layer is smaller than a thickness of the second passivation layer in a region between the conductive patterns, a thickness of the first passivation layer is larger than a thickness of the second passivation layer in a region on a top surface of each of the conductive patterns, and a portion of the first passivation layer on a side surface of each of the conductive patterns is thinner than a remaining portion of the first passivation layer, and the conductive pattern includes a first conductive pattern and a second conductive pattern, each of the first passivation layer and the second passivation layer has an opening that exposes a portion of a top surface of the first conductive pattern, the first conductive pattern is a pad whose top surface is partially exposed by the opening, the second conductive pattern is an interconnection line positioned at the same vertical level as the pad, and the second conductive pattern is completely covered by each of the first passivation layer and the second passivation layer. the second passivation layer has a bottom surface positioned at a vertical level lower than a vertical level of a top surface of each of the conductive patterns in a region between the conductive patterns.

11. The semiconductor device according to claim 10, wherein 12. The semiconductor device according to claim 10, further comprising a through-substrate interconnection structure that penetrates the substrate and the interlayer insulating layer, the through-substrate interconnection structure being connected to the internal interconnection line.

13. The semiconductor device according to claim 10, further comprising a protective layer between the conductive pattern and the first passivation layer, a thickness of the protective layer is smaller than a thickness of the first passivation layer. wherein 14. The semiconductor device according to claim 10, further comprising a third passivation layer on the second passivation layer, a thickness of the third passivation layer is smaller than a thickness of the first passivation layer and smaller than a thickness of the second passivation layer. wherein 15. A semiconductor device comprising: a substrate including a chip region and a peripheral region around the chip region; an integrated circuit element on the chip region of the substrate; an interlayer insulating layer covering the integrated circuit element; an interconnection structure on the interlayer insulating layer, the interconnection structure having a side surface on the peripheral region of the substrate; a conductive pattern on a top surface of the interconnection structure, the conductive pattern being electrically connected to an internal interconnection line in the interconnection structure; a protective layer covering the conductive pattern; and a second passivation layer on the first passivation layer, wherein: the second passivation layer includes an insulating material, the first passivation layer includes an insulating material, and the insulating material of the second passivation layer is different from the insulating material of the first passivation layer, a thickness of the first passivation layer is smaller than a thickness of the second passivation layer in a region between the conductive patterns, a thickness of the first passivation layer is larger than a thickness of the second passivation layer in a region on a top surface of each of the conductive patterns, and a portion of the first passivation layer on a side surface of each of the conductive patterns is thinner than a remaining portion of the first passivation layer, and the conductive pattern includes a first conductive pattern and a second conductive pattern, each of the first passivation layer and the second passivation layer has an opening that exposes a portion of a top surface of the first conductive pattern, the first conductive pattern is a pad whose top surface is partially exposed by the opening, the second conductive pattern is an interconnection line positioned at the same vertical level as the pad, and the second conductive pattern is completely covered by each of the first passivation layer and the second passivation layer. a passivation layer on the protective layer, the passivation layer having an opening partially exposing a top surface of the conductive pattern, wherein the passivation layer includes: a first passivation layer on the protective layer and covering at least a portion of the side surface of the interconnection structure; a second passivation layer on the first passivation layer and including an insulating material different from that of the first passivation layer; and a third passivation layer on the second passivation layer and including an insulating material different from that of the first passivation layer and that of the second passivation layer, wherein a thickness of the conductive pattern is greater than a thickness of each of the first passivation layer to the third passivation layer wherein a portion of the first passivation layer on the side surface of each conductive pattern is thinner than a remaining portion of the first passivation layer, a thickness of the first passivation layer is smaller than a thickness of the second passivation layer in an area between the conductive patterns, and a thickness of the first passivation layer is greater than a thickness of the second passivation layer in an area on the top surface of each conductive pattern, and wherein the conductive pattern includes a first conductive pattern and a second conductive pattern, each of the first passivation layer and the second passivation layer has an opening exposing a portion of a top surface of the first conductive pattern, the first conductive pattern is a pad whose top surface is partially exposed by the opening, the second conductive pattern is an interconnection line positioned at a same vertical level as the pad, and the second conductive pattern is completely covered by each of the first passivation layer and the second passivation layer.

16. The semiconductor device according to claim 15, wherein The second passivation layer has a bottom surface positioned at a vertical level lower than a vertical level of the top surface of each conductive pattern in an area between the conductive patterns.

17. The semiconductor device of claim 15, further comprising a through-substrate and through-interlayer-insulation-layer interconnection structure connected to the internal interconnection line.

18. The semiconductor device of claim 15, wherein: the first passivation layer has an inner side surface positioned between the conductive patterns, and an inclination angle of the inner side surface is smaller than an inclination angle of the side surface of the conductive pattern.

19. The semiconductor device of claim 15, wherein: the first passivation layer includes a high-density-plasma-oxide layer, and the second passivation layer includes a tetraethyl orthosilicate layer.

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