Semiconductor device and solid-state image pickup element

Abstract

A semiconductor device (50) according to the present disclosure includes a first substrate (20) configured to be monolithicized and having a first semiconductor circuit (LOG) including a first terminal (25), and a second substrate (10) configured to have a second semiconductor circuit (PIX) including a second terminal (16), wherein the first terminal (25) and the second terminal (16) are joined. The second substrate (10) includes a first insulating layer (13) arranged above the second substrate (10), and a second insulating layer (14) arranged above at least a portion of the first insulating layer (13) and having the second terminal (16) arranged therein.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a solid-state imaging element. BACKGROUND

[0002] There is a three-dimensional mounting technique for layering a plurality of substrates. At this time, there is a case where substrates having different areas are joined to each other (for example, see Patent Literature 1).

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: JP 2017-73436 A SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In the structure disclosed in Patent Literature 1, dummy terminals and the like that do not contribute to the joining between substrates can become a source of metal contamination.

[0008] Therefore, the present disclosure proposes a semiconductor device and a solid-state imaging element capable of inhibiting dummy terminals and the like that do not contribute to the joining between substrates from becoming a source of metal contamination.

[0009] SOLUTION TO PROBLEM

[0010] According to the present disclosure, there is provided a semiconductor device having: a first substrate configured to be monolithicized and having a first semiconductor circuit including a first terminal; and a second substrate configured to have a second semiconductor circuit including a second terminal, in which the first terminal and the second terminal are joined, and the second substrate has: a first insulating layer arranged above the second substrate; and a second insulating layer at least partially arranged above the first insulating layer, and the second terminal is arranged in the second insulating layer. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a schematic view showing a configuration example of a solid-state imaging element according to an embodiment of the present disclosure.

[0012] Figure 2 is a flowchart showing an example of a process of a manufacturing process of a solid-state imaging element according to an embodiment of the present disclosure.

[0013] Figure 3 is a flowchart showing an example of a process of a manufacturing process of a solid-state imaging element according to an embodiment of the present disclosure.

[0014] Figure 4is a schematic view showing the configuration of each substrate before bonding in the manufacturing process of the solid-state imaging device according to the embodiment of the present disclosure.

[0015] Figure 5 is a flowchart showing an example of the procedure of the cleaning process in the manufacturing process of the solid-state imaging device according to the comparative example of the present disclosure.

[0016] Figure 6 is a flowchart showing an example of the procedure of the cleaning process in the manufacturing process of the solid-state imaging device according to the comparative example of the present disclosure.

[0017] Figure 7 is a schematic view showing a configuration example of the solid-state imaging device according to the first modified example of the embodiment of the present disclosure.

[0018] Figure 8 is a flowchart showing an example of the procedure of the cleaning process in the manufacturing process of the solid-state imaging device according to the first modified example of the embodiment of the present disclosure.

[0019] Figure 9 is a schematic view showing a configuration example of the solid-state imaging device according to the second modified example of the embodiment of the present disclosure.

[0020] Figure 10 is a flowchart showing an example of the procedure of the cleaning process in the manufacturing process of the solid-state imaging device according to the second modified example of the embodiment of the present disclosure.

[0021] Figure 11 is a schematic view showing a configuration example of the solid-state imaging device according to the third modified example of the embodiment of the present disclosure.

[0022] Figure 12 is a flowchart showing an example of the procedure of the cleaning process in the manufacturing process of the solid-state imaging device according to the third modified example of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that in each of the embodiments described below, the same components are denoted by the same reference signs, and overlapping descriptions will be omitted.

[0024] [Embodiment]

[0025] Reference will be made to Figures 1 to 12 A solid-state imaging device according to an embodiment will be described.

[0026] (Configuration Example of Solid-State Imaging Device)

[0027] Figure 1 is a schematic view showing a part of the solid-state imaging device 50 according to the embodiment of the present disclosure. As shown in FIG. 1, the solid-state imaging device 50 includes a substrate 51, a substrate 52, and a substrate 53.Figure 1 As shown, the solid-state imaging element 50 as the semiconductor device of the present embodiment includes a logic substrate 20 as a monolithic first substrate, a storage substrate 30 as a monolithic first substrate, and a pixel substrate 10 as a monolithic second substrate.

[0028] The pixel substrate 10 includes a substrate 11 that has been monolithically processed into a chip. For example, a photoelectric conversion element that is not shown is arranged in the substrate 11. A color filter CF and an on-chip lens OCL are arranged on one face of the substrate 11. A pixel circuit PIX as a second semiconductor circuit including a pixel transistor and the like is arranged on the other face of the substrate 11. However, the pixel circuit PIX can include a photoelectric conversion element and the like.

[0029] The on-chip lens OCL collects emitted light, and the collected light is guided to the photoelectric conversion element via the color filter CF. The photoelectric conversion element converts the received light into an electric signal corresponding to the amount of the received light through photoelectric conversion. The pixel circuit PIX reads the electric signal from the photoelectric conversion element and outputs the electric signal to the logic substrate 20 side.

[0030] A silicon oxide (SiO2) layer 12 is arranged on the pixel circuit PIX. A silicon nitride (SiN) layer 13 as a first insulating layer is arranged on the silicon oxide layer 12. A silicon oxide layer 14 as a second insulating layer is arranged on at least a portion of the silicon nitride layer 13.

[0031] In the silicon oxide layer 14, a terminal 16 as a second terminal is arranged so as to be exposed on a surface of the silicon oxide layer 14. In other words, the terminal 16 is arranged on the silicon nitride layer 13.

[0032] The terminal 16 is electrically connected to a pixel transistor and the like in the pixel circuit PIX through a plug 15 that extends through the silicon nitride layer 13 and the silicon oxide layer 12. The terminal 16 and the plug 15 include, for example, copper (Cu). A barrier metal (not shown) as a liner is interposed between the terminal 16, the plug 15, and the silicon oxide layers 12, 14 and the silicon nitride layer 13. The terminal 16 and the plug 15 are also included in the pixel circuit PIX.

[0033] The logic substrate 20 includes a substrate 21 that has been monolithically processed into a chip. A silicon nitride layer 22 as a third insulating layer is arranged on one face of the substrate 21. A silicon oxide layer 23 as a fourth insulating layer is arranged on the silicon nitride layer 22. However, as will be described later, the silicon nitride layer 22 can not be arranged.

[0034] In the silicon oxide layer 23, a logic circuit LOG as a first semiconductor circuit including, for example, a logic transistor is arranged. The logic circuit LOG processes the electric signal output from the pixel substrate 10.

[0035] Further, in the silicon oxide layer 23, a terminal 25 exposed on a surface of the silicon oxide layer 23 as a first terminal is arranged. The terminal 25 is electrically connected to a logic transistor or the like in the logic circuit LOG through a plug 24 extending through the silicon oxide layer 23. The terminal 25 and the plug 24 include, for example, copper. A barrier metal (not shown) as a liner is interposed between the terminal 25, the plug 24, and the silicon oxide layer 23, the silicon nitride layer 22. The terminal 25 and the plug 24 are also included in the logic circuit LOG.

[0036] The storage substrate 30 includes a substrate 31 which has been singulated into a chip. On one face of the substrate 31, a silicon nitride layer 32 as a third insulating layer is arranged. On the silicon nitride layer 32, a silicon oxide layer 33 as a fourth insulating layer is arranged. However, as will be described later, the silicon nitride layer 32 can not be arranged.

[0037] In the silicon oxide layer 33, a memory circuit MEM as a first semiconductor circuit including, for example, a memory transistor is arranged. The memory circuit MEM holds various data required for the function of the solid-state imaging element 50.

[0038] Further, in the silicon oxide layer 33, a terminal 35 exposed on a surface of the silicon oxide layer 33 as a first terminal is arranged. The terminal 35 is electrically connected to a memory transistor or the like in the memory circuit MEM through a plug 34 extending through the silicon oxide layer 33. The terminal 35 and the plug 34 include, for example, copper. A barrier metal (not shown) as a liner is interposed between the terminal 35, the plug 34, and the silicon oxide layer 33, the silicon nitride layer 32. The terminal 35 and the plug 34 are also included in the memory circuit MEM.

[0039] The pixel substrate 10 and the logic substrate 20 are joined by the terminal 16 included in the pixel substrate 10 and the terminal 25 included in the logic substrate 20. The joining of the terminals 16 and 25 is so-called Cu-Cu joining.

[0040] The pixel substrate 10 and the storage substrate 30 are joined by the terminal 16 included in the pixel substrate 10 and the terminal 35 included in the storage substrate 30. The joining of the terminals 16 and 35 is so-called Cu-Cu joining.

[0041] The surface of the logic substrate 20 side and the storage substrate 30 side of the pixel substrate 10 includes a joining surface JS and a non-joining surface NS. The non-joining surface NS is arranged on the substrate 11 side with respect to the joining surface JS. In the pixel substrate 10, the surface of the silicon oxide layer 14 including the terminal 16 is the joining surface JS. Further, in a region in which a part of the silicon oxide layer 14 is not arranged on the silicon nitride layer 13 or the like, at least the surface of the silicon nitride layer 13 is the non-joining surface NS.

[0042] The end surface of the silicon oxide layer 14, 23, and 33 facing the silicon nitride layer 13 as the non-bonding surface NS has a concave shape curved toward the inside of each layer 14, 23, and 33.

[0043] The surface of the pixel substrate 10 side of the logic substrate 20 includes only the bonding surface JS. That is, in the logic substrate 20, the entire surface of the silicon oxide layer 23 including the terminal 25 is the bonding surface JS.

[0044] The surface of the pixel substrate 10 side of the storage substrate 30 includes only the bonding surface JS. That is, in the storage substrate 30, the entire surface of the silicon oxide layer 33 including the terminal 35 is the bonding surface JS.

[0045] On the pixel substrate 10, the logic substrate 20, and the storage substrate 30, an insulating layer 17 is disposed that covers the entire logic substrate 20, the entire storage substrate 30, and the non-bonding surface NS of the pixel substrate 10. The insulating layer 17 is, for example, a resin layer containing polyimide or the like or an inorganic layer containing silicon oxide or the like.

[0046] On the surface side opposite to each circuit LOG and MEM of the logic substrate 20 and the storage substrate 30, a monolithic support substrate 51 is disposed. The support substrate 51 is bonded to the pixel substrate 10, the logic substrate 20, and the storage substrate 30 via the insulating layer 17.

[0047] (Outline of manufacturing process of solid-state imaging device)

[0048] Next, the outline of the manufacturing process of the solid-state imaging device 50 of the present embodiment will be described with reference to Figure 2 and Figure 3 Figure 2 and Figure 3 are flowcharts showing examples of the processes of the manufacturing process of the solid-state imaging device 50 according to the present embodiment.

[0049] As shown in Figure 2 (a), a logic substrate 20w before monolithicization in which a logic circuit LOG is formed and a storage substrate 30w before monolithicization in which a storage circuit MEM is formed are prepared.

[0050] As shown in Figure 2 (b), the logic substrate 20w and the storage substrate 30w are monolithicized to obtain the logic substrate 20 and the storage substrate 30, respectively. That is, the logic substrate 20w and the storage substrate 30w are cut with a cutting saw or a laser or the like to provide the logic substrate 20 and the storage substrate 30 having a chip shape, respectively.

[0051] As shown in Figure 2 (c), a pixel substrate 10w before monolithicization in which a pixel circuit PIX is formed is prepared. ​

[0052] As Figure 2 (d) shown, the logic substrate 20, the storage substrate 30, and the pixel substrate 10w are joined by the terminals 16, 25, and 35.

[0053] As Figure 2 (e) shown, the back surfaces of the logic substrate 20 and the storage substrate 30 are polished and thinned.

[0054] As Figure 2 (f) shown, the polishing powder of the logic substrate 20 and the storage substrate 30 is cleaned.

[0055] As Figure 3 (g) shown, an insulating layer 17 covering the non-joined surface NS of the logic substrate 20, the storage substrate 30, and the pixel substrate 10w is formed, thereby obtaining a joined substrate 40w including the logic substrate 20, the storage substrate 30, and the pixel substrate 10w.

[0056] As Figure 3 (a) shown, a support substrate 51w before singulation is prepared.

[0057] As Figure 3 (b) shown, the support substrate 51w and the joined substrate 40w are joined via the insulating layer 17.

[0058] As Figure 3 (c) shown, the joined substrate 40w is thinned from the pixel substrate 10w side and cleaned.

[0059] As Figure 3 (d) shown, a color filter CF and an on-chip lens OCL, or the like, are formed on the pixel substrate 10w, to obtain a solid-state imaging device 50w before singulation.

[0060] As Figure 3 (e) shown, the solid-state imaging device 50w is singulated. That is, the solid-state imaging device 50w is cut by a dicing saw or a laser, or the like, to provide a solid-state imaging device 50 having a chip shape.

[0061] As Figure 4 (f) shown, a singulated solid-state imaging device 50 is obtained.

[0062] In this way, the manufacturing process of the solid-state imaging device 50 of the present embodiment is completed.

[0063] (Example of cleaning process of solid-state imaging device)

[0064] Next, an example of a cleaning process in the manufacturing process of the solid-state imaging device 50 of the present embodiment will be described in conjunction with Figure 5 and Figure 4 Figure 4 ​is a schematic view showing the configuration of each substrate 10w, 20, and 30 before bonding in the manufacturing process of the solid-state imaging device 50 according to the embodiment of the present disclosure.

[0065] As shown in Figure 4 The singulated end surface of the logic substrate 20 before bonding has a straight-line shape, as shown in (a). In the logic substrate 20 after the manufacturing process of the solid-state imaging device 50, the end surface of the silicon oxide layer 23 has a concave shape curved toward the inside of the silicon oxide layer 23 due to the cleaning process to be described later.

[0066] As shown in Figure 4 The singulated end surface of the storage substrate 30 before bonding has a straight-line shape, as shown in (b). In the storage substrate 30 after the manufacturing process of the solid-state imaging device 50, the end surface of the silicon oxide layer 33 has a concave shape curved toward the inside of the silicon oxide layer 33 due to the cleaning process to be described later.

[0067] As shown in Figure 5 In the pixel substrate 10w before bonding, the silicon oxide layer 14 is arranged on the entire surface of the silicon nitride layer 13, as shown in (c). In the pixel substrate 10 after the manufacturing process of the solid-state imaging device 50, a part of the silicon oxide layer 14 is missing due to the cleaning process to be described later.

[0068] Further, in the pixel substrate 10w before bonding, the terminal 16d exposed on the surface of the silicon oxide layer 14 as a third terminal can be arranged in the silicon oxide layer 14. In other words, the terminal 16d is arranged on the silicon nitride layer 13.

[0069] The terminal 16d does not have the plug 15 or the like and is not electrically connected to the pixel transistor or the like in the pixel circuit PIX. That is, the terminal 16d is a dummy terminal not included in the pixel circuit PIX. The terminal 16d is provided so that, for example, pattern dependency or the like does not occur in the process of forming another terminal 16.

[0070] Such a terminal 16d can be arranged at a position other than the bonding surface JS between the logic substrate 20, the storage substrate 30, and the pixel substrate 10w. In this case, after the logic substrate 20 and the storage substrate 30 are bonded to the pixel substrate 10w, the terminal 16d is in a state of being exposed on the surface of the silicon oxide layer 14. In this state, the pixel substrate 10w to which the logic substrate 20 and the storage substrate 30 are bonded is subjected to the polishing process and the cleaning process of the logic substrate 20 and the storage substrate 30.

[0071] Figure 5 is a flowchart showing an example of the process of the cleaning process in the manufacturing process of the solid-state imaging device 50 according to the embodiment of the present disclosure. Figure 5 (Aa) to Figure 5(Da) shows a region outside the bonding surface JS between the logic substrate 20 and the pixel substrate 10w and in which the terminal 16d exposed on the surface of the silicon oxide layer 14 is not present. Figure 5 (Ab) to Figure 5 (Db) shows a region outside the bonding surface JS between the logic substrate 20 and the pixel substrate 10w and in which the terminal 16d exposed on the surface of the silicon oxide layer 14 is present.

[0072] First, the cleaning process for the region in which the exposed terminal 16d is not present will be described.

[0073] As shown in Figure 5 (Aa), for example, after the logic substrate 20 is polished, polishing powder D such as silicon is present around the logic substrate 20 and the pixel substrate 10w.

[0074] As shown in Figure 5 (Ba), in order to remove the polishing powder D, a cleaning process is performed using a cleaning liquid such as an aqueous solution of hydrofluoric acid-hydrogen peroxide (FPM).

[0075] At this time, in the region outside the bonding surface JS between the logic substrate 20 and the pixel substrate 10w, the exposed surface of the silicon oxide layer 14 is exposed to the cleaning liquid.

[0076] Accordingly, the silicon oxide layer 14 is dissolved. For example, at least one of the cleaning time, the cleaning temperature, and the concentration of the cleaning liquid is adjusted, and the cleaning process is continued until the silicon oxide layer 14 is completely removed in the layer thickness direction. Here, the dissolution speed of the silicon nitride layer 13 caused by the cleaning liquid is lower than the dissolution speed of the silicon oxide layer 14 caused by the cleaning liquid. That is, the silicon nitride layer 13 is more excellent in the resistance to the cleaning liquid than the silicon oxide layer 14. Accordingly, the silicon nitride layer 13 functions as a barrier layer and the etching of the pixel circuit PIX and the like under the silicon nitride layer 13 is suppressed.

[0077] Further, at this time, the end surface of the monolithic logic substrate 20 is also exposed to the cleaning liquid.

[0078] Accordingly, the end surface of the silicon oxide layer 23 is dissolved and isotropically etched to the inside of the silicon oxide layer 23 to have a recessed shape. Accordingly, in the portion corresponding to the skirt of the end surface of the silicon oxide layer 23, the silicon oxide layer 14 is also isotropically etched to the inside of the silicon oxide layer 14 to have a recessed shape.

[0079] After the cleaning process is completed, a non-bonding surface NS including the surface of the silicon nitride layer 13 exposed by the etching of the silicon oxide layer 14 is formed. The non-bonding surface NS is arranged on the substrate 11 side with respect to the bonding surface JS due to the etching of the cleaning liquid or the like.

[0080] As shown in Figure 5(Ca) The insulating layer 17 is formed so as to cover the entire logic substrate 20 and the non-bonding surface NS of the pixel substrate 10w, as shown. At this stage, the insulating layer 17 has a step corresponding to the thickness of the logic substrate 20 and the height difference between the bonding surface JS and the non-bonding surface NS.

[0081] As Figure 5 (Da) The insulating layer 17 is planarized, as shown.

[0082] Next, the cleaning process for the region in which the exposed terminal 16d exists will be described.

[0083] As Figure 5 (Ab) After the logic substrate 20 is polished, for example, polishing powder D such as silicon exists around the logic substrate 20 and the pixel substrate 10w, as shown.

[0084] As Figure 5 (Bb) In order to remove the polishing powder D, a cleaning process is performed using a cleaning liquid such as FPM, as shown.

[0085] At this time, in the region other than the bonding surface JS between the logic substrate 20 and the pixel substrate 10w, both the exposed surface of the silicon oxide layer 14 and the exposed surface of the terminal 16d are exposed to the cleaning liquid.

[0086] Accordingly, the silicon oxide layer 14 and the terminal 16d are dissolved. In the region in which the above-described exposed terminal 16d does not exist, for example, the cleaning process is continued until the silicon oxide layer 14 is completely removed in the layer thickness direction. Accordingly, in the region in which the exposed terminal 16d exists, the terminal 16d is completely dissolved, or the silicon oxide layer 14 that is the base of the terminal 16d is eroded, and the terminal 16d is separated from the silicon oxide layer 14.

[0087] Note that the erosion of the silicon oxide layer 14 in the region in which the exposed terminal 16d exists proceeds more slowly than the erosion of the silicon oxide layer 14 in the above-described region in which the exposed terminal 16d does not exist. Accordingly, the silicon oxide layer 14 is not completely removed in the layer thickness direction, but is slightly left.

[0088] Further, at this time, the end surface of the monolithic logic substrate 20 is also exposed to the cleaning liquid.

[0089] Accordingly, the end surface of the silicon oxide layer 23 is dissolved and is isotropically eroded toward the inside of the silicon oxide layer 23 to have a recessed shape. Accordingly, at the portion corresponding to the skirt of the end surface of the silicon oxide layer 23, the silicon oxide layer 14 is also isotropically eroded toward the inside of the silicon oxide layer 14 to have a recessed shape.

[0090] After the cleaning process is completed, the terminal 16d disappears from the silicon oxide layer 14. Then, a non-bonding surface NS including a surface of the silicon oxide layer 14 newly exposed by the etching of the cleaning liquid and a surface of the silicon nitride layer 13 exposed, for example, by the disappearance of the terminal 16d is formed. As described above, the non-bonding surface NS can include a surface of the silicon oxide layer 14 that is etched in a portion of the region.

[0091] As Figure 5 (Cb), an insulating layer 17 covering the entire non-bonding surface NS of the logic substrate 20 and the pixel substrate 10w is formed.

[0092] As Figure 5 (Db), the insulating layer 17 is planarized.

[0093] In this way, the cleaning process in the manufacturing process of the solid-state imaging device 50 is completed.

[0094] Note that there is a case where, after the processes of Figure 5 (Ba) and Figure 5 (Bb) and before the processes of Figure 6 (Ca) and Figure 6 (Cb), a process of further thinning the thinned substrate 21 of the logic substrate 20 and the thinned substrate 31 of the storage substrate 30 by chemical mechanical polishing (CMP) or etching is performed to substantially completely remove.

[0095] At this time, the silicon nitride layer 22 of the logic substrate 20 and the silicon nitride layer 32 of the storage substrate 30 serve as a barrier layer. The silicon nitride layers 22 and 32 can not be disposed unless the substrates 21 and 31 are further thinned.

[0096] (Comparative Example)

[0097] Next, the problem of the solid-state imaging device of the comparative example will be described in conjunction with Figure 6 The solid-state imaging device of the comparative example does not include the silicon nitride layer 13 serving as a barrier layer.

[0098] Figure 6 (Aa) and Figure 6 (Ba) are examples in which severe conditions are used as in the above-described embodiment.

[0099] As Figure 6 (Aa), it is assumed that the polishing powder D is removed in the region where the exposed dummy terminal 16d' is not present under the severe conditions as in the above-described embodiment. However, under such conditions, there is a possibility that the silicon oxide layer 14' is completely removed in the layer thickness direction and that, for example, the pixel circuit PIX' is etched and damaged as shown in Figure 6 (Ba).

[0100] Figure 6 (Ab) and Figure 6 (Bb) is an example in which conditions are relaxed compared to the above embodiment.

[0101] As Figure 7 (Ab) shows, it is assumed that the polishing powder D is removed in a region in which the exposed dummy terminal 16d' is present under conditions that are relaxed compared to the above embodiment. However, under such conditions, as Figure 8 (Bb) shows, there is a case in which, for example, a part of the terminal 16d' does not disappear but remains in the silicon oxide layer 14'. In this case, the terminal 16d' can become a metal contamination source.

[0102] The solid-state imaging device 50 of the present embodiment includes a silicon nitride layer 13 arranged above the pixel substrate 10w and a silicon oxide layer 14 arranged above the silicon nitride layer 13 and in which the terminal 16d is arranged. By including the silicon nitride layer 13 in the lower layer of the terminal 16d arranged in the silicon oxide layer 14 in this way, the silicon nitride layer 13 can be used as a barrier layer in the cleaning process after polishing of the logic substrate 20 or the like, and damage to the pixel circuit PIX can be suppressed. Thus, the exposed terminal 16d can be made to disappear by using harsh conditions, and the residue of the terminal 16d can be prevented from becoming a metal contamination source.

[0103] (First Modified Example)

[0104] In the manufacturing process of the solid-state imaging device, the silicon nitride layer can be inserted not only directly below the terminal but also into other portions.

[0105] A solid-state imaging device 50a of a first modified example of the present embodiment will be described with reference to Figure 7 and Figure 7 A solid-state imaging device 50a of a first modified example of the present embodiment will be described with reference to

[0106] Figure 8 is a schematic view showing a configuration example of the solid-state imaging device 50a according to the first modified example of the present embodiment. As Figure 8 shown in

[0107] The silicon nitride layer 13u is formed, for example, to have the same thickness as the silicon nitride layer 13 of the above embodiment. The silicon oxide layer 14 is formed to have a thickness that is, for example, the sum of the silicon oxide layers 12 and 14 of the above embodiment.

[0108] In the silicon oxide layer 14, a terminal 16 exposed on a surface of the silicon oxide layer 14 is arranged. The terminal 16 is electrically connected to a pixel transistor or the like in the pixel circuit PIX through a plug 15 extending through the silicon oxide layer 14 and the silicon nitride layer 13.

[0109] That is, in the pixel substrate 10a of the first modification example, the silicon nitride layer 13u is not arranged directly below the terminal 16, but is arranged at a leg portion of the plug 15.

[0110] In the pixel substrate 10a, a surface of the silicon oxide layer 14 including the terminal 16 is a bonding surface JS. Further, in a region or the like in which the silicon oxide layer 14 is not partially arranged on the silicon nitride layer 13u, at least a surface of the silicon nitride layer 13u is a non-bonding surface NS.

[0111] An end surface of the silicon oxide layer 14, 23, and 33 facing the silicon nitride layer 13u as the non-bonding surface NS has a concave shape curved toward an inner side of each layer 14, 23, and 33.

[0112] Figure 8 is a flowchart showing an example of a process of a cleaning process in a manufacturing process of the solid-state imaging element 50a according to the first modification example of the embodiment of the present disclosure.

[0113] First, the cleaning process for a region in which the exposed terminal 16d is not present will be described.

[0114] As shown in Figure 8 As shown in (Aa), for example, after the logical substrate 20 is polished, there is polishing powder D such as silicon or the like present around the logical substrate 20 and the pixel substrate before being singulated.

[0115] As shown in Figure 8 (Ba), in order to remove the polishing powder D, a cleaning process is performed using a cleaning liquid such as FPM or the like.

[0116] At this time, for example, at least one of a cleaning time, a cleaning temperature, and a concentration of the cleaning liquid or the like is adjusted, and the cleaning process is continued until the silicon oxide layer 14 is completely removed in the layer thickness direction. The silicon nitride layer 13u functions as a barrier layer and suppresses etching of the pixel circuit PIX or the like under the silicon nitride layer 13u.

[0117] After the cleaning process is completed, the non-bonding surface NS including a surface of the silicon nitride layer 13u exposed by etching of the silicon oxide layer 14 is formed.

[0118] As shown in Figure 8(Ca) shows that the insulating layer 17 is formed so as to cover the entire logic substrate 20 and the non-bonding surface NS of the pixel substrate. Here, since the silicon nitride layer 13u is closer to the substrate 11 than in the example of the above-described embodiment, and the silicon oxide layer 14 is formed thicker, the height difference between the bonding surface JS and the non-bonding surface NS is further increased. Therefore, the step of the insulating layer 17 at this stage becomes larger than in the example of the above-described embodiment.

[0119] As Figure 8 (Da) shows that the insulating layer 17 is planarized.

[0120] Next, the cleaning process for the region where the terminal 16d is exposed will be described.

[0121] As Figure 8 (Ab) shows that, for example, after the logic substrate 20 is polished, there is polishing powder D such as silicon around the logic substrate 20 and the pixel substrate before singulation.

[0122] As Figure 9 (Bb) shows that, in order to remove the polishing powder D, a cleaning process is performed using a cleaning liquid such as FPM. The terminal 16d is completely dissolved, or the silicon oxide layer 14 that is the base of the terminal 16d is eroded, and the terminal 16d is separated from the silicon oxide layer 14.

[0123] After the cleaning process is completed, the terminal 16d disappears from the silicon oxide layer 14. Then, the non-bonding surface NS including the surface of the silicon oxide layer 14 newly exposed by the erosion of the cleaning liquid and the surface of the silicon nitride layer 13u exposed by the removal of the silicon oxide layer 14 is formed. As described above, the non-bonding surface NS can include the surface of the silicon oxide layer 14 that is eroded in a part of the region.

[0124] As Figure 10 (Cb) shows that the insulating layer 17 is formed so as to cover the entire logic substrate 20 and the non-bonding surface NS of the pixel substrate.

[0125] As Figure 9 (Db) shows that the insulating layer 17 is planarized.

[0126] In this way, the cleaning process in the manufacturing process of the solid-state imaging element 50a is completed.

[0127] As described above, the solid-state imaging element 50a of the first modified example also has the same effects as the above-described embodiment.

[0128] (Second Modified Example)

[0129] Next, the cleaning process for the region where the terminal 16d is exposed will be described. Figure 9 and Figure 10A solid-state imaging device 50b illustrating a second modification of the present embodiment will be described. The solid-state imaging device 50b of the second modification is different from the above-described first modification in that the silicon oxide layer 14 is not completely removed.

[0130] Figure 10 is a schematic view illustrating a configuration example of the solid-state imaging device 50b according to the second modification of the present embodiment. As Figure 10 indicated, in the pixel substrate 10b of the second modification, the silicon nitride layer 13u is also arranged at the leg portion of the plug 15.

[0131] In the pixel substrate 10b, the surface of the silicon oxide layer 14 including the terminal 16 has a step. In the surface of the silicon oxide layer 14, the face away from the substrate 11 side and bonded to the logic substrate 20 and the memory substrate 30 is a bonding face JS. In the surface of the silicon oxide layer 14, the face located on the substrate 11 side with respect to the surface of the silicon oxide layer 14 constituting the bonding face JS and not bonded to the logic substrate 20 or the memory substrate 30 is a non-bonding face NS.

[0132] The end face of the silicon oxide layer 14, 23, and 33 facing the silicon oxide layer 14 as the non-bonding face NS has a concave shape curved toward the inside of each layer 14, 23, and 33.

[0133] Figure 10 is a flowchart illustrating an example of a process of a cleaning process in the manufacturing process of the solid-state imaging device 50b according to the second modification of the present embodiment.

[0134] First, the cleaning process for the region where the exposed terminal 16d is not present will be described.

[0135] As Figure 10 indicated in (Aa), for example, after the logic substrate 20 is polished, there is polishing powder D such as silicon around the logic substrate 20 and the pixel substrate before singulation.

[0136] As Figure 10 indicated in (Ba), in order to remove the polishing powder D, a cleaning process is performed using a cleaning liquid such as FPM.

[0137] At this time, for example, at least one of the cleaning time, the cleaning temperature, and the concentration of the cleaning liquid, and the like is adjusted, and the cleaning process is completed by leaving the silicon oxide layer 14 of a predetermined thickness on the silicon nitride layer 13u. At this time, for the conditions of the cleaning process, the cleaning time, the cleaning temperature, and the concentration of the cleaning liquid, and the like are set to be sufficient for the terminal 16d to disappear from the surface of the silicon oxide layer 14 in the region where the exposed terminal 16d is present.

[0138] In the pixel substrate 10b of the second modification example, the silicon nitride layer 13u is arranged at the leg portion of the plug 15, and the silicon oxide layer 14 in the pixel substrate 10b is thicker than, for example, the silicon oxide layer 14 in the pixel substrate 10 of the present embodiment. Thus, it is possible to set a condition in which the terminal 16d can be made to disappear even if the silicon oxide layer 14 in the pixel substrate 10b is not completely removed.

[0139] After the cleaning process is completed, the non-bonding surface NS including the surface of the silicon oxide layer 14 newly exposed by the etching is formed.

[0140] As Figure 10 (Ca), the insulating layer 17 covering the entire logic substrate 20 and the non-bonding surface NS of the pixel substrate is formed. Here, since the silicon oxide layer 14 having a predetermined thickness is left on the silicon nitride layer 13u, the height difference between the bonding surface JS and the non-bonding surface NS is smaller than, for example, the first modification example described above. Thus, the step of the insulating layer 17 at this stage is smaller than the step in the first modification example described above.

[0141] As Figure 10 (Da), the insulating layer 17 is planarized.

[0142] Next, the cleaning process for the region in which the exposed terminal 16d exists will be described.

[0143] As Figure 11 (Ab), for example, after the logic substrate 20 is polished, the polishing powder D such as silicon exists around the logic substrate 20 and the pixel substrate before being singulated.

[0144] As Figure 12 (Bb), in order to remove the polishing powder D, the cleaning process is performed using a cleaning liquid such as FPM. For example, as described above, since at least one of the cleaning time, the cleaning temperature, and the concentration of the cleaning liquid is adjusted, the terminal 16d is completely dissolved or the silicon oxide layer 14 that is the base of the terminal 16d is etched, and the terminal 16d is separated from the silicon oxide layer 14.

[0145] After the cleaning process is completed, the terminal 16d disappears from the silicon oxide layer 14. Then, the non-bonding surface NS including the surface of the silicon oxide layer 14 newly exposed by the etching of the cleaning liquid is formed. As described above, in the configuration of the second modification example, the non-bonding surface NS includes the surface of the silicon oxide layer 14 that is substantially etched.

[0146] As Figure 11 (Cb), the insulating layer 17 covering the entire logic substrate 20 and the non-bonding surface NS of the pixel substrate is formed.

[0147] As Figure 11 (Db), the insulating layer 17 is planarized.

[0148] In this way, the cleaning process in the manufacturing process of the solid-state imaging device 50b is completed.

[0149] In the solid-state imaging device 50b of the second modification, in a region in which the terminal 16d is not exposed, the silicon oxide layer 14 having a predetermined thickness is left on the silicon nitride layer 13u. Therefore, it is possible to reduce the thickness of the insulating layer 17, and the film formation of the insulating layer 17 becomes easy. Further, it is possible to reduce the step of the insulating layer 17, and the planarization of the insulating layer 17 becomes easy.

[0150] The solid-state imaging device 50b of the second modification includes the silicon nitride layer 13u arranged at the leg portion of the plug 15. Ideally, in the method of the second modification, the silicon nitride layer 13u is not exposed. However, when there is a difference in the removal amount in the layer thickness direction of the silicon oxide layer 14, the silicon nitride layer 13u functions as a barrier layer, and it is possible to suppress the damage to the pixel circuit PIX. As described above, in the configuration of the second modification, it is possible to expand the process margin by including the silicon nitride layer 13u.

[0151] (Third Modification)

[0152] Next, the solid-state imaging device 50c of the third modification of the present embodiment will be described with reference to Figure 12 and Figure 12 The solid-state imaging device 50c of the third modification differs from the above-described first modification in that the silicon nitride layer 13t as the first insulating layer is thicker.

[0153] Figure 12 is a schematic view showing a configuration example of the solid-state imaging device 50c according to the third modification of the present embodiment. As Figure 12 indicated, the pixel substrate 10c of the third modification includes the silicon nitride layer 13t arranged at the leg portion of the plug 15. However, the silicon nitride layer 13t is formed, for example, thicker than the silicon nitride layer 13u of the above-described first and second modifications. Then, the silicon oxide layer 14 is formed thinner by a corresponding amount than the silicon oxide layer 14 of the above-described first and second modifications.

[0154] In the pixel substrate 10c, the surface of the silicon oxide layer 14 including the terminal 16 is the bonding surface JS. Further, in a region in which the silicon oxide layer 14 is not partially arranged on the silicon nitride layer 13t, at least the surface of the silicon nitride layer 13t is the non-bonding surface NS.

[0155] The end surface of the silicon oxide layer 14, 23, and 33 facing the silicon nitride layer 13t as the non-bonding surface NS has a concave shape curved toward the inside of the respective layers 14, 23, and 33.

[0156] Figure 12is a flowchart showing an example of a process of a cleaning process in the manufacturing process of the solid-state imaging device 50c according to the third modification of the embodiment of the present disclosure.

[0157] First, the cleaning process for the region in which the terminal 16d does not exist will be described.

[0158] As shown in Figure 12 As shown in (Aa), for example, after the logical substrate 20 is polished, polishing powder D such as silicon exists around the logical substrate 20 and the pixel substrate before dicing.

[0159] As shown in Figure 12 As shown in (Ba), in order to remove the polishing powder D, a cleaning process is performed using a cleaning liquid such as FPM.

[0160] At this time, for example, at least one of the cleaning time, the cleaning temperature, and the concentration of the cleaning liquid is adjusted, and the cleaning process is continued until the silicon oxide layer 14 is completely removed in the layer thickness direction. The silicon nitride layer 13t functions as a barrier layer and suppresses etching of the pixel circuit PIX and the like under the silicon nitride layer 13t.

[0161] After the cleaning process is completed, the non-bonding surface NS including the surface of the silicon nitride layer 13t exposed by etching of the silicon oxide layer 14 is formed.

[0162] As shown in Figure 12 As shown in (Ca), the insulating layer 17 covering the entire logical substrate 20 and the non-bonding surface NS of the pixel substrate is formed. Here, since the silicon nitride layer 13t is formed thicker than the silicon nitride layer 13u of the first modification, the height difference between the bonding surface JS and the non-bonding surface NS is, for example, smaller than the height difference in the above-described first modification. Therefore, the step of the insulating layer 17 at this stage is smaller than the step in the above-described first modification.

[0163] As shown in Figure 12 As shown in (Da), the insulating layer 17 is planarized.

[0164] Next, the cleaning process for the region in which the terminal 16d exists will be described.

[0165] As shown in ​ As shown in (Ab), for example, after the logical substrate 20 is polished, polishing powder D such as silicon exists around the logical substrate 20 and the pixel substrate before dicing.

[0166] As shown in ​ As shown in (Bb), in order to remove the polishing powder D, a cleaning process is performed using a cleaning liquid such as FPM. The terminal 16d is completely dissolved, or the silicon oxide layer 14 that is the base of the terminal 16d is etched, and the terminal 16d is separated from the silicon oxide layer 14.

[0167] After the cleaning process is completed, the terminal 16d disappears from the silicon oxide layer 14. Then, a non-bonding surface NS including the surface of the silicon oxide layer 14 newly exposed by the etching of the cleaning liquid and the surface of the silicon nitride layer 13t exposed by the removal of the silicon oxide layer 14 is formed. As described above, the non-bonding surface NS can include the surface of the silicon oxide layer 14 etched in a part of the region.

[0168] As shown in (Cb), the insulating layer 17 covering the entire logic substrate 20 and the non-bonding surface NS of the pixel substrate is formed. ​

[0169] As shown in (Db), the insulating layer 17 is planarized. ​

[0170] In this way, the cleaning process in the manufacturing process of the solid-state imaging element 50c is completed.

[0171] As described above, the solid-state imaging element 50c of the third modification also has the same effects as the above-described embodiments.

[0172] Further, in the solid-state imaging element 50c of the third modification, the silicon nitride layer 13t is thickened, and the silicon oxide layer 14 is formed thinner than the silicon oxide layer 14 of the first modification, for example. Therefore, it is possible to reduce the thickness of the insulating layer 17, and the film formation of the insulating layer 17 becomes easy. Further, it is possible to reduce the step of the insulating layer 17, and the planarization of the insulating layer 17 becomes easy.

[0173] [Other Embodiments]

[0174] In the above-described embodiments and the first to third modifications, the silicon nitride layers 13, 13u, and 13t, and the like are inserted as the barrier layer, but they are not limited thereto. As the barrier layer, a layer configured of a material that is dissolved at a slower speed by a chemical solution for dissolving the terminal 16d than a speed at which the silicon oxide layer 14 is dissolved can be used. Specific examples include a hydrogen-containing silicon nitride (SiNH) layer, a silicon carbon nitride (SiCN) layer, and a hydrogen-containing silicon carbon nitride (SiCNH) layer, and the like.

[0175] In the above-described embodiments and the first to third modifications, the pixel substrate before being singulated, the logic substrate that is singulated, and the storage substrate that is singulated are bonded (Chip on Wafer: Chip on Wafer), but they are not limited thereto. In the manufacturing process of the solid-state imaging element, the pixel substrate, the logic substrate, and the storage substrate can all be singulated and then bonded (Chip to Chip). Alternatively, the pixel substrate, the logic substrate, and the storage substrate can all be bonded in a state before being singulated (Wafer to Wafer).

[0176] ​​In the above embodiment and the first to third modified examples, a solid-state imaging element in which a pixel substrate, a logic substrate, and a memory substrate are bonded together is given as an example, but they are not limited thereto. The combination and the number of the substrates to be bonded are arbitrary. Specifically, examples include a combination of a pixel substrate and at least one logic substrate, a combination of a pixel substrate and at least one memory substrate, and a combination of at least one logic substrate and at least one memory substrate in addition to the combination of a pixel substrate, at least one logic substrate, and at least one memory substrate.

[0177] Note that the effects described in this specification are merely examples and are not limiting, and other effects can be included.

[0178] Further, the present technology can also have the following configuration. (1)

[0180] A semiconductor device has:

[0181] a first substrate configured to be monolithicized and having a first semiconductor circuit including a first terminal; and

[0182] a second substrate configured to have a second semiconductor circuit including a second terminal, wherein

[0183] the first terminal and the second terminal are bonded, and

[0184] the second substrate has:

[0185] a first insulating layer arranged above the second substrate; and

[0186] a second insulating layer at least partially arranged above the first insulating layer, and the second terminal is arranged in the second insulating layer. (2)

[0188] The semiconductor device according to (1), wherein

[0189] the second substrate has:

[0190] a bonding surface bonded with the first substrate; and

[0191] a non-bonding surface arranged on the second substrate side with respect to the bonding surface. (3)

[0193] The semiconductor device according to (2), wherein

[0194] the bonding surface includes the second insulating layer, and

[0195] the non-bonding surface includes at least the first insulating layer. (4)

[0197] The semiconductor device according to (2), wherein

[0198] The bonding surface and the non-bonding surface include the second insulating layer. (5)

[0200] The semiconductor device according to (2), wherein

[0201] The non-bonding surface does not have a metal member. (6)

[0203] The semiconductor device according to any one of (1) to (5), wherein

[0204] A chemical solution for dissolving the second terminal has a lower dissolution rate for the first insulating layer than a dissolution rate for the second insulating layer. (7)

[0206] The semiconductor device according to any one of (1) to (6), wherein

[0207] The first substrate has:

[0208] a third insulating layer arranged above the first substrate; and

[0209] a fourth insulating layer at least partially arranged above the third insulating layer, and the first terminal is arranged in the fourth insulating layer. (8)

[0211] The semiconductor device according to (7), wherein

[0212] The first substrate has a bonding surface bonded to the second substrate. (9)

[0214] The semiconductor device according to (8), wherein

[0215] The bonding surface of the first substrate includes the fourth insulating layer. (10)

[0217] The semiconductor device according to any one of (7) to (9), wherein

[0218] A chemical solution for dissolving the second terminal has a lower dissolution rate for the third insulating layer than a dissolution rate for the fourth insulating layer. (11)

[0220] The semiconductor device according to any one of (1) to (10), wherein

[0221] The second semiconductor circuit includes a pixel circuit. (12)

[0223] The semiconductor device according to any one of (1) to (11), wherein

[0224] The first semiconductor circuit includes a logic circuit. (13)

[0226] The semiconductor device according to any one of (1) to (11), wherein

[0227] The first semiconductor circuit includes a storage circuit. (14)

[0229] The semiconductor device according to any one of (1) to (13), wherein

[0230] An area of the second substrate is larger than an area of the first substrate. (15)

[0232] The semiconductor device according to any one of (1) to (13), wherein

[0233] The second substrate is monolithic, and

[0234] An area of the second substrate is larger than an area of the first substrate. (16)

[0236] A semiconductor device including:

[0237] a first substrate configured to be monolithic and having a first semiconductor circuit including a first terminal; and

[0238] a second substrate configured to have a second semiconductor circuit including a second terminal, wherein

[0239] the first terminal and the second terminal are joined,

[0240] the second substrate has:

[0241] a joining surface joined to the first substrate; and

[0242] a non-joining surface arranged on the second substrate side with respect to the joining surface, and

[0243] in the non-joining surface,

[0244] after joining the first terminal and the second terminal,

[0245] The first insulating layer arranged above the second substrate is a barrier layer, and a second insulating layer arranged above the first insulating layer and in which a third terminal not included in the second semiconductor circuit is arranged is processed by a chemical solution for dissolving the second terminal. (17)

[0247] The semiconductor device according to (16), in which

[0248] The second insulating layer is processed by using the chemical solution,

[0249] The third terminal disappears from the non-bonding surface. (18)

[0251] The semiconductor device according to (16) or (17), in which

[0252] The bonding surface includes the second insulating layer, and

[0253] The non-bonding surface includes at least the first insulating layer. (19)

[0255] The semiconductor device according to (16) or (17), in which

[0256] The bonding surface and the non-bonding surface include the second insulating layer. (20)

[0258] A solid-state imaging element including:

[0259] at least one of a logic substrate configured to be monolithic and having a logic circuit including a first terminal, and a memory substrate configured to be monolithic and having a memory circuit including a first terminal; and

[0260] a pixel substrate configured to have a pixel circuit including a second terminal, in which

[0261] The first terminal and the second terminal are bonded, and

[0262] The pixel substrate has:

[0263] a first insulating layer arranged above the pixel substrate; and

[0264] a second insulating layer at least partially arranged above the first insulating layer and in which the second terminal is arranged.

[0265] List of Reference Signs

[0266] 10 pixel substrate

[0267] 13, 13t, 13u silicon nitride layer

[0268] 14 silicon oxide layer

[0269] 16, 16d, 25, 35 terminal

[0270] 20 logic substrate

[0271] 30 storage substrate

[0272] 50, 50a, 50b, 50c solid-state image pickup element

[0273] JS joint surface

[0274] LOG logic circuit

[0275] MEM storage circuit

[0276] NS non-joint surface

[0277] PIX pixel circuit

Claims

1. A semiconductor device, comprising: a first substrate configured to be monolithicized and having a first semiconductor circuit including a first terminal; a first substrate configured to have a first semiconductor circuit including a first terminal, wherein the first terminal and the second terminal are joined, and the second substrate has: a first insulating layer arranged above the second substrate; and a second insulating layer at least partially arranged above the first insulating layer, and the second terminal is arranged in the second insulating layer, wherein the second terminal is covered by the first insulating layer.

2. The semiconductor device according to claim 1, wherein the second substrate has: a joining surface joined to the first substrate; and a non-joining surface arranged on a side of the second substrate with respect to the joining surface.

3. The semiconductor device according to claim 2, wherein the joining surface includes the second insulating layer; and the non-joining surface includes at least the first insulating layer.

4. The semiconductor device according to claim 2, wherein the joining surface and the non-joining surface include the second insulating layer.

5. The semiconductor device according to claim 2, wherein the non-joining surface has no metal member.

6. The semiconductor device according to any one of claims 1 to 5, wherein a dissolution speed of a chemical solution for dissolving the second terminal with respect to the first insulating layer is lower than a dissolution speed of the chemical solution with respect to the second insulating layer.

7. The semiconductor device according to any one of claims 1 to 5, wherein the first substrate has: a third insulating layer arranged above the first substrate; and a fourth insulating layer at least partially arranged above the third insulating layer, and the first terminal is arranged in the fourth insulating layer.

8. The semiconductor device according to claim 7, wherein the first substrate has a joining surface joined to the second substrate.

9. The semiconductor device according to claim 8, wherein the joining surface of the first substrate includes the fourth insulating layer.

10. The semiconductor device according to claim 7, wherein a dissolution speed of a chemical solution for dissolving the second terminal with respect to the third insulating layer is lower than a dissolution speed of the chemical solution with respect to the fourth insulating layer.

11. The semiconductor device according to any one of claims 1 to 5, wherein the second semiconductor circuit includes a pixel circuit.

12. The semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor circuit includes a logic circuit.

13. The semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor circuit includes a memory circuit.

14. The semiconductor device according to any one of claims 1 to 5, wherein an area of the second substrate is larger than an area of the first substrate.

15. The semiconductor device according to any one of claims 1 to 5, wherein the second substrate is monolithic, and an area of the second substrate is larger than an area of the first substrate.

16. A semiconductor device, comprising: a first substrate configured to have a first semiconductor circuit including a first terminal, wherein the first terminal and the second terminal are joined, and a first substrate configured to be monolithicized and having a first semiconductor circuit including a first terminal; the second substrate has: a first insulating layer arranged above the second substrate; and a second insulating layer at least partially arranged above the first insulating layer, and the second terminal is arranged in the second insulating layer, wherein the second terminal is covered by the first insulating layer. The first terminal and the second terminal are joined, The second substrate has: a joining surface joined to the first substrate; and a non-joining surface arranged on the second substrate side with respect to the joining surface, and in the non-joining surface, after joining the first terminal and the second terminal, a first insulating layer arranged above the second substrate is a barrier layer, and a second insulating layer arranged above the first insulating layer and in which a third terminal not included in the second semiconductor circuit is arranged is processed by a chemical solution for dissolving the second terminal.

17. The semiconductor device according to claim 16, wherein by processing using the chemical solution, the third terminal disappears from the non-joining surface.

18. The semiconductor device according to claim 16, wherein the joining surface includes the second insulating layer, and the non-joining surface includes at least the first insulating layer.

19. The semiconductor device according to claim 16, wherein the joining surface and the non-joining surface include the second insulating layer.

20. A solid-state imaging element comprising: at least one of a logic substrate configured to be monolithic and having a logic circuit including the first terminal, and a memory substrate configured to be monolithic and having a memory circuit including the first terminal; and a pixel substrate configured to have a pixel circuit including a second terminal, wherein the first terminal and the second terminal are joined, and the pixel substrate has: a first insulating layer arranged above the pixel substrate; and a second insulating layer at least partially arranged above the first insulating layer and in which the second terminal is arranged, wherein the second terminal is covered by the first insulating layer.

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