Drive system, drive method, computer system, and readable medium

Abstract

Provided are a driving system, a driving method, a computer system, and a computer-readable medium for automatically detecting an on-chip voltage to adjust a gate voltage of a thin-film transistor. The driving system includes: an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjustment circuit configured to automatically detect a current amplitude of the on-chip voltage output by the input circuit and output a bias voltage corresponding to the current amplitude of the on-chip voltage to a gate of the driven thin-film transistor, wherein a source of the thin-film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage. Transistor gate protection for different I / O (input / output) voltage levels and receiver threshold voltage adjustment can be accomplished by the actions of automatically detecting the on-chip voltage and automatically adjusting it.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a driving system, a driving method, a computer system, and a computer-readable medium for automatically detecting an on-chip voltage to adjust the gate voltage of a thin-film transistor. Background Art

[0002] Oxide thin-film transistors (TFTs) are an important type of semiconductor device and have extensive application value in fields such as transparent and flexible electronics devices and portable electronics device applications.

[0003] The on-chip voltage OVDD of the thin-film transistor can be 3.3V, 2.5V, or 1.8V. Therefore, the input / output driving circuit of the thin-film transistor also needs to meet the reliability constraints of the 3.3V / 2.5V / 1.8V thin-film transistor interface to adapt to different gate voltages.

[0004] If different input / output driving circuits are designed according to different input / output voltages to avoid the gate stress problem of the thin-film transistor, it not only increases the design complexity but also increases the area and power consumption, greatly increasing the cost.

[0005] Therefore, a driving circuit that can adjust the gate voltage of the thin-film transistor according to different on-chip voltages is needed. Summary of the Invention

[0006] According to one aspect of the present invention, there is provided a driving system for automatically detecting an on-chip voltage to adjust the gate voltage of a thin-film transistor, including an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; and an adjustment circuit configured to automatically detect a current amplitude of the on-chip voltage output by the input circuit and output a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the driven thin-film transistor, wherein the source of the thin-film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage.

[0007] According to another aspect of the present invention, there is provided a driving method for automatically detecting an on-chip voltage to adjust the gate voltage of a thin-film transistor, including an input step of receiving an input on-chip voltage by an input circuit and outputting the on-chip voltage; and an adjustment step of automatically detecting a current amplitude of the on-chip voltage output by the input circuit by an adjustment circuit and outputting a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the driven thin-film transistor, wherein the source of the thin-film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage.

[0008] According to another aspect of the present invention, there is provided a computer system, comprising: a processor; a memory coupled to the processor and storing computer-executable instructions therein for performing a driving method as in the embodiments of the present disclosure when executed by the processor.

[0009] According to another aspect of the present invention, there is provided a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements a driving method as in the embodiments of the present disclosure.

[0010] Thus, since the current amplitude of the on-chip voltage is detected, the on-chip voltage with a bias voltage lower than the current amplitude is obtained, thereby protecting the gate of the thin film transistor from being subjected to an inappropriate voltage amplitude, so that the current driving system can be adaptively applied and protect the gate of the thin film transistor regardless of the on-chip voltage of 3.3V, 2.5V, 1.8V or other amplitudes. Therefore, according to various embodiments of the present application, the gate protection of transistors with different I / O (input / output) voltage levels and the adjustment of the receiver threshold voltage can be completed by automatically detecting the on-chip voltage and automatically adjusting. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 A block diagram of a driving system for automatically detecting an on-chip voltage to adjust the gate voltage of a thin film transistor according to an embodiment of the present application is shown.

[0013] Figure 2 A circuit diagram of a specific example circuit structure, a driving system, a receiver circuit, and an input-output level converter including a gate stress protection circuit according to an embodiment of the present application is shown.

[0014] Figure 3 A first embodiment of a circuit structure diagram of an adjustment circuit according to an embodiment of the present application is shown.

[0015] Figure 4A A second embodiment of a circuit structure diagram of an adjustment circuit according to an embodiment of the present application is shown. Figure 4B Shows Figure 4A A graph showing the amplitude relationship between the input voltage and the output voltage of the adjustment circuit shown.

[0016] Figure 5AShows a circuit diagram of an example V / I conversion circuit according to an embodiment of the present application. Figure 5B Shows a circuit diagram of an example I / V conversion circuit according to an embodiment of the present application.

[0017] Figure 6 Shows another embodiment of a drive system according to an embodiment of the present application.

[0018] Figure 7 Shows the counter operations and input pulses in a training mode and a normal operation mode according to an embodiment of the present application.

[0019] Figure 8 Shows a flowchart of a driving method for automatically detecting an on-chip voltage to adjust the gate voltage of a thin film transistor according to an embodiment of the present application.

[0020] Figure 9 Shows a block diagram of an exemplary computer system suitable for implementing embodiments of the present invention.

[0021] Figure 10 Shows a schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure. Detailed Description

[0022] Now, specific embodiments of the present invention will be described in detail. Examples of the present invention are illustrated in the accompanying drawings. Although the present invention will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present invention to the described embodiments. On the contrary, it is intended to cover modifications, variations, and equivalents included within the spirit and scope of the present invention as defined by the appended claims. It should be noted that the method steps described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0023] Figure 1 Shows a block diagram of a drive system 100 for automatically detecting an on-chip voltage to adjust the gate voltage of a thin film transistor according to an embodiment of the present application.

[0024] The drive system 100 includes an input circuit 101 configured to receive an input on-chip voltage and output the on-chip voltage; an adjustment circuit 102 configured to automatically detect a current amplitude of the on-chip voltage output by the input circuit 101 and output a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the thin film transistor (in the gate stress protection circuit 103), wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage.

[0025] Thus, since the current amplitude of the on-chip voltage is detected, the on-chip voltage with a bias voltage lower than the current amplitude is used to protect the gate of the thin-film transistor from being subjected to an inappropriate voltage amplitude, so that the current driving system can adaptively apply and protect the gate of the thin-film transistor regardless of the on-chip voltage amplitude of 3.3V, 2.5V, 1.8V or other amplitudes. Of course, the number of thin-film transistors in the gate stress protection circuit 103 can be more than one, and the source of at least one thin-film transistor is connected to the on-chip voltage. The circuit diagram of the gate stress protection circuit 103 will be introduced later.

[0026] The adjustment circuit 102 can also change the threshold of the thin-film transistor in the receiver circuit 104 according to the detected current amplitude of the on-chip voltage. Of course, the number of thin-film transistors in the receiver circuit 104 can be more than one, and the source of at least one thin-film transistor is connected to the on-chip voltage. The circuit diagram of the receiver circuit 104 will be introduced later.

[0027] Figure 2 The circuit diagram showing a specific example circuit structure including the gate stress protection circuit 103, the driving system 100, the receiver circuit 104, and the input-output level converter 105 according to an embodiment of the present application is shown.

[0028] The adjustment circuit 102 in the driving system 100 receives the on-chip voltage input padio, i.e., OVDD, through the input circuit 101.

[0029] The gate stress protection circuit 103 includes two stacked P-channel Metal Oxide Semiconductor (PMOS) transistors and two stacked N-channel Metal Oxide Semiconductor (NMOS) transistors. Among them, the source of the first PMOS transistor P1 is connected to the on-chip voltage OVDD, its gate is connected to the output terminal of the input-output level converter 105, the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the bias voltage output, pbias, of the adjustment circuit 102. The drain of the second PMOS transistor P2 is connected to the source of the first NMOS transistor N1 through one or more resistors, and the gate of the first NMOS transistor N1 is connected to 1.8V. The drain of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2, and the gate of the second NMOS transistor N2 is connected to the output terminal of the input-output level converter 105. The drain of the second NMOS transistor N2 is grounded.

[0030] The input-output level converter 105 receives the core input drive enable signal coreinput Drv_en and outputs a converted voltage to facilitate inputting a suitable voltage to the gates of the first PMOS transistor P1 and the second NMOS transistor N2 of the gate stress protection circuit 103.

[0031] The adjustment circuit 102 in the drive system 100 can also change the threshold values of one or more thin film transistors in the receiver circuit 104 by outputting a threshold control signal Vth_ctrl according to the currently detected amplitude of the on-chip voltage, so that the threshold values of the thin film transistors change following the change of the amplitude of the on-chip voltage to ensure the normal conduction and cutoff of the thin film transistors. The receiver circuit 104 receives the on-chip voltage padio.

[0032] The following introduces the specific circuit embodiments of two examples of the adjustment circuit 102. Of course, under the teaching and inspiration of this application, the adjustment circuit 102 can be designed to include other circuit structures to achieve the purpose of adjustment.

[0033] Figure 3 The first embodiment of the circuit structure diagram of the adjustment circuit 102 according to an embodiment of the present application is shown.

[0034] The adjustment circuit 102 includes: a reference voltage generator 301 configured to output a plurality of reference voltages related to N optional amplitudes of the on-chip voltage; a plurality of comparators (cmp) 302, each configured to compare the on-chip voltage output by the input circuit 101 with a corresponding one of the reference voltages and output a comparison result; a decision maker 303 configured to determine, based on the comparison results of the plurality of comparators 302, a mode related to the current amplitude of the on-chip voltage output by the input circuit 101 from N modes related to N optional amplitudes of the on-chip voltage, and output a bias voltage corresponding to the mode to the gate of the driven thin film transistor, wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage, where N is a positive integer greater than 1.

[0035] That is to say, by comparing the on-chip voltage with a plurality of reference voltages, the approximate range of the on-chip voltage can be determined, so as to determine which of the optional amplitudes such as 3.3V, 2.5V, and 1.8V the on-chip voltage is.

[0036] The values of the respective reference voltages can be determined based on various optional amplitude values of the on-chip voltage. In one embodiment, the amplitude of each of the plurality of reference voltages can be the intermediate voltage between two adjacent optional amplitudes among the N optional amplitudes.

[0037] For example, when the on-chip voltage is an optional amplitude of 3.3V, 2.5V, or 1.8V, there can be two reference voltages: (3.3 + 2.5) / 2 = 2.9V, (2.5 + 1.8) / 2 = 2.15V. Therefore, if comparator 302 determines that the received on-chip voltage is greater than 2.9V, decision maker 303 determines that the current amplitude of the on-chip voltage is 3.3V. If comparator 302 determines that the on-chip voltage is less than 2.9V but greater than 2.15V, decision maker 303 determines that the currently received on-chip voltage is 2.5V. If comparator 302 determines that the received on-chip voltage is less than 2.15V, decision maker 303 determines that the current amplitude of the on-chip voltage is 1.8V.

[0038] In addition, in one embodiment, the input circuit 101 includes an averaging circuit configured to average the on-chip voltage and output the averaged on-chip voltage. Here, if the input on-chip voltage is a periodic wave with a maximum amplitude of 3.3V, 2.5V, or 1.8V, the averaging circuit is used to average the on-chip voltage, and a stable level can be obtained for comparison with each reference voltage. The averaged on-chip voltages corresponding to the periodic waves of 3.3V, 2.5V, or 1.8V are theoretically 1.65V, 1.25V, and 0.9V, for example. There can be two reference voltages: (1.65 + 1.25) / 2 = 1.45V, (1.25 + 0.9) / 2 = 1.075V. Therefore, if the comparator determines that the received averaged on-chip voltage is greater than 1.45V, the decision maker determines that the current amplitude of the on-chip voltage is 3.3V. If the comparator determines that the received averaged on-chip voltage is less than 1.45V but greater than 1.075V, the decision maker determines that the current amplitude of the on-chip voltage is 2.5V. If the comparator determines that the received averaged on-chip voltage is less than 1.075V, the decision maker determines that the current amplitude of the on-chip voltage is 1.8V.

[0039] Of course, the magnitudes and quantities of the above reference voltages are merely examples. Taking the average value between the two voltages to be judged as the reference voltage can eliminate the judgment errors caused by the fluctuations or errors in the levels of the two voltages. Of course, the magnitude of the reference voltage can vary as long as it can correctly judge the voltages of two different levels with an appropriate accuracy. Additionally, the above example illustrates using 2 reference voltages to judge the magnitudes of 3 voltages. However, in practice, other quantities of reference voltages can also be used. For example, for 3 reference voltages, in an example where the on-chip voltage after averaging is a theoretical value such as 1.65V, 1.25V, and 0.9V, reference voltages of 1.6V, 1.2V, and 0.8V can be adopted. For example, if it is judged that the received averaged on-chip voltage is greater than 1.6V, the decision maker determines that the current magnitude of the on-chip voltage is 3.3V. If it is judged that the received averaged on-chip voltage is less than 1.6V and greater than 1.2V, the decision maker determines that the current magnitude of the on-chip voltage is 2.5V. If it is judged that the received averaged on-chip voltage is less than 1.2V and greater than 0.8V, the decision maker determines that the current magnitude of the on-chip voltage is 1.8V. Of course, if it is judged that the received averaged on-chip voltage is less than 0.8V, the decision maker can ignore the comparison result or determine that there is no on-chip voltage input, only errors or disturbances exist. There are many examples of the magnitudes and quantities of reference voltages, which will not be elaborated one by one here.

[0040] In one embodiment, the averaging circuit for averaging the on-chip voltage includes at least one capacitor and at least one resistor. As Figure 3 shown, the figure shows using a grounded capacitor (with a capacitance value C) and a resistor (with a resistance value R) not shown (such as the resistance of the wire itself or a separate resistor, etc.) to form an RC oscillator as the averaging circuit for averaging. Here, the capacitance value C of the capacitor and the resistance value R are selected such that the frequency of the RC oscillator is basically the same as or matches the frequency of the periodic wave of the input on-chip voltage, so that the RC oscillation cancels out the period of the on-chip voltage, and the averaging circuit outputs a voltage level that is as stable as possible. The larger the capacitance value, the slower the oscillation frequency; the smaller the capacitance value, the faster the oscillation frequency. For example, the capacitance value C is taken as 1 - 5F (farad), although the capacitance value is not limited to this. Additionally, other circuits can also be adopted for the averaging circuit, such as a rectifying circuit, an integrating circuit, etc., as long as the averaging circuit can output a voltage level that is as stable as possible, which will not be elaborated one by one here.

[0041] To implement the above comparison and decision-making more simply, a digital rather than an analog approach can be adopted. A series of digital signals, such as 0 or 1, are obtained through the above comparison. Specifically, each of the multiple comparators outputs a first value, such as binary 1, when the on-chip voltage is greater than a corresponding reference voltage, and outputs a second value, such as binary 0, when the on-chip voltage is less than or equal to a corresponding reference voltage, where each of the N modes corresponds to one of the multiple possible codes composed of the first value and the second value. That is, after the comparison, a string composed of, for example, 0 and 1 can be obtained. Since different magnitudes of on-chip voltages will result in completely different strings composed of 0 and 1 after passing through multiple comparators, different modes can be determined through the differences in such strings.

[0042] Specifically, the output result is a result code composed of the first values and the second values output by multiple comparators, and the decision maker is configured to determine the mode corresponding to the result code from the N modes according to the result code. In the case where, for example, the first value is binary 1 and the second value is binary 0, for example, in the case of using 3 reference voltages, the mode corresponding to 3.3V corresponds to the result code 1, 1, 1 because 3.3V is greater than the 3 reference voltages, the mode corresponding to 2.5V corresponds to the result code 0, 1, 1 because 2.5V is greater than 2 of the 3 reference voltages and less than the largest reference voltage, and the mode corresponding to 1.8V corresponds to the result code 0, 0, 1 because 1.8V is greater than 1 of the 3 reference voltages and less than the largest 2 reference voltages.

[0043] Of course, the above example illustrates 3 optional magnitudes of on-chip voltages, 3 reference voltages, 3 comparators, and a 3-bit result code. However, in practice, the number of reference voltages and the number of bits of the result code can be selected according to the number of optional magnitudes of on-chip voltages. Or, 3 optional magnitudes of on-chip voltages can correspond to 2 reference voltages, 2 comparators, and a 2-bit result code. For example, the mode corresponding to 3.3V corresponds to the result code 1, 1 because 3.3V is greater than the 2 reference voltages, the mode corresponding to 2.5V corresponds to the result code 0, 1 because 2.5V is greater than 1 of the 2 reference voltages and less than the largest reference voltage, and the mode corresponding to 1.8V corresponds to the result code 0, 0 because 1.8V is less than the 2 reference voltages. Three voltage magnitudes can also be distinguished through such comparison. Here, all embodiments are not exhausted, but all embodiments that conform to the principle of this application and can achieve the effects of this application are understood to be included in this application.

[0044] In one embodiment, the reference voltage generator 301 is a bandgap reference power supply (abbreviated as BG), the comparator is an analog-to-digital converter (ADC), and the decision maker is a digital-to-analog converter (DAC). That is, a plurality of reference voltages are generated by a conventional bandgap reference power supply. The comparator can convert the comparison result into a binary number of 0 or 1, and the decision maker converts these binary numbers into a bias voltage corresponding to the mode corresponding to these binary numbers.

[0045] Examples of the bias voltage can be: when the amplitude of the on-chip voltage is 1.8V, the bias voltage is set to 0V; when the amplitude of the on-chip voltage is 2.5V, the bias voltage is set to one-fourth of the on-chip voltage (i.e., 0.625V); when the amplitude of the on-chip voltage is 3.3V, the bias voltage is set to one-third of the on-chip voltage (i.e., 1.1V). Of course, the above only gives examples of the bias voltage, but the present application is not limited thereto. In fact, other bias voltages are also feasible. For example, different bias voltage ratios or fixed different bias voltages corresponding to different on-chip voltages can be given according to the detection result of the on-chip voltage, or the same ratio or fixed value can be set to be applied to the detection results of different on-chip voltages. These adjusted bias voltages depend on the foundry process to avoid gate stress at the output driver.

[0046] Figure 4A A second embodiment of the circuit structure diagram of the adjustment circuit 102' according to an embodiment of the present application is shown. Figure 4B is shown Figure 4A a graph showing the amplitude relationship between the input voltage and the output voltage of the shown adjustment circuit 102'. As Figure 4B shown, for example, the bias voltage Pbias is set to one-third of the input voltage OVDD. That is, when OVDD is 3.3V, the bias voltage Pbias is 1.1V. When OVDD is 1.8V, the bias voltage Pbias is 0.6V, and so on. Of course Figure 4B the shown is a linear relationship, but in fact, the present application is not limited thereto, and other amplitude relationships between the input voltage and the output voltage can also be adopted.

[0047] The adjustment circuit 102' is a V / I and I / V conversion circuit, configured to output a corresponding bias voltage based on the on-chip voltage output by the input circuit 101 according to the input-output relationship between the on-chip voltage and the bias voltage.

[0048] In one embodiment, the V / I and I / V conversion circuit includes: a V / I conversion circuit 4021 configured to convert an input on-chip voltage into a current signal; an I / V conversion circuit 4022 configured to convert the current signal into a corresponding bias voltage.

[0049] As is well known, the V / I and I / V conversion circuit can achieve voltage boosting or reduction. If the input on-chip voltage is converted into a lower output bias voltage, for example, in the previous example, when the amplitude of the on-chip voltage is 1.8V, the bias voltage is set to 0V, when the amplitude of the on-chip voltage is 2.5V, the bias voltage is set to one-fourth of the on-chip voltage, and when the amplitude of the on-chip voltage is 3.3V, the bias voltage is set to one-third of the on-chip voltage. Or, regardless of the amplitude of the on-chip voltage, the input on-chip voltage is reduced to one-fourth, or one-third or other values of the on-chip voltage.

[0050] Figure 5A The circuit diagram of an exemplary V / I conversion circuit 4021 according to an embodiment of the present application is shown. Figure 5B The circuit diagram of an exemplary I / V conversion circuit 4022 according to an embodiment of the present application is shown.

[0051] It can be known that by setting the resistance values of the respective resistors, the V / I conversion circuit 4021 can convert the input voltage into an output current, and this output current is input to the I / V conversion circuit 4022, thereby converting the current into an output voltage. Here, any input voltage can be converted into any output voltage. Here, the specific values of the respective resistors, capacitors, etc. are not elaborated in detail to simplify the description. In fact, those skilled in the art can set the specific values of the respective resistors, capacitors, etc. to achieve the conversion of any input voltage into any output voltage. Of course, the circuit diagrams of the above conversion circuits are only examples. In fact, through combinations of operational amplifiers, capacitors, and resistors, etc., more conversion circuits can be realized. Moreover, the values of the above bias voltages are also examples. In fact, in order to protect the gates of the thin film transistors, other values of bias voltages can also be set and the corresponding V / I and I / V conversion circuits can be designed.

[0052] Figure 6 Another embodiment of the drive system 100 according to an embodiment of the present application is shown.

[0053] In this embodiment, the drive system 100 further includes: a threshold decoder 601 configured to set the gates of some thin film transistors in the receiver to threshold voltages corresponding to the detected mode based on the detected mode, wherein the gate voltages of some other thin film transistors in the receiver are the on-chip voltage.

[0054] In one embodiment, the threshold voltage for the on-chip voltage with an amplitude of 1.8V is set to 0.9V, the threshold voltage for the on-chip voltage with an amplitude of 2.5V is set to 1.25V, and the threshold voltage for the on-chip voltage with an amplitude of 3.3V is set to 1.65V. Of course, the values of the threshold voltage are only examples. In fact, in order to ensure that for on-chip voltages with different amplitudes, the threshold voltage of the transistor is set to an appropriate value so that the transistor can conduct and cut off normally.

[0055] Due to the different amplitudes of the on-chip voltage, the threshold voltages of the transistors in the receiver should also be different accordingly. Otherwise, it may be impossible to drive the transistor to conduct normally, or there may be over-driving, etc. Of course Figure 6 The circuit diagram of the receiver shown is only an example. In fact, other circuit diagrams are also feasible as long as the threshold voltages involved can be set by the threshold decoder 601 to be different corresponding to the different amplitudes of the on-chip voltage.

[0056] In order to output a preset bias voltage or a preset threshold voltage based on the preset amplitude of the on-chip voltage output by the input circuit 101, a training operation can be performed in advance before the normal adjustment operation. In one embodiment, the driving system includes a switch group configured to connect a preset on-chip voltage (e.g., 3.3V, 2.5V, or 1.8V) during the training period and disconnect the coupling with the thin-film transistors P2 and N1 so that the thin-film transistors P2 and N1 are cut off. For example, the gate of the transistor P2 is disconnected from the bias voltage pbias and connected to OVDD, and the gate of the transistor N1 is disconnected from the 1.8V voltage. The training is to output a preset bias voltage (e.g., one-third of the on-chip voltage (i.e., 1.1V), one-fourth of the on-chip voltage (i.e., 0.625V)), 0V, or other preset threshold voltages based on the preset amplitude of the on-chip voltage output by the input circuit 101.

[0057] Here, the training can include adjusting the levels of the respective reference voltages generated by, for example, the reference voltage generator 301 (such as a bandgap reference power supply) in the first embodiment of the adjustment circuit so that the corresponding mode can be correctly obtained by comparing with the reference voltage to obtain the corresponding bias voltage, or adjusting the values of the resistors in the V / I conversion circuit and the I / V conversion circuit in, for example, the second embodiment of the adjustment circuit so that the corresponding output bias voltage can be obtained from the input on-chip voltage.

[0058] Thus, after being trained and adjusted, the switch group is configured to connect the coupling with the thin film transistor during the normal operation period. For example, the gate of transistor N2 is connected to pbias, and the gate of transistor P1 is connected to a 1.8V voltage. Thus, the amplitude of the current on-chip voltage is normally detected, and the corresponding bias voltage and threshold voltage are output.

[0059] Different circuit structures of the threshold decoder 601 can be designed to implement the above operation of setting the corresponding threshold voltage based on the detected mode, and examples are not given one by one here.

[0060] For an example circuit structure of the receiver circuit 104, reference can be made to Figure 6 . The receiver circuit 104 includes, for example, 4 PMOS transistors and 4 NMOS transistors. Among them, the sources and drains of 2 PMOS transistors and 2 NMOS transistors are connected end to end. That is, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the source of the first NMOS transistor, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor is connected to the ground. The input on-chip voltage padio, that is, the input OVDD, is connected to the gates of two PMOS transistors and two NMOS transistors of the receiver circuit 104. The threshold voltage output by the threshold decoder 601 is input to the gates of two first PMOS transistors and two second NOMS transistors. The purpose is to control the threshold voltages of these transistors to match the gate voltages (padio or on-chip voltage OVDD) of other transistors, so that the transistors conduct normally when the voltage between the source and the gate exceeds the threshold voltage and cut off normally when it is lower than the threshold voltage.

[0061] Figure 6 The circuit structure diagram of the receiver circuit 104 shown in [] is only an example. In fact, other circuit structures are also feasible as long as the threshold decoder 601 outputs an appropriate threshold voltage to it. In addition, Figure 6 it is shown that the threshold decoder 601 is a separate device outside the adjustment circuit 102, but this is only an example. In fact, the threshold decoder 601 can also be designed inside the adjustment circuit 102 as part of the adjustment circuit, and no limitation is made here.

[0062] Figure 7 Shows the counter operation and input pulses in the training mode and normal operation mode according to an embodiment of the present application.

[0063] In this embodiment, the training period can be controlled by a counter. During the counting of the counter, a series of training mode pulses with alternating low and high levels (e.g., 010101...) are generated, so that the on-chip voltage received by the input circuit 101 is a periodic wave. Among them, when the signal Train_b takes the value of 1, it indicates that this series of training mode pulses (e.g., 010101...) are connected to an averaging circuit (such as an RC oscillator) for averaging. The frequency of this periodic wave is, for example, 100 MHz. Of course, the present application is not limited to this. And when the counting of the counter ends, the training mode pulses become low level, indicating the start of the normal operation period. Of course, this counter, as well as a series of training mode pulses with alternating low and high levels and the low level, etc. are all examples, and other methods can also be used to control the training period and the normal operation period, such as a timer, etc.

[0064] Here, using input pulses to guide the training mode and the normal operation mode can automatically perform the timing of training and normal operation. Of course, other methods can also be used to guide the training mode and the normal operation mode, such as triggering different modes with different indication signals, etc.

[0065] Therefore, according to various embodiments of the present application, the transistor gate protection for different I / O (input / output) voltage levels and the receiver threshold voltage adjustment can be completed through the actions of automatically detecting the on-chip voltage and automatically adjusting it.

[0066] Figure 8 A flowchart of a driving method 800 for automatically detecting the on-chip voltage to adjust the gate voltage of a thin-film transistor according to an embodiment of the present application is shown.

[0067] This driving method 800 includes: an input step 801, where the input circuit receives the input on-chip voltage and outputs the on-chip voltage; an adjustment step 802, where the adjustment circuit automatically detects the current amplitude of the on-chip voltage output by the input circuit, and outputs a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the driven thin-film transistor, where the source of the thin-film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage.

[0068] In one embodiment, the adjustment step 802 includes: outputting, by a reference voltage generator, a plurality of reference voltages related to N optional amplitudes of the on-chip voltage; comparing, by a plurality of comparators, the on-chip voltage output by the input circuit with a corresponding one of the reference voltages, and outputting a comparison result; determining, by a decision maker, a mode related to the current amplitude of the on-chip voltage output by the input circuit from N modes related to the N optional amplitudes of the on-chip voltage based on the comparison results of the plurality of comparators, and outputting, according to the detected mode, a bias voltage corresponding to the mode to the gate of the driven thin film transistor, wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage, where N is a positive integer greater than 1.

[0069] In one embodiment, the amplitude of each of the plurality of reference voltages is an intermediate voltage between two adjacent optional amplitudes among the N optional amplitudes. The step of comparing, by a plurality of comparators, the on-chip voltage output by the input circuit with a corresponding one of the reference voltages and outputting a comparison result includes: each of the plurality of comparators outputs a first value when the on-chip voltage is greater than a corresponding one of the reference voltages, and outputs a second value when the on-chip voltage is less than or equal to a corresponding one of the reference voltages, where each of the N modes corresponds to one of a plurality of possible codes composed of the first value and the second value; and the output result is a result code composed of the first values output by the plurality of comparators and the second values output. The step of determining, by a decision maker, the mode based on the comparison results of the plurality of comparators includes: the decision maker determines the mode corresponding to the result code from the N modes according to the result code.

[0070] In one embodiment, the reference voltage generator is a bandgap reference power supply, the first value is binary 1, the second value is binary 0, the comparator is an analog-to-digital converter, and the decision maker is a digital-to-analog converter.

[0071] In one embodiment, when the amplitude of the on-chip voltage is 1.8V, the bias voltage is set to 0V; when the amplitude of the on-chip voltage is 2.5V, the bias voltage is set to one quarter of the on-chip voltage; when the amplitude of the on-chip voltage is 3.3V, the bias voltage is set to one third of the on-chip voltage.

[0072] In one embodiment, the adjustment step 802 includes: outputting, by a V / I and I / V conversion circuit, a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage.

[0073] In one embodiment, the step of outputting a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage by the V / I and I / V conversion circuits includes: converting the input on-chip voltage into a current signal by the V / I conversion circuit; converting the current signal into a corresponding bias voltage by the I / V conversion circuit.

[0074] In one embodiment, the bias voltage is set to one-third of the on-chip voltage.

[0075] In one embodiment, the input step 801 includes averaging the on-chip voltage by using an averaging circuit and outputting the averaged on-chip voltage.

[0076] In one embodiment, the averaging circuit includes at least one capacitor and at least one resistor.

[0077] In one embodiment, the method further includes: setting the gates of some thin-film transistors in the receiver to threshold voltages corresponding to the detected mode by a threshold decoder, wherein the gate voltages of some other thin-film transistors in the receiver are the on-chip voltage.

[0078] In one embodiment, the threshold voltage for the on-chip voltage with an amplitude of 1.8V is set to 0.9V, the threshold voltage for the on-chip voltage with an amplitude of 2.5V is set to 1.25V, and the threshold voltage for the on-chip voltage with an amplitude of 3.3V is set to 1.65V.

[0079] In one embodiment, the driving method further includes turning on the on-chip voltage and disconnecting the coupling with the thin-film transistors by a switch group during the training period so that the thin-film transistors are turned off, wherein the training is for outputting a preset bias voltage or a preset threshold voltage based on a preset amplitude of the on-chip voltage output by the input circuit, and turning on the coupling with the thin-film transistors by the switch group during the normal operation period.

[0080] In one embodiment, the training period is controlled by a counter, and during the counting of the counter, a string of training mode pulses with low and high levels alternating is generated so that the on-chip voltage received by the input circuit is a periodic wave, and at the end of the counting of the counter, the training mode pulses become low level, indicating the start of the normal operation period.

[0081] Therefore, according to various embodiments of the present application, the transistor gate protection for different I / O (input / output) voltage levels and the receiver threshold voltage adjustment can be completed through the actions of automatically detecting the on-chip voltage and automatically adjusting.

[0082] Figure 9A block diagram of an exemplary computer system suitable for implementing embodiments of the present invention is shown.

[0083] The computer system may include a processor H1; a memory H2, coupled to the processor H1 and storing computer-executable instructions therein for performing the steps of the various methods of the embodiments of the present invention when executed by the processor.

[0084] The processor H1 may include, but is not limited to, for example, one or more processors or microprocessors, etc.

[0085] The memory H2 may include, but is not limited to, for example, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (such as hard disks, floppy disks, solid state drives, removable disks, CD-ROMs, DVD-ROMs, Blu-ray discs, etc.).

[0086] In addition, the computer system may further include a data bus H3, an input / output (I / O) bus H4, a display H5, and input / output devices H6 (such as, for example, a keyboard, a mouse, a speaker, etc.).

[0087] The processor H1 may communicate with external devices H5, H6, etc. via the I / O bus H4 through a wired or wireless network (not shown).

[0088] The memory H2 may also store at least one computer-executable instruction for performing the steps of the various functions and / or methods in the embodiments described in this technology when run by the processor (H1).

[0089] In one embodiment, the at least one computer-executable instruction may also be compiled into or constitute a software product, wherein when the one or more computer-executable instructions are run by the processor, the steps of the various functions and / or methods in the embodiments described in this technology are performed.

[0090] Figure 10 A schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure is shown.

[0091] As Figure 10As shown, instructions are stored on the computer-readable storage medium 1020, such as the computer-readable instructions 1010. When the computer-readable instructions 1010 are run by a processor, the driving method described with reference to the above figures can be executed. The computer-readable storage medium includes but is not limited to, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. For example, the computer-readable storage medium 1020 may be connected to a computing device such as a computer. Then, when the computing device runs the computer-readable instructions 1010 stored on the computer-readable storage medium 1020, the driving method as described above can be performed.

[0092] The present application provides the following aspects:

[0093] Aspect 1. A driving system for automatically detecting an on-chip voltage to adjust the gate voltage of a thin film transistor, comprising

[0094] an input circuit configured to receive an input on-chip voltage and output the on-chip voltage;

[0095] an adjustment circuit configured to automatically detect a current amplitude of the on-chip voltage output by the input circuit and output a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the driven thin film transistor, wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage.

[0096] Aspect 2. The system according to aspect 1, wherein the adjustment circuit includes:

[0097] a reference voltage generator configured to output a plurality of reference voltages related to N optional amplitudes of the on-chip voltage;

[0098] a plurality of comparators, each configured to compare the on-chip voltage output by the input circuit with a corresponding one of the reference voltages and output a comparison result;

[0099] a decision maker configured to determine, based on the comparison results of the plurality of comparators, a mode related to the current amplitude of the on-chip voltage output by the input circuit from N modes related to N optional amplitudes of the on-chip voltage, and output a bias voltage corresponding to the mode to the gate of the driven thin film transistor,

[0100] wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, the bias voltage is lower than the on-chip voltage, and N is a positive integer greater than 1.

[0101] Aspect 3. The system according to Aspect 2, wherein the magnitude of each of the plurality of reference voltages is an intermediate voltage between two adjacent selectable magnitudes among the N selectable magnitudes.

[0102] Each of the plurality of comparators outputs a first value when the on-chip voltage is greater than a corresponding one of the reference voltages, and outputs a second value when the on-chip voltage is less than or equal to a corresponding one of the reference voltages, wherein each of the N modes corresponds to one of a plurality of possible codes composed of the first value and the second value.

[0103] The output result is a result code composed of the first values output by the plurality of comparators and the second values output.

[0104] The decision maker is configured to determine, according to the result code, the mode corresponding to the result code from the N modes.

[0105] Aspect 4. The system according to Aspect 3, wherein the reference voltage generator is a bandgap reference power supply, the first value is binary 1, the second value is binary 0, the comparator is an analog-to-digital converter, and the decision maker is a digital-to-analog converter.

[0106] Aspect 5. The system according to Aspect 1, wherein when the magnitude of the on-chip voltage is 1.8V, the bias voltage is set to 0V; when the magnitude of the on-chip voltage is 2.5V, the bias voltage is set to one-fourth of the on-chip voltage; when the magnitude of the on-chip voltage is 3.3V, the bias voltage is set to one-third of the on-chip voltage.

[0107] Aspect 6. The system according to Aspect 1, wherein the adjustment circuit includes:

[0108] A V / I and I / V conversion circuit configured to output a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage.

[0109] Aspect 7. The system according to Aspect 6, wherein the V / I and I / V conversion circuit includes:

[0110] A V / I conversion circuit configured to convert the input on-chip voltage into a current signal;

[0111] An I / V conversion circuit configured to convert the current signal into a corresponding bias voltage.

[0112] Aspect 8. The system according to Aspect 1, wherein the adjustment circuit includes:

[0113] A plurality of resistors for dividing the input on-chip voltage.

[0114] Aspect 9. The system according to aspect 1, wherein the bias voltage is set to one third of the on-chip voltage.

[0115] Aspect 10. The system according to aspect 1, wherein the input circuit includes an averaging circuit configured to average the on-chip voltage and output the averaged on-chip voltage.

[0116] Aspect 11. The system according to aspect 10, wherein the averaging circuit includes at least one capacitor and at least one resistor.

[0117] Aspect 12. The system according to aspect 1, wherein the adjustment circuit further includes: a threshold decoder configured to set the gates of some thin film transistors in the receiver to a threshold voltage corresponding to the detected pattern based on the detected pattern, wherein the gate voltages of some other thin film transistors in the receiver are the on-chip voltage.

[0118] Aspect 13. The system according to aspect 12, wherein for the on-chip voltage with an amplitude of 1.8V, the threshold voltage is set to 0.9V, for the on-chip voltage with an amplitude of 2.5V, the threshold voltage is set to 1.25V, and for the on-chip voltage with an amplitude of 3.3V, the threshold voltage is set to 1.65V.

[0119] Aspect 14. The system according to aspect 1 or 13, wherein the driving system includes a switch group configured to turn on the on-chip voltage and disconnect the coupling with the thin film transistors during a training period so that the thin film transistors are turned off, wherein the training is for outputting a preset bias voltage or a preset threshold voltage based on a preset amplitude of the on-chip voltage output by the input circuit, and the switch group is configured to connect the coupling with the thin film transistors during a normal operation period.

[0120] Aspect 15. The system according to aspect 14, wherein the training period is controlled by a counter, and during the counting of the counter, a series of training mode pulses with low and high levels alternating are generated so that the on-chip voltage received by the input circuit is a periodic wave.

[0121] And at the end of the counting of the counter, the training mode pulse becomes low level, indicating the start of the normal operation period.

[0122] Aspect 16. A driving method for automatically detecting an on-chip voltage to adjust the gate voltage of a thin film transistor, including

[0123] An input step of receiving an input on-chip voltage by an input circuit and outputting the on-chip voltage;

[0124] Adjustment step, automatically detected by an adjustment circuit the current amplitude of the on-chip voltage output by the input circuit, and outputs a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the driven thin film transistor, wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage.

[0125] Aspect 17. The method according to aspect 16, wherein the adjustment step includes:

[0126] Output by a reference voltage generator a plurality of reference voltages related to N selectable amplitudes of the on-chip voltage;

[0127] Compare the on-chip voltage output by the input circuit with a corresponding one of the reference voltages by a plurality of comparators, and output a comparison result;

[0128] Determine by a decision maker, based on the comparison results of the plurality of comparators, a mode related to the current amplitude of the on-chip voltage output by the input circuit from N modes related to N selectable amplitudes of the on-chip voltage, and according to the detected mode, output a bias voltage corresponding to the mode to the gate of the driven thin film transistor,

[0129] wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, the bias voltage is lower than the on-chip voltage, and N is a positive integer greater than 1.

[0130] Aspect 18. The method according to aspect 17, wherein the amplitude of each of the plurality of reference voltages is an intermediate voltage between two adjacent selectable amplitudes among the N selectable amplitudes,

[0131] The step of comparing the on-chip voltage output by the input circuit with a corresponding one of the reference voltages by a plurality of comparators, and outputting a comparison result includes:

[0132] Each of the plurality of comparators outputs a first value when the on-chip voltage is greater than a corresponding one of the reference voltages, and outputs a second value when the on-chip voltage is less than or equal to a corresponding one of the reference voltages, wherein each of the N modes corresponds to one of a plurality of possible codes composed of the first value and the second value;

[0133] wherein the output result is a result code composed of the first value output by the plurality of comparators and the second value output;

[0134] The step of determining the mode by the decision maker based on the comparison results of the plurality of comparators includes:

[0135] Determine by the decision maker the mode corresponding to the result code from the N modes according to the result code.

[0136] Aspect 19. The method according to Aspect 18, wherein the reference voltage generator is a bandgap reference power supply, the first value is binary 1, the second value is binary 0, the comparator is an analog-to-digital converter, and the decision maker is a digital-to-analog converter.

[0137] Aspect 20. The method according to Aspect 16, wherein when the amplitude of the on-chip voltage is 1.8V, the bias voltage is set to 0V; when the amplitude of the on-chip voltage is 2.5V, the bias voltage is set to one-fourth of the on-chip voltage; and when the amplitude of the on-chip voltage is 3.3V, the bias voltage is set to one-third of the on-chip voltage.

[0138] Aspect 21. The method according to Aspect 16, wherein the adjusting step includes:

[0139] Outputting a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage by a V / I and I / V conversion circuit.

[0140] Aspect 22. The method according to Aspect 21, wherein the step of outputting a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage by a V / I and I / V conversion circuit includes:

[0141] Converting the input on-chip voltage into a current signal by a V / I conversion circuit;

[0142] Converting the current signal into a corresponding bias voltage by an I / V conversion circuit.

[0143] Aspect 23. The method according to Aspect 16, wherein the bias voltage is set to one-third of the on-chip voltage.

[0144] Aspect 24. The method according to Aspect 16, wherein the input step includes averaging the on-chip voltage by using an averaging circuit and outputting the averaged on-chip voltage.

[0145] Aspect 25. The method according to Aspect 24, wherein the averaging circuit includes at least one capacitor and at least one resistor.

[0146] Aspect 26. The method according to Aspect 16, wherein the method further includes: setting the gates of some thin film transistors in the receiver to threshold voltages corresponding to the detected pattern by a threshold decoder, wherein the gate voltages of some other thin film transistors in the receiver are the on-chip voltage.

[0147] Aspect 27. The system according to aspect 26, wherein the threshold voltage for the on-chip voltage with an amplitude of 1.8V is set to 0.9V, the threshold voltage for the on-chip voltage with an amplitude of 2.5V is set to 1.25V, and the threshold voltage for the on-chip voltage with an amplitude of 3.3V is set to 1.65V.

[0148] Aspect 28. The method according to any one of the foregoing aspects, wherein the method further comprises turning on the on-chip voltage and disconnecting the coupling with the thin-film transistor during a training period by a switch group such that the thin-film transistor is turned off, wherein the training is for outputting a preset bias voltage or a preset threshold voltage based on a preset amplitude of the on-chip voltage output by the input circuit, and turning on the coupling with the thin-film transistor by the switch group during a normal operation period.

[0149] Aspect 29. The method according to aspect 28, wherein the training period is controlled by a counter, and during the counting of the counter, a string of training mode pulses with low and high levels alternating is generated such that the on-chip voltage received by the input circuit is a periodic wave,

[0150] and at the end of the counting of the counter, the training mode pulse becomes low level, indicating the start of the normal operation period.

[0151] Aspect 30. A computer system, comprising:

[0152] A processor;

[0153] A memory, coupled to the processor, and storing computer-executable instructions therein for performing the driving method according to any one of aspects 16-29 when executed by the processor.

[0154] Aspect 31. A computer-readable medium, having a computer program stored thereon, wherein the program, when executed by a processor, implements the driving method according to any one of aspects 16-29.

[0155] Of course, the above specific embodiments are merely examples and not limitations, and those skilled in the art can combine and combine some steps and devices from the above separately described embodiments according to the concept of the present invention to achieve the effects of the present invention, and such combined embodiments are also included in the present invention, and such combinations are not described one by one herein.

[0156] Note that the advantages, advantages, effects, etc. mentioned in this disclosure are merely examples and not limitations, and it cannot be considered that these advantages, advantages, effects, etc. are essential for each embodiment of the present invention. Additionally, the above-disclosed specific details are only for the purposes of illustration and facilitating understanding, rather than limitations, and the above details do not limit the present invention to necessarily adopt the above specific details to implement.

[0157] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The words "or" and "and" used herein refer to the word "and / or" and can be used interchangeably with it, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with it.

[0158] The step flowcharts in this disclosure and the above method descriptions are only illustrative examples and are not intended to require or imply that the steps of each embodiment must be carried out in the order given. As those skilled in the art will recognize, the steps in the above embodiments can be carried out in any order. Words such as "subsequently", "then", "next", etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. In addition, any reference to a singular element using articles such as "a", "an", or "the" is not to be construed as limiting that element to the singular.

[0159] In addition, the steps and apparatuses in each of the embodiments herein are not limited to being implemented in a particular embodiment. In fact, according to the concepts of the present invention, relevant partial steps and partial apparatuses in each of the embodiments herein can be combined to conceive new embodiments, and these new embodiments are also included within the scope of the present invention.

[0160] Each operation of the methods described above can be carried out by any suitable means capable of performing the corresponding functions. Such means can include various hardware and / or software components and / or modules, including but not limited to hardware circuits, application-specific integrated circuits (ASICs), or processors.

[0161] The various illustrative logical blocks, modules, and circuits described can be implemented or carried out using a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array signal (FPGA), or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but alternatively, the processor can be any commercially available processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, a microprocessor cooperating with a DSP core, or any other such configuration.

[0162] The steps of the methods or algorithms described in connection with the present disclosure may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may exist in any form of tangible storage medium. Some examples of storage media that may be used include random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, etc. The storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In an alternative, the storage medium may be integral with the processor. The software modules may be a single instruction or many instructions, and may be distributed over several different code segments, different programs, and across multiple storage media.

[0163] The methods disclosed herein include acts for implementing the described methods. The methods and / or acts may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of acts is specified, the order and / or use of specific acts may be modified without departing from the scope of the claims.

[0164] The above functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as instructions on a tangible computer-readable medium. The storage medium may be any available tangible medium accessible by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other tangible medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers.

[0165] Accordingly, a computer program product may perform the operations set forth herein. For example, such a computer program product may be a computer-readable tangible medium having tangible storage (and / or encoding) thereon of instructions executable by a processor to perform the operations described herein. The computer program product may include packaging materials.

[0166] Software or instructions may also be transmitted over a transmission medium. For example, software may be transmitted from a website, server, or other remote source using a transmission medium such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave.

[0167] In addition, modules and / or other suitable means for performing the methods and techniques described herein can be downloaded and / or otherwise obtained by a user terminal and / or a base station as appropriate. For example, such devices can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, the various methods described herein can be provided via a storage component (such as RAM, ROM, a physical storage medium such as a CD or a floppy disk) so that a user terminal and / or a base station can obtain the various methods when coupled to the device or provided with the storage component. In addition, any other suitable techniques for providing the methods and techniques described herein to a device can be utilized.

[0168] Other examples and implementations are within the scope and spirit of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The features implementing the functions can also be physically located at various positions, including being distributed so that portions of the functions are implemented at different physical locations. Also, as used herein, including in the claims, the "or" used in the listing of items beginning with "at least one" indicates a disjunctive listing so that, for example, the listing of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). In addition, the phrase "exemplary" does not mean that the examples described are preferred or better than other examples.

[0169] Various changes, substitutions, and alterations to the techniques described herein can be made without departing from the teachings of the technology defined by the appended claims. In addition, the scope of the claims of the present disclosure is not limited to the specific aspects of the processes, machines, manufactures, compositions of events, means, methods, and acts described above. Current or later-developed processes, machines, manufactures, compositions of events, means, methods, or acts that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Accordingly, the appended claims include such processes, machines, manufactures, compositions of events, means, methods, or acts within their scope.

[0170] The foregoing description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the invention. Thus, the invention is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0171] The foregoing description has been presented for purposes of illustration and description. In addition, this description is not intended to limit embodiments of the invention to the form disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A driving system for automatically detecting an on-chip voltage to adjust the gate voltage of a thin-film transistor, comprising an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjustment circuit configured to automatically detect a current amplitude of the on-chip voltage output by the input circuit and output a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the driven thin-film transistor, wherein the source of the thin-film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage, wherein, the adjustment circuit comprises: a reference voltage generator configured to output a plurality of reference voltages related to N selectable amplitudes of the on-chip voltage, where N is a positive integer greater than 1; a plurality of comparators, each configured to compare the on-chip voltage output by the input circuit with a corresponding one of the reference voltages and output a comparison result; a decision maker configured to determine, based on the comparison results of the plurality of comparators, a mode related to the current amplitude of the on-chip voltage output by the input circuit from N modes related to N selectable amplitudes of the on-chip voltage, and output a bias voltage corresponding to the mode to the gate of the driven thin-film transistor according to the detected mode, wherein the driving system further comprises: a threshold decoder configured to set the gates of some thin-film transistors in the receiver to threshold voltages corresponding to the mode based on the detected mode, wherein the gate voltages of some other thin-film transistors in the receiver are the on-chip voltage.

2. The system according to claim 1, wherein, the amplitude of each of the plurality of reference voltages is an intermediate voltage between two adjacent selectable amplitudes among the N selectable amplitudes, each of the plurality of comparators outputs a first value when the on-chip voltage is greater than a corresponding one of the reference voltages and outputs a second value when the on-chip voltage is less than or equal to a corresponding one of the reference voltages, wherein each of the N modes corresponds to one of a plurality of possible codes composed of the first value and the second value; the comparison result is a result code composed of the first values output by the plurality of comparators and the second values output; the decision maker is configured to determine the mode corresponding to the result code from the N modes according to the result code.

3. The system according to claim 2, wherein, the reference voltage generator is a bandgap reference power supply, the first value is binary 1, the second value is binary 0, the comparator is an analog-to-digital converter, and the decision maker is a digital-to-analog converter.

4. The system according to claim 1, wherein when the amplitude of the on-chip voltage is 1.8V, the bias voltage is set to 0V, when the amplitude of the on-chip voltage is 2.5V, the bias voltage is set to one-fourth of the on-chip voltage, and when the amplitude of the on-chip voltage is 3.3V, the bias voltage is set to one-third of the on-chip voltage.

5. The system according to claim 1, wherein, the adjustment circuit comprises: A V / I and I / V conversion circuit, configured to output a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage, wherein the V / I and I / V conversion circuit includes: A V / I conversion circuit, configured to convert the input on-chip voltage into a current signal; An I / V conversion circuit, configured to convert the current signal into a corresponding bias voltage, Alternatively, the adjustment circuit includes: A plurality of resistors for dividing the input on-chip voltage.

6. The system according to claim 1, wherein, The input circuit includes an averaging circuit, configured to average the on-chip voltage and output the averaged on-chip voltage, wherein the averaging circuit includes at least one capacitor and at least one resistor.

7. The system according to claim 6, wherein, The threshold voltage for the on-chip voltage with an amplitude of 1.8V is set to 0.9V, the threshold voltage for the on-chip voltage with an amplitude of 2.5V is set to 1.25V, and the threshold voltage for the on-chip voltage with an amplitude of 3.3V is set to 1.65V.

8. The system according to any one of claims 1-7, wherein, The driving system includes a switch group, configured to turn on the on-chip voltage and disconnect the coupling with the thin film transistor during the training period so that the thin film transistor is turned off, wherein the training is to output a preset bias voltage or a preset threshold voltage based on a preset amplitude of the on-chip voltage output by the input circuit, and the switch group is configured to turn on the coupling with the thin film transistor during the normal operation period.

9. The system according to claim 8, wherein, The training period is controlled by a counter, and during the counting of the counter, a series of training mode pulses with alternating low and high levels are generated so that the on-chip voltage received by the input circuit is a periodic wave, and at the end of the counting of the counter, the training mode pulse becomes low level, indicating the start of the normal operation period.

10. A driving method for automatically detecting an on-chip voltage to adjust the gate voltage of a thin film transistor, including An input step, in which an input circuit receives an input on-chip voltage and outputs the on-chip voltage; An adjustment step, in which an adjustment circuit automatically detects the current amplitude of the on-chip voltage output by the input circuit and outputs a bias voltage corresponding to the current amplitude of the on-chip voltage to the gate of the driven thin film transistor, wherein the source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage, wherein, The adjustment step includes: Outputting, by a reference voltage generator, a plurality of reference voltages related to N optional amplitudes of the on-chip voltage, where N is a positive integer greater than 1; Comparing, by a plurality of comparators, the on-chip voltage output by the input circuit with a corresponding reference voltage and outputting a comparison result; The decision maker determines, based on the comparison results of the multiple comparators, a mode related to the current amplitude of the on-chip voltage output by the input circuit from among N modes related to N selectable amplitudes of the on-chip voltage, and outputs a bias voltage corresponding to the mode to the gate of the driven thin film transistor according to the detected mode. Wherein the method further includes: the threshold decoder sets the gates of some of the thin film transistors in the receiver to threshold voltages corresponding to the mode based on the detected mode, and the gate voltages of some other thin film transistors in the receiver are the on-chip voltage.

11. The method according to claim 10, wherein, the amplitude of each of the multiple reference voltages is an intermediate voltage between two adjacent selectable amplitudes among the N selectable amplitudes. The step of the multiple comparators comparing the on-chip voltage output by the input circuit with a corresponding one of the reference voltages and outputting a comparison result includes: each of the multiple comparators outputs a first value when the on-chip voltage is greater than a corresponding one of the reference voltages, and outputs a second value when the on-chip voltage is less than or equal to a corresponding one of the reference voltages, wherein each mode among the N modes corresponds to one code among multiple possible codes composed of the first value and the second value; wherein the comparison result is a result code composed of the first value output by the multiple comparators and the second value output; wherein the step of the decision maker determining the mode based on the comparison results of the multiple comparators includes: the decision maker determines the mode corresponding to the result code from among the N modes according to the result code.

12. The method according to claim 10, wherein, the adjustment step includes: the V / I and I / V conversion circuit outputs a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage. Wherein the step of the V / I and I / V conversion circuit outputting a corresponding bias voltage based on the on-chip voltage output by the input circuit according to the input-output relationship between the on-chip voltage and the bias voltage includes: the V / I conversion circuit converts the input on-chip voltage into a current signal; the I / V conversion circuit converts the current signal into a corresponding bias voltage.

13. The method according to any one of claims 10-12, wherein, the method further includes that the switch group turns on the on-chip voltage and disconnects the coupling with the thin film transistor during the training period so that the thin film transistor is turned off, wherein the training is to output a preset bias voltage or a preset threshold voltage based on a preset amplitude of the on-chip voltage output by the input circuit, and the switch group turns on the coupling with the thin film transistor during the normal operation period.

14. The method according to claim 13, wherein, the training period is controlled by a counter, and during the counting of the counter, a string of training mode pulses with low and high levels alternating is generated so that the on-chip voltage received by the input circuit is a periodic wave. And when the counting of the counter ends, the training mode pulse becomes low level, indicating the start of the normal operation period.

15. A computer system, comprising: a processor; a memory coupled to the processor and storing computer-executable instructions therein for performing the driving method according to any one of claims 10-14 when executed by the processor.

16. A computer-readable medium having stored thereon a computer program, wherein, the program, when executed by a processor, implements the driving method according to any one of claims 10-14.

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