A Minimal FPGA CPU Verification System and Method

Abstract

The present application relates to FPGA technical field, specifically relates to a kind of minimum FPGA CPU verification system and method, including by CPU, RAM and UART composition FPGA end and be equipped with control software controller software PC end, the UART port of the FPGA end is connected with the serial port of the PC end by serial line, when working, FPGA end CPU power-on bootcode, bootcode code cyclically waits UART data.PC end Controllersoftware sends command, is given UART by COM mouth.Transmission.FPGA end CPU receives the data of UART, executes the processing function of corresponding command.The FPGA CPU verification system of the present application is extremely simple, only CPU, UART, RAM can be composed, and has the convenient characteristics of updating test program, has very strong market application prospect.

Description

Technical Field

[0001] This invention relates to the field of FPGA technology, and more specifically to a minimum FPGA CPU verification system and method. Background Technology

[0002] Existing FPGA CPU verification systems require at least one flash memory chip to store the program the CPU needs to execute. This system needs to include a hardware controller for the flash memory and accompanying software. Each time the program is updated, the flash memory needs to be removed, programmed, and then placed back onto the FPGA development board, a rather cumbersome process. Furthermore, writing to flash memory is more complex than writing to RAM, requiring an erase operation before the write operation can begin.

[0003] In the initial stages of CPU verification, a minimal SoC (System-on-a-Chip) is typically prepared for the CPU. This system generally contains only the CPU, UART, and RAM. The program running on the CPU is stored in RAM, and during EDA simulation, it can be loaded into RAM using a background loading method. However, background loading is not possible during FPGA verification. Therefore, this paper proposes a method to solve the problem of program loading in the minimal CPU system for FPGAs. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention discloses a minimum FPGA CPU verification system and method to solve the problem of program loading in a minimum FPGA CPU system.

[0005] This invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention discloses a method for verifying a minimal FPGA CPU, comprising the following steps:

[0007] S1. System initialization, FPGA CPU powers on and starts bootcode;

[0008] The S2.bootcode code loops and waits for UART data.

[0009] S3. The PC-side controller software sends commands and transmits them to the UART via the COM port;

[0010] S4. The FPGA-side CPU receives data from the UART, executes the corresponding command processing function, and completes the verification.

[0011] Furthermore, in the method, the CPU bootcode execution process on the PGA side includes the following sub-steps:

[0012] S21.Uart_init, initializes the UART;

[0013] S22.Uart_recv, receives a UART data packet;

[0014] S23.CalcCRC: Calculate the CRC of the data packet and verify its integrity; if the verification fails, proceed to S24; if the verification succeeds, proceed to S25.

[0015] S24. Send ack_err_crc to the PC to inform the PC that this data packet is incorrect;

[0016] S25. Parse the data packet and determine what command it is;

[0017] S26. If the command is cmd_boot, send ack_suc to indicate that the command has been successfully received, set exit to 1, and jump to addr to start executing the test case;

[0018] S27. If the command is cmd_loop, then resend the received data.

[0019] S28. If the command is cmd_addr, record addr and send the received address back;

[0020] S29. If the command is cmd_write, write the data to addr, add the number of bytes written to addr, and then send the previous CRC back.

[0021] S210. If the command is cmd_read, then read the data in addr and send it to the PC.

[0022] S211. If none of the above commands are found, return ack_err_cmd to inform the PC that an incorrect command was received.

[0023] Furthermore, the method includes the following sub-steps when downloading the program:

[0024] S31.Uart_init, initializes the UART;

[0025] S32. Enter the handshake process, send a loop every 1 second until the ack_data from the FPGA is received, indicating that the handshake is successful. If an incomplete packet is received or no response is received within 3 seconds, resend the command.

[0026] S33. Handshake successful, proceeding to download process;

[0027] S34. Send to target address addr;

[0028] S35. Read 64 bytes from the file;

[0029] S36. Send file data to the FPGA;

[0030] S37. Check if the data responsesecrc is correct;

[0031] S38. Determine if the file has ended. If it has not ended, jump back to S35 and continue sending data.

[0032] S39. Enter the boot process;

[0033] S310. Send the boot address;

[0034] S311. Send the boot command to make the FPGA-side CPU program jump to address 0x8000_0000, thereby starting the test program.

[0035] Furthermore, in the method described above, during the debugging process, it is necessary to read the contents of memory for certain checks. Therefore, reading memory includes the following sub-steps:

[0036] S41.Uart_init, initializes the UART;

[0037] S42. Enter the handshake process, send a loop every 1 second until the ack_data from the FPGA is received, indicating that the handshake is successful. If an incomplete packet is received or no response is received within 3 seconds, resend the command.

[0038] S43. Handshake successful, proceed to read_mem process;

[0039] S44. Send to target address addr;

[0040] S45. Send the read command;

[0041] S46. Receive UART data and check CRC;

[0042] S47. Write the UART data to the file;

[0043] S48. Determine if the process has ended. If not, jump to S45 and continue reading.

[0044] Furthermore, in the method, the data packet format consists of cmd, len, data, and crc8 fields, where cmd is 1 byte long; len is 1 byte, representing the length of the following data; data is the data body; and crc8 is the CRC checksum of the data field, with the low byte sent first.

[0045] Furthermore, in the method, each command must be acknowledged with an ACK before the next command can be sent. If a failure is returned, the command is resent.

[0046] Secondly, the present invention discloses a minimum FPGA CPU verification system, the system being used to execute the minimum FPGA CPU verification method described in the first aspect, comprising an FPGA end consisting of a CPU, RAM and UART and a PC end equipped with controller software, wherein the UART port of the FPGA end is connected to the serial port of the PC end via a serial cable.

[0047] Furthermore, the PC-side controller software is written in Python and controls the PC's serial port to send commands to control the FPGA's bootcode, thereby enabling dynamic program downloading and memory reading functions.

[0048] Furthermore, the address of the FPGA-side RAM is 0x8000_0000~0xbfff_ffff, the CPU reset address is set to 0xb000_0000, and a piece of bootcode is initialized to address 0xb000_0000 through a synthesis tool so that the FPGA-side CPU executes the bootcode by default.

[0049] The beneficial effects of this invention are as follows:

[0050] The FPGA CPU verification system of this invention is extremely simple, requiring only a CPU, UART, and RAM, and has the characteristic of conveniently updating test programs, making it highly promising for market applications. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a block diagram of a minimal FPGA CPU verification system.

[0053] Figure 2 This is a schematic block diagram illustrating the default execution of bootcode code by the FPGA-side CPU in an embodiment of the present invention.

[0054] Figure 3 This is a flowchart of the CPU bootcode execution process on the FPGA side according to an embodiment of the present invention;

[0055] Figure 4 This is a diagram illustrating the program download process according to an embodiment of the present invention;

[0056] Figure 5 This is a schematic diagram illustrating the principle of the communication handshake protocol in an embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Example 1

[0059] This embodiment discloses a minimum FPGA CPU verification method, including the following steps:

[0060] S1. System initialization, FPGA CPU powers on and starts bootcode;

[0061] The S2.bootcode code loops and waits for UART data.

[0062] S3. The PC-side controller software sends commands and transmits them to the UART via the COM port;

[0063] S4. The FPGA-side CPU receives data from the UART, executes the corresponding command processing function, and completes the verification.

[0064] In this embodiment, as Figure 5 As shown, the principle of the communication handshake protocol is as follows: The data packet format consists of cmd, len, data, and crc8 fields, where cmd is 1 byte long; len is 1 byte, representing the length of the following data; data is the data body; and crc8 is the CRC checksum of the data field, with the low byte sent first.

[0065] In this embodiment, each command must be acknowledged with an ACK before the next command can be sent. If a failure is returned, the command is resent.

[0066] Example 2

[0067] This embodiment discloses as follows: Figure 3 The FPGA-side CPU bootcode execution flow is shown below:

[0068] 1. Uart_init, initializes the UART.

[0069] 2. `Uart_recv` receives a UART data packet.

[0070] 3. CalcCRC: Calculate the CRC of the data packet to verify its integrity. If verification fails, proceed to step 4; if verification succeeds, proceed to step 5.

[0071] 4. Due to CRC verification failure, an ack_err_crc is sent to the PC to inform the PC of the error in this data packet.

[0072] 5. Since the CRC verification was successful, what command was parsed from this data packet?

[0073] 6. If the command is cmd_boot, send ack_suc to indicate successful command reception, set exit to 1 to break out of the loop, and jump to addr to begin executing the test cases.

[0074] 7. If the command is cmd_loop, the received data will be resent for path testing.

[0075] 8. If the command is cmd_addr, then record addr for later reading, writing, or booting, and send the received address back to the PC to confirm that the correct address has been received.

[0076] 9. If the command is cmd_write, write the data to addr and add the number of bytes written to addr. Then send back the previous CRC to confirm the correctness of the data packet.

[0077] 10. If the command is cmd_read, then read the data from addr and send it to the PC.

[0078] 11. If none of the above commands are received, return ack_err_cmd to inform the PC that an incorrect command was received.

[0079] In this embodiment, the PC-side controller software is written in Python and controls the PC's serial port to send commands to control the FPGA's bootcode, thereby completing the functions of dynamically downloading programs and reading memory.

[0080] Example 3

[0081] This embodiment discloses as follows: Figure 4 The program download process is shown below:

[0082] 1. Uart_init, initializes the UART.

[0083] 2. Enter the handshake process, sending a loop every 1 second until ack_data is received from the FPGA, indicating a successful handshake. If an incomplete packet is received, or no response is received within 3 seconds, the command is resent.

[0084] 3. After a successful handshake, the download process begins.

[0085] 4. Send to the target address addr, typically 0x8000_0000

[0086] 5. Read 64 bytes from the file.

[0087] 6. Send file data to the FPGA.

[0088] 7. Check if the responsesecrc data is correct.

[0089] 8. Check if the file has ended. If not, jump back to step 5 and continue sending data.

[0090] 9. Entering the boot process

[0091] 10. Send the boot address, typically 0x8000_0000

[0092] 11. Send the boot command to make the FPGA-side CPU program jump to address 0x8000_0000, thereby starting the test program.

[0093] Example 4

[0094] During the debugging process, it may be necessary to read the memory contents for certain checks. Therefore, this embodiment discloses the memory reading process as follows:

[0095] 1. Uart_init, initializes the UART.

[0096] 2. Enter the handshake process, sending a loop every 1 second until ack_data is received from the FPGA, indicating a successful handshake. If an incomplete packet is received, or no response is received within 3 seconds, the command is resent.

[0097] 3. After a successful handshake, the read_mem process begins.

[0098] 4. Send to target address addr

[0099] 5. Send the read command

[0100] 6. Receive UART data and check CRC.

[0101] 7. Write UART data to a file

[0102] 8. Determine if the process has ended. If not, proceed to step 5 and continue reading.

[0103] Example 5

[0104] This embodiment discloses a minimal FPGA CPU verification system, including an FPGA terminal consisting of a CPU, RAM and UART, and a PC terminal equipped with controller software. The UART port of the FPGA terminal is connected to the serial port of the PC terminal via a serial cable.

[0105] In this embodiment, the address of the FPGA-side RAM is 0x8000_0000~0xbfff_ffff, the CPU reset address is set to 0xb000_0000, and a piece of bootcode is initialized to address 0xb000_0000 through synthesis tools so that the FPGA-side CPU executes the bootcode by default.

[0106] The command types supported in this embodiment are as follows:

[0107]

[0108]

[0109] An alternative solution to this embodiment is to add a flash memory chip to store the program that the CPU needs to execute. This system requires hardware including the flash memory and supporting software. Moreover, each time the program is updated, the flash memory needs to be removed, programmed, and then placed back onto the FPGA development board, which is a rather cumbersome process.

[0110] In summary, the FPGA CPU verification system of the present invention is extremely simple, requiring only a CPU, UART, and RAM, and has the characteristic of convenient test program updates, thus possessing strong market application prospects.

[0111] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for verifying a minimal FPGA CPU, characterized in that, The method includes the following steps: S1. System initialization, FPGA CPU powers on and starts bootcode; The S2.bootcode code loops and waits for UART data. S3. The PC-side controller software sends commands and transmits them to the UART via the COM port; S4. The FPGA-side CPU receives data from the UART, executes the corresponding command processing function, and completes the verification.

2. The minimum FPGA CPU verification method according to claim 1, characterized in that, In the method described, the CPU bootcode execution process at the PGA end includes the following sub-steps: S21.Uart_init, initializes the UART; S22.Uart_recv, receives a UART data packet; S23.CalcCRC: Calculate the CRC of the data packet and verify its integrity; if the verification fails, proceed to S24; if the verification succeeds, proceed to S25. S24. Send ack_err_crc to the PC to inform the PC that this data packet is incorrect; S25. Parse the data packet and determine what command it is; S26. If the command is cmd_boot, send ack_suc to indicate that the command has been successfully received, set exit to 1, and jump to addr to start executing the test case; S27. If the command is cmd_loop, then resend the received data. S28. If the command is cmd_addr, record addr and send the received address back; S29. If the command is cmd_write, write the data to addr, add the number of bytes written to addr, and then send the previous CRC back. S210. If the command is cmd_read, then read the data in addr and send it to the PC. S211. If none of the above commands are found, return ack_err_cmd to inform the PC that an incorrect command was received.

3. The minimum FPGA CPU verification method according to claim 1, characterized in that, The method includes the following sub-steps when downloading the program: S31.Uart_init, initializes the UART; S32. Enter the handshake process, send a loop every 1 second until the ack_data from the FPGA is received, indicating that the handshake is successful. If an incomplete packet is received or no response is received within 3 seconds, resend the command. S33. Handshake successful, proceeding to download process; S34. Send to target address addr; S35. Read 64 bytes from the file; S36. Send file data to the FPGA; S37. Check if the data responsesecrc is correct; S38. Determine if the file has ended. If it has not ended, jump back to S35 and continue sending data. S39. Enter the boot process; S310. Send the boot address; S311. Send the boot command to make the FPGA-side CPU program jump to address 0x8000_0000, thereby starting the test program.

4. The minimum FPGA CPU verification method according to claim 1, characterized in that, In the method described above, during the debugging process, it is necessary to read the contents of memory for certain checks. The memory reading process includes the following sub-steps: S41.Uart_init, initializes the UART; S42. Enter the handshake process, send a loop every 1 second until the ack_data from the FPGA is received, indicating that the handshake is successful. If an incomplete packet is received or no response is received within 3 seconds, resend the command. S43. Handshake successful, proceed to read_mem process; S44. Send to target address addr; S45. Send the read command; S46. Receive UART data and check CRC; S47. Write the UART data to the file; S48. Determine if the process has ended. If not, jump to S45 and continue reading.

5. The minimum FPGA CPU verification method according to claim 1, characterized in that, In the method, the data packet format consists of cmd, len, data, and crc8 fields, where cmd is 1 byte long; len is 1 byte and represents the length of the following data; data is the data body; and crc8 is the CRC checksum of the data field, with the low byte sent first.

6. The minimum FPGA CPU verification method according to claim 1, characterized in that, In this method, each command must be acknowledged with an ACK before the next command can be sent. If a failure is returned, the command is resent.

7. A minimum FPGA CPU verification system, said system being used to perform the minimum FPGA CPU verification method as described in any one of claims 1-6, characterized in that, It includes an FPGA consisting of a CPU, RAM and UART, and a PC containing controller software. The UART port of the FPGA is connected to the serial port of the PC via a serial cable.

8. The minimum FPGA CPU verification system according to claim 7, characterized in that, The PC-side controller software is written in Python and controls the PC's serial port to send commands to control the FPGA's bootcode, thereby enabling dynamic program downloading and memory access.

9. The minimum FPGA CPU verification system according to claim 7, characterized in that, The address of the RAM on the FPGA side is 0x8000_0000~0xbfff_ffff, the CPU reset address is set to 0xb000_0000, and a piece of bootcode is initialized to address 0xb000_0000 through synthesis tools so that the CPU on the FPGA side executes the bootcode by default.

Images