Method and system for implementing a vector access cache

Abstract

The application relates to the technical field of processors, in particular to an implementation method and system of a vector memory cache, which comprises the following steps: S1, system initialization, configuring the number of scala and vector available ways; S2, after a load miss or a store miss or a store hit S state, requesting reload data to L2; S3, allocating the number of configured ways to scala ways and vector ways, judging whether the ways are used for scala operation or vector operation; S4, using the scala operation or the vector operation to request reload data; and S5, according to the existence of the ways allocated to the scala or the vector, selecting a way at a suitable position as a refill_way. The application can maximally reduce area and power consumption, effectively improve the hit rate of vector operation, reduce the bandwidth required by L2, and effectively solve the problem of low utilization rate of some ways.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor technology, and particularly relates to a vector memory cache implementation method and system. BACKGROUND

[0002] Disadvantages of the prior art:

[0003] (1) For vector memory instructions, a separate logic unit is used, which has high area and power consumption

[0004] (2) The vector and scala data pollute each other in the D_cache, which reduces the cache hit rate and increases the bandwidth demand for the next level cache

[0005] (3) The utilization rate of some ways of the D_cache is too low, which reduces the cache hit rate.

[0006] Therefore, the following problems need to be solved:

[0007] (1) The vector memory instruction reuses the logic unit of the scala memory instruction, and does not need a separate logic unit for the vector, which minimizes the area and power consumption.

[0008] (2) The number of ways allocated to the vector instruction in the D_cache can be dynamically configured. When there are a large number of vector operations, the number of ways occupied by the vector data in the entire cache can be appropriately increased, which effectively improves the hit rate of the vector operation

[0009] (3) The scala and vector data are located in different ways in the cache, which effectively reduces the mutual pollution of the vector and scala cache and improves the cache hit rate. It also effectively reduces the evict operation and thus reduces the bandwidth demand for the L2

[0010] (4) In some cases, the number of ways allocated to the vector may be small, but the utilization rate is still low. By configuring whether the vector data can write the scala cache area and whether the scala data can write the vector cache area, the problem of low utilization rate of some ways can be effectively solved.

[0011] To this end, the present application provides a vector memory cache implementation method and system. SUMMARY

[0012] In view of the deficiencies of the prior art, the application discloses an implementation method and system of a vector memory cache, and is used to solve the above problems.

[0013] The application is implemented by the following technical solutions:

[0014] In a first aspect, the application discloses an implementation method of a vector memory cache, comprising the following steps:

[0015] S1, system initialization, configuring the number of scala and vector available ways;

[0016] S2, after a load miss or a store miss or a store hit S state, requesting reload data from L2;

[0017] S3, allocating the number of configured ways to scala ways and vector ways, and judging whether to be used for scala operation or vector operation;

[0018] S4, requesting reload data by using scala operation or vector operation;

[0019] S5, according to the existence of the ways allocated to scala or vector, selecting a suitable position of the way as refill_way.

[0020] Further, in the method, if all the ways allocated to scala or vector are valid, but the way is invalid, the request of scala or vector can be used.

[0021] Further, in the method, after a load miss or a store miss or a store hit S state, when requesting reload data from L2, the following steps are included:

[0022] S31, pipeline of load or store instruction, load miss or store miss or store hit S state occurs;

[0023] S32, requesting an entry item from a miss queue, and backfilling set and way information in the cache after allocating a reload data back;

[0024] S33, miss queue sends a reload request to L2;

[0025] S34, L2 backfills reload data to the miss queue;

[0026] S34, miss queue writes the data back from reload to cache, the address of writing is the setway allocated before.

[0027] Further, in the method, if the load hit or the store hit the E / M state, reload is not required to be requested from the L2.

[0028] Further, in the method, the set information is extracted from the address information of request, the way information is determined by whether the request type is vector or scala, whether the way in the corresponding set has been used, the allocation of the way and the share characteristics of the way.

[0029] Further, in the method, if there is unvalid in the way allocated to the vector, a way is selected from the unvalid way as the refill_way.

[0030] Further, in the method, if there is unvalid in the way used by the scala, and the way can be used by the vector, a way is selected from the way used by the scala, and the way can be used by the vector as the refill_way.

[0031] Further, in the method, in other cases, a way is selected as the refill_way in the way used by the vector by using the principle of the most recently unused.

[0032] In the second aspect, the application discloses an implementation system of a vector memory cache, and the system is used for implementing the implementation method of the vector memory cache in the first aspect, and the system is characterized in that the system comprises a cache memory, and the content of the cache memory comprises V, Tag, set (=index), cacheline, D and way.

[0033] Further, the V indicates whether the cacheline is valid; the Tag is tag information which is valid address information; the set (=index) is set information which is part of the valid address; the cacheline is cacheline data information; the D is used to indicate whether the cacheline is dirty or clean; the way is irrelevant to the address information, and the data of the way is in the range of 4-16.

[0034] The application has the following beneficial effects:

[0035] The vector memory access instruction reuses the logic unit of the scala memory access instruction, without separately making a set of logic units for the vector, thereby minimizing area and power consumption.

[0036] The vector instruction can dynamically configure how many ways are allocated in the D_cache, when there are a large number of vector operations, the number of vector data occupying the entire cache way can be appropriately increased, and the hit rate of the vector operation can be effectively improved.

[0037] The scala and vector data are located in different ways in the cache, which can effectively reduce the mutual pollution of the vector and the scala cache, effectively improve the cache hit rate, and effectively reduce the evict operation, thereby reducing the bandwidth demand for the L2.

[0038] In some cases, the way allocated to the vector may be small, but the usage rate is still low, by configuring whether the vector data can write the cache area of the scala and whether the scala data can write the cache area of the vector, the problem of low utilization rate of some ways can be effectively solved. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor under the premise of the drawings.

[0040] Figure 1 It is a principle step diagram of a kind of implementation method of vector memory cache;

[0041] Figure 2 It is a kind of principle diagram of implementation system of vector memory cache;

[0042] Figure 3 It is the detailed flow chart of reload data required to request to L2 after load miss or store miss or store hit S state;

[0043] Figure 4 It is the detailed flow chart of the way information allocated to backfill data after vector operation cache miss. DETAILED DESCRIPTION

[0044] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0045] Embodiment 1

[0046] The embodiment discloses an implementation method of a vector access cache as shown in the figure, comprising the following steps: Figure 1

[0047] S1, system initialization, configuration of scala and the number of available ways of vector;

[0048] S2, after a load miss or a store miss or a store hit S state, request reload data to L2;

[0049] S3, allocate the number of configured ways to scala ways and vector ways, and judge whether to use scala operation or vector operation;

[0050] S4, request reload data using scala operation or vector operation;

[0051] S5, according to the existence of the ways allocated to scala or vector, select the appropriate position of the way as refill_way.

[0052] In the embodiment, if all the ways allocated to scala or vector are valid, but the way is invalid, the request allocated to scala or vector can be used.

[0053] In the embodiment, the vector access type instruction reuses the logic unit of the scala access type instruction, and a set of logic units for vector is not needed, so that the area and power consumption are minimized.

[0054] In the embodiment, the number of ways allocated to vector instructions in D_cache can be dynamically configured, when there are a large number of vector operations, the number of vector data occupying the entire cache way can be appropriately increased, and the hit rate of vector operation can be effectively improved.

[0055] Embodiment 2

[0056] As shown in the figure Figure 3 ​The embodiment shown discloses the detailed process of requesting reload data from L2 after load miss or store miss or store hit S state:

[0057] (1) pipeline on load or store instruction, load miss or store miss or store hit S state (if load hit or store hit E / M state, no need to request reload from L2)

[0058] (2) request an entry item from miss queue, and allocate a reload data backfill position in cache at the same time, that is, set and way information, wherein set is extracted from the address information of the request, and the determination of way information is determined by the type of request (vector or scala), whether the way in the set has been used, and the allocation of way and the share characteristics of way

[0059] (3) miss queue sends a reload request to L2

[0060] (4) L2 backfills reload data to miss queue

[0061] (5) miss queue writes the data returned by reload into cache, and the address for writing is the setway allocated before.

[0062] Embodiment 3

[0063] As Figure 4 The embodiment shown discloses the detailed description of allocating a way information for backfill data after cache miss of vector operation, and the scala operation is basically similar:

[0064] (1) Vector operation requests reload data

[0065] (2) If there is an unvalid way allocated to vector, select a way from the unvalid way as refill_way

[0066] (3) If the way allocated to vector has been used

[0067] If there is an unvalid way in the way used by scala, and the way can be used for vector, select a way from the unvalid way in the way used by scala as refill_way

[0068] In other cases, among the ways used by the vector, the principle of the least recently used way is used to select a way as the refill way.

[0069] Example 4

[0070] like Figure 2 As shown in the figure, this embodiment discloses an implementation system for vector memory access cache, including a cache memory, the contents of which include V, Tag, set (=index), cacheline, D and way.

[0071] In this embodiment, V indicates whether the cacheline is valid.

[0072] In this embodiment, the tag information can also be referred to as valid address information.

[0073] In this embodiment, set(=index): the set signal is also part of the valid address. When comparing whether PA is hit, all the way tag information is selected from the set and compared, instead of reading out the entire cache tag information for comparison.

[0074] In this embodiment, cacheline refers to the cacheline data information.

[0075] In this embodiment, D: is used to indicate whether the cacheline is dirty or clean.

[0076] In this embodiment, way:way and address information are unrelated, and the data for way is generally between 4 and 16.

[0077] Example 5

[0078] This embodiment uses 16 ways as an example to illustrate the specific implementation process, including the parameter configurations involved and the functions that can be achieved:

[0079] Number of available Scala channels

[0080] The number of available ways in vector

[0081] Can the Scala way be used with vectors?

[0082] The specific register functions are as follows:

[0083] way_num 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vector_alloc 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 way_share 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0

[0084] way_num: the number of the way

[0085] vector_alloc: 1 -- indicates that the way is allocated to vector, 0 -- indicates that the way is allocated to scala

[0086] `way_share: 1` -- Indicates that if all ways assigned to Scala / vector for this set are valid, but this particular way is invalid, the way assigned to Scala / vector can be used. `0` -- Indicates that this way can only be used with vector or Scala.

[0087] In the example above:

[0088] `vector_alloc = 16'b1111_0000_0000_0000` indicates that `way12` to `way15` are allocated to `vector`, and `way0` to `way11` are allocated to `Scala`.

[0089] way_share = 16'b0011_1100_0000_0000 indicates that way14 to way15 can only be used in vector. When performing Scala operations, way12 to 13 can be used when way0 to 11 have already been used and way12 to 13 are still invalid.

[0090] Ways 0 through 9 can only be used in Scala. When performing vector operations, if ways 12 through 15 have already been used, and ways 10 through 11 are still invalid, then ways 10 through 11 can be used for vector operations.

[0091] In summary, the present invention reuses the logic unit of Scala memory access instructions for vector memory access instructions, eliminating the need to create a separate logic unit for vector, thereby minimizing area and power consumption.

[0092] The number of ways allocated in D_cache by the vector instruction of this invention can be dynamically configured. When there are a large number of vector operations, the number of cacheways occupied by the vector data can be appropriately increased, which can effectively improve the hit rate of vector operations.

[0093] This invention places Scala and vector data in different ways within the cache, effectively reducing mutual contamination between the vector and Scala caches and improving cache hit rate; it also effectively reduces evict operations, thereby reducing the bandwidth required for L2 cache.

[0094] In some cases, even though the number of ways allocated to a vector may be small, the utilization rate may still be low. By configuring whether vector data can write to the Scala cache area and whether Scala data can write to the vector cache area, this invention can effectively solve the problem of low utilization of certain ways.

[0095] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for implementing a vector-based memory access cache, characterized in that, The method includes the following steps: S1 system initialization, configuring the number of available scalar ways and the number of available vector ways; When S2 experiences a load miss, store miss, or store hit in S state, it requests reload data from L2. S3 divides the number of ways into scalar ways and vector ways, and marks the shareable ways; S4 uses either the scalar way or the vector way to request reload data, depending on whether the request type is scalar or vector. S5 When a cache miss occurs during a vector operation, a way information is assigned to the backfilled data, including: Vector operations request reload data; Check if the way assigned to the vector is invalid; If so, select one way from the invalid way as the refill way; If not, then check if there is an invalid way in the way used by Scala, and whether that way can be used in a vector; If it exists, then an invalid way exists from the way used by Scala, and this way can be used to select a way from the way in the vector as the refill_way; If it does not exist, then among the ways used by the vector, select one as the refill way based on the principle of the least recently used way.

2. The implementation method of vector memory access cache according to claim 1, characterized in that, In the method described, when a load miss, store miss, or store hit occurs in the S state, the process of requesting reload data from L2 includes the following steps: S31, on the pipeline of load or store instructions, a load miss or store miss occurs, or a store hit occurs in S mode; S32. Request an entry from the miss queue, and simultaneously allocate a reload data from the cache and then fill in the set and way information. S33, the miss queue sends a reload request to L2; S34 and L2 fill the miss queue with reload data; S34, the miss queue writes the reloaded data to the cache, and the address to which it is written is the previously allocated set way.

3. The implementation method of vector memory access cache according to claim 2, characterized in that, In this method, if a load hit or store hits the E / M state, there is no need to request a reload from L2.

4. A system for vector memory access cache, said system being used to implement the vector memory access cache implementation method as described in any one of claims 1-3, characterized in that, It includes a cache memory, the contents of which include V, Tag, set (=index), cacheline, D, and way.

5. The system for accessing the vector cache according to claim 4, characterized in that, The V indicates whether the cacheline is valid; the Tag is tag information, which is valid address information; the set (=index) is a set signal, which is part of the valid address; the cacheline is cacheline data information. The D indicates whether the cacheline is dirty or clean; the way is unrelated to address information, and the data of the way is in the range of 4 to 16.

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