Data processing method and device, processor and server

By obtaining the dimensions of the matrix and storing them in the cache according to the target data arrangement, the problem of low read and write efficiency of matrices in L1 cache is solved, and the efficiency of matrix operations is improved.

CN121681995APending Publication Date: 2026-03-17HUAWEI TECH CO LTD
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Patent Information

Application Number
CN202411299479.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-09-14
Publication Date
2026-03-17

AI Technical Summary

Technical Problem

Because matrices of different dimensions have different read and write efficiencies in the cache, the read and write efficiency of matrices in the L1 cache is relatively low, which in turn reduces the efficiency of matrix operations.

Method used

By obtaining the dimensions of the matrix and storing them in the cache in the target data arrangement, the read and write efficiency of the matrix in the cache is improved, thereby improving the efficiency of moving the matrix from the cache to the next cache.

Benefits of technology

It improves the efficiency of reading and writing matrices in the cache and enhances the efficiency of matrix operations.

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Abstract

The embodiment of the invention provides a data processing method and device, a processor and a server, relates to the technical field of AI, and can improve the operation efficiency of a matrix. The data processing method is used for loading a matrix in a multi-level cache; the method comprises the following steps: acquiring a first dimension of a first matrix to be loaded into a first cache; wherein the first dimension is the dimension of the first matrix; the first cache is any cache in the multi-level caches; according to the first dimension, the first matrix is stored in a first cache in a target data arrangement mode; wherein the performance of the target data arrangement mode is superior to that of a first data arrangement mode, and the first data arrangement mode is data arrangement that the matrix of the first dimension is stored in the first cache according to a default storage format of the first cache.
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