Data processing method and device, processor and server

Abstract

The embodiment of the invention provides a data processing method and device, a processor and a server, relates to the technical field of AI, and can improve the operation efficiency of a matrix. The data processing method is used for loading a matrix in a multi-level cache; the method comprises the following steps: acquiring a first dimension of a first matrix to be loaded into a first cache; wherein the first dimension is the dimension of the first matrix; the first cache is any cache in the multi-level caches; according to the first dimension, the first matrix is stored in a first cache in a target data arrangement mode; wherein the performance of the target data arrangement mode is superior to that of a first data arrangement mode, and the first data arrangement mode is data arrangement that the matrix of the first dimension is stored in the first cache according to a default storage format of the first cache.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence (AI), and more particularly to a data processing method, apparatus, processor, and server. Background Technology

[0002] As is well known, matrix operation operators are the core computational units in AI computing. These matrix operation operators are used to perform operations between matrices, such as the matrix multiplication (MatMul) operator, which is used to perform multiplication operations between matrices.

[0003] A common matrix operation process includes: the matrix operator moves (or transfers) the matrix to be processed from the high-bandwidth memory (HBM) of the processor (e.g., the Ascend processor) to the L1 cache; then, the matrix to be processed is moved from the L1 cache to the L0 cache; finally, the matrix to be processed is operated on (e.g., multiplication) based on the matrix to be processed in the L0 cache.

[0004] However, since matrices of different dimensions have different read and write efficiencies in caches (such as L1 caches), when the read and write efficiency of the matrix to be processed in the L1 cache is low, the efficiency of moving the matrix to be processed from the HBM cache to the L1 cache is also low, which in turn reduces the computational efficiency of the matrix to be processed. Summary of the Invention

[0005] This application provides a data processing method, apparatus, processor, and server that can improve the computational efficiency of matrices to be processed.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a data processing method for loading a matrix from a multi-level cache. The method includes: obtaining a first dimension of a first matrix to be loaded into a first cache; wherein the first dimension is the dimension of the first matrix; the first cache is any of the aforementioned multi-level caches; and storing the first matrix in the first cache according to the first dimension in a target data arrangement; wherein the performance of the target data arrangement is better than that of the first data arrangement, which is a data arrangement in which the matrix of the first dimension is stored in the first cache according to the default storage format of the first cache.

[0008] In the data processing method provided in the above embodiments, since the first matrix is ​​stored in the first cache based on a target data arrangement method with better performance, the read and write efficiency of the first matrix in the first cache is improved. Furthermore, since the read and write efficiency of the first matrix in the first cache is improved, the efficiency of moving the first matrix from the first cache to the next cache is also improved. Therefore, the computational efficiency of the first matrix is ​​improved.

[0009] In one possible implementation, storing the first matrix in the first cache according to the first dimension in a target data arrangement includes: determining the target data arrangement according to the first dimension; and storing the first matrix in the first cache in the target data arrangement if the target data arrangement exists.

[0010] In the above implementation, the processing kernel obtains the dimension of the first matrix (i.e., the first dimension) and determines the target data arrangement method based on the first dimension, so that the first matrix is ​​stored in the first cache in the target data arrangement method. Since the above method stores the first matrix in the first cache based on the target data arrangement method with better performance, it improves the read and write efficiency of the first matrix in the first cache, thereby improving the efficiency of moving the first matrix from the first cache to the next cache, and thus improving the operation efficiency of the first matrix.

[0011] In one possible implementation, determining the target data arrangement based on the first dimension includes: determining the target data arrangement corresponding to the first dimension from the correspondence between the dimensions of the matrix and the expected data arrangement; wherein the expected data arrangement corresponding to the second dimension in the correspondence has better performance than the second data arrangement, which is a data arrangement in which the second matrix of the second dimension is stored in the first cache according to the default storage format of the first cache.

[0012] In one possible implementation, the method further includes: storing the first matrix stored in the first cache into the second cache according to the default storage format of the second cache; wherein the multi-level cache includes the second cache, and the performance of the second cache is higher than that of the first cache.

[0013] In one possible implementation, storing the first matrix stored in the first cache into the second cache according to the default storage format of the second cache includes: retrieving the first matrix from the first cache; and storing the first matrix into the second cache according to the third data arrangement method.

[0014] In the above embodiment, after storing the first matrix in the first cache in the target data arrangement, the processing core retrieves the first matrix from the first cache and stores it in the second cache in the third data arrangement. Since the performance of the target data arrangement is better than that of the first data arrangement, the efficiency of retrieving the first matrix from the first cache is improved; thereby, the efficiency of moving the first matrix from the first cache to the second cache is improved, thus improving the computational efficiency of the first matrix.

[0015] In one possible implementation, if the default storage format of the first cache is the same as the default storage format of the second cache, the third data arrangement method is the same as the target data arrangement method.

[0016] In one possible implementation, if the default storage format of the first cache is the same as the default storage format of the second cache, the third data arrangement method is different from the target data arrangement method.

[0017] In one possible implementation, if the default storage format of the first cache is different from the default storage format of the second cache, the third data arrangement method is different from the target data arrangement method.

[0018] In one possible implementation, after storing the first matrix in the first cache according to the first dimension in the target data arrangement, the method further includes: marking the transformation state of the first matrix stored in the first cache as a transformed state; wherein the transformation state includes: a transformed state or an untransformed state; the above-mentioned obtaining the first matrix from the first cache includes: obtaining the third matrix stored in the target data arrangement from the first cache; if the transformation state of the third matrix is ​​a transformed state, converting the third matrix into the first matrix.

[0019] In the above embodiment, after storing the first matrix in the first cache in the target data arrangement, during the process of moving the first matrix from the first cache to the second cache, the third matrix stored in the target data arrangement is obtained from the first cache, and the third matrix is ​​converted back to the first matrix, thereby ensuring the accuracy of the matrix data.

[0020] In one possible implementation, when the first dimension is (x, 1) and the default storage format of the first cache is NZ storage format, the target data arrangement is to store the matrix of the third dimension in the data arrangement of the first cache according to the default storage format of the first cache; wherein, the third dimension is (1, x), and x is an integer greater than 1.

[0021] Secondly, embodiments of this application provide a data processing apparatus for loading matrices from a multi-level cache; the data processing apparatus includes a transceiver module and a storage module;

[0022] The transceiver module is used to obtain the first dimension of the first matrix to be loaded into the first cache; where the first dimension is the dimension of the first matrix; the first cache is any cache in a multi-level cache.

[0023] The storage module is used to store the first matrix in the first cache according to the first dimension in the target data arrangement; wherein, the performance of the target data arrangement is better than that of the first data arrangement, which is the data arrangement of storing the matrix of the first dimension in the first cache according to the default storage format of the first cache.

[0024] In one possible implementation, the data processing device further includes: a processing module;

[0025] The processing module determines the target data layout based on the first dimension;

[0026] The aforementioned storage module is used to store the first matrix in the first cache in the target data arrangement if the target data arrangement exists.

[0027] In one possible implementation, the processing module is used to determine the target data arrangement corresponding to the first dimension from the correspondence between the dimensions of the matrix and the expected data arrangement; wherein, the expected data arrangement corresponding to the second dimension in the correspondence has better performance than the second data arrangement, which is a data arrangement in which the second matrix of the second dimension is stored in the first cache according to the default storage format of the first cache.

[0028] In one possible implementation, the aforementioned storage module is used to store the first matrix stored in the first cache into the second cache according to the default storage format of the second cache; wherein the multi-level cache includes the second cache, and the performance of the second cache is higher than that of the first cache.

[0029] In one possible implementation, the transceiver module is used to retrieve the first matrix from the first cache; the storage module is used to store the first matrix in the second cache according to the third data arrangement.

[0030] In one possible implementation, if the default storage format of the first cache is the same as the default storage format of the second cache, the third data arrangement is the same as the target data arrangement.

[0031] In one possible implementation, if the default storage format of the first cache is the same as that of the second cache, the third data arrangement is different from the target data arrangement.

[0032] In one possible implementation, if the default storage format of the first cache is different from the default storage format of the second cache, the third data arrangement method is different from the target data arrangement method.

[0033] In one possible implementation, the processing module is used to mark the transformation state of the first matrix stored in the first cache as a transformed state; wherein the transformation state includes: a transformed state or an untransformed state; the transceiver module is used to retrieve the third matrix stored in the first cache in the target data arrangement; the processing module is also used to convert the third matrix into the first matrix when the transformation state of the third matrix is ​​a transformed state.

[0034] In one possible implementation, when the first dimension is (x, 1) and the default storage format of the first cache is NZ storage format, the target data arrangement is to store the matrix of the third dimension in the data arrangement of the first cache according to the default storage format of the first cache; where the third dimension is (1, x) and x is an integer greater than 1.

[0035] Thirdly, embodiments of this application provide a processor for running a program, wherein the program executes the methods described in the first aspect above or any possible implementation thereof.

[0036] Fourthly, embodiments of this application provide a server including a memory and at least one processor connected to the memory. The memory is used to store computer program code, which includes computer instructions. When the computer instructions are executed by the at least one processor, the server causes the server to perform the method described in the first aspect or any possible implementation thereof.

[0037] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer instructions, which, when executed on a computer, perform any one of the methods of the first aspect and its possible implementations.

[0038] In a sixth aspect, embodiments of this application provide a computer program product comprising computer instructions that, when executed on a computer, perform the method described in the first aspect and any of its possible implementations.

[0039] It should be understood that the beneficial effects of the technical solutions of the second to sixth aspects of this application and the corresponding possible implementations can be referred to the above-described technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0040] Figure 1This application provides a schematic diagram of a matrix multiplication operation.

[0041] Figure 2 This is another schematic diagram of matrix multiplication provided in an embodiment of this application;

[0042] Figure 3 A hardware schematic diagram of a computing device provided in an embodiment of this application;

[0043] Figure 4 This is one of the schematic flowcharts of a data processing method provided in an embodiment of this application;

[0044] Figure 5 This is a schematic diagram of an NZ storage format provided in an embodiment of this application;

[0045] Figure 6 This is a schematic diagram of a first data arrangement method provided in an embodiment of this application;

[0046] Figure 7 This is a schematic diagram of a target data arrangement method provided in an embodiment of this application;

[0047] Figure 8 This is a second schematic diagram of a data processing method provided in an embodiment of this application;

[0048] Figure 9 This is a third schematic diagram of a data processing method provided in an embodiment of this application;

[0049] Figure 10 This is a schematic diagram of a ZZ storage format provided in an embodiment of this application;

[0050] Figure 11 A schematic diagram of a ZN storage format provided in an embodiment of this application;

[0051] Figure 12 This is a fourth schematic diagram of a data processing method provided in an embodiment of this application;

[0052] Figure 13 This is the fifth schematic diagram of a data processing method provided in the embodiments of this application;

[0053] Figure 14 This is a schematic diagram of a data processing device provided in an embodiment of this application. Detailed Implementation

[0054] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0055] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, rather than to describe a specific order of objects. For example, "first data arrangement" and "second data arrangement" are used to distinguish different data arrangement methods, rather than to describe a specific order of data arrangement methods.

[0056] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0057] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processors means two or more processors.

[0058] To address the problems existing in the background technology, this application provides a data processing method for loading matrices from a multi-level cache. Taking loading matrix data from any cache (such as the first cache) in the multi-level cache as an example, the method includes: obtaining the dimension (which can be called the first dimension) of the first matrix to be loaded into the first cache; and storing the first matrix in the first cache in a target data arrangement according to the first dimension. The target data arrangement has better performance than the first data arrangement, which is a data arrangement where the matrix of the first dimension is stored in the first cache according to the default storage format of the first cache. Since the above method stores the first matrix in the first cache based on the more efficient target data arrangement, the read and write efficiency of the first matrix in the first cache is improved. Furthermore, the improved read and write efficiency of the first matrix in the first cache further improves the efficiency of moving the first matrix from the first cache to the next cache, thus improving the computational efficiency of the first matrix.

[0059] The data processing method described in this application is applied to matrix operation scenarios.

[0060] For example, the data processing method described in the embodiments of this application can be applied to, for example, Figure 1 The matrix multiplication scenario shown includes matrices A, B, bias, and C. Matrix A has dimensions of M rows and K columns, abbreviated as (M, K), matrix B has dimensions of (K, N), the bias matrix has dimensions of (M, N), and matrix C has dimensions of (M, N). The product of matrix A and matrix B, plus the bias matrix, results in matrix C.

[0061] For example, the data processing method described in the embodiments of this application can also be applied to, for example, Figure 2 The matrix multiplication scenario shown includes three batches of matrices: a first batch (matrix 1), a second batch (matrix 2), and a third batch (matrix 3). The first batch includes matrices A1 to A4, the second batch includes matrices B1 to B4, and the third batch includes matrices C1 to C4. Matrix elements within the same batch have the same dimensions. For example, matrices A1 to A4 in the first batch have dimensions (4, M, K), matrices B1 to B4 in the second batch have dimensions (4, K, N), and matrices C1 to C4 in the third batch have dimensions (4, M, N). The second character in parentheses "()" indicates the row dimension, and the third character indicates the column dimension.

[0062] The product of the first batch of matrices and the second batch of matrices is the third batch of matrices; that is, the product of matrix A1 and matrix B1 is matrix C1, the product of matrix A2 and matrix B2 is matrix C2, the product of matrix A3 and matrix B3 is matrix C3, and the product of matrix A4 and matrix B4 is matrix C4.

[0063] This application provides a data processing method applied to a processor in a computing device, wherein the computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smartphone.

[0064] For example, the hardware structure diagram of the above-mentioned computing device is as follows: Figure 3 As shown, where, Figure 3 The various components shown can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0065] like Figure 3 As shown, the computing device may include: a processor 301, a memory 302, and a communication interface 303. The processor 301, memory 302, and communication interface 303 can be connected to each other via a bus 304 or other means.

[0066] The processor 301 may include a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.

[0067] GPU, also known as a visual processor or display chip, is a microprocessor specifically designed for image and graphics processing in personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones). A GPU contains thousands of cores and can process thousands of threads simultaneously, enabling parallel execution of massive computations. FPGA, or programmable logic processor, allows users to repeatedly program it according to their needs. FPGAs excel at handling short, intensive data access. FPGAs allow users to program circuits through tiny logic blocks and can handle any type of digital function. ASIC, or ASIC, is a special-specification integrated circuit designed for a specific purpose, manufactured to meet the requirements of a specific user and electronic system. Examples include tensor processing units (TPUs) and neural network processing units (NPUs). TPUs and NPUs are chips designed for machine learning, suitable for massive data computation, and possess powerful computing capabilities.

[0068] It should be noted that when the processor 301 is a GPU, the processor 301 includes a multi-level cache. When the processor 301 processes data (such as a matrix), it needs to transfer the matrix to be processed to the target cache operable by the processing core in the processor 301 through the multi-level cache, so that the processing core can perform operations on the matrix in the target cache.

[0069] The memory 302 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical memory, disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer. In this embodiment, the memory 302 may store computer instructions and other information.

[0070] In one possible implementation, the memory 302 may exist independently of the processor 301. The memory 302 can be connected to the processor 301 via a bus 304 and is used to store data, instructions, or program code. When the processor 301 calls and executes the instructions or program code stored in the memory 302, it can implement the relevant steps in the data processing method provided in the embodiments of this application.

[0071] In another possible implementation, the memory 302 can also be integrated with the processor 301.

[0072] The communication interface 303 can be a transceiver module used for communication with other devices or communication networks, such as Ethernet, RAN, and wireless local area networks (WLAN). The communication interface 303 can receive commands, messages, or data. The transceiver module can be a transceiver or similar device. Optionally, the communication interface 303 can also be a transceiver circuit located within the processor 301, used to implement signal input and output for heterogeneous processors. The communication interface 303 can be a wired interface (port), such as a fiber distributed data interface (FDDI) or a gigabit Ethernet (GE) interface; alternatively, the communication interface 303 can also be a wireless interface.

[0073] Bus 304 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus. This bus can be divided into address bus, data bus, control bus, etc. The bus can also be divided into serial bus and parallel bus. For ease of representation, Figure 3 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0074] It should be noted that, Figure 3 The computing device mentioned is merely one example of a computing device; it can have more than Figure 3 The more or fewer components shown can be combined into two or more components, or they can have different component configurations. For example, a computing device can also include a smart network card, such as a data processing unit (DPU).

[0075] The data processing method provided in this application embodiment is used to load a matrix from a multi-level cache. This method is applied to the processing core of the processor 301 described above. Figure 4 As shown, the method includes: S110-S120.

[0076] S110, The processing kernel obtains the first dimension of the first matrix to be loaded into the first cache.

[0077] The first cache mentioned above can be any of the multi-level caches in the processor mentioned above; for example, if the processor mentioned above is an Ascend processor, the first cache mentioned above can be the L1 cache in the Ascend processor.

[0078] For example: Assuming the processor is an Ascend processor and the first cache is an L1 cache, the first matrix is ​​a matrix stored in high bandwidth memory (HBM) in ND storage format; wherein, the arrangement of elements in the matrix in ND storage format is as follows: after a row of data is arranged, the data is arranged in the next row, and so on until the entire data matrix is ​​arranged.

[0079] The first dimension mentioned above refers to the dimension of the first matrix. For example, suppose the first matrix is ​​[{1}, {2}, {3}, {4}], where elements in the same {} belong to the same row, and elements in different {} belong to different rows. That is, the first dimension is (4, 1). Here, 4 represents the number of rows in the first matrix, and 1 represents the number of columns in the first matrix. In other words, the first matrix is ​​a two-dimensional matrix with 4 rows and 1 column.

[0080] S120. The processing core stores the first matrix in the first cache according to the first dimension and the target data arrangement.

[0081] The performance of the above target data arrangement method is better than the first data arrangement method, which is a data arrangement in which the matrix of the first dimension is stored in the first cache according to the default storage format of the first cache.

[0082] It should be understood that matrices A and B, which have the same dimensions and contain the same elements, but are stored in storage media with different data arrangements, will have different read and write performance.

[0083] The aforementioned target data arrangement method includes: storing the third-dimensional matrix in the first cache according to the default storage format of the first cache; wherein, the default storage format is the format or rule for storing data in the first cache.

[0084] As can be seen, both the first data arrangement method and the target data arrangement method are data arrangements that store the matrix in the first cache using the default storage format of the first cache. The first data arrangement method is used to indicate the data arrangement of storing the first matrix of the first dimension in the first cache; the target data arrangement method is used to indicate the data arrangement of storing the third matrix of the third dimension in the first cache. In other words, the first data arrangement method and the target data arrangement method are data arrangements of matrices of different dimensions stored in the first cache according to the default storage format.

[0085] Based on this, the above-mentioned S120 is implemented as follows: the first matrix of the first dimension is stored in the first cache according to the data arrangement of the third matrix of the third dimension in the first cache with the default storage format of the first cache; that is, the above-mentioned S120 is implemented by storing the first matrix in the first cache with the data arrangement of the third matrix in the first cache based on the default storage format of the first cache.

[0086] It should be noted that, for ease of explanation, this embodiment of the application takes the content of the first matrix as [{1}, {2}, {3}, {4}], that is, the first dimension of the first matrix is ​​(4, 1), and is referred to as the (4, 1) matrix; and takes the third matrix with the third dimension as the (1, 4) matrix, and the default storage format of the first cache as the NZ storage format as an example for explanation, which will not be repeated hereafter.

[0087] The above NZ storage format is as follows Figure 5 As shown, the NZ storage format is used to represent the storage format of block data; the elements in the matrix of this NZ storage format are stored by dividing the storage area into multiple blocks (e.g., Figure 5 The NZ storage format (shown as a dashed box in the diagram) stores data within a block in a row-major format. After data storage in one block is complete, data is stored in the next block in the same column (e.g., the first column). After all data in all blocks in that column (i.e., the first column) is stored, data is then stored in the first block of the next column (e.g., the second column), and so on, until the entire data matrix is ​​stored.

[0088] Based on this, the data arrangement (i.e., the first data arrangement method) of storing the first matrix (i.e., the (4,1) matrix) in the first cache in NZ storage format is as follows: Figure 6As shown, after arranging element "1" in the first storage unit, invalid data X is inserted in the next storage unit in the same row; however, jumping to the next row, element "2" and invalid data are inserted in different storage units in turn, and so on until the elements in the entire first matrix are arranged. It can be seen that storing the above first matrix in the first cache in NZ storage format requires 3 jumps.

[0089] When the elements contained in the third matrix are exactly the same as those in the first matrix, the elements contained in the third matrix are [{1, 2, 3, 4}]. Since the third matrix is ​​a (1, 4) matrix, the data arrangement of the third matrix stored in the first cache in NZ storage format (i.e., the target data arrangement) is as follows. Figure 7 As shown; after inserting elements "1" and "2" into two consecutive storage units in the first row, jump to the next row and insert two invalid data X; then, after inserting elements "3" and "4" into the two storage units adjacent to element "2" in the first row, jump to the next row again and insert two invalid data X; it can be seen that storing the third matrix of the third dimension in the first cache in NZ storage format requires 2 jumps.

[0090] In summary, when the first matrix of the first dimension is stored in the first cache in the target data arrangement method in the above-mentioned S120, the data arrangement of the first matrix in the first cache is the same as the data arrangement of the third matrix of the third dimension containing the same elements stored in the first cache in the default storage format of the first cache; that is, the above-mentioned S120 stores the first matrix of the first dimension in the first cache according to the data arrangement of the matrix of the different dimension stored in the first cache in the NZ storage format.

[0091] Specifically, the above-mentioned S120 can be implemented by directly storing the first matrix into the first cache based on the target data arrangement, or by converting the first matrix into a third matrix and then storing the converted third matrix into the first cache in NZ storage format. The specific implementation of this application does not limit it.

[0092] It should be understood that the fewer jumps there are during the process of writing (storing) data into the cache, the higher the efficiency of writing the data; and then, when the first matrix in the first dimension and the third matrix in the third dimension contain the same elements, the efficiency of writing the third matrix into the first cache is higher than the efficiency of writing the first matrix into the first cache.

[0093] In addition, such as Figure 6As shown, in the first data arrangement, invalid data X is inserted intermittently between two consecutive elements. Therefore, when reading data based on the first data arrangement, invalid data X will be read once after each element is read. In the case that the contents of the first matrix are [{1}, {2}, {3}, {4}], there will be 4 instances of invalid data X being read. In the case of... Figure 6 In the target data arrangement shown, because the two elements are arranged consecutively, invalid data X will be read once every time two consecutive elements are read. This is then applied to the first matrix described above. Figure 6 After storing the data in the target data arrangement method, there will be two instances of invalid data X being read. In other words, for the first matrix, the number of times invalid data is read using the target data arrangement method is less than the number of times invalid data is read using the first data arrangement method. This means that the read conflict situation of the target data arrangement method is less severe than that of the first data arrangement method. Consequently, the read efficiency of the first matrix stored using the target data arrangement method is higher than that of the first matrix stored using the first data arrangement method.

[0094] For example, after storing a first matrix containing [{1}, {2}, {3}, {4}] in a first cache according to the target data arrangement, the data arrangement of the elements in the first matrix in the first cache is as follows: Figure 7 As shown.

[0095] It should be understood that the (4,1) and (1,4) matrices mentioned above are merely examples. They can be (x,1) and (1,x) matrices, or matrices of other dimensions. In the case where the first dimension is (x,1) and the default storage format of the first cache is NZ storage, the above target data arrangement method is to store the matrix of the third dimension in the data arrangement of the first cache according to the default storage format of the first cache. Here, the third dimension is (1,x), and x is an integer greater than 1.

[0096] Optionally, in another implementation, the target data arrangement described above involves storing the first matrix in the first cache using a target storage format that differs from the default storage format of the first cache. Therefore, the implementation of S120 is as follows: the first matrix is ​​stored in the first cache using the target storage format.

[0097] In the data processing method provided in the above embodiments, since the first matrix is ​​stored in the first cache based on a target data arrangement method with better performance, the read and write efficiency of the first matrix in the first cache is improved. Furthermore, since the read and write efficiency of the first matrix in the first cache is improved, the efficiency of moving the first matrix from the first cache to the next cache is also improved. Therefore, the computational efficiency of the first matrix is ​​improved.

[0098] based on Figure 4The data processing method shown in the present application embodiment provides another data processing method, such as... Figure 8 As shown, the method includes: S210-S250.

[0099] S210, The processing kernel obtains the first dimension of the first matrix to be loaded into the first cache.

[0100] It should be noted that the implementation method of S210 is the same as that of S110. For a detailed description of S210, please refer to the relevant description of S110 above. It will not be repeated here.

[0101] S220. The processing core determines the target data arrangement method based on the first dimension.

[0102] The above S220 is implemented as follows: determine the target data arrangement method corresponding to the first dimension from the correspondence between the dimensions of the matrix and the expected data arrangement method.

[0103] It should be noted that the performance of the expected data arrangement method corresponding to the second dimension in the above correspondence is better than the second data arrangement method; wherein, the second dimension is any dimension in the above correspondence, and the second data arrangement method is the data arrangement of storing the second matrix of the second dimension in the first cache according to the default storage format of the first cache (such as: NZ storage format).

[0104] For example, suppose the above correspondence is as shown in Table 1 below, including the dimensions of two matrices and two expected data arrangement methods. The dimensions of the two matrices include (4, 1) and (6, 5) dimensions; the two expected data arrangement methods include: storing the (1, 4) dimension matrix in the cache according to the NZ storage format, abbreviated as (1, 4)-NZ; storing the (6, 8) dimension matrix in the cache according to the NZ storage format, abbreviated as (6, 8)-NZ. Among them, the expected data arrangement method corresponding to the (4, 1) dimension is (1, 4)-NZ; the expected data arrangement method corresponding to the (6, 5) dimension is (6, 8)-NZ. Then, when the first dimension of the first matrix is ​​(4, 1), (1, 4)-NZ is determined as the expected data arrangement method (i.e., the target data arrangement method) of the first matrix.

[0105] Table 1

[0106] Dimensions of a matrix Expected data arrangement (4，1) (1,4)-NZ (6，5) (6,8)-NZ

[0107] Optionally, the above S220 can be implemented as follows: input the first dimension into the training model, and then use the data arrangement output by the training model as the target data arrangement.

[0108] The above training model is a model trained using multiple matrix dimensions as training data. The labels of the training data are the expected data arrangement corresponding to the training data. For the specific training process, please refer to the relevant technologies, which will not be repeated here.

[0109] S230, Processing kernel determines whether there is a target data arrangement method.

[0110] It should be understood that if the expected data arrangement corresponding to the first dimension does not exist in the above correspondence, the target data arrangement cannot be obtained from the correspondence, meaning the target data arrangement does not exist. Alternatively, if the first dimension is input into the training model and the training model does not output a data arrangement, or if the output data arrangement is the first data arrangement, then it is determined that the target data arrangement does not exist.

[0111] If the above target data arrangement exists, execute S240 as follows.

[0112] If the above target data arrangement method does not exist, execute S250 as follows.

[0113] S240, The processing core stores the first matrix in the first cache in the target data arrangement.

[0114] It should be noted that the implementation method of S240 is the same as that of S120. For a detailed description of S240, please refer to the relevant description of S120 above. It will not be repeated here.

[0115] S250, The processing core stores the first matrix in the first cache in the first data arrangement.

[0116] It should be noted that the implementation method of S250 is the same as that of S120. For a detailed description of S250, please refer to the relevant description of S120 above. It will not be repeated here.

[0117] In the above implementation, the processing kernel obtains the dimension of the first matrix (i.e., the first dimension) and determines the target data arrangement method based on the first dimension, so that the first matrix is ​​stored in the first cache in the target data arrangement method. Since the above method stores the first matrix in the first cache based on the target data arrangement method with better performance, it improves the read and write efficiency of the first matrix in the first cache, thereby improving the efficiency of moving the first matrix from the first cache to the next cache, and thus improving the operation efficiency of the first matrix.

[0118] It should be understood that, if the first cache mentioned above is not the cache used for processing matrix operations (i.e., the last level cache), after S240 or S250, the processing core still needs to move the first matrix stored in the first cache (e.g., L1 cache) to the next level cache, specifically as follows: Figure 9 As shown, it includes: S310.

[0119] S310, The processing core stores the first matrix stored in the first cache into the second cache according to the default storage format of the second cache.

[0120] The multi-level cache in the aforementioned processor includes a second cache, which is the next level cache after the first cache, meaning that the performance of the second cache is better than that of the first cache.

[0121] It should be noted that the default storage format of the second cache may be the same as or different from the default storage format of the first cache. The specific embodiments of this application do not limit it.

[0122] For example, if the default storage format of the second cache may be different from the default storage format of the first cache, and the processor is an Ascend processor and the first cache is an L1 cache, the second cache is an L0 cache, and the default storage format of the second cache is a ZZ storage format or a ZN storage format.

[0123] Among them, the ZZ storage format is as follows Figure 10 As shown, the ZZ storage format uses a storage method that divides the storage area into multiple blocks (such as...). Figure 10 The ZZ storage format (shown as a dashed box in the diagram) stores the matrix data in the first block of the first row (referred to as the first block) using a row-major storage method. After the first sub-row of the first block is full, the second sub-row of the first block stores the matrix data, and so on, until the first block is full. After the first block is full, the first sub-row of the next block in the first row (i.e., the second block) stores the data, and so on, until all blocks in the row containing the first and second blocks (i.e., the first row) are full. Then, the first block of the second row stores the elements, and so on, until all the data in the entire matrix is ​​stored.

[0124] The above ZN storage format is as follows: Figure 11 As shown, the ZN storage format is as follows: the storage area is divided into multiple blocks (such as...). Figure 11The ZN storage format (shown as a dashed box in the diagram) stores the matrix data in the first block of the first row (referred to as the first block) using a column-major storage method. After storing data in the first column of the first block, data is stored in the second column of the first block, and so on, until the first block is completely stored. After storing data in the first block, data is stored in the first column of the second block of the first row, and so on, until all blocks in the row containing the first and second blocks (i.e., the first row) have stored data. Then, data is stored in the first block of the second row, and so on, until all data in the entire matrix has been stored.

[0125] The above-mentioned implementation method of S310 is as follows: Figure 12 As shown, it includes: S311-S312.

[0126] S311, The processing core retrieves the first matrix from the first cache.

[0127] The above-mentioned S311 is implemented by the processing core reading the first matrix from the first cache. For the specific implementation, please refer to S420-S450 below, which will not be repeated here.

[0128] S312. The processing core stores the first matrix into the second cache according to the third data arrangement method.

[0129] The aforementioned third data arrangement method can be a data arrangement method with better performance than the fourth data arrangement method, or it can be the fourth data arrangement method. The fourth data arrangement method is a data arrangement method in which the first matrix is ​​stored in the second cache according to the default storage format of the second cache.

[0130] It should be noted that when the performance of the third data arrangement method is better than that of the fourth data arrangement method, the third data arrangement method is determined based on the first dimension. Its specific implementation is similar to that of S220. Please refer to the relevant description in S220 for details, which will not be repeated hereafter.

[0131] It should be understood that the aforementioned third data arrangement method can be the same as or different from the aforementioned target data arrangement method. Specifically, if the default storage format of the first cache is different from the default storage format of the second cache, the aforementioned third data arrangement method will be different from the target data arrangement method. If the default storage format of the first cache is the same as the default storage format of the second cache, the aforementioned third data arrangement method can be the same as or different from the target data arrangement method.

[0132] It should be noted that the implementation of S312 is similar to that of S120. For a detailed description of S312, please refer to the relevant description of S120 above. It will not be repeated here.

[0133] In the above embodiment, after storing the first matrix in the first cache in the target data arrangement, the processing core retrieves the first matrix from the first cache and stores it in the second cache in the third data arrangement. Since the performance of the target data arrangement is better than that of the first data arrangement, the efficiency of retrieving the first matrix from the first cache is improved; thereby, the efficiency of moving the first matrix from the first cache to the second cache is improved, thus improving the computational efficiency of the first matrix.

[0134] based on Figure 8 The data processing method shown in this application provides a specific implementation method, such as... Figure 13 As shown, the method further includes S410-S460 after S240.

[0135] S410, The processing core marks the transformation state of the first matrix stored in the first cache as transformed.

[0136] The aforementioned conversion states include: a converted state or an unconverted state; wherein, the converted state indicates that the first matrix is ​​not stored in the first cache in the first data arrangement; and the unconverted state indicates that the first matrix is ​​stored in the first cache in the first data arrangement.

[0137] S420: The processing core retrieves the third matrix stored in the target data arrangement from the first cache.

[0138] It should be noted that in the above S120, the processing core stores the first matrix in the first cache with the data arrangement of the third matrix stored in the first cache according to the NZ storage format; that is, when the first matrix of the first dimension is stored in the first cache in the above S120 with the target data arrangement, the data arrangement of the first matrix in the first cache is the same as the data arrangement of the third matrix of the third dimension containing the same elements stored in the first cache in the NZ storage format (e.g., both are as follows). Figure 6 (As shown).

[0139] Based on this, since the target data arrangement method is to store the third matrix in the first cache according to the default storage method of the first cache, after the first matrix is ​​stored in the first cache in the target data arrangement method, the matrix stored in the target data arrangement method that the processing core reads from the first cache is the third matrix with the third dimension.

[0140] S430, The processing kernel determines whether the transformation state of the third matrix is ​​a transformed state.

[0141] If the transformation state of the third matrix mentioned above is untransformed, the processing core executes S440.

[0142] If the transformation state of the third matrix mentioned above is a transformed state, the processing core executes the following S450.

[0143] S440 The processor stores the third matrix in the second cache according to the third data arrangement.

[0144] It should be noted that the implementation of S440 is the same as that of S120. For a detailed description of S440, please refer to the relevant description of S120 above. It will not be repeated here.

[0145] S450, the processing core converts the third matrix into the first matrix.

[0146] The above transformation operations include at least one operation such as transpose, padding with invalid values ​​(e.g., padding with zeros), and removing invalid values; wherein, the transpose operation is the operation of swapping the row dimension and column dimension of the matrix.

[0147] For example, if the first matrix is ​​a (4, 1) matrix and the third matrix is ​​a (1, 4) matrix, the third matrix can be transposed to the first matrix.

[0148] S460: The processing core stores the first matrix in the second cache according to the third data arrangement method.

[0149] It should be noted that the implementation method of S460 is the same as that of S120. For a detailed description of S460, please refer to the relevant description of S120 above. It will not be repeated here.

[0150] It should be understood that, in the case where the second cache is a cache for the processor to perform matrix operations, after S460, the following is also included: the processing core performs matrix operations based on the first matrix in the second cache.

[0151] In the above embodiment, after storing the first matrix in the first cache in the target data arrangement, during the process of moving the first matrix from the first cache to the second cache, the third matrix stored in the target data arrangement is obtained from the first cache, and the third matrix is ​​converted back to the first matrix, thereby ensuring the accuracy of the matrix data.

[0152] The foregoing mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, the data processing apparatus includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0153] This application embodiment can, according to the above method, exemplarily divide a data processing device into functional modules. For example, the data processing device may include functional modules corresponding to each functional division, or two or more functions may be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division; in actual implementation, there may be other division methods.

[0154] When dividing each function into modules according to its corresponding function. Figure 14 A schematic diagram of a possible structure of the data processing apparatus involved in the above embodiments is shown. For example... Figure 14 As shown, the data processing device includes a transceiver module 1410 and a storage module 1420.

[0155] The transceiver module 1410 obtains the first dimension of the first matrix to be loaded into the first cache; for example, it executes step S110 in the above method embodiment.

[0156] The storage module 1420 stores the first matrix in the first cache according to the first dimension in the target data arrangement; for example, it executes step S120 in the above method embodiment.

[0157] Optionally, the above data processing device includes: a processing module 1430.

[0158] The processing module 1430 determines the target data arrangement method based on the first dimension; for example, it executes step S220 in the above method embodiment.

[0159] If the target data arrangement exists, the storage module 1420 stores the first matrix in the first cache according to the target data arrangement; for example, it executes step S240 in the above method embodiment.

[0160] Optionally, the processing module 1430 determines the target data arrangement corresponding to the first dimension from the correspondence between the dimensions of the matrix and the expected data arrangement.

[0161] Optionally, the storage module 1420 stores the first matrix stored in the first cache into the second cache according to the default storage format of the second cache; for example, by executing step S310 in the above method embodiment.

[0162] Optionally, the transceiver module 1410 retrieves the first matrix from the first buffer; for example, by executing step S311 in the above method embodiment.

[0163] The storage module 1420 stores the first matrix in the second cache according to the third data arrangement method; for example, it executes step S312 in the above method embodiment.

[0164] Optionally, if the default storage format of the first cache is the same as the default storage format of the second cache, the third data arrangement method is the same as the target data arrangement method.

[0165] Optionally, if the default storage format of the first cache is the same as that of the second cache, the third data arrangement method is different from the target data arrangement method.

[0166] Optionally, if the default storage format of the first cache is different from the default storage format of the second cache, the third data arrangement method is different from the target data arrangement method.

[0167] Optionally, the processing module 1430 marks the transformation state of the first matrix stored in the first cache as a transformed state; for example, by executing step S410 in the above method embodiment.

[0168] The transceiver module 1410 retrieves the third matrix stored in the target data arrangement from the first cache; for example, it executes step S420 in the above method embodiment.

[0169] When the transformation state of the third matrix is ​​already transformed, the processing module 1430 converts the third matrix into the first matrix; for example, it executes step S450 in the above method embodiment.

[0170] Optionally, if the first dimension is (x, 1) and the default storage format of the first cache is NZ storage format, the target data arrangement is to store the matrix of the third dimension in the data arrangement of the first cache according to the default storage format of the first cache; where the third dimension is (1, x) and x is an integer greater than 1.

[0171] This application provides a processor for running a program, wherein the program executes the method described in the above embodiments.

[0172] This application provides a computing device including a memory and at least one processor connected to the memory. The memory is used to store computer program code, which includes computer instructions. When the computer instructions are executed by the at least one processor, the computing device performs the method described in the above embodiments.

[0173] This application provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, perform the methods described in the above embodiments.

[0174] This application provides a computer program product containing computer instructions that, when executed on a computer, perform the methods described in the above embodiments.

[0175] This application provides a chip including a memory and a processor. The memory stores computer instructions, and the processor retrieves and executes the computer instructions from the memory to perform the methods described in the above embodiments.

[0176] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0177] Through the above description of the embodiments, those skilled in the art will clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0178] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0179] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0180] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0181] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as flash memory, portable hard disk, read-only memory, random access memory, magnetic disk, or optical disk.

[0182] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized by, A method for loading a matrix in a multi-level cache; the method comprises: obtaining a first dimension of a first matrix to be loaded into a first cache; wherein the first dimension is a dimension of the first matrix; and the first cache is any cache in the multi-level cache; storing the first matrix into the first cache according to the first dimension and in a target data arrangement; wherein a performance of the target data arrangement is superior to that of a first data arrangement, and the first data arrangement is a data arrangement of storing a matrix of the first dimension into the first cache according to a default storage format of the first cache.

2. The method of claim 1, wherein, The storing the first matrix into the first cache according to the first dimension and in a target data arrangement comprises: determining the target data arrangement according to the first dimension; in a case where the target data arrangement exists, storing the first matrix into the first cache in the target data arrangement.

3. The method of claim 2, wherein, The determining the target data arrangement according to the first dimension comprises: determining the target data arrangement corresponding to the first dimension from a correspondence relationship between dimensions of matrices and expected data arrangements; wherein a performance of an expected data arrangement corresponding to a second dimension in the correspondence relationship is superior to that of a second data arrangement, and the second data arrangement is a data arrangement of storing a second matrix of the second dimension into the first cache according to the default storage format of the first cache.

4. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: storing the first matrix stored in the first cache into a second cache according to a default storage format of the second cache; wherein the multi-level cache comprises the second cache, and a performance of the second cache is higher than that of the first cache.

5. The method of claim 4, wherein, The storing the first matrix stored in the first cache into the second cache according to the default storage format of the second cache comprises: obtaining the first matrix from the first cache; storing the first matrix into the second cache according to a third data arrangement.

6. The method of claim 5, wherein: in a case where the default storage format of the first cache is identical to that of the second cache, the third data arrangement is identical to the target data arrangement.

7. The method of claim 5, wherein: in a case where the default storage format of the first cache is identical to that of the second cache, the third data arrangement is different from the target data arrangement.

8. The method of any one of claims 5-7, wherein: in a case where the default storage format of the first cache is different from that of the second cache, the third data arrangement is different from the target data arrangement.

9. The method of claim 5, wherein, after the storing the first matrix into the first cache according to the first dimension and in a target data arrangement, the method further comprises: mark a conversion state of the first matrix stored in the first cache as a converted state; wherein the conversion state comprises a converted state or an unconverted state; the obtaining the first matrix from the first cache comprises: obtaining, from the first cache, a third matrix stored in the target data arrangement manner; in a case where a conversion state of the third matrix is the converted state, converting the third matrix into the first matrix.

10. The method of any one of claims 1-9, wherein, in a case where the first dimension is (x, 1) and a default storage format of the first cache is an NZ storage format, the target data arrangement manner is a data arrangement of storing a third dimension matrix into the first cache according to the default storage format of the first cache; wherein the third dimension is (1, x), and x is an integer greater than 1.

11. A data processing apparatus, characterized by, The data processing apparatus for loading a matrix in a multi-level cache; the data processing apparatus comprises a transceiver module and a storage module; the transceiver module is configured to obtain a first dimension of a first matrix to be loaded into a first cache; wherein the first dimension is a dimension of the first matrix; and the first cache is any cache in the multi-level cache; the storage module is configured to store the first matrix into the first cache in a target data arrangement manner according to the first dimension; wherein a performance of the target data arrangement manner is superior to that of a first data arrangement manner, and the first data arrangement manner is a data arrangement of storing a matrix of the first dimension into the first cache according to a default storage format of the first cache.

12. The data processing apparatus according to claim 11, characterized by The data processing apparatus further comprises a processing module; the processing module is configured to determine the target data arrangement manner according to the first dimension; the storage module is configured to store the first matrix into the first cache in the target data arrangement manner in a case where the target data arrangement manner exists.

13. The data processing apparatus of claim 12, wherein the processing module is configured to determine the target data arrangement manner corresponding to the first dimension from a correspondence relationship between dimensions of a matrix and expected data arrangement manners; wherein a performance of an expected data arrangement manner corresponding to a second dimension in the correspondence relationship is superior to that of a second data arrangement manner, and the second data arrangement manner is a data arrangement of storing a second matrix of the second dimension into the first cache according to a default storage format of the first cache.

14. The data processing apparatus of any one of claims 11-13, wherein the storage module is configured to store the first matrix stored in the first cache into a second cache according to a default storage format of the second cache; wherein the multi-level cache comprises the second cache, and a performance of the second cache is higher than that of the first cache.

15. The data processing apparatus of claim 14, wherein the transceiver module is configured to obtain the first matrix from the first cache; The storage module is configured to store the first matrix into the second cache according to a third data arrangement mode. 16.The data processing apparatus of claim 15, wherein, in a case where the default storage format of the first cache is the same as the default storage format of the second cache, the third data arrangement mode is the same as the target data arrangement mode. 17.The data processing apparatus of claim 15, wherein, in a case where the default storage format of the first cache is the same as the default storage format of the second cache, the third data arrangement mode is different from the target data arrangement mode. 18.The data processing apparatus of any one of claims 15-17, wherein, in a case where the default storage format of the first cache is different from the default storage format of the second cache, the third data arrangement mode is different from the target data arrangement mode. 19.The data processing apparatus of claim 15, wherein, the processing module is configured to mark a conversion state of the first matrix stored in the first cache as a converted state, wherein the conversion state comprises a converted state or an unconverted state; the transceiving module is configured to acquire a third matrix stored in the first cache in the target data arrangement mode; the processing module is further configured to convert the third matrix into the first matrix in a case where the conversion state of the third matrix is the converted state. 20.The data processing apparatus of any one of claims 11-19, wherein, in a case where the first dimension is (x, 1) and the default storage format of the first cache is an NZ storage format, the target data arrangement mode is a data arrangement of storing a third dimension matrix into the first cache according to the default storage format of the first cache, wherein the third dimension is (1, x) and x is an integer greater than 1.

21. A processor, comprising: The processor is configured to run a program, wherein the program, when executed, performs the method of any one of claims 1-10.

22. A server, comprising: A server includes a memory and at least one processor connected with the memory, the memory is configured to store computer program code, the computer program code includes computer instructions, when the computer instructions are executed by the at least one processor, the server performs the method of any one of claims 1-10.

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