Advanced CE Coding for Bus Multiplexer Grids for SSDs

Abstract

The present disclosure generally relates to a method and apparatus for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected to the FIM in series or in parallel. Each bus multiplexer can be addressed by a chip enable (CE) command that identifies a specific bus multiplexer and a specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without generating signal interference (SI) or limiting transmission performance.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a method and apparatus for accessing more dies per channel in a data storage device. Background Art

[0002] When scaling client SSD architectures to entry-level enterprise architectures, supporting high-capacity configurations is problematic. Specifically, there are issues with NAND selection and high capacitive loading due to multiple dies in parallel, which leads to signal integrity issues.

[0003] Regarding NAND selection, a typical high-end controller has 8 NAND channels, called Flash Interface Modules (FIMs). Each FIM has two chip enable pins (CEs) that allow the selection of two NAND groups. Due to space limitations, the maximum capacity of a die is, for example, eight dies. As the demand for higher capacity continues to increase, the controller should support more dies per FIM. However, application-specific integrated circuits (ASICs) are limited to 2 CEs.

[0004] Regarding capacitive loading, in order to support the required host performance, the transmission speed should be limited to the limit. Due to signal integrity (SI) issues, the maximum number of dies "connected" to a channel cannot exceed a certain number of dies, such as eight dies. In some cases, fewer dies may produce severe SI problems and limit transmission performance.

[0005] Therefore, there is a need in the art to access more dies per channel in a data storage device while maintaining SI and not limiting transfer performance. Summary of the invention

[0006] The present disclosure generally relates to a method and apparatus for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected to the FIM in series or in parallel. Each bus multiplexer can be addressed by a chip enable (CE) command that identifies a specific bus multiplexer and a specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without generating signal interference (SI) or limiting transmission performance.

[0007] In one embodiment, a data storage device includes: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to one or more memory devices among the plurality of memory devices; and a flash memory interface module coupled to the plurality of bus multiplexers; and a controller coupled to the flash memory interface module, wherein the controller is configured to: send a chip enable command through the flash memory interface controller, wherein the chip enable command includes a bus multiplexer identifier and a memory device identifier.

[0008] In another embodiment, a data storage device includes: a controller; a plurality of flash memory interface modules coupled to the controller; a plurality of bus multiplexers coupled to at least a first flash memory interface module among the plurality of flash memory interface modules; and a plurality of memory devices coupled to a first bus multiplexer among the plurality of bus multiplexers, wherein the controller is configured to: send a first signal to the first flash memory interface module; send a second signal to the first flash memory interface module, wherein the second signal is lower than the first flash memory signal; and send a command signal to the first flash memory interface module, wherein the first signal, the second signal, and the command signal are different.

[0009] In another embodiment, a data storage device includes: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to at least one memory device among the plurality of memory devices; a flash memory interface module coupled to the plurality of bus multiplexers; and an apparatus for delivering a chip enable command signal to a first memory device among the plurality of memory devices, wherein the chip enable command signal includes a bus multiplexer identifier and a memory device identifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order that the manner in which the above-mentioned features of the present disclosure can be understood in detail, the present disclosure briefly summarized above may be described in more detail by reference to embodiments, some examples of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure, and therefore the drawings should not be considered as limiting its scope, as the present disclosure may admit of other equally effective embodiments.

[0011] Figure 1 is a schematic block diagram illustrating a storage system according to one or more techniques of this disclosure, in which a storage device can be used as a storage device of a host device.

[0012] Figure 2 is a schematic diagram of a standard solution for maximizing FIM capacity according to one embodiment.

[0013] Figure 3 is a schematic diagram showing a standard system of connections between a FIM and a memory device.

[0014] Figure 4 is a schematic diagram of a solution for maximizing FIM capacity according to one embodiment.

[0015] Figure 5 Is implemented Figure 4 Schematic diagram of .

[0016] Figure 6 is a graph showing the command state diagram and the timing of the high signal.

[0017] Figure 7 is a graph showing the command status diagram and the timing of the low signal.

[0018] Figure 8 is a flow chart illustrating a method of operating a device that maximizes FIM capacity.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0020] Hereinafter, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. On the contrary, no matter whether any combination of the following features and elements is related to different embodiments, it can be considered to implement and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages over other possible solutions and / or prior art, whether a specific advantage is achieved by a given embodiment does not limit the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely exemplary and should not be regarded as elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to the "present disclosure" should not be interpreted as a generalization of any inventive subject matter disclosed herein, and should not be regarded as elements or limitations of the appended claims unless expressly stated in the claims.

[0021] The present disclosure generally relates to a method and apparatus for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected to the FIM in series or in parallel. Each bus multiplexer can be addressed by a chip enable (CE) command that identifies a specific bus multiplexer and a specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without generating signal interference (SI) or limiting transmission performance.

[0022] Figure 1 1 is a schematic block diagram illustrating a storage system 100 in accordance with one or more techniques of this disclosure, in which a data storage device 106 can be used as a storage device for a host device 104. For example, the host device 104 can utilize a non-volatile memory 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 can include multiple data storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that collectively act as a mass storage device for the host device 104.

[0023] The storage system 100 includes a host device 104 that can store data to and / or retrieve data from one or more storage devices, such as a data storage device 106. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., handheld) computer, a tablet computer, a set-top box, a telephone handset (such as a so-called "smart" phone), a so-called "smart" keyboard, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, etc.

[0024] Data storage device 106 includes controller 108, non-volatile memory 110 (NVM 110), power supply 111, volatile memory 112, and interface 114. Controller 108 includes internal memory or buffer (not shown). In some examples, data storage device 106 may include additional components, which are not shown in the figure for clarity. Figure 1These additional components are not shown in the figure. For example, the data storage device 106 may include a printed board (PB) to which the components of the data storage device 106 are mechanically attached, and the printed board includes conductive traces, etc. that electrically interconnect the components of the data storage device 106. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, a 3.5-inch data storage device (e.g., HDD or SSD), a 2.5-inch data storage device, a 1.8-inch data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), a PCI Express (PCIe) (e.g., PCIex1, x4, x8, x16, PCIe mini card, mini PCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered) to the motherboard of the host device 104.

[0025] The interface 114 of the data storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The electrical connection (e.g., data bus, control bus, or both) of the interface 114 is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, thereby allowing data to be exchanged between the host device 114 and the controller 108. In some examples, the electrical connection of the interface 114 may also permit the data storage device 106 to receive power from the host device 104. For example, Figure 1 As shown, power supply 111 may receive power from host device 104 via interface 114 .

[0026] The data storage device 106 includes an NVM 110, which may include multiple memory devices or memory cells. The NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of the NVM 110 may receive data and a message from the controller 108 indicating that the memory cell stores data. Similarly, a memory cell of the NVM 110 may receive a message from the controller 108 indicating that the memory cell retrieves data. In some examples, each memory cell may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0027] In some examples, each memory cell of NVM 110 may include any type of nonvolatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of nonvolatile memory device.

[0028] NVM 110 may include multiple flash memory devices or memory cells. Flash memory devices may include NAND or NOR-based flash memory devices, and data may be stored based on the charge contained in the floating gate of the transistor of each flash memory cell. In NAND flash memory devices, the flash memory device may be divided into multiple blocks, and the blocks may be divided into multiple pages. Each block in the multiple blocks within a specific memory device may include multiple NAND cells. The rows of NAND cells may be electrically connected using word lines to define one page in multiple pages. Each cell in each page of the multiple pages may be electrically connected to a corresponding bit line. In addition, the NAND flash memory device may be a 2D or 3D device, and may be a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC). The controller 108 may write data to and read data from the NAND flash memory device at the page level, and may erase data from the NAND flash memory device at the block level.

[0029] The data storage device 106 includes a power supply 111 that can provide power to one or more components of the data storage device 106. When operating in standard mode, the power supply 111 can use power provided by an external device such as the host device 104 to provide power to the one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to provide power to one or more components. In some examples, the power supply 111 may include one or more power storage components that are configured to provide power to the one or more components when operating in a shutdown mode, such as when power is not received from an external device. In this way, the power supply 111 can be used as an onboard backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0030] The data storage device 106 also includes a volatile memory 112 that the controller 108 can use to store information. The volatile memory 112 can include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 can store cached information in the volatile memory 112 until the cached information is written to the non-volatile memory 110. Figure 1 As shown, the volatile memory 112 may consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0031] The data storage device 106 includes a controller 108 that can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory before sending the data to the NVM 110. The controller 108 can also include eight NAND channels, each of which can be considered a flash interface module (FIM) (not shown). The number of NAND channels listed is not intended to be limiting, and the controller 108 can include more or fewer NAND channels than the number of NAND channels listed.

[0032] Figure 2 is a schematic diagram of a standard solution for maximizing FIM capacity according to one embodiment. Each FIM has two chip enable (CE) pins. Each CE pin is associated with a NAND group. The maximum NAND group capacity can be eight dies. Therefore, a FIM can have a total of 2 dies, where 8 FIMs have a total of 16 dies. The maximum values ​​listed are not intended to be limiting, and other embodiments exist. To increase the capacity of a memory device, a controller (such as Figure 1 The controller 108 of the embodiment of the present invention needs to support more tube cores for each FIM. However, the tube cores added by each FIM can cause high capacitive load, which can reduce the reliability of the memory device. In addition, high capacitive load can cause signal integrity (SI) to decline and limit TM performance. However, the problem of high capacitive load can be solved by including a bus multiplexer (BM) that divides a single channel into four sub-channels. The bus multiplexer divides the tube cores of the total number of each channel into sub-channels.

[0033] Data storage devices (such as Figure 1 The data storage device 106 may include a controller (such as a Figure 1Controller 108 of the ASIC). The ASIC may include a flash interface module and communicate with the DRAM. Each subchannel in the ASIC may be selected by coding the CE of the ASIC. CE is an input that, when true, permits active operations including data I / O; when false, it blocks active operations and places the memory in a low-power standby mode with the output floating. By combining CE with the ASIC, high capacitive loads may be reduced, thereby achieving better reliability with larger memory capacities.

[0034] Figure 2 An ASIC including eight FIMs (denoted as FIM0-FIM7) is depicted. Each FIM is associated with a BM that divides each channel into four sub-channels. Each sub-channel is associated with a NAND group that may include one or more NAND dies. However, since the ASIC is limited to two CEs, the sub-channels are grouped into two groups. For example, FIM0 is associated with the following sub-channels: CH0 and CH1. By combining the BMs, the maximum die capacity is 8FIM*4 dies / FIM=32 dies. In addition, the bus multiplexing architecture can allow an eight FIM system to contain more than 32 dies (such as 1024 dies).

[0035] Figure 3 is a schematic diagram showing a standard system of connections between a FIM and a memory device. The memory device may be Figure 1 The non-volatile memory of the FIM and may include a NAND package. Each NAND package includes a NAND stack, and each NAND stack is associated with a CE pin. In order to determine whether a read or write references the correct NAND stack, the CE control must be decoded. CEn<1:0> is a 2-bit signal that corresponds to the two CE pins of each available FIM. The following table describes an example of CE control to NAND group decoding.

[0036] surface

[0037]

[0038] The FIM architecture uses a 16-bit signal to communicate with the bus multiplexer to determine the location of the read command or write command in the NAND. The signal travels from the FIM to the BM along a high-speed channel. Since the BM is limited by two chip enables, there are four sub-channels due to the four unique combinations of two-bit signals. In addition, the line decoder takes an n-bit binary number and decodes it into 2^n data lines. The decoder in the BM is a 4 to 16 data line decoder, in which each of the four CE controls is associated with 4 bits, allowing a total of 16 different data bit combinations. Groups of 4 data bits are associated with NAND groups, as shown in the table above, such as NAND GR0 is associated with CEn0(0), CEn1(1), CEn2(1) and CEn3(1). In addition, in order to obtain the data bit, the ASICFIMx is associated with a 2-bit signal corresponding to the BM. For example, the ASIC FIMx of CEn1(0) and CEn0(0) corresponds to BM A. Since the bit data from the decoder corresponds to bits CEn0(0) and CEn1(1) of NAND package 1 and CEn2(1) and CEn3(1) of NAND package 2, BMA corresponds to NAND GR0.

[0039] Figure 4 Schematic diagram of a solution to maximize FIM capacity according to one embodiment. In order to access more dies on each channel and optionally scale the performance or capacity of the test and maintenance (TM) bus architecture, BMs can be connected to the same FIM in parallel or series. Each BM can have n sub-channels. In addition, an ASIC FIMx can have m BMs. Similarly, there can be x ASIC FIMs. The CE architecture allows multiple BMs to be connected in series without high capacitive loading issues. The CE selects a specific BM to be used for data transfer, while the remaining BMs are in idle or low power mode.

[0040] In addition, every n sub-channels is a NAND group. The NAND group can be scaled by capacity, where it can include but is limited to about 8 NAND dies. If the NAND group is scaled by performance, the NAND group can include but is not limited to about 2 NAND dies. For both the NAND group scaled by capacity and the NAND group scaled by performance, a single CE configuration may be required. A single CE may have the ability to select up to but not limited to about 1024 dies per channel.

[0041] Figure 5 Is implemented Figure 4Schematic diagram of . To select a specific subchannel for a read command or a write command, FIMx sends a unique command "CE command" that corresponds to the encoded BM identifier and the NAND group identifier. The combination of identifiers is composed of the data bits in each BM in series. The size of the "CE command" can be approximately 8 bits. The size of the "CE command" is not intended to be limiting. The "CE command" is a code word such as "01h".

[0042] The first number from the first signal corresponds to a BM identifier, where "0" is associated with bus multiplexer 0. The second number from the second signal corresponds to a NAND group number, where "1" is associated with NAND GR1. In this example, the number of subchannels is 2 (i.e., n=2), which corresponds to two NAND groups (NAND GR0 and NAND GR1). In addition, the number of BMs is 8 (i.e., m=8).

[0043] In addition, the code word "71h" refers to BM7 (i.e., the eighth BM in the sequence) and NAND GR1. When a CE command is sent from ASIC FIMx, the unrelated BM ignores the command. The CE command is passed from BM to BM so that the command proceeds sequentially to the target BM and NAND group.

[0044] Each BM is assigned an ID or codeword either statically or after discovery (which can be at system power-up). One benefit of commanding an ID or codeword is that the ID or codeword is compatible with or generated by the FIM process that interfaces with the NAND. Due to the "CE command", compatibility can be used for standard NAND devices. In addition, compatibility can achieve flexibility in hardware and firmware design at many capacity points with or without BM. When the corresponding BM and NAND group receive the "CE command", the relevant data is selected, and the other NAND groups and BMs are idle.

[0045] Figure 6 is a graph showing the command state diagram and the timing of the high signal. The high signal corresponds to the BM address. The high signal is associated with the BM address, so the signal may not involve multiple processes (such as when NANDs share the same data bus, or when firmware and / or hardware is used in a multi-capacity configuration with or without BM).

[0046] Additionally, when the CE command is first received, the NAND location is not selected. The end of the "NAND not selected" period is determined by the first falling edge of ASIC_WEn (i.e., when ASIC_WEn goes low). When ASIC_CLE goes low and the ASIC_CEn signal is high, the start of a period of BM address search is indicated, disabling NAND access. During this period, the ASIC_CLE signal is also high. A high ASIC_CEn signal corresponds to a BM address that is dependent on the first signal (i.e., the signal strength determines the BM address). The BM address can be Figure 5 The code word "71h" is "7". "7" refers to the eighth BM, i.e. Figure 5 The end of the BM address search is indicated by the falling edge of ASIC_CLE.

[0047] When ASIC_CEn goes low, the NAND access data line starts, and when ASIC_CEn goes high, the NAND access data line stops. In addition, the strength of the ASIC_CEn1 signal can indicate which NAND group is to be accessed. NAND access is indicated by the second digit in the code word or CE command. For example, the NAND group location can be Figure 5 The code word "71h" is "1". "1" refers to the second NAND group, that is, Figure 5 By utilizing additional address cycles within a NAND command, multiple NAND addresses can be accessed during a NAND access period.

[0048] ASIC_CEn goes high after a read or write command to a NAND location is completed. Since ASIC_CLE is low, ASIC_CEn is high, and ASIC_WEn is high, the NAND is not selected during this time period. Other combinations of signals not listed may work for a read or write command with a high CEn signal.

[0049] Figure 7 is a graph showing the command state diagram and the timing of the low signals. The low CEn signal corresponds to the NAND bank address. When the CE command is first received, the NAND location is not selected. When ASIC_CEn0, ASIC_CEn1, and ASIC_WEn go low and ASIC_CLE goes high, FIMx is accessing the BM address. The high ASIC_CLE signal and the low ASIC_WEn signal can indicate that the BM address can be accessed. The ASIC_CEn signal corresponds to the BM address that depends on the first signal (i.e., the signal strength determines the BM address). The BM address can be Figure 5 The code word "71h" is "7". "7" refers to the eighth BM, i.e. Figure 5 "Bus Multiplexer 7".

[0050] In addition, the end of the BM address period is indicated by the ASIC_CLE falling edge. When addressing a NAND access, ASIC_CEn1 is low. In addition, the strength of the ASIC_CEn1 signal can indicate which NAND bank is to be accessed. The NAND access is indicated by the second digit in the code word or CE command. For example, the NAND bank location can be Figure 5 The code word "71h" is "1". "1" refers to the second NAND group, that is, Figure 5 By utilizing additional address cycles within a NAND command, multiple NAND addresses can be accessed during a NAND access period.

[0051] ASIC_CEn goes high after a read or write command to a NAND location is completed. Since ASIC_CLE is low, ASIC_CEn is high, and ASIC_WEn is high, the NAND is not selected during this time period. Other combinations of signals not listed may work for a read or write command with a low CEn signal.

[0052] Figure 8 8 is a flow chart illustrating a method 800 of operating a device that maximizes FIM capacity. The method 800 may utilize a controller coupled to an ASIC, such as Figure 1 The method 800 may be implemented by a controller 108 of a data storage device 106, the ASIC comprising one or more FIMs coupled to one or more BMs coupled to one or more NAND groups. Figure 4 , Figure 5 , Figure 6 and Figure 7 At block 802, the ASIC sends a CE command signal. The CE command signal may be similar to Figure 5 , Figure 6 and / or Figure 7 After sending the CE command, at block 804, the controller 108 determines whether the data storage device 106 includes a BM in the memory architecture.

[0053] If at block 804 the data storage device 106 does not have BM capabilities, then at block 820, such as Figure 1 The NAND of the NVM 110 ignores the CE command. At block 816, a read command or a write command associated with the CE command is executed on the associated or selected NAND group.

[0054] However, if at block 804 the data storage device 106 does have BM capability, then at block 806 the BM receives a CE command from the ASIC. At block 806, the CE command is decoded, and at block 812, the relevant BM is selected. Figure 6 and Figure 7 As shown, the relevant BM is selected based on the valid part of the CE command signal. The BM address can be Figure 5 The code word "71h" is "7". "7" refers to the eighth BM, i.e. Figure 5 "Bus Multiplexer 7".

[0055] After selecting the BM at block 812, the relevant NAND group is selected at block 814. Similar to the selection of the BM, Figure 6 and Figure 7 As shown, a NAND group is selected based on the valid portion of the CE command signal corresponding to the NAND group selection. For example, the NAND address may be a NAND address whose location may be determined by Figure 5 The "1" of the code word "71h" indicates the first NAND group. "1" refers to the second NAND group, that is, Figure 5 After selecting the BM address at block 812 and selecting the NAND address at block 814 , a read command or a write command is executed on the relevant NAND location at block 816 .

[0056] By addressing a single bus multiplexer, which can be addressed through a chip enable (CE) command that identifies a specific bus multiplexer as well as a specific memory device for a specific bus multiplexer, more dies can be used per channel without generating SI or limiting transfer performance.

[0057] In one embodiment, a data storage device includes: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to one or more memory devices in the plurality of memory devices; and a flash interface module, which is coupled to the plurality of bus multiplexers; and a controller, which is coupled to the flash interface module, wherein the controller is configured to: send a chip enable command through the flash interface controller, wherein the chip enable command includes a bus multiplexer identifier and a memory device identifier. Each bus multiplexer is configured to ignore chip enable commands directed to different bus multiplexers. Each bus multiplexer is configured to direct the chip enable command to a specific memory device coupled thereto. The controller is configured to send the chip enable command as part of a larger command including a read command or a write command. The chip enable command includes 8 bits. The larger command includes a prefix portion, and wherein the chip enable command is between the prefix portion and the read command or the write command within the larger command. The flash interface module is a first flash interface module, wherein the data storage device includes a plurality of flash interface modules, and wherein each of the plurality of flash interface modules is coupled to a plurality of bus multiplexers. The chip enable command is sent along with the bus multiplexer signal and the memory device signal.

[0058] In another embodiment, a data storage device includes: a controller; a plurality of flash memory interface modules coupled to the controller; a plurality of bus multiplexers coupled to at least a first flash memory interface module of the plurality of flash memory interface modules; and a plurality of memory devices coupled to a first bus multiplexer of the plurality of bus multiplexers, wherein the controller is configured to: send a first signal to the first flash memory interface module; send a second signal to the first flash memory interface module, wherein the second signal is lower than the first flash memory signal; and send a command signal to the first flash memory interface module, wherein the first signal, the second signal, and the command signal are different. The first signal identifies the first bus multiplexer. The second signal identifies the first memory device. The plurality of bus multiplexers are connected in parallel to the first flash memory interface module. The plurality of bus multiplexers are connected in series to the first flash memory interface module. The plurality of bus multiplexers are configured to ignore the first signal, the second signal, and the command signal except the first bus multiplexer. Each bus multiplexer has a unique ID number, which is static or given after discovery by the controller.

[0059] In another embodiment, a data storage device includes: a plurality of memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to at least one memory device in the plurality of memory devices; a flash memory interface module coupled to the plurality of bus multiplexers; and means for delivering a chip enable command signal to a first memory device in the plurality of memory devices, wherein the chip enable command signal includes a bus multiplexer identifier and a memory device identifier. The data storage device further includes means for delivering two different signals to the flash memory interface module. The two different signals are different voltages. The flash memory interface module further includes means for ignoring the chip enable command. The data storage device further includes means for permitting the chip enable command to pass through a bus multiplexer in the plurality of bus multiplexers.

[0060] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A data storage device, comprising: multiple memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to one or more memory devices of the plurality of memory devices; a flash memory interface module coupled to the plurality of bus multiplexers; as well as a controller coupled to the flash interface module, wherein the controller is configured to: Sending a chip enable command through the flash memory interface module, wherein: The chip enable command includes a bus multiplexer identifier and a memory device identifier; The chip enable command includes an ASIC_CE signal, an ASIC_CLE signal, and an ASIC_ALE signal, which are used to identify a bus multiplexer among the plurality of bus multiplexers and a memory device among the plurality of memory devices; The ASIC_CE signal has a high portion and a low portion; The ASIC_ALE signal has a high portion and a low portion; The ASIC_CLE signal has a high portion and a low portion; when identifying the bus multiplexer of the plurality of bus multiplexers and the memory device of the plurality of memory devices, the ASIC_ALE signal is the low portion when the ASIC_CE signal is the low portion and the ASIC_CLE signal is the high portion; and The chip enable command is within another command further including a prefix portion and a read command or a write command, wherein the chip enable command is between the prefix portion and the read command or the write command. 2 . The data storage device of claim 1 , wherein each bus multiplexer is configured to ignore a chip enable command directed to a different bus multiplexer. 3 . The data storage device of claim 1 , wherein each bus multiplexer is configured to direct a chip enable command to a specific memory device coupled thereto. 4 . The data storage device of claim 1 , wherein the controller is configured to send the chip enable command as a part of the other command including the read command or the write command. The data storage device of claim 4 , wherein the chip enable command comprises 8 bits.

6. The data storage device of claim 1, wherein the flash memory interface module is a first flash memory interface module, wherein the data storage device comprises a plurality of flash memory interface modules, and wherein each of the plurality of flash memory interface modules is coupled to the plurality of bus multiplexers.

7. The data storage device of claim 1, wherein the chip enable command is sent together with a bus multiplexer signal and a memory device signal.

8. A data storage device comprising: Controller; a plurality of flash memory interface modules coupled to the controller; a plurality of bus multiplexers coupled to at least a first flash interface module of the plurality of flash interface modules; as well as a plurality of memory devices coupled to a first bus multiplexer of the plurality of bus multiplexers, wherein the controller is configured to: Sending a chip enable command to the first flash memory interface module, wherein sending the chip enable command comprises: sending a first signal to the first flash memory interface module; and sending a second signal to the first flash interface module, wherein the second signal is received after the first signal, and wherein the first signal identifies a bus multiplexer among the plurality of bus multiplexers and the second signal identifies a memory device among the plurality of memory devices; and Sending a command signal to the first flash memory interface module, wherein: the first signal, the second signal and the command signal are different, The chip enable command includes an ASIC_CE signal, an ASIC_CLE signal, and an ASIC_ALE signal, which are used to identify a bus multiplexer among the plurality of bus multiplexers and a memory device among the plurality of memory devices; The ASIC_CE signal has a high portion and a low portion; The ASIC_ALE signal has a high portion and a low portion; The ASIC_CLE signal has a high portion and a low portion; when identifying the bus multiplexer of the plurality of bus multiplexers and the memory device of the plurality of memory devices, the ASIC_ALE signal is the low portion when the ASIC_CE signal is the low portion and the ASIC_CLE signal is the high portion; and The chip enable command is within another command further including a prefix portion and the command signal, wherein the chip enable command is between the prefix portion and the command signal.

9. The data storage device of claim 8, wherein the high portion of the ASIC_CE signal identifies the first bus multiplexer.

10. The data storage device of claim 9, wherein the low portion of the ASIC_CE signal identifies a first memory device.

11. The data storage device of claim 8, wherein the plurality of bus multiplexers are connected in parallel to the first flash interface module.

12. The data storage device of claim 8, wherein the plurality of bus multiplexers are connected in series to the first flash interface module.

13. The data storage device of claim 12, wherein the plurality of bus multiplexers, except the first bus multiplexer, are configured to ignore the high portion of the ASIC_CE signal, the low portion of the ASIC_CE signal, and the command signal.

14. The data storage device of claim 8, wherein each bus multiplexer has a unique ID number, the unique ID number being static or given after discovery by the controller.

15. A data storage device comprising: multiple memory devices; a plurality of bus multiplexers, wherein each bus multiplexer is coupled to at least one memory device of the plurality of memory devices; a flash memory interface module coupled to the plurality of bus multiplexers; as well as means for delivering a chip enable command signal to a first memory device of the plurality of memory devices, wherein: The chip enable command includes an ASIC_CE signal, an ASIC_CLE signal, and an ASIC_ALE signal corresponding to a bus multiplexer of the plurality of bus multiplexers and a memory device of the plurality of memory devices; the ASIC_CE signal has a high portion and a low portion; the ASIC_ALE signal has a high portion and a low portion; the ASIC_CLE signal has a high portion and a low portion; when identifying the bus multiplexer in the plurality of bus multiplexers and the memory device in the plurality of memory devices, when the ASIC_CE signal is the low portion and the ASIC_CLE signal is the high portion, the ASIC_ALE signal is the low portion; and The chip enable command is within another command further including a prefix portion and a read command or a write command, wherein the chip enable command is between the prefix portion and the read command or the write command.

16. The data storage device of claim 15, further comprising means for delivering two different signals to the flash interface module.

17. The data storage device of claim 16, wherein the two different signals are different voltages.

18. The data storage device of claim 15, wherein the flash memory interface module further comprises means for ignoring the chip enable command.

19. The data storage device of claim 15, further comprising means for allowing the chip enable command to pass through the bus multiplexer of the plurality of bus multiplexers.

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