Chip startup method, device and electronic equipment

Abstract

The present application provides a chip startup method, device and electronic device, wherein the master chip is connected to multiple slave chips via a serial management interface SMI bus. The chip startup method implemented by the master chip includes: when the master chip controls the startup of the target slave chip, the configuration information is sent through the SMI bus, and the configuration information includes the chip identifier of the target slave chip and the configuration data for starting the target slave chip; the master chip sends software program data through the SMI bus, and the software program data includes the chip identifier of the target slave chip and the software program image file of the target slave chip; the master chip sends a startup address through the SMI bus, so that the target slave chip performs the startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip startup method, device and electronic equipment. Background Art

[0002] With the development of information technology, the board-level integration of hardware products is becoming increasingly higher, and multiple identical or different service processing chips are often integrated on a hardware board. For example, in addition to the main control CPU, the hardware board of a router card will integrate multiple network processing chips (Network Processor, NP) for network forwarding services and switch processing chips (Switch) for network switching services.

[0003] In order to improve the business processing capabilities of products, the degree of specialization of business processing chips will become higher and higher. They are often only focused on business processing, and therefore other functional modules will be configured as little as possible or not at all. For example, NP chips focus on network forwarding services, and functional modules such as startup control are generally not configured in NP chips.

[0004] In order to facilitate control and management and improve the flexibility of functional services, in chip design, the hardware board-level system often exists in the form of master and slave chips. The master chip is generally the main control CPU, which is used to control and manage the entire board level, and the slave chip is generally a professional processing chip for business processing. In actual applications, the software and hardware design will hand over the software startup of the slave chip to the master chip for control and management. For example, in a router board, the startup of multiple NP chips is controlled and managed by the master chip. Therefore, how to use the master chip to start and control multiple slave chips is crucial.

[0005] In the prior art, generally, an external memory (such as a hard disk, SD card or flash memory) is hung on each slave chip to store the software program corresponding to the slave chip. After the slave chip is powered on, the slave chip will automatically load the software program from its corresponding external memory to the internal memory for startup. This results in the consumption of a relatively large number of external memories when starting the slave chip, which not only increases the hardware cost, but also increases the PCB board area of ​​the business processing chip due to the exponential increase in external memories, and the wiring design is very complicated. In addition, since the software programs are placed one by one in the external memories corresponding to each slave chip, if there are vulnerabilities in the software programs, it is necessary to maintain the software programs in each external memory separately, which will result in a relatively high maintenance cost; and the slave chip startup is started separately, not controlled by the master chip, and is difficult to control in actual applications.

[0006] Therefore, how to start multiple slave chips based on the master chip without the need to separately connect an external memory is one of the technical issues worth considering. Summary of the invention

[0007] In view of this, the present application provides a chip startup method, device and electronic device, which are used to start multiple slave chips based on a master chip without the need to separately connect an external memory.

[0008] Specifically, the present application is implemented through the following technical solutions:

[0009] According to a first aspect of the present application, a chip startup method is provided, which is applied to a slave chip, wherein the slave chip is connected to a master chip via a serial management interface SMI bus, and the slave chip corresponds to a memory space; the method comprises:

[0010] Configuration information sent by the master chip via the SMI bus, the configuration information including a chip identifier of a slave chip that controls startup and configuration data for starting the slave chip;

[0011] The slave chip receives software program data sent by the master chip via the SMI bus, wherein the software program data includes a chip identifier of the slave chip that controls startup and a software program image file of the slave chip;

[0012] The slave chip receives the startup address sent by the master chip via the SMI bus;

[0013] If the slave chip confirms that its chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data, the configuration data and the software program image file are written into the memory space corresponding to the slave chip;

[0014] The slave chip performs a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0015] According to a second aspect of the present application, a chip startup method is provided, which is applied to a master chip, wherein the master chip is connected to a plurality of slave chips via a serial management interface SMI bus; the method comprises:

[0016] When controlling the startup of the target slave chip, the master chip sends configuration information through the SMI bus, wherein the configuration information includes a chip identifier of the target slave chip and configuration data for starting the target slave chip;

[0017] The master chip sends software program data via the SMI bus, wherein the software program data includes a chip identifier of the target slave chip and a software program image file of the target slave chip;

[0018] The master chip sends a startup address to the target slave chip through the SMI bus, so that the target slave chip performs a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0019] According to a third aspect of the present application, a chip startup device is provided, which is arranged in a slave chip, the slave chip is connected to a master chip via a serial management interface SMI bus, and the slave chip corresponds to a memory space; the device includes:

[0020] A receiving module, used to receive configuration information sent by the master chip through the SMI bus, wherein the configuration information includes a chip identifier of a slave chip that controls startup and configuration data for starting the slave chip;

[0021] The receiving module is further used to receive software program data sent by the master chip through the SMI bus, wherein the software program data includes a chip identifier of a slave chip that controls startup and a software program image file of the slave chip;

[0022] The receiving module is further used to receive the startup address sent by the main chip through the SMI bus;

[0023] A judgment module, used to judge whether its own chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data;

[0024] a writing module, configured to write the configuration data and the software program image file into a memory space corresponding to the slave chip if the judgment module confirms that its own chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data;

[0025] A startup module is used to execute a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0026] According to a fourth aspect of the present application, a chip startup device is provided, which is arranged in a master chip, and the master chip is connected to a plurality of slave chips via a serial management interface SMI bus; the device comprises:

[0027] A first sending module, used for sending configuration information through the SMI bus when controlling the startup of the target slave chip, wherein the configuration information includes a chip identifier of the target slave chip and configuration data for starting the target slave chip;

[0028] A second sending module, used for sending software program data through the SMI bus, wherein the software program data includes a chip identifier of the target slave chip and a software program image file of the target slave chip;

[0029] The third sending module is used to send a startup address to the target slave chip through the SMI bus, so that the target slave chip performs a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0030] According to the fifth aspect of the present application, a slave chip is provided, which includes a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores a computer program that can be executed by the processor, and the processor is prompted by the computer program to execute the method provided in the first aspect of the present application.

[0031] According to the sixth aspect of the present application, a main chip is provided, which includes a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores a computer program that can be executed by the processor, and the processor is prompted by the computer program to execute the method provided in the second aspect of the present application.

[0032] According to the seventh aspect of the present application, an electronic device is provided, which includes a master chip and multiple slave chips, wherein the master chip is connected to the multiple slave chips via a serial management interface SMI bus, and each slave chip corresponds to a memory space, wherein each slave chip is used to execute the method provided in the first aspect of the present application, and the master chip is used to execute the method provided in the second aspect of the present application.

[0033] Beneficial effects of the embodiments of the present application:

[0034] The master chip is connected to each slave chip through the SMI bus, and each slave chip corresponds to a memory space. The master chip sends configuration data, software program data and startup address to the target slave chip through the SMI bus, so that after the corresponding target slave chip receives the configuration data, software program data and startup address, it starts the chip according to the startup address and in combination with these two data, thereby realizing the master chip controlling the startup of the slave chip, that is, the startup of the slave chip can be realized without external memory, reducing the hardware cost of the board. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a flowchart of a chip startup method provided in an embodiment of the present application;

[0036] Figure 2 It is a structural diagram of a service board provided in an embodiment of the present application;

[0037] Figure 3 It is a flowchart of another chip startup method provided in an embodiment of the present application;

[0038] Figure 4It is a structural schematic diagram of a chip startup device provided in an embodiment of the present application;

[0039] Figure 5 is a structural schematic diagram of another chip startup device provided in an embodiment of the present application;

[0040] Figure 6 Schematic diagram of the hardware structure of a chip for implementing the chip startup method provided in this embodiment. DETAILED DESCRIPTION

[0041] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.

[0042] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more corresponding listed items.

[0043] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0044] The chip startup method provided by the present application is described in detail below.

[0045] See also Figure 1 , Figure 1 is a flowchart of a chip startup method provided by the present application. The method can be applied to a master chip, which is arranged in a service board, and the service board also includes a plurality of slave chips. Figure 2As shown, the master chip is connected to multiple slave chips via a serial management interface SMI bus, that is, the master chip and the slave chip are connected in series, and all the slave chips and the master chip are serially mounted on the SMI bus. In order to enable the master chip to control the startup of the slave chip, the present application uses a memory space pre-configured for each slave chip to store the software program image file of the slave chip, that is, each slave chip corresponds to a memory space ( Figure 2 (not shown), since the master chip and the slave chip are connected via the SMI bus, the master chip is used to provide the SMI bus clock as the SMI Master, and the slave chip accepts the control of the master chip as the SMI Slave. The master chip and all the slave chips are connected via the SMI bus, and the master chip manages the startup process of the slave chip via the SMI bus, thereby solving the problem of difficulty in the startup management of the slave chip and large consumables in the service board with one master and multiple slaves (one master chip and multiple slave chips).

[0046] It should be noted that the above-mentioned memory space can include but is not limited to the chip's own memory (such as static random access memory (SRAM)), and can also be an external double data rate synchronous dynamic random access memory (DDRSDRAM) and the like.

[0047] On this basis, when the main chip implements the above chip startup method, it may include the following steps:

[0048] S101. When controlling the startup of a target slave chip, the master chip sends configuration information via the SMI bus.

[0049] The above configuration information includes a chip identifier of the target slave chip and configuration data for starting the target slave chip.

[0050] Specifically, according to the IEEE802.3 protocol in the SMI protocol specification, a chip identifier will be configured for each slave chip. In actual applications, the chip identifier can be an SMI ID. The SMI ID of the slave chip is determined during the hardware board-level design. The master chip starts or controls the slave chip by initiating an SMI access. Since each slave chip is connected to the SMI bus, when the master chip sends data to the target slave chip through the SMI bus, it will carry the chip identifier in the data so that the target slave chip can confirm that the data is sent to itself.

[0051] Based on this principle, when the master chip controls the startup of the target slave chip, it will carry the chip ID of the target slave chip in the configuration data. Then the configuration data used to start the slave chip is carried in the above configuration information and sent to the outside through the SMI bus. Since all slave chips are connected to the SMI bus, each slave chip can receive the configuration information, but only the slave chip corresponding to the chip ID carried in the configuration information is the target slave chip and will perform subsequent startup operations. Other slave chips directly discard the received configuration information.

[0052] It should be noted that the services processed by different slave chips may be the same or different, so the configuration data and software programs required when starting the slave chip are also different. Based on this principle, when the control target slave chip is started, the configuration data corresponding to the target slave chip will be carried in the configuration information.

[0053] It should be noted that, in general, the target slave chip can be selected by the master chip in sequence according to the actual needs of the business. For example, the master chip can start the corresponding slave chip according to the order in which each business is executed. For example, the chip startup process can be started from the slave chip corresponding to the first business, and the slave chip corresponding to the first business is used as the target slave chip. After the chip startup process is completed for the slave chip corresponding to the first business, the slave chip corresponding to the second business is used as the target slave chip, and the above chip startup process is repeated.

[0054] Optionally, before the master chip controls the startup of the target slave chip, the master chip may further include the following process: the master chip scans the target slave chip.

[0055] Specifically, before starting the target slave chip, the master chip will first perform a scanning operation. When the target slave chip is scanned, it indicates that the target slave chip is online and ready, and only then will the configuration information be sent to the target slave chip. If the target slave chip cannot be scanned, it indicates that the target slave chip is not online. At this time, even if the configuration information is sent, the target slave chip cannot receive it. Therefore, if the target slave chip cannot be scanned, the configuration information will not be sent to the target slave chip.

[0056] In addition, when the master chip performs a scanning operation on the target slave chip, it can be implemented according to the following process: the master chip will send a detection message through the SMI bus, and the detection message will carry the chip identifier of the target slave chip. When each slave chip receives the detection message, it will parse the chip identifier from it. If the parsed chip identifier is consistent with the chip identifier of the slave chip itself, it indicates that the slave chip is the target slave chip, and it will send a detection response message to the master chip through the SMI bus. After the master chip receives the detection response message, it will indicate that the target slave chip has been successfully scanned. If the chip identifier parsed by the slave chip is inconsistent with the chip identifier of the slave chip itself, it indicates that the slave chip is not the target slave chip, and the detection response message will not be sent to the master chip. If the master chip does not receive the detection response message, it is confirmed that the target slave chip has not been scanned.

[0057] When the target slave chip cannot be scanned, the master chip can continue to scan the next slave chip, and then regard the next slave chip as the target slave chip and repeat the above operation.

[0058] Optionally, based on any of the above embodiments, the chip startup method provided in this embodiment further includes: after the main chip is powered on successfully, performing an initialization operation.

[0059] Specifically, the above initialization operation may include but is not limited to basic hardware initialization and SMI hardware initialization. Specifically, after the main chip is powered on, the main chip will initialize its own basic hardware in turn, and also initialize its own SMI hardware. Then the main chip can enable the SMI bus to control the startup of the slave chip. When the main chip SMI is initialized, it mainly configures the basic parameters of the SMI bus, such as configuration frequency, scanning parameters, etc.

[0060] S102. The main chip sends software program data via the SMI bus.

[0061] The software program data includes a chip identifier of the target slave chip and a software program image file of the target slave chip.

[0062] In this step, after the master chip sends the configuration data to the target slave chip, it can send the software program image file to the target slave chip, so that after the target slave chip receives the software program image file, it starts and executes the software program. Since the software programs corresponding to different slave chips are generally different, and the software programs corresponding to the same type of slave chips can be the same or different. Based on this, when sending the software program data to the target slave chip, the chip identifier of the target slave chip and the software program image file corresponding to the target slave chip will be carried in the software program data.

[0063] S103, the master chip sends a startup address to the target slave chip through the SMI bus, so that the target slave chip performs a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0064] In this step, after the configuration information and software program data are sent to the target slave chip, in order to realize the startup of the target slave chip, the master chip will send a startup address to the target slave chip, so that after the slave chip receives the startup address, it will start the startup operation of the target slave chip from the startup address. During this period, the configuration information may be read or the software program image file may be called. When these two data are needed, the startup operation of the target slave chip is executed based on these two data.

[0065] Specifically, since the software program data is sent by the master chip to the SMI bus, and all slave chips are connected to the SMI bus, each slave chip will receive the software program data, and each slave chip will parse the chip identification of the target slave chip from the software program data. When the chip identification of the target slave chip parsed is consistent with its own chip identification, it indicates that the slave chip is the target slave chip, so that the slave chip will store the software program image file in the software program data and then perform the startup operation. When the chip identification of the target slave chip parsed is inconsistent with its own chip identification, the software program data will be discarded.

[0066] It should be noted that, in this embodiment, the software programs of each slave chip are maintained by the master chip, and the software program will be updated. The master chip will sense the update operation. When the master chip finds that the software program of a certain slave chip (for the convenience of description, the slave chip corresponding to the updated software program is taken as the target slave chip as an example for explanation) is updated, it will generate updated software program data based on the software program image file of the updated software program and the chip identifier of the target slave chip, and then send the updated software program to the outside through the SMI bus. That is, the software program image file included in the software program data in step S102 is the software program image file corresponding to the updated software program. In this way, after the target slave chip receives the updated software program update data, it can execute the startup operation of the chip based on the updated software program image file. In this way, the remote update of the software program of the slave chip is realized, which is convenient and fast, and the update and maintenance cost of the software program is effectively saved, that is, the problem of difficulty in upgrading and updating the firmware of the slave chip and high maintenance cost is solved.

[0067] It should be noted that step S101 and step S102 may be performed simultaneously, or step S101 may be performed first and then step S102.

[0068] It should be noted that the above configuration data, software programs and other related files can be pre-stored in the memory space of the master chip, or in a storage device external to the master chip, depending on the actual situation. Then, when the slave chip is started, the above configuration data and software programs are read from the memory space of the master chip or the external storage device, and then sent to the slave chip.

[0069] By implementing the chip startup method provided in the present application, the master chip is connected to each slave chip through the SMI bus, and each slave chip corresponds to a memory space (such as SRAM inside the chip or DDR outside the chip, etc.). The master chip sends configuration data, software program data and startup address to the target slave chip through the SMI bus, so that after the corresponding target slave chip receives the configuration data, software program data and startup address, it starts to execute the startup process of the slave chip based on the startup address, and then combines these two data to start the slave chip, thereby realizing the master chip controlling the startup of the slave chip, that is, the startup of the slave chip can be realized without external memory (hard disk, SD card or flash memory), thereby reducing the hardware cost of the board.

[0070] Based on the same inventive concept, this embodiment also provides a chip startup method, which is applied to Figure 2 Each slave chip in the service board shown in the figure is connected to the master chip through the SMI bus. Each slave chip corresponds to a memory space. As an SMI Slave, the slave chip supports clause 22 and clause 45 of the IEEE802.3 protocol and supports accessing the memory space through the SMI bus. When implementing the chip startup process, each slave chip can follow Figure 3 The process implementation shown includes the following steps:

[0071] S301. The slave chip receives configuration information sent by the master chip via the SMI bus, where the configuration information includes a chip identifier of the slave chip that controls startup and configuration data for starting the slave chip.

[0072] In this step, after the slave chip receives the configuration information, the chip identifier of the slave chip that the master chip wants to control to start can be parsed from the configuration information.

[0073] S302: The slave chip receives software program data sent by the master chip via the SMI bus, where the software program data includes a chip identifier of the slave chip that controls startup and a software program image file.

[0074] In this step, after receiving the software program data through the SMI bus, the slave chip can parse the chip identifier of the slave chip that the master chip wants to control to start from the software program data, and parse the software program data of the slave chip at the same time.

[0075] S303. The slave chip receives the startup address sent by the master chip via the SMI bus.

[0076] In this step, the above startup address is used to control the startup of the slave chip. After receiving the startup address, the slave chip will store the startup address to prepare for the startup of the slave chip.

[0077] S304: If the slave chip confirms that its chip identification is consistent with the chip identification of the slave chip carried in the configuration information and software program data, the configuration data and the software program image file are written into the memory space corresponding to the slave chip.

[0078] In this step, when the master chip sends configuration information and software program data at the same time, the slave chip can simultaneously determine whether its own chip identification is consistent with the chip identification carried in the configuration information and the chip identification carried in the software program data. When they are consistent, the configuration data is extracted from the configuration information, and the software program image file is extracted from the software program data, and then the extracted configuration data and software program image file are written to the memory space corresponding to the slave chip. When the chip identification of the slave chip is inconsistent with the chip identification in the configuration information, the configuration information is discarded; when the chip identification of the slave chip is inconsistent with the chip identification in the software program data, the software program data is discarded.

[0079] In addition, when the slave chip first receives the configuration information, the slave chip can first extract the chip identifier from the configuration information, and then the slave chip can determine whether its own chip identifier is consistent with the chip identifier being extracted. If they are consistent, the configuration data is extracted from the configuration information, and then the extracted configuration data is written into the memory space corresponding to the slave chip; if they are inconsistent, the configuration information is discarded. Afterwards, when the slave chip receives the software program data, the slave chip can extract the chip identifier from the software program data, and then the slave chip can determine whether its own chip identifier is consistent with the chip identifier being extracted. If they are consistent, the software program image file is extracted from the software program data, and then the extracted software program image file is written into the memory space corresponding to the slave chip; if they are inconsistent, the software program data is discarded.

[0080] It should be noted that in the present application, there are many software programs that need to be executed by the slave chip after power-on, that is, there may be multiple software programs for the slave chip. Therefore, there may be multiple software program image files used to start the slave chip. The present application does not limit the number of software program image files, and the specific number can be determined according to actual conditions.

[0081] S305 , the slave chip performs a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0082] In this step, after executing step S304, the slave chip can extract the configuration data from the memory space to enable the basic configuration required for the slave chip. After the configuration is successful, the startup address is read from the memory space, and then the startup address is used to call the software program image file to perform the startup operation of the slave chip, thereby realizing the startup of the slave chip under the control of the main chip, that is, the controllable startup of the slave chip, and there is no need for the participation of external memory, which greatly saves hardware cost and hardware area.

[0083] It should be noted that the configuration data in this embodiment is basic configuration data for starting up the slave chip, and the configuration data may be, but is not limited to, clock, starting and stopping of several functions, and the like.

[0084] Optionally, the above-mentioned configuration information also includes a first storage address of the configuration data in the memory space corresponding to the slave chip, and the above-mentioned software program data also includes a second storage address of the software program image file in the memory space corresponding to the slave chip; on this basis, step S304 can be executed according to the following process: according to the above-mentioned first storage address, the above-mentioned configuration data is written to the corresponding position in the memory space corresponding to the slave chip; according to the second storage address, the software program image file is written to the corresponding position in the memory space corresponding to the slave chip.

[0085] It should be noted that in the present application, there may be multiple configuration information and software programs used to start the slave chip. Therefore, there may be multiple configuration data, first storage addresses, software program image files, and second storage addresses used to start the slave chip, but the configuration data corresponds to the first storage address one-to-one, and similarly, the software program image file corresponds to the second storage address one-to-one. The present application does not limit the number of configuration data and the first storage address, and similarly, the present application does not limit the number of software program image files and the second storage address, and the specific number can be determined according to actual conditions.

[0086] Specifically, in actual applications, the location in the memory space for storing configuration data is fixed, so the master chip can carry the first storage address of the configuration data in the memory space in the configuration information and send it to the slave chip together. In this way, when the slave chip receives the configuration information, it can parse the first storage address from the configuration information, and then write the configuration data to the location corresponding to the first storage address in the memory space corresponding to the slave chip. Correspondingly, the second storage address of the software program image file is also the address of the software program image file in the memory space, so the software program image file can be written to the location corresponding to the second storage address in the memory space corresponding to the slave chip based on the second storage address. Optionally, when there are multiple software program image files, there are also multiple second storage addresses, which correspond one to one with the software program image files, then based on each second storage address, the software program image file corresponding to the second storage address can be written to the location corresponding to the second storage address in the memory space corresponding to the slave chip.

[0087] It should be noted that the startup address and the second storage address may be the same or different. When the startup address and the second storage address are different, the startup address is also determined according to the second storage address.

[0088] Further, step S305 may be performed according to the following process: the slave chip starts to perform a boot operation according to the boot address; during the boot operation, when configuration data needs to be accessed, the configuration data is read according to the first storage address; and the software program image file is called according to the boot address to perform the boot operation of the slave chip.

[0089] Specifically, after the slave chip writes the configuration data and the software program image file to the corresponding positions of the memory space, when the slave chip executes the chip startup, it can read the configuration data from the memory space based on the first storage address, and then configure the basic functions such as the clock of the slave chip according to the configuration data. Then, the software program image file is read from the memory space according to the second storage address, and the software program image file is executed to complete the startup of the slave chip.

[0090] Optionally, the memory space in this embodiment includes registers and memory areas, and the first storage address is the register address of the register to which the configuration data is to be written; the second storage address is the address of the software program image file in the memory area.

[0091] On this basis, the slave chip can write the configuration data into the corresponding position in the memory space corresponding to the slave chip according to the first storage address according to the following process: the slave chip writes the configuration data into the corresponding register according to the register address.

[0092] Specifically, the configuration data may be written into a register corresponding to the register address in the on-chip storage control corresponding to the slave chip based on the register address. It should be noted that the register corresponding to the above register address is a register specifically used to store configuration data.

[0093] On this basis, the slave chip can write the software program image file into the corresponding position in the memory space corresponding to the slave chip according to the second storage address according to the following process: the slave chip writes the software program image file into the memory area according to the second storage address.

[0094] Specifically, when the second storage address is the address of the memory area, the software program image file is written into the location corresponding to the second storage address in the memory area.

[0095] Furthermore, the chip startup method provided by this embodiment further includes: the slave chip writes the startup address into a target register corresponding to the slave chip.

[0096] On this basis, the slave chip can read the configuration data according to the first storage address and call the software program image file according to the second storage address to perform the startup operation of the slave chip according to the following process: the slave chip reads the startup address from the target register to start the startup operation of the slave chip. During the startup operation, the slave chip reads the configuration data from the register corresponding to the register address, configures the slave chip, and calls the software program image file from the memory area according to the second storage address to perform the startup operation of the configured slave chip. In this way, the startup of the slave chip is controlled without an external memory.

[0097] Optionally, the software program image file included in the above software program data is the software program image file corresponding to the updated software program; similarly, when the software program data includes a second storage address, the second storage address included in the software program data at this time is the second storage address of the updated software program image file.

[0098] Specifically, when the master chip confirms that the software program has been updated, the software program image file and the second storage address corresponding to the updated software program can be carried in the software program data, that is, the updated software program image file and the updated second storage address are carried in the software program data and sent to the slave chip. In this way, after the slave chip receives the updated software program image file and the updated second storage address, it can execute the startup of the slave chip according to the updated second storage address and the updated software program image file. As a result, the remote upgrade and update of the slave chip software is more convenient and reduces the maintenance cost.

[0099] In addition, the slave chip implements the complete SMI Slave function, which can be used as the debugging interface of the master chip to the slave chip, and accesses the registers and memory areas of the slave chip through the SMI bus, enriching the debugging function of the slave chip.

[0100] Based on the same inventive concept, the present application also provides a chip startup device corresponding to the chip startup method implemented by the above-mentioned master chip side. The implementation of the chip startup device can refer to the description of the chip startup method by the above-mentioned master chip, which will not be discussed here one by one.

[0101] See also Figure 4 , Figure 4 A chip startup device provided by an exemplary embodiment of the present application is arranged in a master chip, and the master chip is connected to a plurality of slave chips via a serial management interface SMI bus; the device comprises:

[0102] A first sending module 401 is used to send configuration information through the SMI bus when controlling the startup of the target slave chip, where the configuration information includes a chip identifier of the target slave chip and configuration data for starting the target slave chip;

[0103] A second sending module 402 is used to send software program data through the SMI bus, where the software program data includes a chip identifier of the target slave chip and a software program image file of the target slave chip;

[0104] The third sending module 403 is used to send a startup address to the target slave chip through the SMI bus, so that the target slave chip performs a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0105] Optionally, the software program image file included in the above-mentioned software program data is a software program image file corresponding to the updated software program.

[0106] Optionally, the above configuration information also includes a first storage address of the configuration data in the memory space;

[0107] Optionally, the software program data further includes a second storage address of the software program image file in the memory space;

[0108] By implementing the chip startup device provided in this embodiment, the master chip is connected to each slave chip through the SMI bus, and each slave chip corresponds to a memory space. The master chip sends configuration data, software program data and startup address to the target slave chip through the SMI bus, so that after the corresponding target slave chip receives the configuration data, software program data and startup address, it starts the chip according to the startup address and in combination with these two data, thereby realizing the master chip controlling the startup of the slave chip, that is, the startup of the slave chip can be realized without the need for an external memory, thereby reducing the hardware cost of the board.

[0109] Based on the same inventive concept, the present application also provides a chip startup device corresponding to the chip startup method implemented from the chip side. The implementation of the chip startup device can refer to the description of the chip startup method from the chip side, which will not be discussed here one by one.

[0110] See also Figure 5 , Figure 5 A chip startup device provided by an exemplary embodiment of the present application is provided in a slave chip, the slave chip is connected to the master chip via a serial management interface SMI bus, and the slave chip corresponds to a memory space; the device includes:

[0111] The receiving module 501 is used to receive the configuration information sent by the master chip through the SMI bus, where the configuration information includes the chip identification of the slave chip that controls the startup and the configuration data used to start the slave chip;

[0112] The receiving module 501 is further used to receive software program data sent by the master chip through the SMI bus, wherein the software program data includes a chip identifier of the slave chip that controls startup and a software program image file;

[0113] The receiving module 501 is further used to receive the startup address sent by the main chip through the SMI bus;

[0114] A judgment module 502 is used to judge whether its own chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data;

[0115] The writing module 503 is used to write the configuration data and the software program image file if the above-mentioned judgment module 502 confirms that its own chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data;

[0116] The startup module 504 is used to execute the startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

[0117] Optionally, the configuration information further includes a first storage address of the configuration data in the memory space corresponding to the slave chip; the software program data further includes a second storage address of the software program image file in the memory space corresponding to the slave chip; then

[0118] The writing module 503 is specifically used to write the configuration data to the corresponding position in the memory space corresponding to the slave chip according to the first storage address; write the software program image file to the corresponding position in the memory space corresponding to the slave chip according to the second storage address;

[0119] Optionally, the above memory space includes registers and memory areas, then the first storage address is the register address of the register to which the configuration data is to be written; the second storage address is the address of the software program image file in the memory area; then

[0120] The writing module 503 is specifically used to write the configuration data into the corresponding register according to the register address;

[0121] The writing module 503 is further used to write the software program image file into the memory area according to the second storage address.

[0122] Optionally, the writing module 503 is further used to write the startup address into a target register corresponding to the slave chip.

[0123] Optionally, the software program image file included in the above-mentioned software program data is a software program image file corresponding to the updated software program.

[0124] By implementing the chip startup device provided in this embodiment, the master chip is connected to each slave chip through the SMI bus, and each slave chip corresponds to a memory space. The master chip sends configuration data, software program data and startup address to the target slave chip through the SMI bus, so that after the corresponding target slave chip receives the configuration data, software program data and startup address, it starts the chip according to the startup address and in combination with these two data, thereby realizing the master chip controlling the startup of the slave chip, that is, the startup of the slave chip can be realized without the need for an external memory, thereby reducing the hardware cost of the board.

[0125] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes a master chip and multiple slave chips, wherein the master chip is connected to the multiple slave chips via a serial management interface SMI bus, and each slave chip corresponds to a memory space, wherein each slave chip is used to execute the chip startup method provided by the slave chip in any of the above embodiments of the present application, and the above master chip is used to execute the chip startup method provided by the master chip in any of the above embodiments of the present application. Optionally, the above electronic device may include but is not limited to Figure 2 Business boards and cards shown, etc.

[0126] Based on the same inventive concept, the embodiment of the present application provides a chip, which can be the above-mentioned master chip or slave chip. Figure 6As shown, the chip includes a processor 601 and a machine-readable storage medium 602, the machine-readable storage medium 602 stores a computer program that can be executed by the processor 601, and the processor 601 is prompted by the computer program to execute the chip startup method provided in any embodiment of the present application. In addition, the electronic device also includes a communication interface 603 and a communication bus 604, wherein the processor 601, the communication interface 603, and the machine-readable storage medium 602 communicate with each other through the communication bus 604.

[0127] The machine-readable storage medium 602 includes a memory space.

[0128] The communication bus mentioned in the above chip can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0129] The communication interface is used for communication between the above chip and other devices.

[0130] When the machine-readable storage medium includes a memory space, the memory space may be a random access memory (RAM), or may include a DDR SRAM (Double Data Rate Synchronous Dynamic Random Access Memory).

[0131] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0132] In addition, an embodiment of the present application provides a machine-readable storage medium, which stores a computer program. When called and executed by a processor, the computer program prompts the processor to execute the chip startup method on the master chip side provided by any embodiment of the present application (when the chip is a master chip), or execute the chip startup method on the slave chip side provided by any embodiment of the present application (when the chip is a slave chip).

[0133] As for the chip and machine-readable storage medium embodiments, since the method contents involved are basically similar to those of the aforementioned method embodiments, the description is relatively simple, and the relevant parts may refer to the partial description of the method embodiments.

[0134] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0135] The implementation process of the functions and effects of each unit / module in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0136] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can refer to the partial description of the method embodiments. The device embodiments described above are merely schematic, wherein the units / modules described as separate components may or may not be physically separated, and the components displayed as units / modules may or may not be physical units / modules, that is, they may be located in one place, or they may be distributed on multiple network units / modules. Some or all of the units / modules may be selected according to actual needs to achieve the purpose of the present application. A person of ordinary skill in the art may understand and implement it without creative work.

[0137] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A chip startup method, characterized in that: Applied to a slave chip, the slave chip is connected to a master chip via a serial management interface SMI bus, and the slave chip corresponds to a memory space; the method comprises: The slave chip receives configuration information sent by the master chip through the SMI bus, wherein the configuration information includes a chip identifier of the slave chip that controls startup and configuration data for starting the slave chip; the configuration information also includes a first storage address of the configuration data in a memory space corresponding to the slave chip; The slave chip receives software program data sent by the master chip through the SMI bus, wherein the software program data includes a chip identifier of the slave chip that controls startup and a software program image file of the slave chip; the software program data also includes a second storage address of the software program image file in a memory space corresponding to the slave chip; The slave chip receives the startup address sent by the master chip via the SMI bus; If the slave chip confirms that its chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data, the configuration data is written into a corresponding position in the memory space corresponding to the slave chip according to the first storage address; Writing the software program image file into a corresponding position in the memory space corresponding to the slave chip according to the second storage address; The slave chip performs a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

2. The method according to claim 1, characterized in that The memory space includes a register and a memory area, the first storage address is the register address of the register to which the configuration data is to be written; the second storage address is the address of the software program image file in the memory area; Writing the configuration data into a corresponding position in a memory space corresponding to the slave chip according to the first storage address includes: The slave chip writes the configuration data into the corresponding register according to the register address; The slave chip writes the software program image file to a corresponding position in the memory space corresponding to the slave chip according to the second storage address, including: The slave chip writes the software program image file into the memory area according to the second storage address.

3. The method according to claim 1, characterized in that The method further comprises: The slave chip writes the startup address into a target register corresponding to the slave chip.

4. The method according to claim 1, characterized in that: The software program image file included in the software program data is the software program image file corresponding to the updated software program, and the second storage address included in the software program data is the storage address of the updated software program image file in the memory space corresponding to the slave chip.

5. A chip startup method, characterized in that: Applied in a master chip, the master chip is connected to a plurality of slave chips via a serial management interface SMI bus; the method comprises: When controlling the startup of the target slave chip, the master chip sends configuration information through the SMI bus, wherein the configuration information includes a chip identifier of the target slave chip and configuration data for starting the target slave chip; the configuration information also includes a first storage address of the configuration data in a memory space corresponding to the slave chip; The master chip sends software program data through the SMI bus, the software program data including the chip identifier of the target slave chip and the software program image file of the target slave chip; the software program data also includes a second storage address of the software program image file in the memory space corresponding to the slave chip; The master chip sends a startup address to the target slave chip through the SMI bus, so that if the target slave chip confirms that its own chip identifier is consistent with the chip identifier of the slave chip carried in the configuration information and the software program data, then according to the first storage address, the configuration data is written to the corresponding position in the memory space corresponding to the slave chip; according to the second storage address, the software program image file is written to the corresponding position in the memory space corresponding to the slave chip; and the startup operation of the slave chip is performed according to the configuration data, the software program image file and the startup address.

6. The method according to claim 5, characterized in that The software program image file included in the software program data is a software program image file corresponding to the updated software program.

7. A chip startup device, characterized in that: The device is arranged in a slave chip, the slave chip is connected to the master chip via a serial management interface SMI bus, and the slave chip corresponds to a memory space; the device comprises: A receiving module, used to receive configuration information sent by the master chip through the SMI bus, wherein the configuration information includes a chip identifier of a slave chip that controls startup and configuration data for starting the slave chip; the configuration information also includes a first storage address of the configuration data in a memory space corresponding to the slave chip; The receiving module is further used to receive software program data sent by the master chip through the SMI bus, wherein the software program data includes a chip identifier of a slave chip that controls startup and a software program image file of the slave chip; the software program data also includes a second storage address of the software program image file in a memory space corresponding to the slave chip; The receiving module is further used to receive the startup address sent by the main chip through the SMI bus; A judgment module, used to judge whether its own chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data; a writing module, configured to write the configuration data into a corresponding position in the memory space corresponding to the slave chip according to the first storage address if the judgment module confirms that its own chip identification is consistent with the chip identification of the slave chip carried in the configuration information and the software program data; and write the software program image file into a corresponding position in the memory space corresponding to the slave chip according to the second storage address; A startup module is used to execute a startup operation of the slave chip according to the configuration data, the software program image file and the startup address.

8. A chip startup device, characterized in that: The device is arranged in a master chip, and the master chip is connected to a plurality of slave chips via a serial management interface SMI bus; the device comprises: A first sending module, used to send configuration information through the SMI bus when controlling the startup of the target slave chip, the configuration information including the chip identifier of the target slave chip and configuration data for starting the target slave chip; the configuration information also includes a first storage address of the configuration data in the memory space corresponding to the slave chip; A second sending module is used to send software program data through the SMI bus, wherein the software program data includes a chip identifier of the target slave chip and a software program image file of the target slave chip; the software program data also includes a second storage address of the software program image file in a memory space corresponding to the slave chip; The third sending module is used to send a startup address to the target slave chip through the SMI bus, so that if the target slave chip confirms that its own chip identifier is consistent with the chip identifier of the slave chip carried in the configuration information and the software program data, then according to the first storage address, the configuration data is written to the corresponding position in the memory space corresponding to the slave chip; according to the second storage address, the software program image file is written to the corresponding position in the memory space corresponding to the slave chip; and the startup operation of the slave chip is performed according to the configuration data, the software program image file and the startup address.

9. A slave chip, characterized in that: The slave chip includes a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores a computer program that can be executed by the processor, and the processor is prompted by the computer program to execute the method according to any one of claims 1 to 4.

10. A main chip, characterized in that: The main chip includes a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores a computer program that can be executed by the processor, and the processor is prompted by the computer program to execute the method of claim 5 or 6.

11. An electronic device, characterized in that: The electronic device includes a master chip and multiple slave chips, the master chip is connected to the multiple slave chips via a serial management interface SMI bus, each slave chip corresponds to a memory space, wherein each slave chip is used to execute any of the methods described in claims 1 to 4, and the master chip is used to execute the method described in claim 5 or 6.

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