Display substrate and manufacturing method thereof, display panel and display device

Abstract

A display substrate and a manufacturing method thereof, a display panel and a display device. The display substrate comprises a base substrate, and a light shielding layer (S1) and a thin film transistor array layer sequentially located on the base substrate; the light shielding layer (S1) comprises a plurality of imaging pinholes (H1); a first protective layer (P0) is arranged between the light shielding layer (S1) and the thin film transistor array layer; a first region is arranged on the base substrate, and the orthographic projection of the metal film layer included in the thin film transistor array layer on the base substrate is arranged outside the first region; at least a part of the orthographic projection of the imaging pinhole (H1) on the base substrate is arranged in the first region; the orthographic projection of the first protective layer (P0) on the base substrate at least covers a part of the first region; the first region comprises a pinhole region (A0); the orthographic projection of the first protective layer (P0) on the base substrate at least covers the pinhole region (A0); the display substrate further comprises a buffer layer (Bf). The display substrate and the manufacturing method thereof, the display panel and the display device can improve the fingerprint recognition effect.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, a display panel and a display device. Background Art

[0002] With the advent of the era of full-screen mobile phones, under-screen fingerprint recognition has been widely studied. In related technologies, the principle of pinhole imaging can be used for under-screen fingerprint recognition. In the effective display area, at fixed intervals, small holes are designed in the pixels as imaging holes (the diameter of the imaging holes is generally greater than or equal to 5 um (micrometers) and less than or equal to 15 um), and a metal layer is deposited as a light shielding layer at the position of the effective display area outside the imaging holes. In related technologies, there is room for improvement in the imaging effect of fingerprint recognition using the principle of pinhole imaging. Summary of the invention

[0003] In one aspect, an embodiment of the present invention provides a display substrate, comprising a base substrate, and a light shielding layer and a thin film transistor array layer sequentially located on the base substrate; the light shielding layer comprises a plurality of imaging pinholes;

[0004] A first protective layer is disposed between the light shielding layer and the thin film transistor array layer;

[0005] The base substrate is provided with a first region, the orthographic projection of the metal film layer included in the thin film transistor array layer on the base substrate is arranged outside the first region; at least a part of the orthographic projection of the imaging pinhole on the base substrate is arranged in the first region;

[0006] The orthographic projection of the first protective layer on the base substrate at least covers a portion of the first area;

[0007] The first region includes a pinhole region, and at least a portion of the orthographic projection of the imaging pinhole on the substrate is disposed in the pinhole region;

[0008] The orthographic projection of the first protective layer on the base substrate at least covers the pinhole area;

[0009] The display substrate further includes a buffer layer disposed between the first protection layer and the thin film transistor array layer.

[0010] Optionally, the first region includes a first sub-region;

[0011] The thin film transistor array layer includes a reset power line, a first reset transistor, a threshold compensation transistor and a driving transistor;

[0012] The first sub-region does not overlap with an orthographic projection of a first conductive portion included in the semiconductor material layer pattern of the first reset transistor on the substrate and an orthographic projection of a second conductive portion included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate;

[0013] The first conductive portion is electrically connected to a first electrode included in the first reset transistor; the first electrode is electrically connected to the reset power line;

[0014] The second conductive portion is electrically connected to a second electrode included in the threshold compensation transistor; and the second electrode is electrically connected to a gate of the driving transistor.

[0015] Optionally, the first area includes a second sub-area;

[0016] The thin film transistor array layer includes a gate line, a threshold compensation transistor and a driving transistor;

[0017] The second sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate, the orthographic projection of the second conductive part included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate, and the orthographic projection of the first gate metal pattern on the substrate;

[0018] The second conductive portion is electrically connected to a second electrode included in the threshold compensation transistor; the second electrode is electrically connected to a gate of the driving transistor;

[0019] The first gate metal pattern is a gate metal pattern between the gate line and the gate of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

[0020] Optionally, the first area includes a third sub-area;

[0021] The thin film transistor array layer includes a gate line, a threshold compensation transistor and a driving transistor;

[0022] The third sub-region is between the orthographic projection of the gate line on the substrate, the orthographic projection of the third conductive portion included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate, and the orthographic projection of the first gate metal pattern on the substrate;

[0023] The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the third conductive portion is arranged on the first channel portion and the second channel portion without overlapping;

[0024] The first gate metal pattern is a gate metal pattern between the gate line and the gate of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

[0025] Optionally, the first area includes a fourth sub-area;

[0026] The thin film transistor array layer includes a gate line, a first capacitor, a threshold compensation transistor and a first light emission control transistor;

[0027] The fourth sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the first plate of the first capacitor on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate, and the orthographic projection of the fourth conductive portion included in the semiconductor material layer pattern of the first light emission control transistor on the substrate;

[0028] The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the semiconductor material layer pattern of the first light emission control transistor includes a third channel portion;

[0029] The fourth conductive portion is disposed between the second channel portion and the third channel portion.

[0030] Optionally, the first area includes a fifth sub-area;

[0031] The thin film transistor array layer includes a first capacitor, a threshold compensation transistor, a first light emission control transistor, a first power line and a light emission control signal line;

[0032] The fifth sub-region does not overlap with the orthographic projection of the first electrode plate of the first capacitor on the substrate, the orthographic projection of the light emitting control signal line on the substrate, the orthographic projection of the first power line on the substrate, and the orthographic projection of the fourth conductive portion included in the semiconductor material layer pattern of the first light emitting control transistor on the substrate;

[0033] The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the semiconductor material layer pattern of the first light emission control transistor includes a third channel portion;

[0034] The fourth conductive portion is disposed between the second channel portion and the third channel portion.

[0035] Optionally, the display substrate described in at least one embodiment of the present invention further includes an anode layer disposed on a side of the thin film transistor array layer away from the first protective layer;

[0036] The thin film transistor array layer includes a first power line and a first light emission control transistor;

[0037] The pinhole area does not overlap with the orthographic projection of the first power line on the base substrate and the orthographic projection of the third electrode included in the first light emission control transistor on the base substrate;

[0038] The third electrode is electrically connected to the anode layer.

[0039] Optionally, the film forming temperature of the first protective layer is lower than a threshold temperature;

[0040] The threshold temperature is greater than or equal to 230 degrees Celsius and less than or equal to 380 degrees Celsius.

[0041] Optionally, the first protective layer is made of inorganic material or organic material.

[0042] Optionally, the first protective layer is made of silicon oxide or silicon nitride.

[0043] Optionally, the thickness of the first protective layer is greater than or equal to 100 nanometers and less than or equal to 400 nanometers.

[0044] Optionally, the display substrate described in at least one embodiment of the present invention further includes a fingerprint recognition layer; the fingerprint recognition layer is arranged on a side of the base substrate away from the light shielding layer, and the fingerprint recognition layer includes a fingerprint recognition sensor;

[0045] The light shielding layer is arranged on the light incident side of the fingerprint recognition sensor, and the imaging pinhole allows light to be incident on the fingerprint recognition sensor through the pinhole.

[0046] Optionally, the light-shielding layer is made of a light-opaque material.

[0047] Optionally, the display substrate described in at least one embodiment of the present invention further includes a planar layer and an anode layer sequentially arranged on a side of the thin film transistor array layer away from the buffer layer;

[0048] The orthographic projection of the imaging pinhole on the substrate does not overlap with the orthographic projection of the anode layer on the substrate.

[0049] Optionally, the buffer layer is made of silicon nitride, silicon oxide or polysilicon.

[0050] Optionally, the thickness of the buffer layer is greater than or equal to 200 nanometers and less than or equal to 600 nanometers.

[0051] Optionally, the metal film layer includes a first metal layer, a second metal layer and a third metal layer;

[0052] The gate line, the reset control signal line, the light emitting control signal line, the second plate of the first storage capacitor, and the gates of each transistor included in the pixel circuit are located in the first metal layer;

[0053] A reset power line and a first plate of the first storage capacitor are located in the second metal layer;

[0054] A first power line, a data line, and a first electrode and a second electrode included in the transistor are located in the third metal layer.

[0055] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a display substrate, comprising:

[0056] A light shielding layer is formed on a base substrate; a first region is provided on the base substrate, the light shielding layer includes a plurality of imaging pinholes, and at least a part of the orthographic projection of the imaging pinholes on the base substrate is provided in the first region;

[0057] forming a first protective layer on a side of the light shielding layer away from the base substrate;

[0058] forming a thin film transistor array layer on the first protective layer, so that an orthographic projection of a metal film layer included in the thin film transistor array layer on the base substrate is disposed outside the first region;

[0059] The orthographic projection of the first protective layer on the base substrate at least covers a portion of the first area;

[0060] The first region includes a pinhole region, and at least a portion of an orthographic projection of the imaging pinhole on the substrate is disposed within the pinhole region; the orthographic projection of the first protective layer on the substrate at least covers the pinhole region.

[0061] Optionally, the step of forming a first protective layer on a side of the light shielding layer away from the base substrate includes:

[0062] A first protective layer is formed on a side of the light shielding layer away from the base substrate by using a low temperature process; the film forming temperature of the first protective layer is lower than a threshold temperature;

[0063] The threshold temperature is greater than or equal to 230 degrees Celsius and less than or equal to 380 degrees Celsius.

[0064] In a third aspect, an embodiment of the present invention further provides a display panel, comprising the above-mentioned display substrate.

[0065] In a fourth aspect, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0066] The display substrate and its manufacturing method, display panel and display device described in the present invention set at least a part of the orthographic projection of the imaging hole included in the light-shielding layer on the base substrate within the first area, so that the imaging hole will not be blocked by the metal film layer included in the thin film transistor array layer, thereby enabling good fingerprint recognition. In addition, the display substrate described in the embodiment of the present invention is provided with a first protective layer between the light-shielding layer and the thin film transistor array layer, so as to effectively prevent plasma from gathering on the light-shielding layer, prevent the arc from breaking through the light-shielding layer, and improve the fingerprint recognition effect; and in the display substrate described in the embodiment of the present invention, the orthographic projection of the first protective layer on the base substrate at least covers a part of the first area, thereby preventing the part of the light-shielding layer corresponding to the first area from being broken through by the arc to generate light leakage holes, and avoiding the stray light passing through the light leakage holes from affecting the fingerprint imaging effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a structural diagram of a related display substrate;

[0068] Figure 2 is a schematic diagram of a light leakage hole in a related display substrate;

[0069] Figure 3 is a structural diagram of a display substrate according to at least one embodiment of the present invention;

[0070] Figure 4 is a structural diagram of a display substrate according to at least one embodiment of the present invention;

[0071] Figure 5 is a circuit diagram of at least one embodiment of a pixel circuit included in a thin film transistor array layer;

[0072] Figure 6 It is a schematic diagram of a partial layout of a semiconductor material layer pattern in a thin film transistor array layer;

[0073] Figure 7 is Figure 6 A schematic diagram of each conductive part is shown on the basis of FIG.

[0074] Figure 8 It is a partial layout schematic diagram of source and drain metal layer patterns included in the thin film transistor array layer;

[0075] Fig. 9 is a partial layout schematic diagram of a first gate metal layer pattern included in a thin film transistor array layer;

[0076] Fig.10 is a partial layout schematic diagram of a second gate metal layer pattern included in a thin film transistor array layer;

[0077] Fig.11 yes Figure 7 The semiconductor material layer pattern shown, Figure 8 The source and drain metal layer patterns shown, Fig. 9 The first gate metal layer pattern and Fig.10 A top view of the superimposed second gate metal layer patterns shown;

[0078] Fig.12 is a schematic diagram of the position of the first sub-area A1;

[0079] Fig.13 is a schematic diagram of the position of the second sub-area A2;

[0080] Fig.14 is a schematic diagram of the location of the third sub-area A3;

[0081] Fig.15 is a schematic diagram of the location of the fourth sub-area A4;

[0082] Fig.16 is a schematic diagram of the location of the fifth sub-area A5;

[0083] Fig.17 is a schematic diagram of the position of the small hole area A0;

[0084] Fig.18 is Fig.12 A schematic diagram of adding tangent line A-A' on the basis;

[0085] Fig.19 It is a cross-sectional view along the tangent line AA'. DETAILED DESCRIPTION

[0086] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0087] The display substrate described in at least one embodiment of the present invention comprises a base substrate, and a light shielding layer and a thin film transistor array layer sequentially located on the base substrate; the light shielding layer comprises a plurality of imaging pinholes;

[0088] A first protective layer is disposed between the light shielding layer and the thin film transistor array layer;

[0089] A first region is provided on the substrate, and an orthographic projection of a metal film layer included in the thin film transistor array layer on the substrate is arranged outside the first region; at least a part of the orthographic projection of the imaging pinhole on the substrate is arranged in the first region;

[0090] The orthographic projection of the first protective layer on the base substrate at least covers a portion of the first area;

[0091] The first region includes a pinhole region, and at least a portion of the orthographic projection of the imaging pinhole on the substrate is disposed in the pinhole region;

[0092] The orthographic projection of the first protective layer on the base substrate at least covers the pinhole area;

[0093] The display substrate further includes a buffer layer disposed between the first protection layer and the thin film transistor array layer.

[0094] In at least one embodiment of the present invention, the base substrate may be a flexible substrate, for example, a PI (polyimide) substrate, but the present invention is not limited thereto.

[0095] In at least one embodiment of the present invention, the light shielding layer may be made of metal material, but is not limited thereto.

[0096] The display substrate described in at least one embodiment of the present invention sets at least a part of the positive projection of the imaging hole included in the light-shielding layer on the base substrate within the first area, so that the imaging hole will not be blocked by the metal film layer included in the thin-film transistor array layer, thereby enabling good fingerprint recognition. In addition, the display substrate described in the embodiment of the present invention is provided with a first protective layer between the light-shielding layer and the thin-film transistor array layer to effectively prevent plasma from gathering on the light-shielding layer, prevent the arc from breaking through the light-shielding layer, and improve the fingerprint recognition effect.

[0097] In the related art, when manufacturing a display substrate, after depositing the light-shielding layer, it is necessary to continue to deposit the semiconductor layer and the inorganic layer. Because the semiconductor layer and the inorganic layer are deposited using a high-temperature and high-frequency film-forming process, plasma aggregation will form on the surface of the light-shielding metal layer, and then an arc will break through the light-shielding layer to form light leakage holes on the light-shielding layer, causing weak light leakage and affecting the fingerprint recognition effect. Based on this, the display substrate described in at least one embodiment of the present invention sets at least a part of the positive projection of the imaging holes included in the light-shielding layer on the base substrate within the first area, and a first protective layer is provided between the light-shielding layer and the thin-film transistor array layer.

[0098] In a specific implementation, the orthographic projection of the first protective layer on the base substrate covers at least a portion of the first area, thereby preventing the portion of the light-shielding layer corresponding to the first area from being punctured by an electric arc to produce light leakage holes, thereby preventing stray light passing through the light leakage holes from affecting the fingerprint imaging effect.

[0099] In at least one embodiment of the present invention, the first region may include a pinhole region, and at least a portion of the orthographic projection of the imaging pinhole on the substrate is disposed in the pinhole region.

[0100] In a specific implementation, the orthographic projection of the first protection layer on the base substrate at least covers the small hole area.

[0101] In at least one embodiment of the present invention, the buffer layer may be made of silicon nitride, silicon oxide or polysilicon, but is not limited thereto.

[0102] In a specific implementation, the thickness of the buffer layer may be greater than or equal to 200 nanometers and less than or equal to 600 nanometers, but is not limited thereto.

[0103] like Figure 1 As shown, in the embodiment of the related display substrate, the first protective layer is not provided; Figure 1 In the invention, the base substrate comprises a first base substrate P1 and a second base substrate P2;

[0104] A fingerprint recognition layer S0 is provided on a side of the first substrate P1 facing away from the second substrate P2;

[0105] A first barrier film layer B1 is provided between the first substrate P1 and the second substrate P2;

[0106] A second barrier film layer B2 is provided between the second substrate P2 and the light shielding layer S1;

[0107] The light shielding layer S1 includes a first imaging pinhole H1;

[0108] exist Figure 1 In the embodiment of the related display substrate shown, the thin film transistor array layer includes an active layer AT1, a first gate metal layer G1, a second gate metal layer G2, a first gate insulating layer GI1, a second gate insulating layer GI2, a third insulating layer GI3 and a source-drain metal layer Sd arranged in sequence; wherein the metal film layer in the thin film transistor array layer includes: a first gate metal layer G1, a second gate metal layer G2 and a source-drain metal layer Sd;

[0109] exist Figure 1 In the embodiment of the related display substrate shown, a buffer layer Bf is provided between the light shielding layer S1 and the thin film transistor array layer, a planarization layer Pn is provided above the source and drain metal layer Sd, and an anode layer An is provided on the planarization layer Pn;

[0110] exist Figure 1 In the embodiment of the related display substrate shown, the anode layer An may be made of metal, for example, may be made of silver, but not limited thereto.

[0111] exist Figure 1 In the embodiment of the related display substrate shown, the light shielding layer S1 may be a metal layer. The light shielding layer S1 may be made of a metal material. The pattern of the metal layer may include a signal line, but is not limited thereto.

[0112] exist Figure 1 In the embodiment of the related display substrate shown, the third insulating layer GI3 may be an interlayer insulating layer, but is not limited thereto.

[0113] exist Figure 1 In the figure, only the first imaging pinhole H1 is shown. In actual operation, the light shielding layer S1 includes a plurality of imaging pinholes.

[0114] exist Figure 1 In the figure, the dotted line shows the light passing through the first imaging pinhole H1.

[0115] exist Figure 1 In the embodiment of the related display substrate shown in FIG. 1 , the first imaging pinhole H1 allows light to enter the fingerprint recognition layer S0 through the first imaging pinhole H1 so as to perform fingerprint recognition. However, after depositing the light shielding layer S1, it is necessary to continue to deposit the semiconductor layer and the inorganic layer (wherein the semiconductor layer may be, for example, an active layer, and the inorganic layer may be, for example, a buffer layer), and because the deposition of the semiconductor layer and the inorganic layer adopts a high-temperature and high-frequency film-forming process, plasma aggregation will be formed on the surface of the light shielding metal layer, and then the light shielding metal layer will be formed. Figure 2 As shown, the electric arc breaks through the light shielding layer to form a light leakage hole H0 on the light shielding layer, causing weak light leakage. After the light leakage is detected by the fingerprint recognition sensor included in the fingerprint recognition layer S0, it will affect the fingerprint recognition effect.

[0116] Based on this, in the embodiment of the present invention, after depositing the light shielding layer, the first protective layer is deposited before Multi deposition (multi-layer deposition refers to the simultaneous deposition of an inorganic layer and a semiconductor layer), which can effectively prevent the arc from breaking through the light shielding layer.

[0117] exist Figure 2 In the figure, the dotted line shows the light, which includes: the light passing through the first imaging pinhole H1, and the light passing through the light leakage pinhole H0. Preferably, the film forming temperature of the first protective layer is less than the threshold temperature;

[0118] The threshold temperature is greater than or equal to 230 degrees Celsius and less than or equal to 380 degrees Celsius, but is not limited thereto.

[0119] In actual operation, the threshold temperature may be adjusted accordingly according to actual conditions.

[0120] In a preferred case, the first protective layer is a low-temperature protective layer. After the light shielding layer is deposited, the first protective layer is formed by a low-temperature process, and then a high-temperature and high-power film is formed. The first protective layer can effectively prevent plasma from gathering on the light shielding layer to prevent arc breakdown. The specific film forming conditions depend on the imaging clarity and process requirements.

[0121] In at least one embodiment of the present invention, the first protective layer may be made of an inorganic material or an organic material. For example, the first protective layer may be made of silicon oxide or silicon nitride, but is not limited thereto.

[0122] In a specific implementation, the thickness of the first protective layer may be greater than or equal to 100 nanometers and less than or equal to 400 nanometers, but is not limited thereto.

[0123] In at least one embodiment of the present invention, the first protective layer may be a transparent film layer; or, the first protective layer is opaque, in which case a photomask is required to dig out the first protective layer at the imaging pinhole position to prevent the pinhole from blocking light transmission during imaging.

[0124] Specifically, the first protective layer may be made of silicon oxide or silicon nitride, but is not limited thereto.

[0125] In a specific implementation, the thickness of the first protective layer may be greater than or equal to 100 nanometers and less than or equal to 400 nanometers, but is not limited thereto.

[0126] Specifically, the display substrate according to at least one embodiment of the present invention may further include a fingerprint recognition layer; the fingerprint recognition layer is arranged on a side of the base substrate away from the light shielding layer, and the fingerprint recognition layer includes a fingerprint recognition sensor;

[0127] The light shielding layer is arranged on the light incident side of the fingerprint recognition sensor, and the imaging pinhole allows light to be incident on the fingerprint recognition sensor through the imaging pinhole so as to perform fingerprint recognition.

[0128] In a specific implementation, the fingerprint recognition layer may include a plurality of fingerprint recognition sensors arranged in an array, but is not limited thereto.

[0129] In at least one embodiment of the present invention, the light shielding layer is made of a light-proof material, such as metal, but not limited thereto.

[0130] Specifically, the display substrate according to at least one embodiment of the present invention may further include a planar layer and an anode layer which are sequentially arranged on a side of the thin film transistor array layer away from the buffer layer;

[0131] The orthographic projection of the imaging pinhole on the substrate does not overlap with the orthographic projection of the anode layer on the substrate.

[0132] In at least one embodiment of the present invention, the buffer layer may be made of silicon nitride, silicon oxide or polysilicon, but is not limited thereto.

[0133] In a specific implementation, the thickness of the buffer layer may be greater than or equal to 200 nanometers and less than or equal to 600 nanometers, but is not limited thereto.

[0134] In a specific implementation, the anode layer may be made of, for example, a material capable of reflecting light, but is not limited thereto.

[0135] In a preferred case, the orthographic projection of the imaging hole on the base substrate does not overlap with the orthographic projection of the anode layer on the base substrate, so that the imaging hole will not be blocked by the anode layer that can block light, and fingerprint imaging will not be affected.

[0136] Specifically, the display substrate described in at least one embodiment of the present invention may further include an organic light-emitting layer and a cathode layer which are sequentially arranged on a side of the anode layer away from the planar layer.

[0137] In a specific implementation, the cathode layer may be made of, for example, a transparent conductive material, but is not limited thereto.

[0138] like Figure 3 As shown, the display substrate described in at least one embodiment of the present invention includes a base substrate, and a light shielding layer S1, a first protective layer P0 and a thin film transistor array layer sequentially located on the base substrate; the light shielding layer S1 includes a first imaging pinhole H1;

[0139] The base substrate includes a first base substrate P1 and a second base substrate P2;

[0140] A fingerprint recognition layer S0 is provided on a side of the first substrate P1 facing away from the second substrate P2;

[0141] A first barrier film layer B1 is provided between the first substrate P1 and the second substrate P2;

[0142] A second barrier film layer B2 is provided between the second substrate P2 and the light shielding layer S1;

[0143] The light shielding layer S1 includes a first imaging pinhole H1;

[0144] exist Figure 3In the display substrate described in at least one embodiment of the present invention, the thin film transistor array layer includes an active layer AT1, a first gate metal layer G1, a second gate metal layer G2, a first gate insulating layer GI1, a second gate insulating layer GI2, a third insulating layer GI3 and a source-drain metal layer Sd arranged in sequence; wherein the metal film layer in the thin film transistor array layer includes: a first gate metal layer G1, a second gate metal layer G2 and a source-drain metal layer Sd;

[0145] exist Figure 3 In the display substrate described in at least one embodiment of the present invention, a buffer layer Bf is provided between the light shielding layer S1 and the thin film transistor array layer, a planarization layer Pn is provided above the source and drain metal layer Sd, and an anode layer An is provided on the planarization layer Pn.

[0146] In at least one embodiment of the present invention, the third insulating layer GI3 may be an interlayer insulating layer, but is not limited thereto.

[0147] exist Figure 3 In at least one embodiment of the display substrate shown in FIG. 1 , the anode layer An may be made of silver, or ITO (indium tin oxide), silver, and ITO may be stacked in sequence, but the present invention is not limited thereto; and Figure 3 In the figure, only the first imaging pinhole H1 is shown, but in actual operation, the light shielding layer S1 may include a plurality of imaging pinholes.

[0148] In a specific embodiment, the plurality of imaging pinholes may correspond to the pixel regions one by one, or one imaging pinhole may be provided in the plurality of pixel regions, as long as the imaging accuracy is met.

[0149] exist Figure 3 In at least one embodiment of the display substrate shown, the orthographic projection of the first imaging hole H1 on the second substrate substrate P2 does not overlap with the orthographic projection of the metal film layer in the thin film transistor array layer on the second substrate substrate P2, and the orthographic projection of the first imaging hole H1 on the second substrate substrate P2 does not overlap with the orthographic projection of the anode layer An on the second substrate substrate P2, so that the first imaging hole H1 is not blocked by the metal film layer and the anode layer An.

[0150] And, in making Figure 3 In at least one embodiment of the display panel shown, after the light-shielding layer S1 is deposited, a first protective layer P0 is formed by a low-temperature process, and then a high-temperature and high-power film is formed on the first protective layer P0. The first protective layer P0 can effectively prevent plasma from gathering on the light-shielding layer S1, prevent the arc from breaking through the light-shielding layer S1 and forming small light leakage holes, thereby improving the clarity of fingerprint recognition.

[0151] In at least one embodiment of the present invention, a first protective layer P0 is formed by a low-temperature process, and then a high-temperature and high-power film is formed on the first protective layer P0. Since the film forming temperatures and / or film forming powers of the two film layers are different, there will be a more obvious interface between the two film layers.

[0152] In the making Figure 3 In at least one embodiment of the display panel shown, the film forming temperature of the first protection layer P0 may be less than 230 degrees Celsius, but is not limited thereto.

[0153] exist Figure 3 In the figure, the dotted line indicates the light passing through the first imaging pinhole H1.

[0154] exist Figure 3 In the display substrate described in at least one embodiment of the present invention, the light shielding layer S1 may be a metal layer, and the pattern of the metal layer may include a signal line, but is not limited thereto.

[0155] In a specific implementation, in order to prevent problems such as static electricity, the light shielding layer S1 cannot be in a floating state, that is, the light shielding layer S1 needs to be connected to a voltage.

[0156] like Figure 4 As shown, in Figure 3 On the basis of the display substrate according to at least one embodiment of the present invention shown, the display substrate according to at least one embodiment of the present invention may further include a pixel defining layer D1 disposed on a side of the anode layer An away from the planar layer Pn, wherein the pixel defining layer D1 defines a pixel area;

[0157] The display substrate further includes an organic light emitting layer 41 disposed in the pixel region, and a cathode layer 42 disposed on the organic light emitting layer 41;

[0158] When the cathode layer 42 is touched by a finger, the light directed toward the finger emitted by the organic light-emitting layer 41 is reflected by the finger to form downward light, which passes through the imaging holes included in the light-shielding layer S1 and is emitted to the fingerprint recognition layer S0. The fingerprint recognition layer S0 detects the light and performs fingerprint recognition.

[0159] In at least one embodiment of the present invention, in addition to the pinhole area, the first area may also include other areas. The orthographic projection of the metal film layer included in the thin film transistor array layer on the substrate is not arranged in the other area, but the orthographic projection of the imaging pinhole on the substrate is not in the other area. Instead, the orthographic projection of the imaging pinhole on the substrate may be close to the other area. Therefore, if the first protective layer is not used to protect the other area, the fingerprint imaging effect may also be affected.

[0160] In a specific implementation, the thin film transistor array layer may include a pixel circuit; a circuit diagram of at least one embodiment of the pixel circuit may be as follows: Figure 5 shown.

[0161] like Figure 5 As shown, the pixel circuit may include a light emitting element 120, a driving circuit 122, a first light emitting control circuit 123, and a second light emitting control circuit 124. The driving circuit 122 includes a control terminal, a first terminal, and a second terminal, and is configured to provide the light emitting element 120 with a driving current for driving the light emitting element 120 to emit light. For example, the second light emitting control circuit 123 is connected to the first terminal of the driving circuit 122 and the first power line VDD, and is configured to control the connection or disconnection between the driving circuit 122 and the first power line VDD, and the first light emitting control circuit 124 is electrically connected to the second terminal of the driving circuit 122 and the first light emitting voltage applying electrode of the light emitting element 120, and is configured to control the connection or disconnection between the driving circuit 122 and the light emitting element 120.

[0162] like Figure 5 As shown, the pixel circuit 121 further includes a data writing circuit 126, a first storage circuit 127, a threshold compensation circuit 128, a reset circuit 129 and a second storage circuit 130. The data writing circuit 126 is electrically connected to the first end of the driving circuit 122, and is configured to write the data voltage on the data line Vd into the storage circuit 127 under the control of the scanning signal; the first storage circuit 127 is electrically connected to the control end of the driving circuit 122 and the first power line VDD, and is configured to store the data voltage; the threshold compensation circuit 128 is electrically connected to the control end of the driving circuit 122 and the second end of the driving circuit 122, and is configured to perform threshold compensation on the driving circuit 122; the reset circuit 129 is electrically connected to the control end of the driving circuit 122 and the first light emitting voltage applying electrode of the light emitting element 120, and is configured to reset the control end of the driving circuit 122 and the first light emitting voltage applying electrode of the light emitting element 120 under the control of the reset control signal.

[0163] For example, Figure 5 As shown, the driving circuit 122 includes a driving transistor T1, the control end of the driving circuit 122 includes the gate of the driving transistor T1, the first end of the driving circuit 122 includes the first electrode of the driving transistor T1, and the second end of the driving circuit 122 includes the second electrode of the driving transistor T1.

[0164] For example, Figure 5As shown, the data write circuit 126 includes a data write transistor T2, the first storage circuit 127 includes a first storage capacitor C2, the threshold compensation circuit 128 includes a threshold compensation transistor T3, the second light emitting control circuit 123 includes a second light emitting control transistor T4, the first light emitting control circuit 124 includes a first light emitting control transistor T5, and the reset circuit 129 includes a first reset transistor T6 and a second reset transistor T7.

[0165] For example, Figure 5 As shown, the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data voltage, and the gate of the data writing transistor T2 is configured to be electrically connected to the gate line Ga to receive the scanning signal; the first electrode plate CC1a of the first storage capacitor C2 is electrically connected to the first power line VDD, and the second electrode plate CC2a of the first storage capacitor C2 is electrically connected to the gate of the driving transistor T1; the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 is configured to be electrically connected to the gate line Ga to receive the scanning signal; the first electrode of the first reset transistor T6 is configured to be electrically connected to the reset power line Vinit to receive the reset signal, the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the reset control signal line Rst to receive the reset control signal; The first electrode of the second reset transistor T7 is configured to be electrically connected to the reset power line Vinit to receive a reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first light-emitting voltage applying electrode of the light-emitting element 120, and the gate of the second reset transistor T7 is configured to be electrically connected to the reset control signal line Rst to receive the reset control signal; the first electrode of the second light-emitting control transistor T4 is electrically connected to the first power line VDD, the second electrode of the second light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the second light-emitting control transistor T4 is configured to be electrically connected to the light-emitting control signal line EM to receive the light-emitting control signal; the first electrode of the first light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the first light-emitting control transistor T5 is electrically connected to the first light-emitting voltage applying electrode of the light-emitting element 120, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control signal line EM to receive the light-emitting control signal; the second light-emitting voltage applying electrode of the light-emitting element 120 is electrically connected to the second power line VSS.

[0166] For example, Figure 5As shown, the second storage circuit 130 may include a second storage capacitor C11; the first plate CC3a of the second storage capacitor C11 is electrically connected to the first light-emitting voltage applying electrode of the light-emitting element 120, and the second plate CC4a of the second storage capacitor C11 is electrically connected to the gate of the driving transistor T1.

[0167] For example, one of the first power line VDD and the second power line VSS is a high voltage line, and the other is a low voltage line. Figure 5 In at least one embodiment shown, the first power line VDD is a voltage source to output a constant first voltage, the first voltage is a positive voltage, and the second power line VSS can be a voltage source to output a constant second voltage, the second voltage is a negative voltage, etc. For example, in some examples, the second power line VSS can be grounded.

[0168] For example, the reset power line Vinit can be a DC reference voltage line to output a constant DC reference voltage. Vinit can be a high voltage line or a low voltage line, as long as it can provide a reset signal to reset the gate of the driving transistor T1 and the first light-emitting voltage applying electrode of the light-emitting element 120, and the present invention is not limited to this.

[0169] It should be noted that the gate of T7 and the gate of T6 may be connected to different reset control signal lines, the first electrode of T6 and the first electrode of T7 may be connected to different reset power lines, the gate of T4 and the gate of T5 may be connected to different light-emitting control signal lines, and the gate of T3 and the gate of T2 may be connected to different gate lines, but the present invention is not limited thereto.

[0170] It should be noted that Figure 5 The driving circuit 122, data writing circuit 126, storage circuit 127, threshold compensation circuit 128 and reset circuit 129 in the pixel circuit shown are only for illustration. The specific structures of the driving circuit 122, data writing circuit 126, storage circuit 127, threshold compensation circuit 128 and reset circuit 129 can be set according to actual application requirements, and the embodiments of the present invention do not specifically limit this.

[0171] For example, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present invention take the transistor as a P-type transistor as an example to elaborate on the technical solution of the present invention. That is to say, in the description of the present invention, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light-emitting control transistor T4, the first light-emitting control transistor T5, the first reset transistor T6 and the second reset transistor T7 can all be P-type transistors. However, the transistors of the embodiments of the present invention are not limited to P-type transistors. Those skilled in the art can also use N-type transistors to implement the functions of one or more transistors in the embodiments of the present invention according to actual needs.

[0172] It should be noted that the transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present invention, in order to distinguish transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present invention can be interchangeable as needed.

[0173] In a specific implementation, the thin film transistor array layer may include a semiconductor material layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer.

[0174] In at least one embodiment of the present invention, the semiconductor material layer may be an active layer, but is not limited thereto.

[0175] Figure 6 It is a partial layout schematic diagram of a semiconductor material layer pattern. The semiconductor material layer pattern may be an active layer pattern, but is not limited thereto.

[0176] like Figure 6 As shown, the semiconductor material layer pattern of the threshold compensation transistor T3 may include a first channel portion T3a1 and a second channel portion T3a2;

[0177] The semiconductor material layer pattern of the first light emission control transistor T5 may include a third channel portion T5a;

[0178] The semiconductor material layer pattern of the driving transistor T1 may include a fourth channel portion T1a;

[0179] The semiconductor material layer pattern of the data writing transistor T2 may include a fifth channel portion T2a;

[0180] The semiconductor material layer pattern of the second light emission control transistor T4 may include a sixth channel portion T4a;

[0181] The semiconductor material layer pattern of the first reset transistor T6 may include a seventh channel portion T6a1 and an eighth channel portion T6a2;

[0182] The semiconductor material layer pattern of the second reset transistor T7 may include a ninth channel portion T7a.

[0183] exist Figure 7 in Figure 6 On the basis of the semiconductor material layer pattern shown, the semiconductor material layer pattern labeled 71 is the first conductive portion included in the first reset transistor T6, and the semiconductor material layer pattern labeled 72 is the second conductive portion included in the threshold compensation transistor T3;

[0184] exist Figure 7 In the figure, the reference numeral 73 may be a third conductive portion included in the semiconductor material layer of the threshold compensation transistor T3; the third conductive portion 73 is disposed between the first channel portion T3a1 and the second channel portion T3a2;

[0185] The reference numeral 74 may be a fourth conductive portion included in the semiconductor material layer pattern of the first light emission control transistor T5; the fourth conductive portion 74 is disposed between the second channel portion T3a2 and the third channel portion T5a.

[0186] Figure 8 It is a partial layout diagram of the source and drain metal layer graphics.

[0187] exist Figure 8 , the first electrode of the first reset transistor T6 is labeled 342a, the second electrode of the threshold compensation transistor T3 is labeled 341a, and the third electrode of the first light emission control transistor T5 is labeled 343a; the data line is labeled Vd, and the first power line is labeled VDD;

[0188] In at least one embodiment of the present invention, the first electrode 342a of T6 may be the source of T6, the second electrode 341a of T3 may be the source of T3, and the third electrode 343a of T5 may be the drain of T5, but the present invention is not limited thereto.

[0189] exist Fig. 9 , the gate labeled T6g is the gate of T6, the gate labeled T7g is the gate of T7, the gate labeled T2g is the gate of T2, the gate labeled T4g is the gate of T4, the gate labeled T5g is the gate of T5, and the gate labeled T3g is the gate of T3;

[0190] The gate of T1 is multiplexed into CC2a and CC4a;

[0191] exist Fig. 9 In the figure, the line labeled Rst is a reset control signal line, the line labeled Ga is a gate line, and the line labeled EM is a light emitting control signal line;

[0192] exist Fig. 9 In the figure, the reference numeral 90 is a first gate metal pattern, and the first gate metal pattern 90 is a gate metal pattern between the gate line Ga and the gate T3g of T3.

[0193] exist Fig.10 Among them, the one labeled Vinit is the reset power line, and the one labeled CC1a is the first electrode plate of C2.

[0194] Fig.11 Yes Figure 7 The semiconductor material layer pattern shown, Figure 8 The source and drain metal layer patterns shown, Fig. 9 The first gate metal layer pattern and Fig.10 A top view of the second gate metal layer patterns superimposed.

[0195] exist Fig.11 , the via hole labeled 383a is the first via hole, the via hole labeled 382a is the second via hole, the via hole labeled 383a is the third via hole, the via hole labeled 384a is the fourth via hole, the via hole labeled 385a is the fifth via hole, the via hole labeled 386a is the sixth via hole, the via hole labeled 387a is the seventh via hole, and the via hole labeled 388a is the eighth via hole;

[0196] The third electrode 343 a of T5 may be electrically connected to the anode layer through the eighth via hole 388 a .

[0197] like Fig.11 As shown, the first conductive portion 71 is electrically connected to the first electrode 342a included in the first reset transistor through the seventh via hole 387a; the first electrode 342a is electrically connected to the reset power line Vinit through the sixth via hole 386a;

[0198] The second conductive portion 72 is electrically connected to the second electrode 341 a included in the threshold compensation transistor through the fourth via hole 384 a ; the second electrode 341 a is electrically connected to the gate of the driving transistor through the fifth via hole 385 a .

[0199] In at least one embodiment of the present invention, the first region may include a first sub-region;

[0200] The thin film transistor array layer includes a reset power line, a first reset transistor, a threshold compensation transistor and a driving transistor;

[0201] The first sub-region does not overlap with an orthographic projection of a first conductive portion included in the semiconductor material layer pattern of the first reset transistor on the substrate and an orthographic projection of a second conductive portion included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate;

[0202] The first conductive portion is electrically connected to a first electrode included in the first reset transistor; the first electrode is electrically connected to the reset power line;

[0203] The second conductive portion is electrically connected to a second electrode included in the threshold compensation transistor; and the second electrode is electrically connected to a gate of the driving transistor.

[0204] like Fig.12 As shown, the first area may include a first sub-area A1;

[0205] The first sub-region A1 does not overlap with an orthographic projection of a first conductive portion 71 included in the semiconductor material layer pattern of the first reset transistor T6 on the substrate and an orthographic projection of a second conductive portion 72 included in the semiconductor material layer pattern of the threshold compensation transistor T3 on the substrate;

[0206] The first conductive portion 71 is electrically connected to the first electrode 342a included in the first reset transistor T6; the first electrode 342a is electrically connected to the reset power line Vinit;

[0207] The second conductive portion 72 is electrically connected to the second electrode 341 a included in the threshold compensation transistor T3 ; the second electrode 341 a is electrically connected to the gate of the driving transistor T1 .

[0208] In at least one embodiment of the present invention, the first region may include a second sub-region;

[0209] The thin film transistor array layer includes a gate line, a threshold compensation transistor and a driving transistor;

[0210] The second sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate, the orthographic projection of the second conductive part included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate, and the orthographic projection of the first gate metal pattern on the substrate;

[0211] The second conductive portion is electrically connected to a second electrode included in the threshold compensation transistor; the second electrode is electrically connected to a gate of the driving transistor;

[0212] The first gate metal pattern is a gate metal pattern between the gate line and the gate of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

[0213] like Fig.13 As shown, the first area may include a second sub-area A2;

[0214] The second sub-region A2 does not overlap with the orthographic projection of the gate line Ga on the base substrate, the orthographic projection of the second electrode 341a included in the threshold compensation transistor T3 on the base substrate, the orthographic projection of the second conductive portion 72 included in the semiconductor material layer pattern of the threshold compensation transistor T3 on the base substrate, and the orthographic projection of the first gate metal pattern 90 on the base substrate;

[0215] The second conductive portion 72 is electrically connected to the second electrode 341a included in the threshold compensation transistor T3; the second electrode 341a is electrically connected to the gate of the driving transistor T1;

[0216] The first gate metal pattern 90 is a gate metal pattern between the gate line Ga and the gate of the threshold compensation transistor T3 included in the first gate metal layer in the thin film transistor array layer.

[0217] In at least one embodiment of the present invention, the first region may include a third sub-region;

[0218] The thin film transistor array layer includes a gate line, a threshold compensation transistor and a driving transistor;

[0219] The third sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the third conductive portion included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate, and the orthographic projection of the first gate metal pattern on the substrate;

[0220] The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the third conductive portion is disposed between the first channel portion and the second channel portion;

[0221] The first gate metal pattern is a gate metal pattern between the gate line and the gate of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

[0222] like Fig.14 As shown, the first area may include a third sub-area A3;

[0223] The third sub-region A3 does not overlap with the orthographic projection of the gate line Ga on the substrate, the orthographic projection of the third conductive portion 73 included in the semiconductor material layer pattern of the threshold compensation transistor T3 on the substrate, and the orthographic projection of the first gate metal pattern 90 on the substrate;

[0224] The semiconductor material layer pattern of the threshold compensation transistor T3 includes a first channel portion T3a1 and a second channel portion T3a2, and the third conductive portion 73 is disposed between the first channel portion T3a1 and the second channel portion T3a2;

[0225] The first gate metal pattern 90 is a gate metal pattern between the gate line Ga and the gate of the threshold compensation transistor T3 included in the first gate metal layer in the thin film transistor array layer.

[0226] In at least one embodiment of the present invention, the first region may include a fourth sub-region;

[0227] The thin film transistor array layer includes a gate line, a first capacitor, a threshold compensation transistor and a first light emission control transistor;

[0228] The fourth sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the first plate of the first capacitor on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate, and the orthographic projection of the fourth conductive portion included in the semiconductor material layer pattern of the first light emission control transistor on the substrate;

[0229] The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the semiconductor material layer pattern of the first light emission control transistor includes a third channel portion;

[0230] The fourth conductive portion is disposed between the second channel portion and the third channel portion.

[0231] like Fig.15 As shown, the first area may include a fourth sub-area A4;

[0232] The fourth sub-region A4 does not overlap with the orthographic projection of the gate line Ga on the substrate, the orthographic projection of the first plate CC1a of the first capacitor C2 on the substrate, the orthographic projection of the second electrode 341a included in the threshold compensation transistor T3 on the substrate, and the orthographic projection of the fourth conductive portion 74 included in the semiconductor material layer pattern of the first light emission control transistor T5 on the substrate;

[0233] The semiconductor material layer pattern of the threshold compensation transistor T3 includes a first channel portion T3a1 and a second channel portion T3a2, and the semiconductor material layer pattern of the first light emission control transistor T5 includes a third channel portion T5a;

[0234] The fourth conductive portion 74 is disposed between the second channel portion T3a2 and the third channel portion T5a.

[0235] In at least one embodiment of the present invention, the first region may include a fifth sub-region;

[0236] The thin film transistor array layer includes a first capacitor, a threshold compensation transistor, a first light emission control transistor, a first power line and a light emission control signal line;

[0237] The fifth sub-region does not overlap with the orthographic projection of the first electrode plate of the first capacitor on the substrate, the orthographic projection of the light emitting control signal line on the substrate, the orthographic projection of the first power line on the substrate, and the orthographic projection of the fourth conductive portion included in the semiconductor material layer pattern of the first light emitting control transistor on the substrate;

[0238] The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the semiconductor material layer pattern of the first light emission control transistor includes a third channel portion;

[0239] The fourth conductive portion is disposed between the second channel portion and the third channel portion.

[0240] like Fig.16 As shown, the first area may include a fifth sub-area A5;

[0241] The fifth sub-region A5 does not overlap with the orthographic projection of the first electrode plate CC1a of the first capacitor C2 on the substrate, the orthographic projection of the light emitting control signal line EM on the substrate, the orthographic projection of the first power line VDD on the substrate, and the orthographic projection of the fourth conductive portion 74 included in the semiconductor material layer pattern of the first light emitting control transistor T5 on the substrate;

[0242] The semiconductor material layer pattern of the threshold compensation transistor T3 includes a first channel portion T3a1 and a second channel portion T3a2, and the semiconductor material layer pattern of the first light emission control transistor T5 includes a third channel portion T5a;

[0243] The fourth conductive portion 74 is disposed between the second channel portion T3a2 and the third channel portion T5a.

[0244] In a specific implementation, the display substrate described in at least one embodiment of the present invention further includes an anode layer disposed on a side of the thin film transistor array layer away from the first protective layer;

[0245] The thin film transistor array layer includes a first power line and a first light emission control transistor;

[0246] The pinhole area does not overlap with the orthographic projection of the first power line on the base substrate and the orthographic projection of the third electrode included in the first light emission control transistor on the base substrate;

[0247] The third electrode is electrically connected to the anode layer.

[0248] like Fig.17 As shown, the pinhole area A0 does not overlap with the orthographic projection of the first power line VDD on the base substrate and the orthographic projection of the third electrode 343a included in the first light emission control transistor T5 on the base substrate.

[0249] like Fig.18 As shown, in Fig.12 On this basis, a tangent line A-A' is added. Fig.19 It is a cross-sectional view along the tangent line AA'.

[0250] like Fig.19 As shown, in the first sub-region A1, at least a first gate insulating layer GI1, a second gate insulating layer GI2 and a third insulating layer GI3 are provided.

[0251] exist Fig.19 Among them, labeled S0 is the fingerprint recognition layer, labeled P1 is the first base substrate, labeled B1 is, labeled P2 is the second base substrate, labeled B2 is, labeled S1 is the shading layer, labeled P0 is the first protective layer, labeled Bf is the buffer layer, labeled AT1 is the active layer, labeled Sd is the source and drain metal layer, and labeled Pn is the planarization layer.

[0252] In at least one embodiment of the present invention, each sub-region included in the first region may be provided with at least a first gate insulating layer GI1 , a second gate insulating layer GI2 , and a third insulating layer GI3 , but the present invention is not limited thereto.

[0253] And, in Fig.17 In the figure, the cross-sectional view along the tangent line passing through the via hole on the left side of the small hole area A0, the small hole area A0 and the via hole on the right side of the small hole area A0 can also be as shown in FIG. Fig.19 As shown, but not limited to.

[0254] In a specific implementation, the metal film layer included in the thin film transistor array layer may include a first metal layer, a second metal layer and a third metal layer;

[0255] The gate line, the reset control signal line, the light emitting control signal line, the second plate of the first storage capacitor, and the gates of each transistor included in the pixel circuit are located in the first metal layer;

[0256] A reset power line and a first plate of the first storage capacitor are located in the second metal layer;

[0257] A first power line, a data line, and a first electrode and a second electrode included in the transistor are located in the third metal layer.

[0258] In at least one embodiment of the present invention, the first metal layer may be a first gate metal layer, the second metal layer may be a second gate metal layer, and the third metal layer may be a source-drain metal layer, but the present invention is not limited thereto.

[0259] A method for manufacturing a display substrate according to at least one embodiment of the present invention comprises:

[0260] A light shielding layer is formed on a base substrate; a first region is provided on the base substrate, the light shielding layer includes a plurality of imaging pinholes, and at least a part of the orthographic projection of the imaging pinholes on the base substrate is provided in the first region;

[0261] forming a first protective layer on a side of the light shielding layer away from the base substrate;

[0262] forming a thin film transistor array layer on the first protective layer, so that an orthographic projection of a metal film layer included in the thin film transistor array layer on the base substrate is disposed outside the first region;

[0263] The orthographic projection of the first protective layer on the base substrate at least covers a portion of the first area;

[0264] The first region includes a pinhole region, and at least a portion of an orthographic projection of the imaging pinhole on the substrate is disposed within the pinhole region; the orthographic projection of the first protective layer on the substrate at least covers the pinhole region.

[0265] The manufacturing method of the display substrate described in at least one embodiment of the present invention sets at least a part of the positive projection of the imaging hole included in the light-shielding layer on the base substrate within the first area, so that the imaging hole will not be blocked by the metal film layer included in the thin-film transistor array layer, thereby enabling good fingerprint recognition. In addition, the display substrate described in at least one embodiment of the present invention is provided with a first protective layer between the light-shielding layer and the thin-film transistor array layer to effectively prevent plasma from gathering on the light-shielding layer, prevent the arc from breaking through the light-shielding layer, and improve the fingerprint recognition effect.

[0266] In a specific implementation, the orthographic projection of the first protective layer on the base substrate covers at least a portion of the first area, thereby preventing the portion of the light-shielding layer corresponding to the first area from being punctured by an electric arc to produce light leakage holes, thereby preventing stray light passing through the light leakage holes from affecting the fingerprint imaging effect.

[0267] In a preferred embodiment, the step of forming a first protective layer on a side of the light shielding layer away from the base substrate comprises:

[0268] A first protective layer is formed on a side of the light shielding layer away from the base substrate by using a low temperature process; the film forming temperature of the first protective layer is lower than a threshold temperature;

[0269] The threshold temperature is greater than or equal to 230 degrees Celsius and less than or equal to 380 degrees Celsius.

[0270] In a preferred case, the first protective layer is a low-temperature protective layer. After the light shielding layer is deposited, the first protective layer is formed by a low-temperature process, and then a high-temperature and high-power film is formed. The first protective layer can effectively prevent plasma from gathering on the light shielding layer to prevent arc breakdown. The specific film forming conditions depend on the imaging clarity and process requirements.

[0271] In at least one embodiment of the present invention, the step of forming a first protective layer on a side of the light shielding layer away from the base substrate by using a low temperature process may include:

[0272] The first protective layer is formed by using inorganic material or organic material through a low temperature process on the side of the light shielding layer away from the base substrate.

[0273] A display panel according to at least one embodiment of the present invention includes the above-mentioned display substrate.

[0274] A display device according to at least one embodiment of the present invention includes the above-mentioned display panel.

[0275] The display device provided in at least one embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0276] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: It includes a substrate, and a light shielding layer and a thin film transistor array layer sequentially located on the substrate; the light shielding layer includes a plurality of imaging pinholes; A first protective layer is disposed between the light shielding layer and the thin film transistor array layer; A first area is provided on the base substrate, and an orthographic projection of the metal film layer included in the thin film transistor array layer on the base substrate is arranged outside the first area; At least a part of the orthographic projection of the imaging pinhole on the substrate is disposed within the first region; The orthographic projection of the first protective layer on the base substrate at least covers a portion of the first area; The first region includes a pinhole region, and at least a portion of the orthographic projection of the imaging pinhole on the substrate is disposed in the pinhole region; The orthographic projection of the first protective layer on the base substrate at least covers the pinhole area; The display substrate further includes a buffer layer disposed between the first protection layer and the thin film transistor array layer; The first region includes a first sub-region; The thin film transistor array layer includes a reset power line, a first reset transistor, a threshold compensation transistor and a driving transistor; The first sub-region does not overlap with an orthographic projection of a first conductive portion included in the semiconductor material layer pattern of the first reset transistor on the substrate and an orthographic projection of a second conductive portion included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate; The first conductive portion is electrically connected to a first electrode included in the first reset transistor; the first electrode is electrically connected to the reset power line; The second conductive portion is electrically connected to a second electrode included in the threshold compensation transistor; the second electrode is electrically connected to a gate of the driving transistor; The film forming temperature of the first protective layer is lower than a threshold temperature; The threshold temperature is greater than or equal to 230 degrees Celsius and less than or equal to 380 degrees Celsius; The first protective layer is made of an inorganic material and is directly disposed on the light shielding layer.

2. The display substrate according to claim 1, wherein: The first region includes a second sub-region; The thin film transistor array layer includes a gate line, a threshold compensation transistor and a driving transistor; The second sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate, the orthographic projection of the second conductive part included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate, and the orthographic projection of the first gate metal pattern on the substrate; The second conductive portion is electrically connected to a second electrode included in the threshold compensation transistor; the second electrode is electrically connected to a gate of the driving transistor; The first gate metal pattern is a gate metal pattern between the gate line and the gate of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

3. The display substrate according to claim 1, wherein: The first region includes a third sub-region; The thin film transistor array layer includes a gate line, a threshold compensation transistor and a driving transistor; The third sub-region is between the orthographic projection of the gate line on the substrate, the orthographic projection of the third conductive portion included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate, and the orthographic projection of the first gate metal pattern on the substrate; The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the third conductive portion is arranged on the first channel portion and the second channel portion without overlapping; The first gate metal pattern is a gate metal pattern between the gate line and the gate of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

4. The display substrate according to claim 1, wherein: The first region includes a fourth sub-region; The thin film transistor array layer includes a gate line, a first capacitor, a threshold compensation transistor and a first light emission control transistor; The fourth sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the first plate of the first capacitor on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate, and the orthographic projection of the fourth conductive portion included in the semiconductor material layer pattern of the first light emission control transistor on the substrate; The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the semiconductor material layer pattern of the first light emission control transistor includes a third channel portion; The fourth conductive portion is disposed between the second channel portion and the third channel portion.

5. The display substrate according to claim 1, wherein: The first region includes a fifth sub-region; The thin film transistor array layer includes a first capacitor, a threshold compensation transistor, a first light emission control transistor, a first power line and a light emission control signal line; The fifth sub-region does not overlap with the orthographic projection of the first electrode plate of the first capacitor on the substrate, the orthographic projection of the light emitting control signal line on the substrate, the orthographic projection of the first power line on the substrate, and the orthographic projection of the fourth conductive portion included in the semiconductor material layer pattern of the first light emitting control transistor on the substrate; The semiconductor material layer pattern of the threshold compensation transistor includes a first channel portion and a second channel portion, and the semiconductor material layer pattern of the first light emission control transistor includes a third channel portion; The fourth conductive portion is disposed between the second channel portion and the third channel portion.

6. The display substrate according to claim 1, wherein: It also includes an anode layer disposed on a side of the thin film transistor array layer away from the first protective layer; The thin film transistor array layer includes a first power line and a first light emission control transistor; The pinhole area does not overlap with the orthographic projection of the first power line on the base substrate and the orthographic projection of the third electrode included in the first light emission control transistor on the base substrate; The third electrode is electrically connected to the anode layer.

7. The display substrate according to claim 1, wherein: The first protection layer is made of silicon oxide or silicon nitride.

8. The display substrate according to claim 1, wherein: The thickness of the first protective layer is greater than or equal to 100 nanometers and less than or equal to 400 nanometers.

9. The display substrate according to claim 1, wherein: It also includes a fingerprint recognition layer; the fingerprint recognition layer is arranged on a side of the base substrate away from the light shielding layer, and the fingerprint recognition layer includes a fingerprint recognition sensor; The light shielding layer is arranged on the light incident side of the fingerprint recognition sensor, and the imaging pinhole allows light to be incident on the fingerprint recognition sensor through the pinhole.

10. The display substrate according to claim 1, wherein: The light-shielding layer is made of light-proof material.

11. The display substrate according to claim 1, wherein: It also includes a planar layer and an anode layer which are sequentially arranged on a side of the thin film transistor array layer away from the buffer layer; The orthographic projection of the imaging pinhole on the substrate does not overlap with the orthographic projection of the anode layer on the substrate.

12. The display substrate according to any one of claims 1 to 11, characterized in that: The buffer layer is made of silicon nitride, silicon oxide or polysilicon.

13. The display substrate according to any one of claims 1 to 11, characterized in that: The thickness of the buffer layer is greater than or equal to 200 nanometers and less than or equal to 600 nanometers.

14. The display substrate according to claim 1, wherein: The metal film layer includes a first metal layer, a second metal layer and a third metal layer; The gate line, the reset control signal line, the light emitting control signal line, the second plate of the first storage capacitor, and the gates of each transistor included in the pixel circuit are located in the first metal layer; A reset power line and a first plate of the first storage capacitor are located in the second metal layer; A first power line, a data line, and a first electrode and a second electrode included in the transistor are located in the third metal layer.

15. A method for manufacturing a display substrate, characterized in that: include: forming a light shielding layer on the base substrate; A first area is provided on the substrate, the light shielding layer includes a plurality of imaging pinholes, and at least a part of the orthographic projection of the imaging pinholes on the substrate is provided in the first area; forming a first protective layer on a side of the light shielding layer away from the base substrate; forming a thin film transistor array layer on the first protective layer, so that an orthographic projection of a metal film layer included in the thin film transistor array layer on the base substrate is disposed outside the first region; The orthographic projection of the first protective layer on the base substrate at least covers a portion of the first area; The first area includes a pinhole area, and at least a part of the orthographic projection of the imaging pinhole on the substrate is arranged in the pinhole area; the orthographic projection of the first protective layer on the substrate at least covers the pinhole area; The step of forming a first protective layer on a side of the light shielding layer away from the base substrate comprises: A first protective layer is formed on a side of the light shielding layer away from the base substrate by using a low temperature process; the film forming temperature of the first protective layer is lower than a threshold temperature; The threshold temperature is greater than or equal to 230 degrees Celsius and less than or equal to 380 degrees Celsius; The first protective layer is made of an inorganic material and is directly disposed on the light shielding layer; The first region includes a second sub-region; The thin film transistor array layer includes a gate line, a threshold compensation transistor and a driving transistor; The second sub-region does not overlap with the orthographic projection of the gate line on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate, the orthographic projection of the second conductive part included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate, and the orthographic projection of the first gate metal pattern on the substrate; The second conductive portion is electrically connected to a second electrode included in the threshold compensation transistor; the second electrode is electrically connected to a gate of the driving transistor; The first gate metal pattern is a gate metal pattern between the gate line and the gate of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

16. A display panel, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 14.

17. A display device, characterized in that: Comprising the display panel as claimed in claim 16.

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