Asynchronous data movement pipeline

Abstract

The present invention discloses an asynchronous data movement pipeline, specifically devices, systems, and techniques for parallelizing operations in one or more programs with the copying of data from global memory to shared memory within each of the one or more programs. In at least one embodiment, the programs perform operations on shared data, then asynchronously copy the shared data to shared memory, and continue to perform additional operations in parallel while the shared data is copied to the shared memory until an indicator provided by an application programming interface (API) for facilitating parallel computing, such as CUDA, notifies the program that the shared data has been copied to the shared memory.

Description

Technical Field

[0001] At least one embodiment relates to a processing resource for executing parallel operations in one or more programs that utilize an application programming interface for performing parallel computing, such as CUDA. For example, at least one embodiment relates to a processor or computing system for safely executing operations while waiting for data dependencies to be copied from another parallel program using various novel techniques described herein. Background Art

[0002] Memory dependencies have presented a performance bottleneck in parallel computing platforms, such as graphics processing units (GPUs). During execution, a multithreaded program running on a parallel computing platform has various threads performing computations on shared, global data structures in parallel. Changes made by one thread can affect the performance of another thread as it waits for those changes to propagate to the shared memory data structures. Synchronizing this interdependent data causes threads to stall execution and wait for data to become available, resulting in reduced parallel performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram illustrating thread synchronization in a classic parallel computing environment on a graphics processing unit (GPU), according to at least one embodiment;

[0004] Figure 2A is a block diagram illustrating hardware data flow for copying global memory data to shared memory according to at least one embodiment;

[0005] Figure 2B is a block diagram illustrating data flow between global memory, shared memory, and computation according to at least one embodiment;

[0006] Figure 3A is a block diagram illustrating a single stage pipeline for performing bulk data transfers to shared memory by a single thread, according to at least one embodiment;

[0007] Figure 3B is a block diagram illustrating a multi-stage pipeline for performing bulk data transfers to shared memory by a single thread, according to at least one embodiment;

[0008] Figure 4 is a block diagram illustrating a multi-stage pipeline for performing bulk data transfers from thread blocks to shared memory, according to at least one embodiment;

[0009] Figure 5 A process for performing pipelined bulk data transfers on parallel processing units by one or more threads is shown in accordance with at least one embodiment;

[0010] Figure 6 An exemplary data center is shown in accordance with at least one embodiment;

[0011] Figure 7 A processing system according to at least one embodiment is shown;

[0012] Figure 8 A computer system according to at least one embodiment is shown;

[0013] Figure 9 A system according to at least one embodiment is shown;

[0014] Figure 10 An exemplary integrated circuit according to at least one embodiment is shown;

[0015] Figure 11 A computing system according to at least one embodiment is shown;

[0016] Figure 12 An APU is shown according to at least one embodiment;

[0017] Figure 13 A CPU according to at least one embodiment is shown;

[0018] Figure 14 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0019] Figure 15A and Figure 15B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0020] Figure 16A illustrates a graphics core according to at least one embodiment;

[0021] Figure 16B GPGPU according to at least one embodiment is shown;

[0022] Figure 17A A parallel processor according to at least one embodiment is shown;

[0023] Figure 17B illustrates a processing cluster according to at least one embodiment;

[0024] Figure 17C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0025] Figure 18 A graphics processor according to at least one embodiment is shown;

[0026] Figure 19 A processor according to at least one embodiment is shown;

[0027] Figure 20 A processor according to at least one embodiment is shown;

[0028] Figure 21 illustrates a graphics processor core according to at least one embodiment;

[0029] Figure 22 illustrates a PPU according to at least one embodiment;

[0030] Figure 23 shows a GPC according to at least one embodiment;

[0031] Figure 24 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0032] Figure 25 illustrates a software stack for a programming platform according to at least one embodiment;

[0033] Figure 26 According to at least one embodiment, Figure 25 CUDA implementation of the software stack;

[0034] Figure 27 According to at least one embodiment, Figure 25 ROCm implementation of the software stack;

[0035] Figure 28 According to at least one embodiment, Figure 25 OpenCL implementation of the software stack;

[0036] Figure 29 illustrates software supported by a programming platform according to at least one embodiment;

[0037] Figure 30 According to at least one embodiment, Figures 25-28 Compiled code executed on the programming platform;

[0038] Figure 31 According to at least one embodiment, Figures 25-28 More detailed compiled code executed on the programming platform;

[0039] Figure 32 Transforming source code before compiling it according to at least one embodiment is shown;

[0040] Figure 33A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0041] Figure 33BA method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 33A CUDA source code system;

[0042] Figure 33C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 33A CUDA source code system;

[0043] Figure 34 According to at least one embodiment, Figure 33C An example kernel converted by the CUDA to HIP conversion tool;

[0044] Figure 35 More details are shown according to at least one embodiment. Figure 33C a non-CUDA-enabled GPU; and

[0045] Figure 36 shows how threads of an exemplary CUDA grid are mapped to Figure 35 different computing units. DETAILED DESCRIPTION

[0046] Figure 1 1 is a block diagram illustrating thread synchronization 114, 118 with shared memory 104 in a classic parallel computing environment on a graphics processing unit (GPU), according to at least one embodiment. In at least one embodiment, one or more processes 102 are logical groupings of computing units in a software program. In at least one embodiment, a process 102 can be executed on one or more hardware computing units, such as a parallel processing unit (PPU) or a graphics processing unit (GPU), each of which includes multiple hardware cores for executing instructions, as further described herein. In at least one embodiment, a process 102 uses one or more hardware computing units to execute one or more threads 106, 108, 110, 112 corresponding to the process 102.

[0047] In at least one embodiment, threads 106, 108, 110, 112 are separate computing units that contain instructions that, when executed by a hardware computing unit, perform operations on data, as further described herein. In at least one embodiment, threads 106, 108, 110, 112 contain instructions that, when executed, perform operations on data or process data. In at least one embodiment, one or more threads 106, 108, 110, 112 contain instructions that, when executed, modify data objects stored in shared memory 104. In at least one embodiment, one or more threads 106, 108, 110, 112 perform operations on data objects shared between the one or more threads 106, 108, 110, 112. In at least one embodiment, data objects shared between one or more threads 106, 108, 110, 112 are stored in shared memory 104.

[0048] In at least one embodiment, shared memory 104 is memory on a parallel processing unit (PPU) or other computing unit (such as a central processing unit (CPU) or a graphics processing unit (GPU)) that is used to facilitate data storage and sharing between multiple threads 106, 108, 110, 112, as described above. In at least one embodiment, shared memory 104 is physical memory. In at least one embodiment, shared memory 104 is an abstraction of physical memory, such as virtual memory. In at least one embodiment, the abstraction of physical memory for shared memory 104 is provided by hardware on the PPU or GPU. In at least one embodiment, the abstraction of physical memory for shared memory 104 is provided by software running on the PPU or GPU to facilitate parallel computing by other software programs, such as Compute Unified Device Architecture (CUDA) or other software described herein.

[0049] In at least one embodiment, shared memory 104 contains data used by one or more threads 106, 108, 110, 112 to perform computations. In at least one embodiment, the data stored in shared memory 104 is unique to each thread 106, 108, 110, 112. In at least one embodiment, the data stored in shared memory 104 is data modified by one or more threads 106, 108, 110, 112. In at least one embodiment, if one thread 106, 108, 110, 112 depends on data stored in shared memory 104, the data modified by that thread 106, 108, 110, 112 is used by another thread 106, 108, 110, 112. In at least one embodiment, the data stored in shared memory 104 is synchronized 114, 118 to ensure that each thread 106, 108, 110, 112 uses the latest data from shared memory 104.

[0050] In at least one embodiment, the synchronization 114, 118 is a set of software instructions that, when executed, updates data values ​​in one or more threads 106, 108, 110, 112 from the shared memory 104. In at least one embodiment, the synchronization 114, 118 copies data 116, 120 from the threads 106, 108, 110, 112 to the shared memory 104 to ensure that the shared memory 104 contains the latest data values. In at least one embodiment, the synchronization 114, 118 copies shared data values ​​116, 120 in the shared memory 104 to one or more threads 106, 108, 110, 112 to ensure that the threads 106, 108, 110, 112 are using the latest data values.

[0051] In at least one embodiment, threads 106, 108, 110, 112 are synchronized 114, 118 before performing computations on shared data values, as described above. Once the data values ​​are synchronized 114 from shared memory 104, in an embodiment, threads 106, 108, 110, 112 perform computations on the shared data values. In at least one embodiment, once threads 106, 108, 110, 112 have completed performing computations on the shared data values, threads 106, 108, 110, 112 synchronize 118 with shared memory 104 a second time. In at least one embodiment, once the shared data in each thread 106, 108, 110, 112 has been synchronized 118, computations can continue using the synchronized data 124 from shared memory 104 in each thread 106, 108, 110, 112. In at least one embodiment, data-dependent computations in threads 106 , 108 , 110 , 112 that require the use of synchronization data 124 must wait for synchronization operation 118 in order to continue.

[0052] Figure 2A is a block diagram illustrating hardware data flow for copying global memory 204, 216 data to shared memory 212, 220, in accordance with at least one embodiment. In at least one embodiment, an older hardware configuration 202 for copying global memory 204 data to shared memory 212 for use by software threads or other computing units requires copying data from global memory 204 to several other memory structures.

[0053] In at least one embodiment, global memory 204, 216 is memory associated with a software thread or other computational unit (such as a cooperative thread array (CTA) or cooperative group (CG) described below) that stores data values ​​associated with the software thread or computational unit. In at least one embodiment, global memory 204, 216 is hardware memory. In at least one embodiment, global memory 204, 216 is an abstraction of hardware memory, such as virtual memory. In at least one embodiment, the abstraction of hardware memory is implemented in hardware or software. In at least one embodiment, to copy data from global memory 204 to shared memory 212, older hardware configurations 202 would first copy the data from global memory 204 to L2 cache 206.

[0054] In at least one embodiment, the L2 cache 206 is a physical memory included on the processor that stores data before the data is moved or copied to a physical memory not included on the processor. In at least one embodiment, the L2 cache 206 is further described herein in conjunction with a parallel processing unit (PPU) or a graphics processing unit (GPU) architecture. In at least one embodiment, to copy data from global memory 204 to shared memory 212, older hardware configurations 202 copy data from the L2 cache 206 to the L1 cache 208. In at least one embodiment, the L1 cache 208 is a physical memory included on the processor that stores temporary data before the data is moved or copied to a physical memory not included on the processor, such as the shared memory 212.

[0055] In at least one embodiment, to copy data from global memory 204 to shared memory 212, the older hardware configuration 202 copies the data from L1 cache 208 to one or more registers in register file 210. In at least one embodiment, register file 210 is a processor register array for a parallel processing unit, central processing unit, or graphics processing unit, as well as any other hardware computing unit such as an application specific integrated circuit. In at least one embodiment, register file 210 is an on-chip register group that stores data values ​​used directly in computations. In at least one embodiment, register file 210 is a random access physical memory. In at least one embodiment, to copy data from global memory 204 to shared memory 212, the older hardware configuration 202 copies the data from register file 210 to shared memory 212.

[0056] In at least one embodiment, shared memory 212, 220 is memory on a parallel processing unit (PPU) or other computing unit (such as a central processing unit (CPU) or graphics processing unit (GPU)) that facilitates data storage and sharing between multiple processes, threads, or other abstractions of software instructions (such as cooperative thread arrays (CTAs) or cooperative groups (CGs) described further herein). In at least one embodiment, shared memory 212, 220 is random access physical memory. In at least one embodiment, shared memory 212, 220 is any other type of physical memory. In at least one embodiment, shared memory 212, 220 is an abstraction of physical memory (such as virtual memory) as described herein. In at least one embodiment, the abstraction of physical memory for shared memory 212, 220 is provided by hardware on the PPU, GPU, or any other computing hardware described herein. In at least one embodiment, the abstraction of physical memory for shared memory 212, 220 is provided by software running on the PPU, GPU, or any other computing hardware described herein to facilitate parallel computing performed by other software programs (such as Compute Unified Device Architecture (CUDA) or other software described herein).

[0057] In at least one embodiment, as described above, newer hardware configurations 214 for copying global memory 216 data to shared memory 220 for use by software threads or other computing units do not require the use of additional memory structures. In at least one embodiment, data values ​​shared between processes, threads, or other groups of software instructions (such as those described herein) are copied directly from global memory 216 associated with a single process, thread, or other group of software instructions to L2 cache 218, as described above. In an embodiment, the shared data values ​​are then copied directly from L2 cache 218 to shared memory 220, thereby reducing the amount of computation associated with copying data to L1 cache 208 and register file 210.

[0058] Figure 2B is a block diagram illustrating data flow between global memory (GMEM) 224, 230, 238, 246, shared memory (SMEM) 226, 232, 240, 248, and computation (COMP) 234, 242, 250, according to at least one embodiment. In at least one embodiment, GMEM 224, 230, 238, 246 is a global memory, as described above in conjunction with Figure 1 and Figure 2A In at least one embodiment, iterations 222, 228, 236, 244 are computation cycles of a central processing unit (CPU), a graphics processing unit (GPU), a parallel processing unit (PPU), or any other type of hardware computing unit. In at least one embodiment, iterations 222, 228, 236, 244 are epochs of time during which operations are performed on a CPU, GPU, PPU, or other type of hardware computing unit.

[0059] In at least one embodiment, during iteration 0222, data values ​​are copied from GMEM 224 to SMEM 226. In at least one embodiment, data values ​​are not available for computation 234 during iteration 0222. In at least one embodiment, SMEM 226, 232, 240, 248 are shared memories, as described above in conjunction with Figure 1 and Figure 2A In at least one embodiment, the data copied from GMEM 224 to SMEM 226 in iteration 0 222 is available for use by COMP 224 in iteration 1 228. In at least one embodiment, COMP 224 is a computation performed by a process, thread, or other computation group as described herein.

[0060] In at least one embodiment, one or more threads execute instructions to load data values ​​from GMEM 224, 230, 238, 246 and store the data values ​​to SMEM 226, 232, 248. In at least one embodiment, the instructions to load data values ​​from GMEM 224, 230, 238, 246 and store the data values ​​to SMEM 226, 232, 248 are asynchronous copies or asynchronous copies (async-copy). In at least one embodiment, the asynchronous copies are micro-operations and are executed asynchronously. In at least one embodiment, the asynchronous copies or any other instructions for performing operations (such as asynchronous copies) are provided by an application programming interface (API) to facilitate parallel computing, such as CUDA or any other API further described herein.

[0061] In at least one embodiment, one or more threads submit asynchronous copy operations to the pipeline, such as the following in conjunction with Figure 3A 、 Figure 3B and Figure 4 As further described herein. In at least one embodiment, a pipeline is used to facilitate the collection of memory data for asynchronous copy operations from GMEM 224, 230, 238, 246 to SMEM 226, 232, 248. In at least one embodiment, the pipeline is a queue, such as a first-in-first-out (FIFO) queue. In at least one embodiment, once one or more threads submit an asynchronous copy operation to the pipeline, the one or more threads wait for the asynchronous copy operation to complete. In at least one embodiment, if a single thread loads data from GMEM 224, 230, 238, 246 and stores the data to SMEM 226, 232, 248, the single thread submits the asynchronous copy and waits. If multiple threads or thread blocks (e.g., a cooperative thread array (CTA), a cooperative group (CG), or any other thread grouping further described herein) load data from GMEM 224, 230, 238 and store the data to SMEM 226, 232, 248, in at least one embodiment, the multiple threads submit the data using asynchronous copy and wait for completion by the pipeline. In at least one embodiment, completion by the pipeline is once data or batches of data are available from the pipeline, as described below in conjunction with Figure 3A 、 Figure 3B and Figure 4 described.

[0062] In at least one embodiment, the initiating thread of the asynchronous replica is a producer thread. In at least one embodiment, the producer thread does not use the results of the asynchronous replica. In at least one embodiment, the thread that uses the results of the asynchronous replica initiated by the producer thread is a consumer thread. In at least one embodiment, the data submitted by the producer thread for the asynchronous replica is source data loaded from GMEM 224, 230, 238, or 246. In at least one embodiment, the data received by the consumer thread from the asynchronous replica is destination data stored in SMEM 226, 232, or 248. In at least one embodiment, the source and destination data copied by each asynchronous replica operation is 4 bytes, 8 bytes, or 16 bytes.

[0063] In at least one embodiment, the source and destination data must be of a type that is easily copied, such as native data types supported by an API to facilitate parallel computing, such as CUDA or any other API further described herein. In at least one embodiment, the source data is in GMEM 224, 230, 238, 246. In at least one embodiment, the destination data is in SMEM 226, 232, 248. In at least one embodiment, the source and destination data are compatible aligned to 16, 8, or 4 bytes, where wider alignment allows memory to be copied with greater granularity via asynchronous copies.

[0064] In at least one embodiment, during iteration 1 228, new data values ​​are copied from GMEM 230 to SMEM 232. In at least one embodiment, the SMEM 232 values ​​copied from GMEM 230 in iteration 1 228 can be used for calculations in iteration 2 236. In at least one embodiment, COMP 234 in iteration 1 uses data values ​​stored in SMEM 226 during iteration 0 222.

[0065] In at least one embodiment, during iteration 2236, new data values ​​from COMP 234 executed during iteration 1228 are copied from GMEM 238 to SMEM 240. In at least one embodiment, the SMEM 240 values ​​copied from GMEM 238 in iteration 2236 are available for computation in a subsequent iteration 244. In at least one embodiment, the Kth iteration 244 includes computations using the SMEM 226, 232, 240 data values ​​copied from GMEM 224, 230, 238 during the (K-1)th iterations 222, 228, 236.

[0066] Figure 3Ais a block diagram illustrating a single-stage pipeline for performing pipelined bulk data transfers to shared memory by a single thread 302, according to at least one embodiment. In at least one embodiment, the thread 302 is a single unit that executes in parallel on a parallel processing unit (PPU), a graphics processing unit (GPU), or any other hardware unit for performing parallel computations, as further described herein. In at least one embodiment, the thread 302 includes instructions 318 that, when executed, perform operations on the GPU or other PPU or any other hardware unit for performing parallel computations as described herein. In at least one embodiment, the instructions 318 in the thread 302, when executed, perform one or more asynchronous copy operations on the data 308, 310, 312 over time. In at least one embodiment, the data 308, 310, 312 copied by each asynchronous copy operation is 4 bytes, 8 bytes, or 16 bytes, as described above in combination. Figure 2B In at least one embodiment, the one or more asynchronous copy operations on data 308, 310, 312 are one or more software instructions that, when executed, perform an asynchronous copy of data from the global memory or other memory of thread 302 to the shared memory, as described above in conjunction with Figure 2B described.

[0067] In at least one embodiment, an application programming interface (API) that facilitates parallel computing, such as CUDA or any other API further described herein, provides one or more mechanisms or instructions to batch asynchronous copies within a thread 302 or across thread groups, for example, as described below in conjunction with Figure 4 In at least one embodiment, the instructions provided by the API (e.g., CUDA) are LDGDEPBAR and ARRIVES.LDGSTSBAR, which are global load dependency barrier instructions and barrier reach instructions for performing shared memory writes and facilitating visibility of shared memory writes, respectively. In at least one embodiment, the sequence of batched asynchronous copies of data 308, 310, 312 forms a pipeline or asynchronous pipeline 306.

[0068] In at least one embodiment, the asynchronous pipeline 306 is a batch of data or data groups 308, 310, 312 from the asynchronous replica operation. In at least one embodiment, the asynchronous pipeline 306 is a queue or a first-in-first-out (FIFO) queue. In at least one embodiment, as described above in conjunction with Figure 2BAs depicted, the asynchronous pipeline 306 receives data 308, 310, 312 from the asynchronous replica operation. In at least one embodiment, the asynchronous replica operation loads the data 308, 310, 312 from global memory or other memory (such as the memory further described herein) and stores the data to shared memory at any time after committing the data.

[0069] In at least one embodiment, a submit batch 314 operation is received by the asynchronous pipeline 306. In at least one embodiment, the submit batch 314 operation is one or more instructions that, when executed, partition a batch of asynchronous replica operations. In at least one embodiment, the submit batch 314 operation introduces a batch tag into the asynchronous pipeline 306. In at least one embodiment, the batch tag is a call to an API as described above, or any other technique that indicates the conclusion of a batch of asynchronous replica operations. In at least one embodiment, the submit batch 314 operation optionally includes a local store operation for the threads 302 in the batch of asynchronous replica operations, such that the batch waits 304, 316 for both the asynchronous replica operation and the local weak store operation submitted by the batch 304, 316 to complete.

[0070] In at least one embodiment, the asynchronous pipeline 306 waits 304, 316 for the batch of asynchronous copy operations to complete. In at least one embodiment, the batch of asynchronous copy operations is complete when all asynchronous copy operations submitted to the asynchronous pipeline 306 prior to submitting the batch 314 of operations have completed their individual loads from global memory or other memory (such as the memory further described herein) and stores to shared memory. In at least one embodiment, the wait or wait until completion 304, 316 operation stores the sequence of operations or instructions after the wait or wait until completion 304, 316 operation if those operations or instructions must occur after the wait or wait until completion 304, 316 operation.

[0071] In at least one embodiment, asynchronous pipeline 306 completes batches of asynchronous copies of data 308, 310, 312 in first-in, first-out (FIFO) order. In at least one embodiment, the individual asynchronous copies of data 308, 310, 312 are only partially ordered into fully ordered batches.

[0072] Figure 3B is a block diagram illustrating a multi-stage pipeline for performing pipelined bulk data transfers to shared memory via a single thread, according to at least one embodiment. In at least one embodiment, thread 320 is as described above in conjunction with Figure 3A In at least one embodiment, thread 320 includes instructions 322 that, when executed, perform batch processing of asynchronous copy operations on data 326, 328, 330, 334, 336, 338, as described above in conjunction with Figure 3A In at least one embodiment, once thread 320 submits batch asynchronous copy operations on data 326, 328, 330, 334, 336, 338 to asynchronous pipeline 344, thread 320 submits 332, 340 as described above in conjunction with Figure 3A Batch processing as described.

[0073] In at least one embodiment, as described above in combination Figure 3A As described above, instructions 322 in thread 320 that depend on data 326, 328, 330, 334, 336, 338 wait until the data is completed 324, 342. In at least one embodiment, the asynchronous pipeline 344 has a logical helper thread that loads data 326, 328, 330, 336, 338 from global memory or other memory for each asynchronous copy submitted by thread 320, and stores the data 326, 328, 330, 336, 338 to shared memory, as described above in conjunction with Figure 2B In at least one embodiment, the logical helper threads exist only to model the asynchronous behavior of the asynchronous pipeline 344 and are not physically identifiable threads, such as those described herein.

[0074] In at least one embodiment, the asynchronous pipeline 344 maintains an internal count of batches that have been submitted and not yet completed. In at least one embodiment, a logic helper thread maintains this internal count of batches in the asynchronous pipeline 344 as an incomplete batch count. In at least one embodiment, when the asynchronous pipeline 344 receives a batch of asynchronous copy operations from thread 320, the logic helper thread for the asynchronous pipeline 344 increments the incomplete batch count. In at least one embodiment, the incomplete batch count is a count indicating how many batches of asynchronous copy operations have not yet completed, where completion occurs when all asynchronous copy operations are submitted to the asynchronous pipeline 344 before the batch 332 is submitted, and the 340 operations have completed their individual loads from global memory or other memory and stored to shared memory. As each batch of asynchronous copy operations submitted by thread 320 completes, the incomplete batch count is decremented.

[0075] In at least one embodiment, a thread for an API to facilitate parallel computation (such as a CUDA thread or any other API thread further described herein) waits for batches of asynchronous replica operations to complete by waiting for the incomplete batch count in the asynchronous pipeline 344 to be less than or equal to a value. For example, when the incomplete batch count in the asynchronous pipeline 344 is zero, in at least one embodiment, all batches of asynchronous replicas for thread 320 are complete. In at least one embodiment, once a batch 332, 340 has been submitted for completion, it is available to thread 320. In an embodiment, in a multi-stage pipeline (such as Figure 3B ), a single stage includes operations on batches of asynchronous copies of data 326, 328, 330, 334, 336, 338 submitted to the asynchronous pipeline and the submission of batches 332, 340. In at least one embodiment, the first stage of asynchronous copy operations on the data 326, 328, 330 completes and is available immediately after the second stage of asynchronous copy operations on the data 334, 336, 338 has submitted its batch 340. In at least one embodiment, the second stage of asynchronous copy operations on the data 334, 336, 338 will complete after being submitted 340 and will be available after the subsequent stage or batch of asynchronous copy operations on the data.

[0076] Figure 4 is a block diagram illustrating a multi-stage pipeline for performing bulk data transfers by thread blocks 402 to shared memory, according to at least one embodiment. In at least one embodiment, thread blocks 402 are logical groups 404 of individual threads. In at least one embodiment, threads 404 are execution units that include instructions that, when executed, perform operations on shared data, including parallel operations, as described above in conjunction with Figure 1 In at least one embodiment, the line block 402 is a cooperative line array (CTA), a cooperative group (CG), a group of lines on a warp, or any other logical grouping of lines as further described herein.

[0077] In at least one embodiment, the previous wait for completion 406 is as described above in conjunction with Figure 3A and 3B The described wait is performed, and if one or more asynchronous copy operations 410, 416 in the previous batch of asynchronous copy operations 410, 416 are submitted to the asynchronous pipeline 408 and have completed, then the updated shared data value is available to one or more threads 404 in the thread block 402. In at least one embodiment, one or more threads 404 in the thread group 402 submit batches of asynchronous copy operations 410, 416 of data values ​​412, 418 to the asynchronous pipeline 408. In at least one embodiment, the batches of asynchronous copy operations 410, 416 are performed as described above in conjunction with Figure 2B In at least one embodiment, data 412, 418 is a basic data type for an application programming interface (API) to facilitate parallel computing, such as CUDA and other APIs further described herein, which can use asynchronous copy operations (such as those described above in conjunction with Figure 2B described data) is copied.

[0078] In at least one embodiment, an API that facilitates parallel computing, such as CUDA or other APIs further described herein, provides instructions that are a mechanism for batching asynchronous copies across threads 404 in a thread block 402. For example, in an embodiment, CUDA provides the LDGDEPBAR and ARRIVES.LDGSTSBAR instructions. In at least one embodiment, LDGDEPBAR and ARRIVES.LDGSTSBAR are global load dependency barrier instructions and barrier reach instructions for performing shared memory writes and facilitating visibility of shared memory writes, respectively.

[0079] In at least one embodiment, once batches of asynchronous copy operations 410, 416 have been submitted to the asynchronous pipeline 408 by one or more threads 404 in thread block 402, batches of operations 414, 420 are submitted, as described above in conjunction with Figure 3A and Figure 3B As described above, the one or more threads 404 in the thread block 402 are executed. In at least one embodiment, submitting the batch 414, 420 operation indicates the end of the operation of the single batch asynchronous copy 410, 416. In at least one embodiment, one or more threads 404 in the thread block 402 will wait until the completion 422 of the data 412, 418 submitted by the batch asynchronous copy operation 410, 416 before using the data 412, 418, as described above in conjunction with Figure 3A and Figure 3B described.

[0080] In at least one embodiment, each thread 404 in thread block 402 shares a logical helper thread and asynchronous pipeline 408, as described above in conjunction with Figure 3B In at least one embodiment, a logical helper thread shared among threads 404 of thread group 402 drives batched asynchronous copy operations 410, 416 to completion. In at least one embodiment, completion occurs when all individual asynchronous copy operations in batches 410, 416 submitted to asynchronous pipeline 408 prior to submitting batches 414, 420 of operations have completed their individual loads from global memory or other memory and stores to shared memory.

[0081] In at least one embodiment, sharing the asynchronous copy operations in a batch 410, 416 across multiple threads 404 in a thread block 402 is warp sharing. In at least one embodiment, when a warp is shared, the individual submissions of the asynchronous copy operations by each thread 404 in the thread block 402 are aggregated into a batch 410, 416 across the warp. In at least one embodiment, a warp is a computational processing block on a parallel processing unit (PPU), a graphics processing unit (GPU), or any other execution unit capable of performing parallel computations, as further described herein. In at least one embodiment, after aggregating the asynchronous copy operations into a batch 410, 416 across the warp, the submission batch 414, 420 operations are only executed once for any number of threads 414 in the thread block 402 executing on the warp. In at least one embodiment, the submission batch 414, 420 operations are executed by a single thread 404 selected from the thread block 402 by a runtime, such as a CUDA runtime, to facilitate parallel computations.

[0082] In at least one embodiment, when the operations of the commit batches 414, 420 are executed by the threads 404 selected from the thread block 402, as described above in conjunction with Figure 3B As described, the count of incomplete batches in the asynchronous pipeline 408 is incremented by the logic helper thread for each subset of threads that converge. In at least one embodiment, thread 404 converges with the other threads in thread block 402 when each thread executes instructions at the same point in time or at an ordered point in an ordered instruction set, as further described herein. In at least one embodiment, the count of incomplete batches in the asynchronous pipeline 408 is incremented by the logic helper thread by a non-deterministic value between 1 and 32.

[0083] In at least one embodiment, each thread 404 in a thread block 402 or each thread 404 on a warp assumes that the count of incomplete batches is incremented by 1. In at least one embodiment, each thread 404 in a thread block 402 or each thread 404 on a warp waits until the count of incomplete batches is less than a threshold (such as the number of threads) to ensure that the thread 404 waits 406, 422 for its submitted asynchronous copy. In at least one embodiment, if the logical helper thread and the asynchronous pipeline 408 are shared, the threads 404 of the warp must converge on the submitted batch 414, 420 operations.

[0084] In at least one embodiment, the logic helper thread and the asynchronous pipeline 408 need not be shared between one or more threads 404 on a warp. In at least one embodiment, if the logic helper thread and the asynchronous pipeline 408 are not shared, then committing batches 414, 420 operations does not require the threads 404 of a warp to be converged.

[0085] Figure 5A process for performing a single-stage pipeline batch data transfer by one or more threads on a parallel processing unit (PPU), such as a graphics processing unit (GPU), according to at least one embodiment is shown. In at least one embodiment, the process begins by performing a batch asynchronous copy operation using a pipeline (502), as described above in conjunction with Figure 3A 、 Figure 3B and Figure 4 In at least one embodiment, if thread blocks or thread groups, such as cooperative thread arrays (CTAs), cooperative groups (CGs), threads executing on a warp, or any other logical grouping of threads as further described herein, submit asynchronous copy operations in parallel, these asynchronous copy operations are aggregated into batched asynchronous copy operations, as described above in conjunction with Figure 4 As stated.

[0086] If the batch has been submitted 506, then in an embodiment, the submit batch 508 operation is performed by the thread, as described above in conjunction with Figure 3A and Figure 3B If a thread block or thread group (such as a CTA, CG, or any other logical grouping of threads further described herein) executing on a warp has submitted a batch, threads from that group are selected or picked by a runtime (such as the CUDA runtime described herein or any other runtime, depending on the embodiment) for facilitating parallel computation. In at least one embodiment, the picked or selected threads perform the submit batch operation 508, as described above in conjunction with Figure 4 In one embodiment, if the batch has not yet been committed 506 , or more outstanding asynchronous replica operations are to be committed, then those outstanding asynchronous replica operations are committed 504 .

[0087] In at least one embodiment, once a commit batch 508 has been executed by a single thread, the thread waits for its batch to complete 510, as described above in conjunction with Figure 3A and Figure 3B In at least one embodiment, if a thread block has submitted an aggregate batch 504 of asynchronous replica operations, then those threads wait for the aggregate batch to complete 510, as described above in conjunction with Figure 4 In at least one embodiment, the thread or thread group performs other operations independent of the data submitted in batch asynchronous copy 504, and the other operations comprise another stage in the pipeline.

[0088] In at least one embodiment, if execution of the one or more threads performing pipeline batch data transfers is complete 512, the process ends 514. In at least one embodiment, if execution of the one or more threads performing pipeline batch data transfers is not complete 512, such as when the one or more threads are about to execute additional pipeline stages, execution continues by submitting a new asynchronous copy of the batch 504. In at least one embodiment, the one or more threads are completed 512 when the one or more threads or other computational units have completed all of their operations or a parent process or thread on a central processing unit (CPU) indicates completion of the one or more threads running on a parallel processing unit (PPU) or graphics processing unit (GPU).

[0089] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0090] Data Center

[0091] Figure 6 An example data center 600 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 600 includes, but is not limited to, a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640.

[0092] In at least one embodiment, Figure 6 As shown, the data center infrastructure layer 610 may include a resource coordinator 612, grouped computing resources 614, and node computing resources ("node CRs") 616(1)-616(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 616(1)-616(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 616(1)-616(N) may be servers having one or more of the above-mentioned computing resources.

[0093] In at least one embodiment, the grouped computing resources 614 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 614 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0094] In at least one embodiment, resource coordinator 612 may configure or otherwise control one or more nodes CR 616(1)-616(N) and / or grouped computing resources 614. In at least one embodiment, resource coordinator 612 may comprise a software design infrastructure ("SDI") management entity for data center 600. In at least one embodiment, resource coordinator 612 may comprise hardware, software, or some combination thereof.

[0095] In at least one embodiment, Figure 6As shown, framework layer 620 includes, but is not limited to, a job scheduler 632, a configuration manager 634, a resource manager 636, and a distributed file system 638. In at least one embodiment, framework layer 620 may include a framework that supports software 652 of software layer 630 and / or one or more applications 642 of application layer 640. In at least one embodiment, software 652 or applications 642 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 620 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize distributed file system 638 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 632 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 600. In at least one embodiment, configuration manager 634 may be capable of configuring different layers, such as software layer 630 and framework layer 620, including Spark and a distributed file system 638 for supporting large-scale data processing. In at least one embodiment, the resource manager 636 can manage clustered or grouped computing resources that are mapped to or allocated to support the distributed file system 638 and the job scheduler 632. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 614 on the data center infrastructure layer 610. In at least one embodiment, the resource manager 636 can coordinate with the resource coordinator 612 to manage these mapped or allocated computing resources.

[0096] In at least one embodiment, the software 652 included in the software layer 630 may include software used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 638 of the framework layer 620. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0097] In at least one embodiment, the one or more applications 642 included in the application layer 640 may include one or more types of applications used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 638 of the framework layer 620. The one or more types of applications may include, but are not limited to, CUDA applications.

[0098] In at least one embodiment, any of configuration manager 634, resource manager 636, and resource coordinator 612 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 600 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0099] Computer-based systems

[0100] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0101] Figure 7 A processing system 700 is shown in accordance with at least one embodiment. In at least one embodiment, system 700 includes one or more processors 702 and one or more graphics processors 708, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 702 or processor cores 707. In at least one embodiment, processing system 700 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0102] In at least one embodiment, the processing system 700 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the processing system 700 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 700 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 700 is a television or set-top box device having one or more processors 702 and a graphical interface generated by one or more graphics processors 708.

[0103] In at least one embodiment, one or more processors 702 each include one or more processor cores 707 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 707 is configured to process a specific instruction set 709. In at least one embodiment, the instruction set 709 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 707 can each process a different instruction set 709, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 707 can also include other processing devices, such as a digital signal processor (DSP).

[0104] In at least one embodiment, the processor 702 includes a cache memory (cache) 704. In at least one embodiment, the processor 702 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among the various components of the processor 702. In at least one embodiment, the processor 702 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can use known cache coherence techniques to share this logic among the processor cores 707. In at least one embodiment, the processor 702 also includes a register file 706. The processor 702 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 706 may include general purpose registers or other registers.

[0105] In at least one embodiment, one or more processors 702 are coupled to one or more interface buses 710 to transmit communication signals, such as address, data, or control signals, between the processors 702 and other components in the system 700. In at least one embodiment, the interface bus 710 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 710 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 702 includes an integrated memory controller 716 and a platform controller hub 730. In at least one embodiment, the memory controller 716 facilitates communication between storage devices and other components of the processing system 700, while the platform controller hub (PCH) 730 provides connections to input / output (I / O) devices via a local I / O bus.

[0106] In at least one embodiment, the storage device 720 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the storage device 720 can be used as system memory for the processing system 700 to store data 722 and instructions 721 for use when one or more processors 702 execute applications or processes. In at least one embodiment, the memory controller 716 is also coupled to an optional external graphics processor 712, which can communicate with one or more graphics processors 708 in the processor 702 to perform graphics and media operations. In at least one embodiment, a display device 711 can be connected to the processor 702. In at least one embodiment, the display device 711 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (e.g., a DisplayPort, etc.). In at least one embodiment, the display device 711 can include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0107] In at least one embodiment, the platform controller hub 730 enables peripheral devices to connect to the storage device 720 and the processor 702 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 746, a network controller 734, a firmware interface 728, a wireless transceiver 726, a touch sensor 725, and a data storage device 724 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 724 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 725 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 726 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 728 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 734 can enable network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 710. In at least one embodiment, the audio controller 746 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 700 includes an optional legacy I / O controller 740 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 700. In at least one embodiment, the platform controller hub 730 may also be connected to one or more universal serial bus (USB) controllers 742, which connect input devices such as a keyboard and mouse 743 combination, a camera 744, or other USB input devices.

[0108] In at least one embodiment, instances of the memory controller 716 and the platform controller hub 730 may be integrated into a discrete external graphics processor, such as the external graphics processor 712. In at least one embodiment, the platform controller hub 730 and / or the memory controller 716 may be external to one or more of the processors 702. For example, in at least one embodiment, the processing system 700 may include the external memory controller 716 and the platform controller hub 730, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 702.

[0109] Figure 8A computer system 800 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 800 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 800 is formed by a processor 802, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 800 can include, but is not limited to, components such as the processor 802, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 800 can include a processor such as the Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0110] In at least one embodiment, the computer system 800 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0111] In at least one embodiment, computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 800 is a single-processor desktop or server system. In at least one embodiment, computer system 800 may be a multi-processor system. In at least one embodiment, processor 802 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 802 may be coupled to a processor bus 810 that may transmit data signals between processor 802 and other components in computer system 800.

[0112] In at least one embodiment, the processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, the processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to the processor 802. In at least one embodiment, the processor 802 may include a combination of internal and external caches. In at least one embodiment, the register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0113] In at least one embodiment, an execution unit 808, including but not limited to logic for performing integer and floating point operations, is also located in the processor 802. The processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809 in the instruction set of the general-purpose processor 802, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 802. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0114] In at least one embodiment, execution unit 808 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0115] In at least one embodiment, the system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can initiate data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814.

[0116] In at least one embodiment, the computer system 800 can use the system I / O 822 as a proprietary hub interface bus to couple the MCH 816 to the I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 can provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 820, chipset, and processor 802. Examples can include, but are not limited to, an audio controller 829, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data store 824, a traditional I / O controller 823 including user input 825 and a keyboard interface, a serial expansion port 827 (e.g., USB), and a network controller 834. The data store 824 can include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0117] In at least one embodiment, Figure 8 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 8 An exemplary SoC may be shown. In at least one embodiment, Figure 8 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of system 800 are interconnected using a Compute Express Link (CXL) interconnect.

[0118] Figure 9 A system 900 is shown in accordance with at least one embodiment. In at least one embodiment, the system 900 is an electronic device that utilizes a processor 910. In at least one embodiment, the system 900 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0119] In at least one embodiment, system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface, such as an I / O bus. 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, USB (Revisions 1, 2, 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 9 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 9 An exemplary SoC may be shown. In at least one embodiment, Figure 9 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0120] In at least one embodiment, Figure 9The system may include a display 924, a touch screen 925, a touchpad 930, a near field communication unit ("NFC") 945, a sensor hub 940, a thermal sensor 946, a fast chipset ("EC") 935, a trusted platform module ("TPM") 938, a BIOS / firmware / flash memory ("BIOS, FW Flash") 922, a DSP 960, a solid-state disk ("SSD") or a hard disk drive ("HDD") 920, a wireless local area network unit ("WLAN") 950, a Bluetooth unit 952, a wireless wide area network unit ("WWAN") 956, a global positioning system (GPS) 955, a camera ("USB 3.0 camera") 954 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented in, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0121] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components discussed above. In at least one embodiment, an accelerometer 941, an ambient light sensor (“ALS”) 942, a compass 943, and a gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, a thermal sensor 939, a fan 937, a keyboard 946, and a touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, a speaker 963, an earpiece 964, and a microphone (“mic”) 965 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 964, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 964 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF).

[0122] Figure 10An exemplary integrated circuit 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1000 is a SoC, which may be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1000 includes one or more application processors 1005 (e.g., CPUs), at least one graphics processor 1010, and may additionally include an image processor 1015 and / or a video processor 1020, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1000 includes peripheral or bus logic including a USB controller 1025, a UART controller 1030, an SPI / SDIO controller 1035, and an I / O controller. 2 S / I 2 C controller 1040. In at least one embodiment, integrated circuit 1000 may include a display device 1045 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1050 and a Mobile Industry Processor Interface (MIPI) display interface 1055. In at least one embodiment, storage may be provided by a flash memory subsystem 1060, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1065 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1070.

[0123] Figure 11 A computing system 1100 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 1100 includes a processing subsystem 1101 having one or more processors 1102 and system memory 1104 communicating via an interconnect path that may include a memory hub 1105. In at least one embodiment, memory hub 1105 may be a separate component within a chipset assembly or integrated within one or more processors 1102. In at least one embodiment, memory hub 1105 is coupled to an I / O subsystem 1111 via a communication link 1106. In at least one embodiment, I / O subsystem 1111 includes an I / O hub 1107, which enables computing system 1100 to receive input from one or more input devices 1108. In at least one embodiment, I / O hub 1107 may enable a display controller, included in one or more processors 1102, to provide output to one or more display devices 1110A. In at least one embodiment, the one or more display devices 1110A coupled to the I / O hub 1107 may include local, internal, or embedded display devices.

[0124] In at least one embodiment, the processing subsystem 1101 includes one or more parallel processors 1112 coupled to the memory hub 1105 via a bus or other communication link 1113. In at least one embodiment, the communication link 1113 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1112 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1112 form a graphics processing subsystem that can output pixels to one of one or more display devices 1110A coupled via the I / O hub 1107. In at least one embodiment, the one or more parallel processors 1112 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1110B.

[0125] In at least one embodiment, a system storage unit 1114 can be connected to the I / O hub 1107 to provide a storage mechanism for the computing system 1100. In at least one embodiment, an I / O switch 1116 can be used to provide an interface mechanism to enable connections between the I / O hub 1107 and other components, such as a network adapter 1118 and / or a wireless network adapter 1119 that can be integrated into the platform, as well as various other devices that can be added via one or more add-in devices 1120. In at least one embodiment, the network adapter 1118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1119 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0126] In at least one embodiment, computing system 1100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1107. Figure 11 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0127] In at least one embodiment, one or more parallel processors 1112 include circuits optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1112 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computing system 1100 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1112, memory hub 1105, processor 1102, and I / O hub 1107 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1100 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1111 and display device 1110B are omitted from computing system 1100.

[0128] Processing system

[0129] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0130] Figure 12 An accelerated processing unit ("APU") 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1200 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 1200 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1200 includes, but is not limited to, a core complex 1210, a graphics complex 1240, a fabric 1260, an I / O interface 1270, a memory controller 1280, a display controller 1292, and a multimedia engine 1294. In at least one embodiment, the APU 1200 can include, but is not limited to, any combination of any number of core complexes 1210, any number of graphics complexes 1240, any number of display controllers 1292, and any number of multimedia engines 1294. For purposes of illustration, multiple instances of similar objects are referred to herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0131] In at least one embodiment, core complex 1210 is a CPU, graphics complex 1240 is a GPU, and APU 1200 is a processing unit that is not limited to integrating 1210 and 1240 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1210, while other tasks may be assigned to graphics complex 1240. In at least one embodiment, core complex 1210 is configured to execute primary control software associated with APU 1200, such as an operating system. In at least one embodiment, core complex 1210 is the main processor of APU 1200, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1210 issues commands that control the operations of graphics complex 1240. In at least one embodiment, core complex 1210 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1240 may be configured to execute device executable code derived from CUDA source code.

[0132] In at least one embodiment, core complex 1210 includes, but is not limited to, cores 1220(1)-1220(4) and L3 cache 1230. In at least one embodiment, core complex 1210 may include, but is not limited to, any number of cores 1220 and any combination of any number and type of caches. In at least one embodiment, cores 1220 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1220 is a CPU core.

[0133] In at least one embodiment, each core 1220 includes, but is not limited to, a fetch / decode unit 1222, an integer execution engine 1224, a floating-point execution engine 1226, and an L2 cache 1228. In at least one embodiment, the fetch / decode unit 1222 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1224 and the floating-point execution engine 1226. In at least one embodiment, the fetch / decode unit 1222 can simultaneously dispatch one micro-op to the integer execution engine 1224 and another micro-op to the floating-point execution engine 1226. In at least one embodiment, the integer execution engine 1224 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1226 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1222 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1224 and the floating-point execution engine 1226.

[0134] In at least one embodiment, each core 1220(i) can access an L2 cache 1228(i) included in the core 1220(i), where i is an integer representing a specific instance of the core 1220. In at least one embodiment, each core 1220 included in a core complex 1210(j) is connected to the other cores 1220 included in the core complex 1210(j) via an L3 cache 1230(j) included in the core complex 1210(j), where j is an integer representing a specific instance of the core complex 1210. In at least one embodiment, a core 1220 included in a core complex 1210(j) can access all L3 caches 1230(j) included in the core complex 1210(j), where j is an integer representing a specific instance of the core complex 1210. In at least one embodiment, the L3 cache 1230 can include, but is not limited to, any number of slices.

[0135] In at least one embodiment, graphics complex 1240 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1240 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1240 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 1240 is configured to perform both graphics-related operations and graphics-independent operations.

[0136] In at least one embodiment, graphics complex 1240 includes, but is not limited to, any number of compute units 1250 and L2 cache 1242. In at least one embodiment, compute units 1250 share L2 cache 1242. In at least one embodiment, L2 cache 1242 is partitioned. In at least one embodiment, graphics complex 1240 includes, but is not limited to, any number of compute units 1250 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1240 includes, but is not limited to, any amount of specialized graphics hardware.

[0137] In at least one embodiment, each compute unit 1250 includes, but is not limited to, any number of SIMD units 1252 and shared memory 1254. In at least one embodiment, each SIMD unit 1252 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1250 can execute any number of thread blocks, but each thread block executes on a single compute unit 1250. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1252 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 1254.

[0138] In at least one embodiment, fabric 1260 is a system interconnect that facilitates data and control transfers across core complex 1210, graphics complex 1240, I / O interface 1270, memory controller 1280, display controller 1292, and multimedia engine 1294. In at least one embodiment, APU 1200 may include, in addition to or in lieu of fabric 1260, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1200. In at least one embodiment, I / O interface 1270 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1270. In at least one embodiment, peripheral devices coupled to I / O interface 1270 may include, but are not limited to, a keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0139] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 1280 facilitates data transfer between APU 1200 and unified system memory 1290. In at least one embodiment, core complex 1210 and graphics complex 1240 share unified system memory 1290.

[0140] In at least one embodiment, the APU 1200 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1280 and memory devices (e.g., shared memory 1254) that can be dedicated to a component or shared among multiple components. In at least one embodiment, the APU 1200 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1328, L3 cache 1230, and L2 cache 1242), each of which can be private to a component or shared among any number of components (e.g., core 1220, core complex 1210, SIMD units 1252, compute units 1250, and graphics complex 1240).

[0141] Figure 13 A CPU 1300 according to at least one embodiment is shown. In at least one embodiment, the CPU 1300 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1300 can be configured to execute application programs. In at least one embodiment, the CPU 1300 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1300 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1300 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1300 includes, but is not limited to, any number of core complexes 1310, structures 1360, I / O interfaces 1370, and memory controller AMAD80.

[0142] In at least one embodiment, core complex 1310 includes, but is not limited to, cores 1320(1)-1320(4) and L3 cache 1330. In at least one embodiment, core complex 1310 may include, but is not limited to, any number of cores 1320 and any combination of any number and type of caches. In at least one embodiment, cores 1320 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1320 is a CPU core.

[0143] In at least one embodiment, each core 1320 includes, but is not limited to, a fetch / decode unit 1322, an integer execution engine 1324, a floating-point execution engine 1326, and an L2 cache 1328. In at least one embodiment, the fetch / decode unit 1322 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1324 and the floating-point execution engine 1326. In at least one embodiment, the fetch / decode unit 1322 can simultaneously dispatch one micro-op to the integer execution engine 1324 and another micro-op to the floating-point execution engine 1326. In at least one embodiment, the integer execution engine 1324 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1326 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1322 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1324 and the floating-point execution engine 1326.

[0144] In at least one embodiment, each core 1320(i) can access an L2 cache 1328(i) included in the core 1320(i), where i is an integer representing a specific instance of the core 1320. In at least one embodiment, each core 1320 included in a core complex 1310(j) is connected to the other cores 1320 in the core complex 1310(j) via an L3 cache 1330(j) included in the core complex 1310(j), where j is an integer representing a specific instance of the core complex 1310. In at least one embodiment, a core 1320 included in a core complex 1310(j) can access all L3 caches 1330(j) included in the core complex 1310(j), where j is an integer representing a specific instance of the core complex 1310. In at least one embodiment, the L3 cache 1330 can include, but is not limited to, any number of slices.

[0145] In at least one embodiment, fabric 1360 is a system interconnect that facilitates data and control transfers across core complexes 1310(1)-1310(N) (where N is an integer greater than zero), I / O interface 1370, and memory controller 1380. In at least one embodiment, CPU 1300 may include, in addition to or in lieu of fabric 1360, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1300. In at least one embodiment, I / O interface 1370 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 1370. In at least one embodiment, peripherals coupled to I / O interface 1370 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0146] In at least one embodiment, memory controller 1380 facilitates data transfers between CPU 1300 and system memory 1390. In at least one embodiment, core complex 1310 and graphics complex 1340 share system memory 1390. In at least one embodiment, CPU 1300 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1380 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1300 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1328 and L3 cache 1330), each of which can be private to a component or shared among any number of components (e.g., core 1320 and core complex 1310).

[0147] Figure 14An exemplary accelerator integrated slice 1490 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0148] The application effective address space 1482 within system memory 1414 stores process elements 1483. In one embodiment, process elements 1483 are stored in response to GPU calls 1481 from application 1480 executing on processor 1407. Process elements 1483 contain the processing state of the corresponding application 1480. A work descriptor (WD) 1484 contained in process element 1483 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, WD 1484 is a pointer to a job request queue in application effective address space 1482.

[0149] Graphics acceleration module 1446 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 1484 to graphics acceleration module 1446 to start a job in a virtualized environment can be included.

[0150] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 1446 or individual graphics processing engine. Because the graphics acceleration module 1446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1446 is allocated.

[0151] In operation, the WD fetch unit 1491 in the accelerator integrated slice 1490 fetches the next WD 1484, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1446. Data from the WD 1484 can be stored in registers 1445 for use by the memory management unit (MMU) 1439, the interrupt management circuit 1447, and / or the context management circuit 1448, as shown. For example, one embodiment of the MMU 1439 includes segment / page roaming circuitry for accessing the segment / page tables 1486 within the OS virtual address space 1485. The interrupt management circuit 1447 can process interrupt events (INT) 1492 received from the graphics acceleration module 1446. When executing a graph operation, the effective address 1493 generated by the graphics processing engine is converted into a real address by the MMU 1439.

[0152] In one embodiment, the same register set 1445 is replicated for each graphics processing engine and / or graphics acceleration module 1446 and can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1490. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0153] Table 1 – Registers initialized by the hypervisor

[0154] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0155] Example registers that may be initialized by the operating system are shown in Table 2.

[0156] Table 2 – Operating System Initialization Registers

[0157] 1 Process and thread identification 2 Effective Address (EA) environment save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Mask of Authority 6 Job Descriptor

[0158] In one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0159] Figure 15A and 15B An exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0160] Figure 15A An exemplary graphics processor 1510 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 15B An additional exemplary graphics processor 1540 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, according to at least one embodiment. Figure 15A The graphics processor 1510 is a low power graphics processor core. In at least one embodiment, Figure 15B The graphics processor 1540 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1510, 1540 can be Figure 10 A variant of the graphics processor 1010.

[0161] In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D through 1515N-1 and 1515N). In at least one embodiment, the graphics processor 1510 can execute different shader programs via separate logic, such that the vertex processor 1505 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1515A-1515N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1505 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 1515A-1515N use the primitives and vertex data generated by the vertex processor 1505 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 1515A-1515N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0162] In at least one embodiment, graphics processor 1510 additionally includes one or more MMUs 1520A-1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide a mapping of virtual to physical addresses for graphics processor 1510, including for vertex processor 1505 and / or fragment processors 1515A-1515N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B may synchronize with other MMUs within the system, including with Figure 10 One or more MMUs associated with one or more application processors 1005, graphics processor 1015, and / or video processor 1020 enable each processor 1005-1020 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable graphics processor 1510 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0163] In at least one embodiment, graphics processor 1540 includes Figure 15A 1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B of the graphics processor 1510. In at least one embodiment, the graphics processor 1540 includes one or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F, through 1555N-1 and 1555N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1540 includes an inter-core task manager 1545 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1555A-1555N and a tiling unit 1558 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0164] Figure 16AFIGURE 1 shows a graphics core 1600 according to at least one embodiment. In at least one embodiment, the graphics core 1600 may include Figure 10 In at least one embodiment, the graphics core 1600 may be Figure 15B 15. In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, texture units 1618, and cache / shared memory 1620, which are common to execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 may include multiple slices 1601A-1601N or partitions of each core, and a graphics processor may include multiple instances of graphics core 1600. Slices 1601A-1601N may include support logic including local instruction caches 1604A-1604N, thread schedulers 1606A-1606N, thread dispatchers 1608A-1608N, and a set of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N may include a set of additional function units (AFUs) 1612A-1612N, floating point units (FPUs) 1614A-1614N, integer arithmetic logic units (ALUs) 1616A-1616N, address calculation units (ACUs) 1613A-1613N, double precision floating point units (DPFPUs) 1615A-1615N, and matrix processing units (MPUs) 1617A-1617N.

[0165] In one embodiment, the FPUs 1614A-1614N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1615A-1615N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1616A-1616N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1617A-1617N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1617A-1617N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1612A-1612N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0166] Figure 16BA general purpose graphics processing unit (GPGPU) 1630 is shown in at least one embodiment. In at least one embodiment, GPGPU 1630 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 1630 can be configured to enable highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 1630 can be directly linked to other instances of GPGPU 1630 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 1630 includes a host interface 1632 to enable connection to a host processor. In at least one embodiment, host interface 1632 is a PCIe interface. In at least one embodiment, host interface 1632 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1630 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 1636A-1636H using a global scheduler 1634. In at least one embodiment, compute clusters 1636A-1636H share cache memory 1638. In at least one embodiment, cache memory 1638 can serve as a higher level cache for cache memories within compute clusters 1636A-1636H.

[0167] In at least one embodiment, GPGPU 1630 includes memory 1644A-1644B coupled to compute clusters 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, memory 1644A-1644B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0168] In at least one embodiment, computing clusters 1636A-1636H each include a set of graphics cores, such as Figure 16A The graphics core 1600, which may include multiple types of integer and floating-point logic units, can perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1636A-1636H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0169] In at least one embodiment, multiple instances of GPGPU 1630 can be configured to operate as a compute cluster. Compute clusters 1636A-1636H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1630 communicate via host interface 1632. In at least one embodiment, GPGPU 1630 includes an I / O hub 1639 that couples GPGPU 1630 to GPU link 1640, enabling direct connections to other instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1630 are located in separate data processing systems and communicate via a network device accessible via host interface 1632. In at least one embodiment, GPU link 1640 may be configured to connect to a host processor, in addition to or in place of host interface 1632. In at least one embodiment, GPGPU 1630 may be configured to execute CUDA programs.

[0170] Figure 17A A parallel processor 1700 is shown in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0171] In at least one embodiment, parallel processor 1700 includes parallel processing unit 1702. In at least one embodiment, parallel processing unit 1702 includes an I / O unit 1704 that enables communication with other devices, including other instances of parallel processing unit 1702. In at least one embodiment, I / O unit 1704 can be directly connected to other devices. In at least one embodiment, I / O unit 1704 connects to other devices using a hub or switch interface (e.g., memory hub 1705). In at least one embodiment, the connection between memory hub 1705 and I / O unit 1704 forms a communication link. In at least one embodiment, I / O unit 1704 is connected to a host interface 1706 and a memory crossbar switch 1716, where host interface 1706 receives commands for performing processing operations and memory crossbar switch 1716 receives commands for performing memory operations.

[0172] In at least one embodiment, when host interface 1706 receives command buffers via I / O unit 1704, host interface 1706 can direct work operations to execute those commands to front end 1708. In at least one embodiment, front end 1708 is coupled to scheduler 1710, which is configured to dispatch commands or other work items to processing array 1712. In at least one embodiment, scheduler 1710 ensures that processing array 1712 is properly configured and in a valid state before dispatching tasks to a processing array 1712. In at least one embodiment, scheduler 1710 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 1712. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 1712 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1712 by scheduler 1710 logic within a microcontroller that includes scheduler 1710 .

[0173] In at least one embodiment, the processing array 1712 can include up to "N" processing clusters (e.g., cluster 1714A, cluster 1714B, through cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of the processing array 1712 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 1710 can allocate work to the clusters 1714A-1714N of the processing array 1712 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 1710 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 1712. In at least one embodiment, different clusters 1714A-1714N of the processing array 1712 can be assigned to process different types of programs or to perform different types of computations.

[0174] In at least one embodiment, processing array 1712 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 1712 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing array 1712 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0175] In at least one embodiment, processing array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1712 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 1712 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1702 may transfer data from system memory via I / O units 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1722) during processing and then written back to system memory.

[0176] In at least one embodiment, when parallel processing units 1702 are used to perform graph processing, scheduler 1710 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1714A-1714N of processing array 1712. In at least one embodiment, portions of processing array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1714A-1714N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1714A-1714N for further processing.

[0177] In at least one embodiment, the processing array 1712 can receive processing tasks to be executed via the scheduler 1710, which receives commands defining the processing tasks from the front end 1708. In at least one embodiment, the processing tasks can include an index of the data to be processed, which can include, for example, surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 1710 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 1708. In at least one embodiment, the front end 1708 can be configured to ensure that the processing array 1712 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0178] In at least one embodiment, each of one or more instances of parallel processing unit 1702 can be coupled to parallel processor memory 1722. In at least one embodiment, parallel processor memory 1722 can be accessed via memory crossbar 1716, which can receive memory requests from processing array 1712 and I / O unit 1704. In at least one embodiment, memory crossbar 1716 can access parallel processor memory 1722 via memory interface 1718. In at least one embodiment, memory interface 1718 can include multiple partition units (e.g., partition unit 1720A, partition unit 1720B, through partition unit 1720N), which can each be coupled to a portion of parallel processor memory 1722 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 1720A-1720N are configured to be equal to the number of memory cells, such that the first partition unit 1720A has a corresponding first memory cell 1724A, the second partition unit 1720B has a corresponding memory cell 1724B, and the Nth partition unit 1720N has a corresponding Nth memory cell 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not be equal to the number of memory devices.

[0179] In at least one embodiment, memory units 1724A-1724N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 1724A-1724N, allowing partition units 1720A-1720N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1722. In at least one embodiment, local instances of parallel processor memory 1722 may be eliminated in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0180] In at least one embodiment, any of the clusters 1714A-1714N of the processing array 1712 can process data to be written to any memory unit 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 can be configured to transmit the output of each cluster 1714A-1714N to any partition unit 1720A-1720N or another cluster 1714A-1714N, which can perform other processing operations on the output. In at least one embodiment, each cluster 1714A-1714N can communicate with a memory interface 1718 via the memory crossbar 1716 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 1716 has connections to memory interface 1718 for communicating with I / O unit 1704, and to local instances of parallel processor memory 1722, thereby enabling processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory that is not local to parallel processing unit 1702. In at least one embodiment, memory crossbar 1716 may use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N.

[0181] In at least one embodiment, multiple instances of parallel processing unit 1702 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1702 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1702 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1702 or parallel processor 1700 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0182] Figure 17BA processing cluster 1794 according to at least one embodiment is shown. In at least one embodiment, processing cluster 1794 is included in a parallel processing unit. In at least one embodiment, processing cluster 1794 is an instance of one of the processing clusters 1714A-1714N of Figure 17. In at least one embodiment, processing cluster 1794 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines in each processing cluster 1794.

[0183] In at least one embodiment, the operation of the processing cluster 1794 can be controlled by a pipeline manager 1732 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1732 receives instructions from the scheduler 1710 of FIG. 17 and manages the execution of these instructions by the graphics multiprocessor 1734 and / or the texture unit 1736. In at least one embodiment, the graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 1794. In at least one embodiment, one or more instances of the graphics multiprocessor 1734 can be included within the processing cluster 1794. In at least one embodiment, the graphics multiprocessor 1734 can process data, and the data crossbar 1740 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1732 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 1740.

[0184] In at least one embodiment, each graphics multiprocessor 1734 within a processing cluster 1794 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0185] In at least one embodiment, instructions transmitted to processing cluster 1794 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1734. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1734. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1734. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1734, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1734.

[0186] In at least one embodiment, the graphics multiprocessor 1734 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 1734 can abandon the internal cache and use cache memory within the processing cluster 1794 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 can also access a partition unit (e.g., Figure 17A L2 cache within partition units 1720A-1720N) of the graphics multiprocessor 1734 is shared across all processing clusters 1794 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1734 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1702 can be used as global memory. In at least one embodiment, processing cluster 1794 includes multiple instances of graphics multiprocessor 1734, which can share common instructions and data, which can be stored in L1 cache 1748.

[0187] In at least one embodiment, each processing cluster 1794 may include an MMU 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1745 may reside within memory interface 1718 of FIG. 17 . In at least one embodiment, MMU 1745 includes a set of page table entries (PTEs) that map virtual addresses to physical addresses of tiles (more on tiles below) and, optionally, cache line indices. In at least one embodiment, MMU 1745 may include a translation lookaside buffer (TLB) or a cache that may reside within graphics multiprocessor 1734 or L1 cache 1748 or processing cluster 1794. In at least one embodiment, physical addresses are processed to distribute surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0188] In at least one embodiment, processing clusters 1794 can be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs processed tasks to a data crossbar 1740 to provide the processed tasks to another processing cluster 1794 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1716. In at least one embodiment, a pre-raster operations unit (preROP) 1742 is configured to receive data from the graphics multiprocessor 1734 and direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 1720A-1720N of FIG. 17 ). In at least one embodiment, the PreROP 1742 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0189] Figure 17C A graphics multiprocessor 1796 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1796 is Figure 17B1734. In at least one embodiment, the graphics multiprocessor 1796 is coupled to the pipeline manager 1732 of the processing cluster 1794. In at least one embodiment, the graphics multiprocessor 1796 has an execution pipeline that includes, but is not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more GPGPU cores 1762, and one or more LSUs 1766. The GPGPU cores 1762 and the LSUs 1766 are coupled to cache memory 1772 and shared memory 1770 via a memory and cache interconnect 1768.

[0190] In at least one embodiment, the instruction cache 1752 receives a stream of instructions to be executed from the pipeline manager 1732. In at least one embodiment, the instructions are cached in the instruction cache 1752 and dispatched for execution by the instruction unit 1754. In one embodiment, the instruction unit 1754 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 1762. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1756 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 1766.

[0191] In at least one embodiment, register file 1758 provides a set of registers for the functional units of graphics multiprocessor 1796. In at least one embodiment, register file 1758 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 1762, LSU 1766) connected to graphics multiprocessor 1796. In at least one embodiment, register file 1758 is divided between each functional unit such that a dedicated portion of register file 1758 is allocated to each functional unit. In at least one embodiment, register file 1758 is divided between the different thread groups being executed by graphics multiprocessor 1796.

[0192] In at least one embodiment, the GPGPU cores 1762 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 1796. The GPGPU cores 1762 may be architecturally similar or may be architecturally different. In at least one embodiment, a first portion of the GPGPU core 1762 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-1708 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1796 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1762 may also include fixed-function or special-function logic.

[0193] In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0194] In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network that connects each functional unit of the graphics multiprocessor 1796 to the register file 1758 and the shared memory 1770. In at least one embodiment, the memory and cache interconnect 1768 is a crossbar interconnect that allows the LSU 1766 to implement load and store operations between the shared memory 1770 and the register file 1758. In at least one embodiment, the register file 1758 can operate at the same frequency as the GPGPU core 1762, resulting in very low latency for data transfers between the GPGPU core 1762 and the register file 1758. In at least one embodiment, the shared memory 1770 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 1796. In at least one embodiment, the cache memory 1772 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 1736. In at least one embodiment, the shared memory 1770 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1772, threads executing on GPGPU core 1762 may programmatically store data in shared memory.

[0195] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0196] Figure 18A graphics processor 1800 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 1800 includes a ring interconnect 1802, a pipeline front end 1804, a media engine 1837, and graphics cores 1880A-1880N. In at least one embodiment, ring interconnect 1802 couples graphics processor 1800 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 1800 is one of many processors integrated within a multi-core processing system.

[0197] In at least one embodiment, graphics processor 1800 receives batches of commands via ring interconnect 1802. In at least one embodiment, the input commands are interpreted by command streamer 1803 in pipeline front end 1804. In at least one embodiment, graphics processor 1800 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 1880A-1880N. In at least one embodiment, for 3D geometry processing commands, command streamer 1803 provides the commands to geometry pipeline 1836. In at least one embodiment, for at least some media processing commands, command streamer 1803 provides the commands to video front end 1834, which is coupled to media engine 1837. In at least one embodiment, media engine 1837 includes a video quality engine (VQE) 1830 for video and image post-processing, and a multi-format encoding / decoding (MFX) 1833 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1836 and the media engine 1837 each generate execution threads for thread execution resources provided by at least one graphics core 1880A.

[0198] In at least one embodiment, graphics processor 1800 includes scalable thread execution resources featuring modular graphics cores 1880A-1880N (sometimes referred to as core slices), each of which has multiple sub-cores 1850A-1850N, 1860A-1860N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 1800 can have any number of graphics cores 1880A-1880N. In at least one embodiment, graphics processor 1800 includes graphics core 1880A having at least a first sub-core 1850A and a second sub-core 1860A. In at least one embodiment, graphics processor 1800 is a low-power processor having a single sub-core (e.g., 1850A). In at least one embodiment, graphics processor 1800 includes multiple graphics cores 1880A-1880N, each of which includes a set of first sub-cores 1850A-1850N and a set of second sub-cores 1860A-1860N. In at least one embodiment, each of the first sub-cores 1850A-1850N includes at least a first set of execution units (EUs) 1852A-1852N and media / texture samplers 1854A-1854N. In at least one embodiment, each of the second sub-cores 1860A-1860N includes at least a second set of execution units 1862A-1862N and samplers 1864A-1864N. In at least one embodiment, each of the sub-cores 1850A-1850N, 1860A-1860N shares a set of shared resources 1870A-1870N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic.

[0199] Figure 19 A processor 1900 is shown according to at least one embodiment. In at least one embodiment, processor 1900 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, processor 1900 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, processor 1910 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in integer and floating-point form, may operate with packed data elements associated with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, processor 1910 may execute instructions to accelerate CUAD programs.

[0200] In at least one embodiment, processor 1900 includes an in-order front end ("Front End") 1901 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 1901 may include several units. In at least one embodiment, instruction prefetcher 1926 retrieves instructions from memory and provides them to instruction decoder 1928, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 1928 decodes received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") for execution. In at least one embodiment, instruction decoder 1928 parses instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 1930 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 1934 for execution. In at least one embodiment, when trace cache 1930 encounters a complex instruction, microcode ROM 1932 provides the microinstructions necessary to complete the operation.

[0201] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, instruction decoder 1928 may access microcode ROM 1932 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at instruction decoder 1928. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in microcode ROM 1932. In at least one embodiment, trace cache 1930 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from microcode ROM 1932 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 1932 completes the micro-op sequencing for the instruction, the front end 1901 of the machine may resume fetching micro-ops from trace cache 1930.

[0202] In at least one embodiment, an out-of-order execution engine ("OOO engine") 1903 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 1903 includes, but is not limited to, an allocator / register renamer 1940, a memory microinstruction queue 1942, an integer / floating-point microinstruction queue 1944, a memory scheduler 1946, a fast scheduler 1902, a slow / general floating-point scheduler ("slow / general FP scheduler") 1904, and a simple floating-point scheduler ("simple FP scheduler") 1906. In at least one embodiment, the fast scheduler 1902, the slow / general floating-point scheduler 1904, and the simple floating-point scheduler 1906 are also collectively referred to as "microinstruction schedulers 1902, 1904, 1906." The allocator / register renamer 1940 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 1940 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 1940 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 1942 for memory operations and an integer / floating-point microinstruction queue 1944 for non-memory operations, preceding the memory scheduler 1946 and the microinstruction schedulers 1902, 1904, 1906. In at least one embodiment, the microinstruction schedulers 1902, 1904, 1906 determine when a microinstruction is ready to execute based on the readiness of its dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 1902 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating-point scheduler 1904 and the simple floating-point scheduler 1906 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 1902, 1904, 1906 arbitrate over dispatch ports to schedule microinstructions for execution.

[0203] In at least one embodiment, execution block 1911 includes, but is not limited to, integer register file / branch network 1908, floating point register file / branch network ("FP register file / branch network") 1910, address generation units ("AGUs") 1912 and 1914, fast arithmetic logic units ("fast ALUs") 1916 and 1918, slow ALU 1920, floating point ALU ("FP") 1922, and floating point move unit ("FP move") 1924. In at least one embodiment, integer register file / branch network 1908 and floating point register file / bypass network 1910 are also referred to herein as "register files 1908, 1910." In at least one embodiment, ALUs 1912 and 1914, fast ALUs 1916 and 1918, slow ALU 1920, floating-point ALU 1922, and floating-point move unit 1924 are also referred to herein as "execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0204] In at least one embodiment, register files 1908 and 1910 may be arranged between microinstruction schedulers 1902, 1904, and 1906 and execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924. In at least one embodiment, integer register file / branch network 1908 performs integer operations. In at least one embodiment, floating-point register file / branch network 1910 performs floating-point operations. In at least one embodiment, each of register files 1908 and 1910 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 1908 and 1910 can communicate data with each other. In at least one embodiment, integer register file / branch network 1908 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 1910 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0205] In at least one embodiment, execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924 can execute instructions. In at least one embodiment, register files 1908 and 1910 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 1900 can include, but is not limited to, any number of execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924, and combinations thereof. In at least one embodiment, floating-point ALU 1922 and floating-point move unit 1924 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 1922 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 1916 and 1918. In at least one embodiment, fast ALUs 1916 and 1918 can execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 1920, as slow ALU 1920 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 1912 and 1914. In at least one embodiment, fast ALU 1916, fast ALU 1918, and slow ALU 1920 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 1916, fast ALU 1918, and slow ALU 1920 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 1922 and floating point shift unit 1924 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 1922 and floating point shift unit 1924 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0206] In at least one embodiment, microinstruction schedulers 1902, 1904, 1906 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 1900, processor 1900 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0207] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0208] Figure 20 A processor 2000 is shown in accordance with at least one embodiment. In at least one embodiment, the processor 2000 includes, but is not limited to, one or more processor cores (cores) 2002A-2002N, an integrated memory controller 2014, and an integrated graphics processor 2008. In at least one embodiment, the processor 2000 may include additional cores, up to and including the additional processor core 2002N represented by the dashed box. In at least one embodiment, each processor core 2002A-2002N includes one or more internal cache units 2004A-2004N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2006.

[0209] In at least one embodiment, the internal cache units 2004A-2004N and the shared cache unit 2006 represent a cache memory hierarchy within the processor 2000. In at least one embodiment, the cache memory units 2004A-2004N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2006 and 2004A-2004N.

[0210] In at least one embodiment, the processor 2000 may also include a set of one or more bus controller units 2016 and a system agent core 2010. In at least one embodiment, the one or more bus controller units 2016 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2010 provides management functions for various processor components. In at least one embodiment, the system agent core 2010 includes one or more integrated memory controllers 2014 to manage access to various external memory devices (not shown).

[0211] In at least one embodiment, one or more processor cores 2002A-2002N include support for simultaneous multithreading. In at least one embodiment, system agent core 2010 includes components for coordinating and operating processor cores 2002A-2002N during multithreaded processing. In at least one embodiment, system agent core 2010 may additionally include a power control unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2002A-2002N and graphics processor 2008.

[0212] In at least one embodiment, the processor 2000 further includes a graphics processor 2008 to perform graphics processing operations. In at least one embodiment, the graphics processor 2008 is coupled to a shared cache unit 2006 and a system agent core 2010 including one or more integrated memory controllers 2014. In at least one embodiment, the system agent core 2010 also includes a display controller 2011 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2011 may also be a separate module coupled to the graphics processor 2008 via at least one interconnect, or may be integrated within the graphics processor 2008.

[0213] In at least one embodiment, a ring-based interconnect 2012 is used to couple the internal components of the processor 2000. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2008 is coupled to the ring interconnect 2012 via an I / O link 2013.

[0214] In at least one embodiment, I / O link 2013 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2018 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 2002A-2002N and graphics processor 2008 uses embedded memory module 2018 as a shared LLC.

[0215] In at least one embodiment, the processor cores 2002A-2002N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2002A-2002N are heterogeneous in terms of ISA, where one or more processor cores 2002A-2002N execute a common instruction set, while one or more other processor cores 2002A-2002N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2002A-2002N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2000 can be implemented on one or more chips or as a SoC integrated circuit.

[0216] Figure 21 A graphics processor core 2100 is shown in accordance with at least one described embodiment. In at least one embodiment, the graphics processor core 2100 is included within a graphics core array. In at least one embodiment, the graphics processor core 2100 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2100 is an example of a graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2100 can include fixed function blocks 2130 coupled to multiple sub-cores 2101A-2101F, also referred to as sub-slices, which include modular blocks of general-purpose and fixed-function logic.

[0217] In at least one embodiment, fixed function block 2130 includes a geometry / fixed function pipeline 2136, which may be shared by all sub-cores in graphics processor 2100, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2136 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0218] In at least one embodiment, fixed function block 2130 also includes a graphics SoC interface 2137, a graphics microcontroller 2138, and a media pipeline 2139. Graphics SoC interface 2137 provides an interface between graphics core 2100 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2138 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2100, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2139 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2139 implements media operations via requests to computational or sampling logic within sub-cores 2101-2101F.

[0219] In at least one embodiment, the SoC interface 2137 enables the graphics core 2100 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2137 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2100 and the CPU within the SoC. In at least one embodiment, the SoC interface 2137 may also implement power management controls for the graphics core 2100 and enable interfaces between the clock domain of the graphics core 2100 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2137 enables the reception of command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2139 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2136, geometry and fixed function pipeline 2114) when graph processing operations are to be performed.

[0220] In at least one embodiment, the graphics microcontroller 2138 can be configured to perform various scheduling and management tasks for the graphics core 2100. In at least one embodiment, the graphics microcontroller 2138 can perform graph and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2102A-2102F, 2104A-2104F in the sub-cores 2101A-2101F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2100 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2138 may also facilitate a low power or idle state for the graphics core 2100, thereby providing the graphics core 2100 with the ability to save and restore registers across low power state transitions within the graphics core 2100 independent of the operating system and / or graphics driver software on the system.

[0221] In at least one embodiment, the graphics core 2100 may have more or fewer sub-cores than the sub-cores 2101A-2101F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, the graphics core 2100 may also include shared function logic 2110, shared and / or cache memory 2112, geometry / fixed function pipelines 2114, and additional fixed function logic 2116 to accelerate various graphics and compute processing operations. In at least one embodiment, the shared function logic 2110 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within the graphics core 2100. The shared and / or cache memory 2112 may be the LLC for the N sub-cores 2101A-2101F within the graphics core 2100 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2114 may be included in place of geometry / fixed function pipeline 2136 within fixed function block 2130 and may include the same or similar logic units.

[0222] In at least one embodiment, graphics core 2100 includes additional fixed-function logic 2116, which may include various fixed-function acceleration logic for use by graphics core 2100. In at least one embodiment, additional fixed-function logic 2116 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, including a full geometry pipeline and a culling pipeline within geometry / fixed-function pipelines 2116, 2136, which may be included in additional fixed-function logic 2116. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2116 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0223] In at least one embodiment, the additional fixed function logic 2116 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0224] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2101A-2101F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2101A-2101F includes multiple EU arrays 2102A-2102F, 2104A-2104F, thread dispatch and inter-thread communication (TD / IC) logic 2103A-2103F, 3D (e.g., texture) samplers 2105A-2105F, media samplers 2106A-2106F, shader processors 2107A-2107F, and shared local memory (SLM) 2108A-2108F. Each EU array 2102A-2102F, 2104A-2104F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2103A-2103F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, 3D samplers 2105A-2105F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2106A-2106F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2101A-2101F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2101A-2101F may utilize shared local memory 2108A-2108F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0225] Figure 22A parallel processing unit ("PPU") 2200 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2200 is configured with machine-readable code that, if executed by PPU 2200, causes PPU 2200 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 2200 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2200. In at least one embodiment, PPU 2200 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2200 is configured to perform computations, such as linear algebra operations and machine learning operations. Figure 22 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0226] In at least one embodiment, one or more PPUs 2200 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2200 are configured to accelerate CUDA programs. In at least one embodiment, a PPU 2200 includes, but is not limited to, an I / O unit 2206, a front-end unit 2210, a scheduler unit 2212, a work distribution unit 2214, a hub 2216, a crossbar switch ("Xbar") 2220, one or more general processing clusters ("GPCs") 2218, and one or more partitioning units ("memory partitioning units") 2222. In at least one embodiment, a PPU 2200 is connected to a host processor or other PPUs 2200 via one or more high-speed GPU interconnects ("GPU interconnects") 2208. In at least one embodiment, a PPU 2200 is connected to a host processor or other peripheral devices via an interconnect 2202. In one embodiment, a PPU 2200 is connected to local memory including one or more memory devices ("memory") 2204. In at least one embodiment, the memory device 2204 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem, with multiple DRAM dies stacked within each device.

[0227] In at least one embodiment, the high-speed GPU interconnect 2208 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2200 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPUs 2200 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2208 transmits data and / or commands to other units of the PPU 2200, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via the hub 2216. Figure 22 Other components that may not be explicitly shown.

[0228] In at least one embodiment, the I / O unit 2206 is configured to receive data from the host processor ( Figure 22 2206). In at least one embodiment, the I / O unit 2206 communicates with the host processor directly via the system bus 2202 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2206 can communicate with one or more other processors (e.g., one or more PPUs 2200) via the system bus 2202. In at least one embodiment, the I / O unit 2206 implements a PCIe interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2206 implements an interface for communicating with external devices.

[0229] In at least one embodiment, the I / O unit 2206 decodes packets received via the system bus 2202. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2200 to perform various operations. In at least one embodiment, the I / O unit 2206 sends the decoded commands to various other units of the PPU 2200 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2210 and / or to the hub 2216 or other units of the PPU 2200, such as one or more replication engines, video encoders, video decoders, power management units, etc. ( Figure 22 In at least one embodiment, I / O unit 2206 is configured to route communications between the various logical units of PPU 2200.

[0230] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2200 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2200—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2202 via memory requests transmitted via the I / O unit 2206 over the system bus 2202. In at least one embodiment, the host processor writes a command stream into the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2200, causing the front end unit 2210 to receive pointers to one or more command streams and manage the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2200.

[0231] In at least one embodiment, the front end unit 2210 is coupled to a scheduler unit 2212 that configures the various GPCs 2218 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2212 is configured to track state information related to the various tasks managed by the scheduler unit 2212, where the state information may indicate which GPC 2218 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2212 manages multiple tasks that execute on one or more GPCs 2218.

[0232] In at least one embodiment, the scheduler unit 2212 is coupled to a work distribution unit 2214, which is configured to dispatch tasks for execution on the GPCs 2218. In at least one embodiment, the work distribution unit 2214 tracks a plurality of scheduled tasks received from the scheduler unit 2212 and manages a pending task pool and an active task pool for each GPC 2218. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2218; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by the GPC 2218, such that as a task on a GPC 2218 completes execution, the task is evicted from the active task pool of the GPC 2218, and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2218. In at least one embodiment, if an active task is idle on a GPC 2218, such as while waiting for data dependencies to be resolved, the active task is evicted from the GPC 2218 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2218.

[0233] In at least one embodiment, the work distribution unit 2214 communicates with one or more GPCs 2218 via an XBar 2220. In at least one embodiment, the XBar 2220 is an interconnect network that couples many units of the PPU 2200 to other units of the PPU 2200 and can be configured to couple the work distribution unit 2214 to a specific GPC 2218. In at least one embodiment, one or more other units of the PPU 2200 can also be connected to the XBar 2220 through a hub 2216.

[0234] In at least one embodiment, tasks are managed by a scheduler unit 2212 and assigned to one of the GPCs 2218 by a work distribution unit 2214. The GPC 2218 is configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2218, routed to a different GPC 2218 via an XBar 2220, or stored in memory 2204. In at least one embodiment, the results can be written to memory 2204 via a partition unit 2222, which implements a memory interface for writing data to or reading data from memory 2204. In at least one embodiment, the results can be transferred to another PPU 2200 or CPU via a high-speed GPU interconnect 2208. In at least one embodiment, the PPU 2200 includes, but is not limited to, U partition units 2222, which equal the number of separate and distinct memory devices 2204 coupled to the PPU 2200.

[0235] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2200. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2200, and the PPU 2200 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2200, and the driver core outputs the tasks to one or more streams processed by the PPU 2200. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0236] Figure 23 FIG2 shows a GPC 2300 according to at least one embodiment. In at least one embodiment, the GPC 2300 is Figure 222218. In at least one embodiment, each GPC 2300 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2300 includes, but is not limited to, a pipeline manager 2302, a pre-raster operations unit ("PROP") 2304, a raster engine 2308, a work distribution crossbar ("WDX") 2316, a memory management unit ("MMU") 2318, one or more data processing clusters ("DPCs") 2306, and any suitable combination of components.

[0237] In at least one embodiment, the operation of the GPC 2300 is controlled by a pipeline manager 2302. In at least one embodiment, the pipeline manager 2302 manages the configuration of one or more DPCs 2306 to process tasks assigned to the GPC 2300. In at least one embodiment, the pipeline manager 2302 configures at least one of the one or more DPCs 2306 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2306 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2314. In at least one embodiment, the pipeline manager 2302 is configured to route packets received from the work distribution unit to appropriate logic within the GPC 2300, and in at least one embodiment, some packets may be routed to fixed-function hardware units in the PROP 2304 and / or raster engine 2308, while other packets may be routed to the DPC 2306 for processing by the primitive engine 2312 or SM 2314. In at least one embodiment, pipeline manager 2302 configures at least one of DPCs 2306 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2302 configures at least one of DPCs 2306 to execute at least a portion of a CUDA program.

[0238] In at least one embodiment, PROP unit 2304 is configured to route data generated by raster engine 2308 and DPC 2306 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Figure 22Memory partitioning unit 2222, etc., described in more detail. In at least one embodiment, PROP unit 2304 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 2308 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2308 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2308 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2306).

[0239] In at least one embodiment, each DPC 2306 included in a GPC 2300 includes, but is not limited to, an M-pipeline controller ("MPC") 2310; a primitive engine 2312; one or more SMs 2314; and any suitable combination thereof. In at least one embodiment, the MPC 2310 controls the operation of the DPC 2306, routing packets received from the pipeline manager 2302 to appropriate units within the DPC 2306. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2312, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2314.

[0240] In at least one embodiment, SM 2314 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2314 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group and implements a single instruction, multiple data ("SIMD") architecture, wherein each thread in a thread group (e.g., a warp) is configured to process a different data set based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2314 implements a single instruction, multiple thread ("SIMT") architecture, wherein each thread in a thread group is configured to process a different data set based on the same instruction set, but wherein individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 24 At least one embodiment of SM 2314 is described in more detail.

[0241] In at least one embodiment, the MMU 2318 provides a communication channel between the GPC 2300 and the memory partition unit (e.g., Figure 22 The MMU 2318 provides an interface between the memory and the partition unit 2222, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2318 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0242] Figure 24 Streaming Multiprocessor ("SM") 2400 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2400 is Figure 23SM 2314. In at least one embodiment, SM 2400 includes, but is not limited to, an instruction cache 2402; one or more scheduler units 2404; a register file 2408; one or more processing cores ("cores") 2410; one or more special function units ("SFUs") 2412; one or more load / store units ("LSUs") 2414; an interconnect network 2416; a shared memory / level 1 ("L1") cache 2418; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of SMs 2400. In at least one embodiment, scheduler unit 2404 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2400. In at least one embodiment, the scheduler unit 2404 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2404 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperating groups to various functional units (e.g., processing core 2410, SFU 2412, and LSU 2414) during each clock cycle.

[0243] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0244] In at least one embodiment, the dispatch unit 2406 is configured to send instructions to one or more of the functional units, and the scheduler unit 2404 includes, but is not limited to, two dispatch units 2406 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 2404 includes a single dispatch unit 2406 or additional dispatch units 2406.

[0245] In at least one embodiment, each SM 2400 includes, but is not limited to, a register file 2408 that provides a set of registers for the functional units of SM 2400. In at least one embodiment, register file 2408 is partitioned between each functional unit, allocating a dedicated portion of register file 2408 to each functional unit. In at least one embodiment, register file 2408 is partitioned between the different warps executed by SM 2400, and register file 2408 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 2400 includes, but is not limited to, a plurality of L processing cores 2410. In at least one embodiment, SM 2400 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2410. In at least one embodiment, each processing core 2410 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2410 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0246] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2410. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0247] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4×4×4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0248] In at least one embodiment, each SM 2400 includes, but is not limited to, M SFUs 2412 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 2412 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 2412 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 2400. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2418. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 2400 includes, but is not limited to, two texture units.

[0249] In at least one embodiment, each SM 2400 includes, but is not limited to, N LSUs 2414 that implement load and store operations between the shared memory / L1 cache 2418 and the register file 2408. In at least one embodiment, each SM 2400 includes, but is not limited to, an interconnection network 2416 that connects each functional unit to the register file 2408, and the LSUs 2414 connect to the register file 2408 and the shared memory / L1 cache 2418. In at least one embodiment, the interconnection network 2416 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2408, and to connect the LSUs 2414 to memory locations in the register file 2408 and the shared memory / L1 cache 2418.

[0250] In at least one embodiment, the shared memory / L1 cache 2418 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 2400 and the primitive engines, as well as between threads within the SM 2400. In at least one embodiment, the shared memory / L1 cache 2418 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 2400 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2418 is used to cache reads and writes in at least one embodiment. In at least one embodiment, one or more of the shared memory / L1 cache 2418, the L2 cache, and the memory is a backing store.

[0251] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use the shared memory or as a cache; for example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2418 enables the shared memory / L1 cache 2418 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure each thread generates unique results, use SM 2400 to execute the program and perform computations, use shared memory / L1 cache 2418 to communicate between threads, and use LSU 2414 to read and write global memory through shared memory / L1 cache 2418 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 2400 writes commands to scheduler unit 2404 that can be used to start new work on a DPC.

[0252] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0253] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0254] Software Construction for General Computing

[0255] The following figures illustrate, but are not limited to, exemplary software configurations for implementing at least one embodiment.

[0256] Figure 25 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL, or Intel One API.

[0257] In at least one embodiment, the programming platform's software stack 2500 provides an execution environment for applications 2501. In at least one embodiment, applications 2501 may include any computer software capable of being launched on the software stack 2500. In at least one embodiment, applications 2501 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0258] In at least one embodiment, the application 2501 and the software stack 2500 run on hardware 2507. In at least one embodiment, the hardware 2507 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, for example, using CUDA, the software stack 2500 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, the software stack 2500 can be used with devices from different vendors. In at least one embodiment, the hardware 2507 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within the hardware 2507, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within the hardware 2507 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0259] In at least one embodiment, the programming platform's software stack 2500 includes, but is not limited to, a plurality of libraries 2503, a runtime 2505, and device kernel drivers 2506. In at least one embodiment, each of the libraries 2503 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 2503 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2503 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2503 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 2503 are associated with corresponding APIs 2502, which may include one or more APIs that expose the functions implemented in the libraries 2503.

[0260] In at least one embodiment, the application 2501 is written as source code that is compiled into executable code as follows in conjunction with Figure 27-32 25. In at least one embodiment, the executable code of application 2501 can be run at least in part on an execution environment provided by software stack 2500. In at least one embodiment, during the execution of application 2501, code that needs to be run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, runtime 2505 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 2505 can include any technically feasible runtime system capable of supporting the execution of application 2501.

[0261] In at least one embodiment, runtime 2505 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 2504). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0262] In at least one embodiment, the runtime library and corresponding API 2504 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0263] In at least one embodiment, the device kernel driver 2506 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 2506 can provide APIs such as API 2504 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 2506 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2506 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the need for the device kernel driver 2506 to compile the IR code at runtime.

[0264] Figure 26 According to at least one embodiment, Figure 25 26. In at least one embodiment, the CUDA software stack 2600, on which the application 2601 can be launched, includes a CUDA library 2603, a CUDA runtime 2605, a CUDA driver 2607, and a device kernel driver 2608. In at least one embodiment, the CUDA software stack 2600 executes on hardware 2609, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0265] In at least one embodiment, the application 2601, the CUDA runtime 2605, and the device kernel driver 2608 can perform similar functions as the application 2501, the runtime 2505, and the device kernel driver 2506, respectively. Figure 25. In at least one embodiment, the CUDA driver 2607 includes a library (libcuda.so) that implements the CUDA driver API 2606. In at least one embodiment, similar to the CUDA runtime API 2604 implemented by the CUDA runtime library (cudart), the CUDA driver API 2606 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2606 differs from the CUDA runtime API 2604 in that the CUDA runtime API 2604 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 2604, in at least one embodiment, the CUDA driver API 2606 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2606 may expose functions for context management that are not exposed by the CUDA runtime API 2604. In at least one embodiment, the CUDA driver API 2606 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 2604. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 2605, can be considered separate from the driver components, including the user-mode CUDA driver 2607 and the kernel-mode device driver 2608 (sometimes also referred to as a "display" driver).

[0266] In at least one embodiment, the CUDA libraries 2603 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 2601). In at least one embodiment, the CUDA libraries 2603 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers, among others. In at least one embodiment, the CUDA libraries 2603 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference, among others.

[0267] Figure 27 According to at least one embodiment, Figure 25In at least one embodiment, the ROCm software stack 2700, on which an application 2701 can be launched, includes a language runtime 2703, a system runtime 2705, thunks 2707, a ROCm kernel driver 2708, and a device kernel driver. In at least one embodiment, the ROCm software stack 2700 executes on hardware 2709, which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0268] In at least one embodiment, application 2701 may execute a combination of the above Figure 25 In addition, in at least one embodiment, the language runtime 2703 and the system runtime 2705 can perform functions similar to those described above in conjunction with the application 2501. Figure 25 The language runtime 2703 and the system runtime 2705 have similar functionality to the runtime 2505 discussed above. In at least one embodiment, the language runtime 2703 differs from the system runtime 2705 in that the system runtime 2705 is a language-agnostic runtime that implements the ROCr system runtime API 2704 and leverages the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 2705, the language runtime 2703 is an implementation of a language-specific runtime API 2702 layered on top of the ROCr system runtime API 2704. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 26 Similar functions to the CUDA runtime API 2604 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0269] In at least one embodiment, thunk (ROCt) 2707 is an interface that can be used to interact with the underlying ROCm driver 2708. In at least one embodiment, the ROCm driver 2708 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 25 The HSA kernel driver 2506 may function similarly to the discussed device kernel driver 2506. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0270] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2700 above the language runtime 2703 and provide Figure 26 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, and the like.

[0271] Figure 28 According to at least one embodiment, Figure 25 2500. In at least one embodiment, the OpenCL software stack 2800, on which an application 2801 can be launched, includes an OpenCL framework 2810, an OpenCL runtime 2806, and a driver 2807. In at least one embodiment, the OpenCL software stack 2800 executes on hardware 2609 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0272] In at least one embodiment, the application 2801, the OpenCL runtime 2806, the device kernel driver 2807 and the hardware 2808 can each execute in conjunction with the above Figure 25 Similar functionality is discussed for application 2501, runtime 2505, device kernel driver 2506, and hardware 2507. In at least one embodiment, application 2801 also includes an OpenCL kernel 2802 having code to be executed on the device.

[0273] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 2803 and runtime API 2805. In at least one embodiment, runtime API 2805 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 2805 can use to manage the device's command queue, program and kernel objects, shared memory objects, and the like. In at least one embodiment, platform API 2803 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

[0274] In at least one embodiment, a compiler 2804 is also included in the OpenCL framework 2810. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by a compiler 2804, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0275] Figure 29 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 2904 is configured to support various programming models 2903, middleware and / or libraries 2902, and frameworks 2901 that applications 2900 can rely on. In at least one embodiment, application 2900 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can depend on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0276] In at least one embodiment, the programming platform 2904 can be a combination of the above Figure 26 、 Figure 27 and Figure 28 In at least one embodiment, the programming platform 2904 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, the programming platform 2904 supports multiple programming models 2903, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 2903 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 2903 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0277] In at least one embodiment, the library and / or middleware 2902 provides an abstract implementation of the programming model 2904. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 2904, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 2902 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 2902 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0278] In at least one embodiment, application framework 2901 depends on libraries and / or middleware 2902. In at least one embodiment, each application framework 2901 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0279] Figure 30 Compiled code is shown in accordance with at least one embodiment to Figures 25-28In at least one embodiment, compiler 3001 receives source code 3000, which includes both host code and device code. In at least one embodiment, compiler 3001 is configured to convert source code 3000 into host executable code 3002 for execution on a host and device executable code 3003 for execution on a device. In at least one embodiment, source code 3000 can be compiled offline before executing the application, or compiled online during execution of the application.

[0280] In at least one embodiment, source code 3000 may include code in any programming language supported by compiler 3001, such as C++, C, Fortran, etc. In at least one embodiment, source code 3000 may be included in a single-source file having a mixture of host code and device code, and indicating the location of the device code therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3000 may include multiple source code files, rather than a single source file, in which host code and device code are separated.

[0281] In at least one embodiment, compiler 3001 is configured to compile source code 3000 into host executable code 3002 for execution on a host and device executable code 3003 for execution on a device. In at least one embodiment, compiler 3001 performs operations including parsing source code 3000 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3000 comprises a single source file, compiler 3001 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 3003 and host executable code 3002, respectively, and link device executable code 3003 and host executable code 3002 together in a single file, as described below with respect to Figure 31 discussed in more detail.

[0282] In at least one embodiment, host executable code 3002 and device executable code 3003 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3002 may include native object code, while device executable code 3003 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3002 and device executable code 3003 may include target binary code.

[0283] Figure 31 is compiled code according to at least one embodiment to Figures 25-28 31. In at least one embodiment, the compiler 3101 is configured to receive source code 3100, compile the source code 3100, and output an executable file 3110. In at least one embodiment, the source code 3100 is a single source file, such as a .cu file, a .hip.cpp file, or a file in another format, which includes both host code and device code. In at least one embodiment, the compiler 3101 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0284] In at least one embodiment, compiler 3101 includes a compiler front end 3102, a host compiler 3105, a device compiler 3106, and a linker 3109. In at least one embodiment, compiler front end 3102 is configured to separate device code 3104 from host code 3103 in source code 3100. In at least one embodiment, device code 3104 is compiled by device compiler 3106 into device executable code 3108, which, as described, may include binary code or IR code. In at least one embodiment, host code 3103 is separately compiled by host compiler 3105 into host executable code 3107. In at least one embodiment, for NVCC, host compiler 3105 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3106 may be, but is not limited to, a Low-Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3105 and the device compiler 3106 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0285] In at least one embodiment, after source code 3100 is compiled into host executable code 3107 and device executable code 3108, a linker 3109 links the host and device executable codes 3107 and 3108 together in an executable file 3110. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0286] Figure 3232. The method of converting source code before compiling it is shown in accordance with at least one embodiment. In at least one embodiment, source code 3200 is passed through a conversion tool 3201, which converts source code 3200 into converted source code 3202. In at least one embodiment, a compiler 3203 is used to compile the converted source code 3202 into a host executable code 3204 and a device executable code 3205, similar to the process by which compiler 3001 compiles source code 3000 into host executable code 3002 and device executable code 3003, as described above in conjunction with Figure 30 discussed.

[0287] In at least one embodiment, the conversion performed by the conversion tool 3201 is used to port the source code 3200 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, the conversion tool 3201 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, the conversion of the source code 3200 may include parsing the source code 3200 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figures 33A-34 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3201 may sometimes be incomplete, requiring additional manual effort to fully port the source code 3200.

[0288] Configuring GPUs for general computing

[0289] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code in accordance with at least one embodiment.

[0290] Figure 33AA system 3300 is shown configured to compile and execute CUDA source code 3310 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3300 includes, but is not limited to, CUDA source code 3310, a CUDA compiler 3350, a host executable 3370(1), a host executable 3370(2), a CUDA device executable 3384, a CPU 3390, a CUDA-enabled GPU 3394, a GPU 3392, a CUDA to HIP conversion tool 3320, HIP source code 3330, a HIP compiler driver 3340, an HCC 3360, and an HCC device executable 3382.

[0291] In at least one embodiment, CUDA source code 3310 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3390, GPU 3392, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3390.

[0292] In at least one embodiment, CUDA source code 3310 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, global functions 3312, device functions 3314, host functions 3316, and host / device functions 3318 can be intermixed within CUDA source code 3310. In at least one embodiment, each global function 3312 is executable on a device and callable from a host. Thus, in at least one embodiment, one or more of global functions 3312 can serve as an entry point for a device. In at least one embodiment, each global function 3312 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3312 define a kernel that is executable on a device and callable from such a device. In at least one embodiment, a kernel is executed N times (where N is any positive integer) in parallel by N different threads on the device during execution.

[0293] In at least one embodiment, each device function 3314 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3316 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3316 defines both a host version of the function that is executable on the host and can only be called from such a host, and a device version of the function that is executable on a device and can only be called from such a device.

[0294] In at least one embodiment, CUDA source code 3310 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA runtime API 3302. In at least one embodiment, the CUDA runtime API 3302 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host and device memory, managing systems with multiple devices, and the like. In at least one embodiment, CUDA source code 3310 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, CUDA APIs include, but are not limited to, the CUDA runtime API 3302, the CUDA driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and relative to the CUDA runtime API 3302, the CUDA driver API is a lower-level API that provides finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0295] In at least one embodiment, the CUDA compiler 3350 compiles input CUDA code (e.g., CUDA source code 3310) to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, the CUDA compiler 3350 is NVCC. In at least one embodiment, the host executable code 3370(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3390. In at least one embodiment, the CPU 3390 can be any processor optimized for sequential instruction processing.

[0296] In at least one embodiment, the CUDA device executable code 3384 is a compiled version of the device code included in the input source code that is executable on the CUDA-enabled GPU 3394. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, IR code, such as PTX code, which is further compiled by a device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3394). In at least one embodiment, the CUDA-enabled GPU 3394 can be any processor optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3394 is developed by NVIDIA Corporation of Santa Clara, California.

[0297] In at least one embodiment, the CUDA to HIP conversion tool 3320 is configured to convert CUDA source code 3310 into functionally similar HIP source code 3330. In at least one embodiment, the HIP source code 3330 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language and includes, but is not limited to, a functionally similar version of the CUDA mechanism for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism for defining global functions 3312. However, such a HIP programming language may lack support for dynamic parallelism, and therefore, global functions 3312 defined in the HIP code are only callable from the host.

[0298] In at least one embodiment, HIP source code 3330 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, HIP source code 3330 may also include any number of calls to any number of functions specified in HIP runtime API 3332. In one embodiment, HIP runtime API 3332 includes, but is not limited to, functionally similar versions of a subset of functions included in CUDA runtime API 3302. In at least one embodiment, HIP source code 3330 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, HIP APIs include, but are not limited to, HIP runtime API 3332, HIP driver APIs, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0299] In at least one embodiment, the CUDA to HIP conversion tool 3320 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3320 converts any number of calls to functions specified in the CUDA runtime API 3302 to any number of calls to functions specified in the HIP runtime API 3332.

[0300] In at least one embodiment, the CUDA to HIP conversion tool 3320 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3320 is a tool called hipify-clang, which performs a more complex and robust conversion process than hipify-perl, which involves parsing the CUDA code using clang (a compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3320, correctly converting the CUDA code to HIP code may also require modifications (e.g., manual editing).

[0301] In at least one embodiment, HIP compiler driver 3340 is a front end that determines target device 3346 and then configures a compiler compatible with target device 3346 to compile HIP source code 3330. In at least one embodiment, target device 3346 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3340 can determine target device 3346 in any technically feasible manner.

[0302] In at least one embodiment, if the target device 3346 is CUDA compatible (e.g., a CUDA-enabled GPU 3394), the HIP compiler driver 3340 generates HIP / NVCC compile commands 3342. In at least one embodiment and in conjunction with Figure 33B As described in more detail, HIP / NVCC compile commands 3342 configure CUDA compiler 3350 to use, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries to compile HIP source code 3330. In at least one embodiment and in response to HIP / NVCC compile commands 3342, CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384.

[0303] In at least one embodiment, if the target device 3346 is not CUDA compatible, the HIP compiler driver 3340 generates HIP / HCC compilation commands 3344. In at least one embodiment and as in conjunction with Figure 33C As described in more detail, HIP / HCC compile command 3344 configures HCC 3360 to compile HIP source code 3330 using the HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3344, HCC 3360 generates host executable code 3370(2) and HCC device executable code 3382. In at least one embodiment, HCC device executable code 3382 is a compiled version of the device code contained in HIP source code 3330 that can be executed on GPU 3392. In at least one embodiment, GPU 3392 can be any processor optimized for parallel instruction processing, not compatible with CUDA, and compatible with HCC. In at least one embodiment, GPU 3392 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, GPU 3392 is a non-CUDA-enabled GPU 3392.

[0304] For illustrative purposes only, Figure 33A3390 and different devices. In at least one embodiment, three different flows are depicted that can be implemented to compile CUDA source code 3310 for execution on a CPU 3390 and different devices. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3310 for execution on the CPU 3390 and a CUDA-enabled GPU 3394 without converting the CUDA source code 3310 into HIP source code 3330. In at least one embodiment, the indirect CUDA flow converts CUDA source code 3310 into HIP source code 3330 and then compiles the HIP source code 3330 for execution on the CPU 3390 and a CUDA-enabled GPU 3394. In at least one embodiment, the CUDA / HCC flow converts CUDA source code 3310 into HIP source code 3330 and then compiles the HIP source code 3330 for execution on the CPU 3390 and a GPU 3392.

[0305] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3350 receives a CUDA source code 3310 and a CUDA compile command 3348 that configures the CUDA compiler 3350 to compile the CUDA source code 3310. In at least one embodiment, the CUDA source code 3310 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3348, the CUDA compiler 3350 generates a host executable code 3370 (1) and a CUDA device executable code 3384 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3370 (1) and the CUDA device executable code 3384 can be executed on a CPU 3390 and a CUDA-enabled GPU 3394, respectively. In at least one embodiment, the CUDA device executable code 3384 includes but is not limited to binary code. In at least one embodiment, the CUDA device executable code 3384 includes but is not limited to PTX code and is further compiled into binary code for a specific target device at runtime.

[0306] The indirect CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and a series of bubble notes B1-B6. In at least one embodiment and as indicated by bubble note B1, CUDA to HIP conversion tool 3320 receives CUDA source code 3310. In at least one embodiment and as indicated by bubble note B2, CUDA to HIP conversion tool 3320 converts CUDA source code 3310 into HIP source code 3330. In at least one embodiment and as indicated by bubble note B3, HIP compiler driver 3340 receives HIP source code 3330 and determines whether target device 3346 is CUDA-enabled.

[0307] In at least one embodiment and as indicated by bubble note B4, the HIP compiler driver 3340 generates HIP / NVCC compile commands 3342 and sends both the HIP / NVCC compile commands 3342 and the HIP source code 3330 to the CUDA compiler 3350. Figure 33B As described in more detail, the HIP / NVCC compile command 3342 configures the CUDA compiler 3350 to compile the HIP source code 3330 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3342, the CUDA compiler 3350 generates host executable code 3370 (1) and CUDA device executable code 3384 (indicated by bubble note B5). In at least one embodiment and as indicated by bubble note B6, the host executable code 3370 (1) and the CUDA device executable code 3384 can be executed on a CPU 3390 and a CUDA-enabled GPU 3394, respectively. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0308] The CUDA / HCC process that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as indicated by bubble comment C1, a CUDA to HIP conversion tool 3320 receives CUDA source code 3310. In at least one embodiment and as indicated by bubble comment C2, the CUDA to HIP conversion tool 3320 converts the CUDA source code 3310 into HIP source code 3330. In at least one embodiment and as indicated by bubble comment C3, a HIP compiler driver 3340 receives the HIP source code 3330 and determines that the target device 3346 is not CUDA-enabled.

[0309] In at least one embodiment, the HIP compiler driver 3340 generates HIP / HCC compile commands 3344 and sends both the HIP / HCC compile commands 3344 and the HIP source code 3330 to the HCC 3360 (indicated by bubble comment C4). Figure 33C As described in more detail, HIP / HCC compile command 3344 configures HCC 3360 to compile HIP source code 3330 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3344, HCC 3360 generates host executable code 3370(2) and HCC device executable code 3382 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3370(2) and HCC device executable code 3382 can be executed on CPU 3390 and GPU 3392, respectively.

[0310] In at least one embodiment, after converting the CUDA source code 3310 to the HIP source code 3330, the HIP compiler driver 3340 can then be used to generate executable code for the CUDA-enabled GPU 3394 or GPU 3392 without having to re-implement the CUDA to HIP conversion tool 3320. In at least one embodiment, the CUDA to HIP conversion tool 3320 converts the CUDA source code 3310 to the HIP source code 3330, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3340 then configures the HCC 3360 to generate a host executable code 3370 (2) and an HCC device executable code 3382 based on the HIP source code 3330. In at least one embodiment, the HIP compiler driver 3340 then configures the CUDA compiler 3350 to generate a host executable code 3370 (1) and a CUDA device executable code 3384 based on the stored HIP source code 3330.

[0311] Figure 33B 3390 and a CUDA-enabled GPU 3394 configured to compile and execute Figure 33A In at least one embodiment, the system 3304 includes, but is not limited to, the CUDA source code 3310, a CUDA to HIP conversion tool 3320, a HIP source code 3330, a HIP compiler driver 3340, a CUDA compiler 3350, a host executable 3370(1), a CUDA device executable 3384, a CPU 3390, and a CUDA-enabled GPU 3394.

[0312] In at least one embodiment and as previously incorporated herein Figure 33A As depicted, CUDA source code 3310 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, CUDA source code 3310 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0313] In at least one embodiment, the CUDA to HIP conversion tool 3320 converts the CUDA source code 3310 into HIP source code 3330. In at least one embodiment, the CUDA to HIP conversion tool 3320 converts each kernel call in the CUDA source code 3310 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3310 into any number of other functionally similar HIP calls.

[0314] In at least one embodiment, the HIP compiler driver 3340 determines that the target device 3346 is CUDA-enabled and generates HIP / NVCC compile commands 3342. In at least one embodiment, the HIP compiler driver 3340 then configures the CUDA compiler 3350 via the HIP / NVCC compile commands 3342 to compile the HIP source code 3330. In at least one embodiment, as part of configuring the CUDA compiler 3350, the HIP compiler driver 3340 provides access to a HIP to CUDA translation header 3352. In at least one embodiment, the HIP to CUDA translation header 3352 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3350 uses the HIP to CUDA translation header 3352 in conjunction with a CUDA runtime library 3354 corresponding to the CUDA runtime API 3302 to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, the host executable code 3370(1) and the CUDA device executable code 3384 can then be executed on the CPU 3390 and the CUDA-enabled GPU 3394, respectively. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0315] Figure 33C A system 3306 is shown that is configured to compile and execute using a CPU 3390 and a non-CUDA enabled GPU 3392 according to at least one embodiment. Figure 33A CUDA source code 3310. In at least one embodiment, system 3306 includes, but is not limited to, CUDA source code 3310, CUDA to HIP conversion tool 3320, HIP source code 3330, HIP compiler driver 3340, HCC 3360, host executable code 3370(2), HCC device executable code 3382, CPU 3390, and GPU 3392.

[0316] In at least one embodiment, and as previously incorporated herein Figure 33AAs depicted, CUDA source code 3310 includes, but is not limited to, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, CUDA source code 3310 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0317] In at least one embodiment, the CUDA to HIP conversion tool 3320 converts the CUDA source code 3310 into HIP source code 3330. In at least one embodiment, the CUDA to HIP conversion tool 3320 converts each kernel call in the CUDA source code 3310 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3310 into any number of other functionally similar HIP calls.

[0318] In at least one embodiment, the HIP compiler driver 3340 then determines that the target device 3346 is not CUDA-enabled and generates HIP / HCC compile commands 3344. In at least one embodiment, the HIP compiler driver 3340 then configures the HCC 3360 to execute the HIP / HCC compile commands 3344, thereby compiling the HIP source code 3330. In at least one embodiment, the HIP / HCC compile commands 3344 configure the HCC 3360 to use, but are not limited to, the HIP / HCC runtime library 3358 and the HCC header 3356 to generate host executable code 3370(2) and HCC device executable code 3382. In at least one embodiment, the HIP / HCC runtime library 3358 corresponds to the HIP runtime API 3332. In at least one embodiment, the HCC header 3356 includes, but is not limited to, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3370(2) and HCC device executable code 3382 may execute on CPU 3390 and GPU 3392, respectively.

[0319] Figure 34 According to at least one embodiment, Figure 33C33. Example kernel converted by CUDA to HIP conversion tool 3320. In at least one embodiment, CUDA source code 3310 divides the overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in a cooperative manner. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0320] In at least one embodiment, the CUDA source code 3310 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads, and the grid includes, but is not limited to, an arbitrary number of thread blocks.

[0321] In at least one embodiment, a kernel is a function in device code defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 3410 is used to specify the size of the grid on which the kernel is executed and the associated streams for a given kernel call. In at least one embodiment, the CUDA kernel launch syntax 3410 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct that is inserted between the kernel name ("KernelName") and the bracketed list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3410 includes, but is not limited to, CUDA launch function syntax rather than execution configuration syntax.

[0322] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel is given a unique thread ID that can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0323] In at least one embodiment, with respect to CUDA kernel launch syntax 3410, "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 3410, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 3410, "stream" is an optional parameter that specifies the associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands that are executed in order (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0324] In at least one embodiment, the CUDA source code 3310 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code that executes on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x 16 and the numBlocks variable as N / 16xN / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 3410, kernel MatAdd is executed using a grid of thread blocks of size N / 16×N / 16, where each thread block has a size of 16×16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes kernel MatAdd to perform one pairwise addition.

[0325] In at least one embodiment, while converting CUDA source code 3310 to HIP source code 3330, CUDA-to-HIP conversion tool 3320 converts each kernel call in CUDA source code 3310 from CUDA kernel launch syntax 3410 to HIP kernel launch syntax 3420, and converts any number of other CUDA calls in source code 3310 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3420 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, SharedMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 3420 as in CUDA kernel launch syntax 3410 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in the HIP kernel launch syntax 3420 and optional in the CUDA kernel launch syntax 3410.

[0326] In at least one embodiment, in addition to the kernel call to cause the kernel MatAdd to execute on the device, Figure 34 A portion of the HIP source code 3330 depicted in Figure 34 3310 is the same as a portion of the CUDA source code 3310 depicted in FIG. In at least one embodiment, kernel MatAdd is defined in HIP source code 3330 with the same “__global__” declaration specifier as kernel MatAdd is defined in CUDA source code 3310. In at least one embodiment, the kernel call in HIP source code 3330 is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while the corresponding kernel call in CUDA source code 3310 is “MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);".

[0327] Figure 35 More details are shown according to at least one embodiment. Figure 33C 3392. In at least one embodiment, the GPU 3392 is developed by Advanced Micro Devices, Inc. of Santa Clara, NC. In at least one embodiment, the GPU 3392 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3392 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3392 is configured to perform operations unrelated to graphics. In at least one embodiment, the GPU 3392 is configured to perform both graphics-related operations and graphics-unrelated operations. In at least one embodiment, the GPU 3392 can be configured to execute device code included in the HIP source code 3330.

[0328] In at least one embodiment, the GPU 3392 includes, but is not limited to, any number of programmable processing units 3520, a command processor 3510, an L2 cache 3522, a memory controller 3570, a DMA engine 3580(1), a system memory controller 3582, a DMA engine 3580(2), and a GPU controller 3584. In at least one embodiment, each programmable processing unit 3520 includes, but is not limited to, a workload manager 3530 and any number of compute units 3540. In at least one embodiment, the command processor 3510 reads commands from one or more command queues (not shown) and dispatches the commands to the workload manager 3530. In at least one embodiment, for each programmable processing unit 3520, the associated workload manager 3530 dispatches work to the compute units 3540 included in the programmable processing unit 3520. In at least one embodiment, each compute unit 3540 can execute any number of thread blocks, but each thread block executes on a single compute unit 3540. In at least one embodiment, a work group is a thread block.

[0329] In at least one embodiment, each compute unit 3540 includes, but is not limited to, any number of SIMD units 3550 and shared memory 3560. In at least one embodiment, each SIMD unit 3550 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each SIMD unit 3550 includes, but is not limited to, a vector ALU 3552 and a vector register file 3554. In at least one embodiment, each SIMD unit 3550 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3560.

[0330] In at least one embodiment, programmable processing units 3520 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3520 includes, but is not limited to, any number of specialized graphics hardware in addition to compute units 3540. In at least one embodiment, each programmable processing unit 3520 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 3530, and any number of compute units 3540.

[0331] In at least one embodiment, the compute units 3540 share an L2 cache 3522. In at least one embodiment, the L2 cache 3522 is partitioned. In at least one embodiment, all compute units 3540 in a GPU 3392 can access GPU memory 3590. In at least one embodiment, a memory controller 3570 and a system memory controller 3582 facilitate data transfers between the GPU 3392 and a host, and a DMA engine 3580(1) enables asynchronous memory transfers between the GPU 3392 and the host. In at least one embodiment, a memory controller 3570 and a GPU controller 3584 facilitate data transfers between the GPU 3392 and other GPUs 3392, and a DMA engine 3580(2) enables asynchronous memory transfers between the GPU 3392 and other GPUs 3392.

[0332] In at least one embodiment, the GPU 3392 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components within or external to the GPU 3392. In at least one embodiment, the GPU 3392 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, the GPU 3392 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, the GPU 3392 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3570 and system memory controller 3582) and memory devices (e.g., shared memory 3560) that are dedicated to a component or shared between multiple components. In at least one embodiment, GPU3392 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3522), each of which can be private or shared among any number of components (e.g., SIMD units 3550, compute units 3540, and programmable processing units 3520).

[0333] Figure 36 shows how threads of an exemplary CUDA grid 3620 are mapped to Figure 353640. In at least one embodiment, and for illustration purposes only, the grid 3620 has a GridSize of BX times BY times 1 and a BlockSize of TX times TY times 1. Thus, in at least one embodiment, the grid 3620 includes, but is not limited to, (BX*BY) thread blocks 3630, and each thread block 3630 includes, but is not limited to, (TX*TY) threads 3640. Threads 3640 are Figure 36 Depicted as a curved arrow.

[0334] In at least one embodiment, the grid 3620 is mapped to the programmable processing units 3520(1), which include, but are not limited to, compute units 3540(1)-3540(C). In at least one embodiment and as shown, the (BJ*BY) thread blocks 3630 are mapped to compute unit 3540(1), and the remaining thread blocks 3630 are mapped to compute unit 3540(2). In at least one embodiment, each thread block 3630 may include, but are not limited to, any number of warps, and each warp is mapped to Figure 35 Different SIMD units 3550.

[0335] In at least one embodiment, the warps in a given thread block 3630 may synchronize together and communicate via shared memory 3560 included in the associated compute unit 3540. For example, and in at least one embodiment, the warps in thread block 3630(BJ, 1) may synchronize together and communicate via shared memory 3560(1). For example, and in at least one embodiment, the warps in thread block 3630(BJ+1, 1) may synchronize together and communicate via shared memory 3560(2).

[0336] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0337] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. Unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0338] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to generally refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to plurality (e.g., "a plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0339] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0340] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system comprising multiple devices operating in different ways such that the distributed computer system performs the operations described herein and such that no single device performs all of the operations.

[0341] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0342] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0343] In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0344] Unless expressly stated otherwise, it is understood that throughout this specification, terms such as “process,” “calculate,” “compute,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0345] In a similar manner, the term "processor" may refer to any device or portion of a memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As non-limiting examples, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process may refer to multiple processes to execute instructions continuously or intermittently, sequentially, or in parallel. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0346] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, a computer system, or a computer-implemented machine. The process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0347] Although the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. In addition, although specific responsibilities are defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0348] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A machine-readable medium having stored thereon an application programming interface (API), said API, if executed by one or more processors, causing said one or more processors to at least: Based in part on a request to the API to wait until output from one or more second threads is available in shared memory, blocking one or more first instructions of a first thread while processing one or more second instructions of the first thread, wherein The one or more first instructions of the first thread are dependent on the output of the one or more second threads, and the one or more second instructions of the first thread are not dependent on the output of the one or more second threads.

2. The machine-readable medium of claim 1 , wherein: said output from said one or more second threads is one or more shared data items; the one or more first instructions of the first thread being dependent on the one or more shared data items; the one or more second instructions of the first thread do not depend on the one or more shared data items; The one or more second instructions of the first thread make a first request to the API to copy one or more additional shared data items to the shared memory; and The one or more second instructions of the first thread make a second request to the API to wait until the one or more additional shared data items are available in shared memory. 3 . The machine-readable medium of claim 2 , wherein the one or more additional shared data items are copied from a first global memory for the first thread, and the one or more shared data items are copied from a second global memory for the second thread.

4. The machine-readable medium of claim 2 , wherein the one or more shared data items and the one or more additional shared data items are available in the shared memory when each of the one or more shared data items and each of the one or more additional shared data items have been loaded from the global memory and stored into the shared memory. 5 . The machine-readable medium of claim 2 , wherein the one or more first instructions of the first thread are executed upon receiving an indication from the API. 6 . The machine-readable medium of claim 5 , wherein the indication is generated by the API based at least in part on whether the one or more shared data items have been copied from global memory and stored in the shared memory.

7. The machine-readable medium of claim 1, wherein the output from the one or more second threads is available in the shared memory when one or more shared data items have been copied from global memory and stored in the shared memory.

8. The machine-readable medium of claim 1, wherein the application programming interface comprises one or more software function calls for executing parallel computing operations by the first thread and the one or more second threads on one or more parallel processing units.

9. A method comprising: Based at least in part on a request to an application programming interface (API) to wait until output from one or more second threads is available in a shared memory, blocking one or more first instructions of a first thread while processing one or more second instructions of the first thread, wherein the one or more first instructions of the first thread are dependent on the output of the one or more second threads and the one or more second instructions of the first thread are not dependent on the output of the one or more second threads.

10. The method according to claim 9, wherein: the output from the one or more second threads being available in the shared memory when the one or more first shared data items have been copied to the shared memory by the one or more second threads; When a first indication is generated by the API, the one or more first instructions of the first thread use the one or more first shared data items; The one or more second instructions of the first thread submit one or more second shared data items to the API to be copied to the shared memory; as well as The one or more second instructions of the first thread await a second indication to be generated by the API. 11 . The method of claim 10 , wherein the first indication is generated by the API when the one or more first shared data items have been loaded from a global memory and stored into the shared memory. 12 . The method of claim 10 , wherein the second indication is generated by the API when the one or more second shared data items have been loaded from global memory and stored into the shared memory.

13. The method according to claim 10, wherein: The second thread submits one or more third data items to the API to be copied to the shared memory; and The second thread waits for a third indication generated by the API.

14. The method of claim 13, wherein the third indication is generated by the API when the one or more third data items have been copied from the global memory to the shared memory.

15. The method of claim 9, wherein the output from the one or more second threads is available in the shared memory when one or more shared data items have been copied from global memory and stored in the shared memory.

16. The method of claim 9, wherein the API comprises one or more software function interfaces that, when called by the first thread and the one or more second threads, perform parallel computing operations.

17. A system comprising: One or more processors configured to, based at least in part on a request to an application programming interface (API) to wait until output from one or more second threads is available in a shared memory, block one or more first instructions of a first thread while processing one or more second instructions of the first thread, wherein the one or more first instructions of the first thread are dependent on the output of the one or more second threads and the one or more second instructions of the first thread are not dependent on the output of the one or more second threads.

18. The system of claim 17, wherein: said output from said one or more second threads is one or more first shared data items; the one or more first instructions of the first thread being dependent on the one or more first shared data items; the one or more second instructions of the first thread do not depend on the one or more first shared data items; The one or more second instructions of the first thread make a first request to the API to copy one or more second shared data items to the shared memory; and The one or more second instructions of the first thread make a second request to the API to wait until the one or more second shared data items are available in shared memory.

19. The system of claim 18, wherein the one or more second shared data items are copied from a first global memory for the first thread, and the one or more first shared data items are copied from a second global memory for the second thread.

20. The system of claim 18, wherein the one or more first shared data items and the one or more second shared data items are available in the shared memory when each of the one or more first shared data items and each of the one or more second shared data items have been loaded from the global memory and stored into the shared memory.

21. The system of claim 17, wherein the API comprises one or more software function calls for executing parallel computing operations by the first thread and the one or more second threads on one or more parallel processing units.

22. The system of claim 17, wherein the output from the one or more second threads is available in the shared memory when one or more shared data items have been copied from global memory and stored in the shared memory.

23. A processor comprising: One or more circuits for performing one or more operations, the one or more operations blocking one or more first instructions of a first thread while processing one or more second instructions of the first thread based at least in part on a request to an application programming interface (API) to wait until output from one or more second threads is available in a shared memory, wherein the one or more first instructions of the first thread are dependent on the output of the one or more second threads, and the one or more second instructions of the first thread are not dependent on the output of the one or more second threads.

24. The processor of claim 23, wherein: the output from the one or more second threads being available in the shared memory when the one or more first shared data items have been copied to the shared memory by the one or more second threads; The one or more second instructions of the first thread submit one or more second shared data items to the API to be copied to the shared memory; When a first indication is generated by the API, the one or more first instructions of the first thread use the one or more first shared data items; as well as The one or more second instructions of the first thread await a second indication to be generated by the API.

25. The processor of claim 24, wherein the first indication is generated by the API when the one or more first shared data items have been loaded from global memory and stored into the shared memory.

26. The processor of claim 24, wherein the second indication is generated by the API when the one or more second shared data items have been loaded from global memory and stored into the shared memory.

27. The processor of claim 24, wherein: The second thread submits one or more third shared data items to the API to be copied to the shared memory; and The second thread waits for a third indication from the API, the indication being generated when each of the one or more third shared data items has been loaded from the global memory and stored in the shared memory.

28. The processor of claim 23, wherein the output from the one or more second threads is available in the shared memory when one or more shared data items have been copied from global memory and stored in the shared memory.

29. The processor of claim 23, wherein the API comprises one or more software function interfaces that, when called by the first thread and the one or more second threads, perform parallel computing operations.

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