Clock domain crossing synchronization circuit and method based on multi-phase clock

Abstract

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a multi-phase clock based cross-clock domain synchronization circuit and method. BACKGROUND

[0002] In a data transmission system, serial data and clock are sent by a transmitter (TX) to a receiver (RX), under the driving of an input clock, the RX converts the serial data into parallel data and sends the parallel data into a digital signal processor (DSP). However, since the clock of the DSP and the input clock of the RX circuit are asynchronous clocks, their frequencies are the same but their phase relationship is uncertain, so in order to enable the data to be correctly sampled by the DSP, the data and the clock of the DSP must be aligned, thereby realizing cross-clock domain transmission of the data.

[0003] At present, the traditional method is to use an asynchronous first-in-first-out memory (FIFO) to realize cross-clock domain transmission of the data, in the application process, the data is written into the FIFO under the driving of a first clock, and a write pointer (wptr) is incremented by one; the data is read out from the FIFO under the driving of a second clock, and a read pointer (rptr) is incremented by one. The size relationship between the wptr and the rptr is detected to ensure that the FIFO is not full or empty, so the data written into the FIFO is unchanged before being read out by the second clock, thereby realizing stable sampling of the cross-clock domain data.

[0004] As can be seen from the working principle of the FIFO, the data needs to be sampled once by the first clock when being written into the FIFO, and the data needs to be sampled once by the second clock when being read out from the FIFO, since the cross-clock domain transmission of the data occurs on parallel data, therefore using the FIFO will bring a large delay. Taking a 1to8 RX serial-to-parallel conversion as an example, the period of the parallel data is 8ui (unit time), therefore using the FIFO technology will bring a delay of at least 16ui, thereby failing to meet the application requirements of a Die to Die high-speed data transmission system.

[0005] Therefore, there is an urgent need for a cross-clock domain data transmission scheme with lower delay. SUMMARY

[0006] The embodiment of the present application provides a multi-phase clock based cross-clock domain synchronization circuit and method, to solve the problem of long delay time existing in the prior art data transmission scheme and the problem of failure to meet the high-speed data transmission requirements.

[0007] To achieve the above object, the present application provides a multi-phase clock based cross-clock domain synchronization circuit, comprising a selector, an asynchronous clock synchronization module and a digital signal processor; wherein, The serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is configured to output corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; The asynchronous clock synchronization module is configured to output corresponding alignment data to the digital signal processor according to the input RX parallel data, a clock of the digital signal processor, and the low-frequency clock; The asynchronous clock synchronization module is configured to perform phase alignment between the RX parallel data and the clock of the digital signal processor. The digital signal processor is configured to perform data processing on the alignment data.

[0008] In addition, an optional technical solution is that the low-frequency clock is obtained based on a TX transmitted clock; wherein the TX transmitted clock is frequency-divided to obtain a low-frequency clock with a corresponding phase number, and the low-frequency clock is input into the selector.

[0009] In addition, an optional technical solution is that the asynchronous clock synchronization module comprises a first flip-flop array, a second flip-flop array, a third flip-flop array, a delay element array, a first selector array, a second selector, and a logic gate. The delay element array is connected with the second flip-flop array. The first flip-flop array and the second flip-flop array are respectively connected with input ends of the first selector array. An output end of the first selector array is connected with the logic gate. An output end of the logic gate is connected with the second selector. The second selector is connected with the third flip-flop array, and the alignment data is output through the third flip-flop array.

[0010] In addition, an optional technical solution is that the low-frequency clock is respectively input into the first flip-flop array, the second selector, and the second flip-flop array after being processed through the delay element array. A clock of the digital signal processor is respectively input into the first flip-flop array and the second flip-flop array. The RX parallel data is input into the third flip-flop array.

[0011] In addition, an optional technical solution is that an output signal of the logic gate is a one-hot code generated according to an output signal of the first selector array; wherein the one-hot code is respectively input into the second selector and input into the first selector array after being processed.

[0012] In addition, an optional technical solution is that the clock of the digital signal processor and the low-frequency clock have the same frequency.

[0013] Further, the optional technical solution is that the low-frequency clock is sampled by a clock of the digital signal processor to obtain a selection signal; wherein, when the selection signal sel <n>= 0, select signal sel <n-1>When the value of the parameter is 1, the RX parallel data is sampled and aligned using the nth bit of the low-frequency clock; n is the number of bits of the low-frequency clock.

[0014] In another aspect, the application further provides a multi-phase clock-based cross-clock domain synchronization method, which uses the above-mentioned multi-phase clock-based cross-clock domain synchronization circuit to synchronously transmit serial data to be transmitted; wherein the method comprises: inputting the serial data to be transmitted and a low-frequency clock into a selector, and inputting the low-frequency clock into an asynchronous clock synchronization module; acquiring RX parallel data corresponding to the serial data through the selector and sending the RX parallel data to the asynchronous clock synchronization module; aligning the RX parallel data with the clock of a digital signal processor based on the asynchronous clock synchronization module, acquiring aligned data and sending the aligned data to the digital signal processor; processing the aligned data through the digital signal processor.

[0015] In addition, the optional technical solution is that a selection signal is obtained by sampling the low-frequency clock through the clock of the digital signal processor; wherein when the selection signal sel <n>= 0, select signal sel <n-1>When the value is 1, the RX parallel data is sampled and aligned using the nth bit of the low-frequency clock; n is the number of bits of the low-frequency clock.

[0016] In addition, the optional technical solution further comprises: delaying the nth bit low-frequency clock to obtain a corresponding delayed clock signal; The delayed clock signal is sampled by the clock of the digital signal processor to ensure that the selection signal sel <n-1>is 1; The delayed time is greater than jitter of the clock of the digital signal processor.

[0017] The multi-phase clock based cross-clock domain synchronization circuit and method provided by the application can perform phase alignment between RX parallel data and the clock of the digital signal processor based on the asynchronous clock synchronization module, obtain aligned data and send the aligned data to the digital signal processor, effectively reduce the delay time, and be applicable to various types of serial-parallel conversion circuits.

[0018] To achieve the above and related purposes, one or more aspects of the application include specific features that will be described in detail later and particularly pointed out in the claims. The following description and drawings detail certain exemplary aspects of the application. However, these aspects indicate only some of the various ways in which the principles of the application can be used. In addition, the application is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a structural schematic diagram of a multi-phase clock based cross-clock domain synchronization circuit according to an embodiment of the application; Figure 2 is a circuit structure schematic diagram of an asynchronous clock synchronization module according to an embodiment of the application; Figure 3 is a timing diagram of a multi-phase clock based cross-clock domain synchronization circuit according to an embodiment of the application; Figure 4 is a flowchart of a multi-phase clock based cross-clock domain synchronization method according to an embodiment of the application.

[0020] Reference signs: first flip-flop array 1, second flip-flop array 2, third flip-flop array 3, delay element array 4, second selector 5, first selector array 6, logic gate 7.

[0021] The implementation of the application, functional features and advantages will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the application will be described below with reference to the drawings in the embodiments of the application. In the description of the embodiments of the application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this document only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone.

[0023] In the embodiments of the present application, "a plurality of" means two or more than two, unless otherwise specified. "At least one of the following" or similar expressions means any combination of the items, including any combination of single item or multiple items. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the same items or similar items with basically the same function and role are distinguished by using "first", "second", etc. The person skilled in the art can understand that "first", "second", etc. do not limit the quantity and execution order, and "first", "second", etc. also do not necessarily mean different.

[0024] At the same time, in the embodiments of the present application, "exemplary" or "for example" and the like are used to represent as an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. On the contrary, "exemplary" or "for example" and the like are used to present the relevant concept in a specific manner, for the convenience of understanding.

[0025] In view of the problem that the existing technology has a long delay and cannot meet the demand of high-speed data transmission, the present application provides a multi-phase clock-based cross-clock domain synchronization circuit and method, which does not need to write data into a FIFO and then read it out, can effectively reduce the delay of data transmission, and can be applied to various types of serial-parallel conversion circuits.

[0026] The technical solutions of the present application will be described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor fall within the scope of protection of the present application.

[0027] Specifically, Figure 1 The schematic circuit structure of the multi-phase clock-based cross-clock domain synchronization circuit according to the embodiments of the present application is shown.

[0028] As Figure 1 shown, the multi-phase clock-based cross-clock domain synchronization circuit according to the embodiments of the present application includes a selector, an asynchronous clock synchronization module and a digital signal processor. The serial data to be transmitted and the low-frequency clock are both input into the selector, so that the selector outputs corresponding RX parallel data according to the serial data and the low-frequency clock. Since the clock of the low-frequency clock and the digital signal processor is asynchronous, the frequencies of the two are the same but the phase relationship is not determined. Therefore, in order to enable the data to be correctly sampled by the digital signal processor, the RX parallel data and the clock of the digital signal processor need to be aligned.

[0029] To this end, in the application, the obtained RX parallel data and low frequency clock are input into an asynchronous clock synchronization module, and the asynchronous clock synchronization module outputs corresponding aligned data to a digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low frequency clock; in the process, the RX parallel data is phase-aligned with the clock of the digital signal processor by the asynchronous clock synchronization module, so that the digital signal processor can correctly sample and realize relevant data processing on the aligned data.

[0030] The low frequency clock can be obtained based on the clock transmitted by the TX, the clock transmitted by the TX is frequency-divided (8 frequency division), the low frequency clock corresponding to the phase number is obtained, and the low frequency clock is input into the selector (1:8).

[0031] Specifically, as shown in Figure 1 The data represents serial data to be transmitted by the TX, the clock represents the clock transmitted by the TX, the clock transmitted by the TX is frequency-divided, for example, 8 frequency division is performed to obtain 8-phase low frequency clock ck8t<7:0>, under the driving of the low frequency clock ck8t<7:0>, the serial data data is converted into 8-way low-speed parallel data d8t<7:0> (i.e. RX parallel data), and the parallel data d8t<7:0> is further aligned with the clock ck_dig of the digital signal processor (DSP) after passing through the asynchronous clock synchronization module (async clock align), to obtain aligned data d8t_dig<7:0>, and is sent to the DSP.

[0032] Figure 2 The schematic circuit structure of the asynchronous clock synchronization module according to the embodiment of the application is shown, Figure 3 The synchronization timing diagram of the cross-clock-domain synchronization circuit based on the multi-phase clock according to the embodiment of the application is shown.

[0033] As 1 to Figure 3 As shown, the asynchronous clock synchronization module of the embodiment of the application further comprises: a first flip-flop array 1 (x8 means comprising 8 first flip-flops), a second flip-flop array 2 (x8 means comprising 8 second flip-flops), a third flip-flop array 3 (x8 means comprising 8 third flip-flops), a delay array 4 (x8 means comprising 8 delays), a first selector array 6 (x8 means comprising 8 first selectors), a second selector 5 and a logic gate 7 (x8 means comprising 8 logic gates); wherein the delay array 4 is connected with the second flip-flop array 2; the first flip-flop array 1 and the second flip-flop array 2 are respectively connected with the input end of the first selector array 6; the output end of the first selector array 6 is connected with the logic gate; the output end of the logic gate 7 is connected with the second selector 5; the second selector 5 is connected with the third flip-flop array 3, and finally outputs the processed aligned data through the third flip-flop array 3.

[0034] Wherein, the low frequency clock ck8t<7:0> is input into the first flip-flop array 1, input into the second selector 5, and input into the second flip-flop array 2 after delay processing through the delay array 4; the clock ck_dig of the digital signal processor is input into the first flip-flop array 1 and the second flip-flop array 2, and the RX parallel data d8t<7:0> is input into the third flip-flop array 3.

[0035] In addition, the output signal of the logic gate is a one-hot code generated according to the output signal of the first selector array; wherein the one-hot code is input into the second selector and input into the first selector array after processing.

[0036] Specifically, the RX parallel data ck8t<7:0> is sampled by the clock ck_dig of the digital signal processor to obtain the selection signal sel<7:0>, wherein sel<7> is obtained by sampling ck8t<7> by ck_dig, sel<6> is obtained by sampling ck8t<0> by ck_dig, and so on. Since ck8t<7:0> is an 8-phase clock, the difference between adjacent two phases is 1ui (unit time), so there are 4 continuous 0s and 4 continuous 1s in sel<7:0>, and there is only one change edge from 0 to 1.

[0037] Wherein, the output signal of the first selector array 6 is Figure 3 For example, sel<6> is 0 and sel<5> is 1, so it can be determined that the rising edge of ck_dig is between the falling edge of ck8t<6> and the falling edge of ck8t<5>. In order to enable the data to be correctly sampled by ck_dig, the data is first sampled using the falling edge of ck8t<6>, wherein the RX parallel data d8t<7:0> is originally aligned with the rising edge of ck8t<7>, and the data is sampled using the rising edge of ck8t<6> here, and the aligned data d8t_dig<7:0> obtained is aligned with the rising edge of ck8t<6>. In this case, the rising edge of the clock ck_dig of the digital signal processor is located in the middle of the aligned data, and the timing degree is also the largest at this time, so the phase relationship between the data and ck_dig can be determined. At this time, the aligned data is sent to the DSP, and when the data is sampled by ck_dig, there is sufficient margin for the setup time and the hold time, so that the cross-clock-domain propagation of the data is realized.

[0038] It should be noted that the above sel<6> and sel<5> are only specific examples given for ease of description, and in actual application, sel <n>= 0, sel <n-1>If the value is 1, then use ck8t <n>The data is sampled to align, where n is a positive integer (in the example shown, n ranges from 0 to 7).

[0039] As a specific example, d8t<7:0> represents 8 parallel data of 8 ui width, ck8t<7:0> represents 8 clocks of 8 ui period, the interval between every two adjacent clocks is 1 ui, and ck_dig represents a clock of 8 ui period transmitted by the DSP, where ck_dig and ck8t<7:0> are asynchronous clocks, have the same frequency but an uncertain phase relationship.

[0040] In addition, sel_onehot<7:0> represents a one-hot code, that is, only one bit is 1 and the other 7 bits are 0 at a time. sel_onehot<7:0> represents 8 signals, which respectively control one two-way MUX (i.e., the first selector array). ck_dig samples ck8t<7:0> through the first flip-flop array 1, and the sampling result is connected to the 0 end of the two-way MUX (when the control signal is 0, the MUX outputs the signal of the port). ck8t<7:0> passes through a delay array, i.e., a delay module, to obtain ck8t_delay<7:0>, and ck_dig samples ck8t_delay<7:0> through the second flip-flop array, and the sampling result is connected to the 1 end of the two-way MUX (when the control signal is 1, the MUX outputs the signal of the port).

[0041] In addition, without loss of generality, it is assumed that initially sel_onehot<7:0> are all 0, so the signal output from the 0 end of the first selector array MUX, i.e., sel<7:0>, is the sampling result of ck_dig on ck8t<7:0>. It is assumed that at this time the phase relationship of the asynchronous clocks is Figure 3 As shown, at this time ck_dig samples ck8t<7:6> and ck8t<1:0> to be 0, and ck8t<5:2> to be 1, so sel<7:6> and sel<1:0> are 0, and sel<5:2> is 1. That is, sel<7:0> is 8’b00111100, and sel<6:0,7> is 8’b01111000. Therefore, after passing through a one-end inverting logic gate, i.e., an AND gate, only sel_onehot<6> is 1, and sel_onehot<7> and sel_onehot<5:0> are all 0. At this time, sel_onehot<7:0> is 8’b01000000, and sel_onehot<0,7:1> is 8’b00100000. Thus, the 5th two-way MUX outputs the signal of the 1 end, and the other 7 two-way MUXs still output the signal of the 0 end, thereby realizing the processing of the metastable state.

[0042] The signal sel<6:0,7> = 8' b01111000 is defined by splicing: the high 7 bits are <6:0> (that is, bit6 to bit0) of the original signal, and the lowest bit (bit0) is bit7 of the original signal; according to the assignment 8' b01111000, it can be known that bit7 to bit1 of the spliced signal correspond to <6:0> of the original signal, and the value is 0111100; bit0 of the spliced signal corresponds to bit7 of the original signal, and the value is 0.

[0043] In addition, sel_onehot<7:0> also serves as a control signal of an eight-to-one MUX (second selector), which output signal of which port is output by the eight-to-one MUX according to which bit of sel_onehot<7:0> is 1; at this time, sel_onehot<6> is 1, so the eight-to-one MUX outputs ck8t<6>, that is, ck8t<6> drives the third flip-flop array dff to sample the input d8t<7:0> parallel data to obtain d8t_dig<7:0>, so that the data is aligned with the ck_dig clock, and the cross-clock-domain data synchronization is completed.

[0044] In the cross-clock-domain synchronization circuit based on multiple-phase clocks in the embodiment of the application, the selection signal is obtained by sampling a low-frequency clock by using a clock of a digital signal processor; wherein when the selection signal sel <n>= 0, select signal sel <n-1>When the value is 1, the n-th bit of the low-frequency clock is sampled and aligned by using the clock of the digital signal processor, which can also be understood as sampling and aligning the RX parallel data by the n-th bit of the low-frequency clock; n is the number of bits of the low-frequency clock.

[0045] In addition, in order to ensure the accuracy and reliability of data transmission, the metastability problem caused by clock jitter needs to be further considered, and according to the timing diagram shown in the accompanying drawings of the present application, Figure 3 As can be seen from the timing diagram, when ck_dig just samples the falling edge of ck8t<5>, the jitter of ck_dig will cause the sampling time to jitter, so that the sel<5> obtained by sampling will jitter between 0 and 1, and the clock of the selected alignment data will jitter between ck8t<6> and ck8t<5>, thereby reducing the timing margin of the data and even causing data errors.

[0046] Therefore, in order to avoid the metastability problem, in the specific embodiments of the present application, when sel<6> is 0 and sel<5> is 1, the original sel<5> is obtained by sampling ck8t<5> by ck_dig, and is changed to sel<5> obtained by sampling ck8t_delay<5> by ck_dig, ck8t_delay<5> is obtained by ck8t<5> through delay processing, and the delay time needs to be greater than the jitter time. At this time, even if ck_dig jitters due to jitter, sel<5> still remains 1, so that the selected clock will not jitter. When the phase of ck_dig changes and sel<5> becomes 0, the selected clock will become ck8t<5> at this time, sel<5> will be obtained by sampling ck8t<5> by ck_dig again, and sel<4> will be obtained by sampling ck8t_delay<4> by ck_dig, so that the jitter of ck_dig will not cause the metastability problem.

[0047] It should be noted that according to different application scenarios and requirements, part of the modules or devices in the circuit can be replaced without changing the working principle of the cross-clock domain synchronization circuit based on the multi-phase clock of the present application, for example, the above-mentioned flip-flops can be selected as rising edge sampling or falling edge sampling dff, or high-level conduction latch or low-level conduction latch; the implementation mode of the delay line array can include inverters, buffers, transmission gates, delay lines, etc., and the selector can adopt various structures such as transmission gates and tri-state gates.

[0048] In addition, the logic for generating sel_onehot<7:0> through signals sel<7:0> and sel<6:0,7> is not limited to the "AND gate" (logic gate) shown in the accompanying drawings, and the logic satisfying the following truth table Table 1 is also within the scope of the present application.

[0049] Table 1

[0050] Further, in the above-described embodiment of the multi-phase clock-based cross-clock domain synchronization circuit according to the present application, when sel <n>= 0 and sel <n-1>For 1, select ck8t <n>Synchronizing data, it should be noted that by other deformation methods but essentially by the technical solution of identifying the jump of the sampling results of two adjacent, one or more sampling points apart, such as sel <n>= 1 and sel <n-1>= 0; or sel <n>= 0 and sel <n-1>sel <n+1> is 1 ; or sel <n+1> is 0 and sel <n-1>=1, or sel<n+1> =1 and sel <n-1>= 0, according to the actual circuit requirements, except for the selection of ck8t <n>In addition to the above, other phase clocks can be selected.

[0051] In addition, the circuit structure of the embodiment of the present application is not only applicable to 1 to 8 serial-to-parallel circuits, but also applicable to all 1 to N (N is a positive integer) serial-to-parallel circuits.

[0052] Corresponding to the above-mentioned multi-phase clock-based cross-clock domain synchronization circuit, the present application also provides a multi-phase clock-based cross-clock domain synchronization method, which synchronously transmits the serial data to be transmitted by using the above-mentioned multi-phase clock-based cross-clock domain synchronization circuit.

[0053] Specifically, the multi-phase clock-based cross-clock domain synchronization method according to the embodiment of the present application at least includes the following steps: S100: input the serial data to be transmitted and the low-frequency clock into the selector, and input the low-frequency clock into the asynchronous clock synchronization module; S200: obtain the RX parallel data corresponding to the serial data by the selector, and send the RX parallel data to the asynchronous clock synchronization module; S300: perform phase alignment between the RX parallel data and the clock of the digital signal processor based on the asynchronous clock synchronization module, obtain the aligned data, and send the aligned data to the digital signal processor; S400: perform data processing on the aligned data by the digital signal processor.

[0054] wherein the low-frequency clock is sampled by the clock of the digital signal processor to obtain the selection signal; wherein when the selection signal sel <n>= 0, select signal sel <n-1>When the value is 1, the RX parallel data is sampled and aligned by the n-th bit of the low-frequency clock; n is the number of bits of the low-frequency clock.

[0055] In addition, the multi-phase clock-based cross-clock domain synchronization method can further include delaying the n-th bit low-frequency clock to obtain a corresponding delayed clock signal; sampling the delayed clock signal by a clock of the digital signal processor to ensure that the selection signal sel <n-1>is 1; and the time of the delay is greater than the jitter of the clock of the digital signal processor, ensuring the reliability of the sampling.

[0056] In particular, as Figure 4 As shown in the flow, first, it is judged whether the signal ck8t <n>whether selected as sync data, if not, directly sample ck8t through ck_dig without considering jitter <n-1>obtaining a selection signal sel <n-1>, if so, sample ck8t_delay by ck_dig <n-1>obtaining a selection signal sel <n-1>Then, it is judged whether the signal satisfies sel <n>= 0 and sel <n-1>= 1, if yes then select ck8t <n>The synchronous data is aligned with the ck_dig signal and transmitted, and the step is executed in a loop to complete the synchronous transmission of all data.

[0057] It should be noted that the embodiment of the multi-phase clock based cross-clock domain synchronization method can refer to the specific description in the embodiment of the multi-phase clock based cross-clock domain synchronization circuit, which will not be repeated here.

[0058] According to the multi-phase clock based cross-clock domain synchronization circuit provided by the application, the serial data and the clock transmitted by the transmitter are input into the asynchronous clock synchronization module after being processed by the selector and the frequency divider, the parallel data obtained by the processing are phase-aligned with the clock of the digital signal processor through the asynchronous clock synchronization module, and the aligned data obtained are transmitted to the digital signal processor for synchronous sampling processing. The circuit structure is simple, the delay time can be effectively reduced, and the circuit can be applied to various types of serial-parallel conversion circuits.

[0059] The multi-phase clock based cross-clock domain synchronization circuit and method according to the application are described above with reference to the accompanying drawings by way of example. However, those skilled in the art should understand that various improvements can be made to the multi-phase clock based cross-clock domain synchronization circuit and method according to the application without departing from the content of the application. Therefore, the protection scope of the application should be determined by the content of the appended claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A cross-clock domain synchronization circuit based on a multi-phase clock, characterized in that, It includes a selector, an asynchronous clock synchronization module, and a digital signal processor; among which, The serial data to be transmitted and the low-frequency clock are input into the selector, and the selector is used to output the corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock. The asynchronous clock synchronization module is used to output corresponding alignment data to the digital signal processor based on the input RX parallel data, the clock of the digital signal processor, and the low-frequency clock. The asynchronous clock synchronization module is used to phase-align the RX parallel data with the clock of the digital signal processor. The digital signal processor is used to process the alignment data.

2. The cross-clock domain synchronization circuit based on multi-phase clocks as described in claim 1, characterized in that, The low-frequency clock is obtained based on the clock transmitted by TX; wherein, The clock transmitted by TX is divided to obtain a low-frequency clock with the corresponding number of phases, and the low-frequency clock is input into the selector.

3. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 1, characterized in that, The asynchronous clock synchronization module includes: a first flip-flop array, a second flip-flop array, a third flip-flop array, a delay array, a first selector array, a second selector, and logic gates; The delay array is connected to the second trigger array; The first trigger array and the second trigger array are respectively connected to the input terminals of the first selector array; The output of the first selector array is connected to the logic gate; The output of the logic gate is connected to the second selector; The second selector is connected to the third trigger array, and the alignment data is output through the third trigger array.

4. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 3, characterized in that, The low-frequency clock is input to the first trigger array, the second selector, and after being processed by the delay array, it is input to the second trigger array. The clock of the digital signal processor is input to the first flip-flop array and the second flip-flop array respectively; The RX parallel data is input to the third trigger array.

5. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 3, characterized in that, The output signal of the logic gate is a one-hot code generated based on the output signal of the first selector array; wherein the one-hot code is input to the second selector and, after processing, input to the first selector array.

6. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 3, characterized in that, The clock of the digital signal processor has the same frequency as the low-frequency clock.

7. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 1, characterized in that, A selection signal is obtained by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1> When the value is 1, the nth bit of the low-frequency clock is used to sample and align the RX parallel data; n is the number of bits in the low-frequency clock. < / n> 8. A cross-clock domain synchronization method based on a multi-phase clock, characterized in that, Synchronous transmission of serial data to be transmitted is performed using a cross-clock domain synchronization circuit of a multiphase clock as described in any one of claims 1 to 7; wherein the method includes: The serial data to be transmitted and the low-frequency clock are input into the selector, and the low-frequency clock is input into the asynchronous clock synchronization module; The selector acquires the RX parallel data corresponding to the serial data and sends it to the asynchronous clock synchronization module. The asynchronous clock synchronization module performs phase alignment between the RX parallel data and the clock of the digital signal processor, obtains the aligned data, and sends it to the digital signal processor. The alignment data is processed by the digital signal processor.

9. The cross-clock domain synchronization method based on multi-phase clocks as described in claim 8, characterized in that, A selection signal is obtained by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1>When the value is 1, the nth bit of the low-frequency clock is used to sample and align the RX parallel data; n is the number of bits in the low-frequency clock.< / n-1> < / n> 10. The cross-clock domain synchronization method based on multi-phase clocks as described in claim 9, characterized in that, Also includes: Delay the nth low-frequency clock bit to obtain the corresponding delayed clock signal; The delayed clock signal is sampled using the clock of the digital signal processor to ensure that the selection signal sel <n-1> =1;< / n-1> The delay time is greater than the clock jitter of the digital signal processor.

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