Display device

Abstract

The inventive concept relates to a display device. Specifically, a display device according to an embodiment of the inventive concept includes pixels, a scan driver, a data driver, an emission driver, and a timing controller, wherein the scan driver provides a first scan signal, a third scan signal, and a fourth scan signal at a first frequency and provides a second scan signal at a second frequency, the second frequency being a common divisor of the first frequency, the data driver provides data signals at the second frequency, and the emission driver provides emission control signals at the first frequency.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2020 - 0041664, filed on Apr. 6, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical field

[0003] The present inventive concept relates to a display device. Background art

[0004] Recently, various flat panel display devices capable of reducing weight and volume have been developed. The flat panel display devices include a liquid crystal display device, a field emission display device, a plasma display device, an organic light emitting display device, and the like.

[0005] The organic light emitting display device uses an organic light emitting diode to display an image, and in the organic light emitting diode, light is generated through the recombination of electrons and holes. The organic light emitting display device has advantages of a fast response speed and driving with low power consumption.

[0006] Such a display device includes a data driver that provides a data signal to a data line, a scan driver that sequentially provides a scan signal to a scan line, and a display area including a plurality of pixels connected to the scan line and the data line.

[0007] Pixels are selected when a scan signal is provided to the scan line and receive a data signal from the data line. The pixels display an image while generating light having a predetermined brightness corresponding to the data signal.

[0008] Recently, a method of driving a display device at a low frequency has been used to improve the driving efficiency of the display device and minimize power consumption. Accordingly, there is a need for a method capable of improving the display quality when the display device is driven at a low frequency. Summary of the invention

[0009] The technical problem to be solved by the present inventive concept is to provide a display device that minimizes the difference in brightness even when the driving frequency changes.

[0010] In addition, another technical problem to be solved by the present inventive concept is to provide a display device that can improve (remove) hysteresis (difference in threshold voltage shift) caused by the difference in conduction bias (and difference in gray scale) between adjacent pixels and screen smear (ghosting phenomenon) caused by hysteresis deviation by periodically applying a bias having a constant voltage to a driving transistor regardless of the data signal and image gray scale.

[0011] The technical problems of the inventive concept are not limited to the above-mentioned technical problems. Through the following description, those skilled in the art will clearly understand other technical problems not mentioned.

[0012] To solve the above technical problems, in one aspect, a display device according to an embodiment of the inventive concept may include: pixels connected to a first scan line, a second scan line, a third scan line, a data line, and an emission control line; and an initialization voltage providing circuit for providing an initialization voltage to the pixels. Each of the plurality of pixels may include: a light emitting diode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node. The first node is electrically connected to a first power line. The second transistor is connected between the data line and the first node and includes a gate electrode connected to the third scan line. The third transistor is connected between the second node and the third node and includes a gate electrode connected to the second scan line. The fourth transistor is connected between the third node and a first initialization voltage line and includes a gate electrode connected to the first scan line. The fourth transistor may be turned on during a first period and a second period, and the initialization voltage providing circuit may provide a first initialization voltage of a first level during the first period and a first initialization voltage of a second level higher than the first level during the second period.

[0013] In an embodiment, each of the plurality of pixels may further include: a fifth transistor and a sixth transistor. The fifth transistor is connected between the first power line and the first node and includes a gate electrode connected to the emission control line. The sixth transistor is connected between the third node and a fourth node and includes a gate electrode connected to the emission control line, wherein the fourth node is connected to a first electrode of the light emitting diode.

[0014] In an embodiment, during a first period after an emission control signal having an off level is provided to the fifth transistor and the sixth transistor, a first scan signal having an on level may be provided to the first scan line. During a period overlapping at least a part of the first period, a second scan signal having an on level may be provided to the second scan line. And during the period when the first scan signal and the second scan signal having an on level are provided, a first initialization voltage of a first level may be applied to the second node.

[0015] In an embodiment, a third scan signal having an on level may be provided to the third scan line during a period between the first period and the second period, and a data signal may be applied to the first node during the period when the third scan signal having an on level is provided.

[0016] In an embodiment, the provision of the second scan signal having a conductive level may be stopped after a period in which the third scan signal having a conductive level is provided, and the first scan signal having a conductive level may be provided during a second period after the provision of the second scan signal having a conductive level is stopped.

[0017] In an embodiment, the first initialization voltage may change from a first level to a second level synchronously with the time when the first scan signal having a conductive level is provided.

[0018] In an embodiment, each of the plurality of pixels may further include a seventh transistor connected between the fourth node and the second initialization voltage line and including a gate electrode connected to the fourth scan line.

[0019] In an embodiment, the fourth scan signal having a conductive level may be provided to the fourth scan line after a first period, and a second initialization voltage may be applied to the fourth node through the second initialization voltage line during the period in which the fourth scan signal having a conductive level is provided.

[0020] In an embodiment, the fourth scan signal may be the same as the third scan signal.

[0021] In an embodiment, the third transistor may be an oxide semiconductor transistor, and the first, second, fourth, fifth, and sixth transistors may be polysilicon semiconductor transistors.

[0022] In an embodiment, the emission control line may include a first emission control line and a second emission control line, and each of the plurality of pixels may further include: a fifth transistor connected between the first power supply line and the first node and including a gate electrode connected to the first emission control line; and a sixth transistor connected between the third node and the first electrode of the light-emitting diode and including a gate electrode connected to the second emission control line.

[0023] In an embodiment, during a first period after the first emission control signal having a non-conductive level is provided to the fifth transistor, the first scan signal having a conductive level may be provided to the first scan line, the second scan signal having a conductive level may be provided to the second scan line during a period overlapping at least a part of the first period, the second emission control signal having a non-conductive level may be provided to the second emission control line during a period overlapping at least a part of the first period, and the first initialization voltage having a first level may be applied to the second node and the first electrode of the light-emitting diode during the period in which the first scan signal, the second scan signal, and the second emission control signal having a conductive level are provided.

[0024] In an embodiment, a third scan signal having an on level during a period between a first period and a second period may be provided to a third scan line, and a data signal may be applied to a first node during a period in which the third scan signal having the on level is provided.

[0025] In an embodiment, after a period in which a third scan signal having an off level is provided, provision of a second scan signal having an on level may be stopped, and a first scan signal having an on level may be provided during a second period after the provision of the second scan signal having the on level is stopped.

[0026] In an embodiment, a first initialization voltage may change from a first level to a second level in synchronization with a time when the first scan signal is provided.

[0027] In an embodiment, the third transistor and the fourth transistor may be oxide semiconductor transistors, and the first transistor, the second transistor, the fifth transistor, and the sixth transistor may be polysilicon semiconductor transistors.

[0028] In an embodiment, the display device may further include: a first sub-scan driver configured to sequentially provide a first scan signal to a first scan line at a first frequency; a second sub-scan driver configured to sequentially provide a second scan signal to a second scan line at a second frequency; a third sub-scan driver configured to sequentially provide a third scan signal to a third scan line at the first frequency; and a fourth sub-scan driver configured to sequentially provide a fourth scan signal to a fourth scan line at the first frequency.

[0029] In an embodiment, the first sub-scan driver may provide the first scan signal during a display scan period and a self-scan period included in one frame period, the second sub-scan driver may provide the second scan signal during the display scan period and not provide the second scan signal during the self-scan period, the third sub-scan driver may provide the third scan signal during the display scan period and the self-scan period, and the fourth sub-scan driver may provide the fourth scan signal during the display scan period and the self-scan period.

[0030] In an embodiment, the first frequency may be a multiple of the second frequency, and the second frequency may be a frequency corresponding to an image refresh rate of a pixel.

[0031] In an embodiment, the second level of the first initialization voltage may be equal to or higher than a level of a first power supply voltage provided to a first power line. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept.

[0033] Figure 1 is a block diagram showing a display device according to an embodiment of the inventive concept.

[0034] Figure 2 is a circuit diagram of a pixel according to an embodiment of the inventive concept.

[0035] Figure 3 and Figure 4 are timing diagrams for explaining a method of driving the Figure 2 pixels shown in

[0036] Figures 5 to 10 is a timing diagram showing an embodiment of a gate start pulse and an emission start pulse according to an image refresh rate.

[0037] Figure 11 is a conceptual diagram for explaining a method of driving a display device according to an image refresh rate.

[0038] Figure 12 is a circuit diagram of a pixel according to another embodiment of the inventive concept.

[0039] Figure 13 and Figure 14 are timing diagrams for explaining a method of driving the Figure 12 pixels shown in DETAILED DESCRIPTION

[0040] Advantages and features of the inventive concept and methods for implementing the same will become more apparent through the following exemplary embodiments described with reference to the accompanying drawings. However, the inventive concept is not limited to the following exemplary embodiments, but may be implemented in various different forms. The exemplary embodiments are provided only to complete the disclosure of the inventive concept and to fully inform those skilled in the art to which the inventive concept pertains of the scope of the inventive concept. The inventive concept is defined only by the scope of the appended claims.

[0041] When assigning reference numerals to components of each drawing, even if the same components are shown in different drawings, the same reference numerals may be assigned to them as much as possible. In addition, when describing the inventive concept, when it is determined that a detailed description of a related well-known configuration or function may obscure the subject matter of the inventive concept, a detailed description thereof may be omitted.

[0042] When describing components of the inventive concept, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish one component from another. The essence, order, or number of components is not limited by the terms. When a component is described as "connected" or "coupled" to another component, the component may be directly connected to or coupled to the other component. However, it should be understood that other components may be "interposed" between each component, or each component may be "connected" or "coupled" through other components. Also, unless the context clearly indicates otherwise, singular expressions may include plural expressions.

[0043] Figure 1 is a block diagram showing a display device 1 according to an embodiment of the inventive concept.

[0044] Referring to Figure 1 , the display device 1 according to an embodiment of the inventive concept may display an image at various image refresh rates (driving frequency, screen update frequency, or screen refresh rate) according to driving conditions. Here, the image refresh rate may refer to the frequency at which a data signal is substantially written to a driving transistor of a pixel PXnm. For example, the image refresh rate may be a screen refresh rate, a screen update frequency, and a screen refresh frequency, and may indicate the frequency at which a display screen changes within one second.

[0045] In an embodiment, the display device 1 may adjust an output frequency of the scan driver 30 and an output frequency of the data driver 20 according to driving conditions. For example, the display device 1 may display an image corresponding to various image refresh rates between 1 Hz and 120 Hz. However, this is an example, and the display device 1 may even display an image at an image refresh rate of 120 Hz or higher (e.g., 240 Hz or 480 Hz).

[0046] The display device 1 may include a timing controller 10, a data driver 20, a scan driver 30, a transmit driver 40, a display area 50, and an initialization voltage providing circuit 60.

[0047] The timing controller 10 may receive input image data IRGB and a plurality of timing signals Vsync, Hsync, DE, and CLK from a host system such as an application processor (AP) through a predetermined interface. Here, the plurality of timing signals Vsync, Hsync, DE, and CLK may include, for example, a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE, and a clock signal CLK.

[0048] The vertical sync signal Vsync may include a plurality of pulses and may indicate a start time of a current frame period and an end time of a previous frame period. An interval between adjacent pulses of the vertical sync signal Vsync may correspond to one frame period.

[0049] The horizontal synchronization signal Hsync may include a plurality of pulses and may indicate the end time of the previous horizontal period and the start time of a new horizontal period. The interval between adjacent pulses of the horizontal synchronization signal Hsync may correspond to one horizontal period.

[0050] The data enable signal DE may have an enable level for a specific horizontal period. When the data enable signal DE is at the enable level, it may indicate that the input image data IRGB is provided during the corresponding horizontal period.

[0051] The input image data IRGB may be provided in units of pixel rows during each of the corresponding horizontal periods.

[0052] The timing controller 10 may rearrange the input image data IRGB and provide the image data RGB to the data driver 20. Specifically, the timing controller 10 may generate the image data RGB corresponding to the gray value based on the input image data IRGB to correspond to the specifications of the display device 1, and provide the image data RGB to the data driver 20.

[0053] In addition, the timing controller 10 may generate control signals to be provided to the data driver 20, the scan driver 30, and the emission driver 40 based on the plurality of timing signals Vsync, Hsync, DE, and CLK to correspond to the specifications of the display device 1.

[0054] In an embodiment, the timing controller 10 may generate a data drive control signal DCS based on the plurality of timing signals Vsync, Hsync, DE, and CLK, and provide the data drive control signal DCS to the data driver 20.

[0055] The data driver 20 may convert the rearranged image data RGB into a data signal (or data voltage) having an analog format. Specifically, the data driver 20 may use the image data RGB and the data drive control signal DCS received from the timing controller 10 to generate data signals (or data voltages) to be provided to the plurality of data lines DL1, DL2 to DLm. For example, the data driver 20 may sample the gray value in response to the data drive control signal DCS, and provide the data signal (or data voltage) corresponding to the gray value to the plurality of data lines DL1, DL2 to DLm in units of pixel rows (e.g., pixels connected to the same scan line).

[0056] The data driver 20 can supply data signals to a plurality of data lines DL1, DL2 to DLm according to the image refresh rate in response to a scan signal during one frame period. The data signals supplied to the plurality of data lines DL1, DL2 to DLm can be supplied synchronously with the second scan signal supplied to the plurality of second scan lines GWNL1 to GWNLn and the third scan signal (and / or the fourth scan signal supplied to the plurality of fourth scan lines GBL1 to GBLn) supplied to the plurality of third scan lines GWPL1 to GWPLn.

[0057] Meanwhile, in an embodiment, the timing controller 10 can supply a gate start pulse GSP and a clock signal CLK to the scan driver 30 based on a plurality of timing signals Vsync, Hsync, DE, and CLK. Here, the gate start pulse GSP can be used to control the first timing of the scan signal supplied from the scan driver 30, and the clock signal CLK can be used to shift the gate start pulse GSP.

[0058] The scan driver 30 can receive the clock signal CLK, the gate start pulse GSP, and similar signals from the timing controller 10 and generate scan signals to be supplied to the plurality of first scan lines GIL1 to GILn, the plurality of second scan lines GWNL1 to GWNLn, the plurality of third scan lines GWPL1 to GWPLn, and the plurality of fourth scan lines GBL1 to GBLn, where n can be a natural number.

[0059] The scan driver 30 can include a plurality of sub-scan drivers 31, 32, 33, and 34. For example, the scan driver 30 can include a first sub-scan driver 31, a second sub-scan driver 32, a third sub-scan driver 33, and a fourth sub-scan driver 34. In this case, the gate start pulse GSP can include a first gate start pulse GSP1, a second gate start pulse GSP2, a third gate start pulse GSP3, and a fourth gate start pulse GSP4 respectively supplied to the first sub-scan driver 31, the second sub-scan driver 32, the third sub-scan driver 33, and the fourth sub-scan driver 34. In this case, the pulse widths of the gate start pulse GSP including the first gate start pulse GSP1, the second gate start pulse GSP2, the third gate start pulse GSP3, and the fourth gate start pulse GSP4 can be different, and the widths of the corresponding scan signals can also be different. Meanwhile, the plurality of sub-scan drivers 31, 32, 33, and 34 can commonly receive the clock signal CLK.

[0060] For ease of explanation, the scan driver 30 and the gate start pulse GSP supplied to the scan driver 30 are illustrated as if they include separate sub-scan drivers, e.g., a first sub-scan driver 31, a second sub-scan driver 32, a third sub-scan driver 33, and a fourth sub-scan driver 34, as well as separate gate start pulses GSP, e.g., a first gate start pulse GSP1, a second gate start pulse GSP2, a third gate start pulse GSP3, and a fourth gate start pulse GSP4. According to the design, at least some of the scan driver 30 and the emission driver 40 may be integrated into one driving circuit, module, or the like.

[0061] In an embodiment, the first sub-scan driver 31 may sequentially supply a first scan signal to a plurality of first scan lines GIL1 to GILn in response to the first gate start pulse GSP1, the second sub-scan driver 32 may sequentially supply a second scan signal to a plurality of second scan lines GWNL1 to GWNLn in response to the second gate start pulse GSP2, the third sub-scan driver 33 may sequentially supply a third scan signal to a plurality of third scan lines GWPL1 to GWPLn in response to the third gate start pulse GSP3, and the fourth sub-scan driver 34 may sequentially supply a fourth scan signal to a plurality of fourth scan lines GBL1 to GBLn in response to the fourth gate start pulse GSP4. Each of the plurality of sub-scan drivers 31, 32, 33, and 34 may include a plurality of scan stages connected in the form of a shift register. For example, the scan signal may be generated by sequentially transmitting the pulse of the conduction level of the gate start pulse GSP supplied to the scan start line to the next scan stage.

[0062] In an embodiment, the first sub-scan driver 31, the third sub-scan driver 33, and the fourth sub-scan driver 34 may supply the scan signals to the plurality of first scan lines GIL1 to GILn, the plurality of third scan lines GWPL1 to GWPLn, and the plurality of fourth scan lines GBL1 to GBLn, respectively, at a constant first frequency regardless of the image refresh rate of the display device 1.

[0063] In an embodiment, the first frequency may be greater than the image refresh rate of the display device 1. For example, the first frequency may be set to about twice the maximum image refresh rate of the display device 1 (the maximum driving frequency set in the display device 1). Specifically, when the maximum image refresh rate of the display device 1 is 120 Hz, the first frequency may be set to 240 Hz. Thus, during one frame period, the scan operation of sequentially outputting the scan signals (e.g., the first scan signal, the third scan signal, and the fourth scan signal) to the scan lines (e.g., GIL1 to GILn, GWPL1 to GWPLn, GBL1 to GBLn) may be repeated multiple times.

[0064] For example, at all driving frequencies at which the display device 1 can be driven, the first sub-scan driver 31, the third sub-scan driver 33, and the fourth sub-scan driver 34 can perform one scan during the display scan period, and can perform at least one scan during the self-scan period according to the image refresh rate. The number of repetitions of the scan operation during the self-scan period is determined according to the image refresh rate. In this case, when the image refresh rate decreases, the number of repetitions of the scan operation performed during the self-scan period within one frame period can be increased. When the image refresh rate increases, the number of repetitions of the scan operation performed during the self-scan period within one frame period can be decreased.

[0065] In an embodiment, the first frequency can correspond to the output frequencies of the first gate start pulse GSP1, the third gate start pulse GSP3, and the fourth gate start pulse GSP4 respectively provided from the timing controller 10 to the first sub-scan driver 31, the third sub-scan driver 33, and the fourth sub-scan driver 34. In this case, the output frequencies of the first gate start pulse GSP1, the third gate start pulse GSP3, and the fourth gate start pulse GSP4 can be the same.

[0066] Meanwhile, in an embodiment, the second sub-scan driver 32 can provide the second scan signal to the plurality of second scan lines GWNL1 to GWNLn at a second frequency.

[0067] In an embodiment, the second frequency can be the same as the image refresh rate of the display device 1. For example, when the image refresh rate of the display device 1 is 120 Hz, the second frequency can be set to 120 Hz. In this case, within one frame period, a scan operation in which a scan signal (for example, the second scan signal) is sequentially output to the scan lines (for example, GWNL1 to GWNLn) can be performed. For example, at all driving frequencies at which the display device 1 can be driven, the second sub-scan driver 32 can perform one scan operation during the display scan period.

[0068] In an embodiment, the second frequency can be set to a common divisor of the first frequency, and can correspond to the output frequency of the second gate start pulse GSP2 provided from the timing controller 10 to the second sub-scan driver 32.

[0069] In an embodiment, the image refresh rate can be the output frequency of the second sub-scan driver 32 that provides the second scan signal to the plurality of second scan lines GWNL1 to GWNLn.

[0070] According to an embodiment, the third sub-scan driver 33 and the fourth sub-scan driver 34 may be combined into a single sub-scan driver. In this case, the plurality of third scan lines GWPL1 to GWPLn and the plurality of fourth scan lines GBL1 to GBLn may be connected to the same node and may receive the same gate start pulse. In this case, the third gate start pulse GSP3 and the fourth gate start pulse GSP4 may be the same. The sub-scan driver integrating the third sub-scan driver 33 and the fourth sub-scan driver 34 may provide scan signals to the plurality of third scan lines GWPL1 to GWPLn and the plurality of fourth scan lines GBL1 to GBLn.

[0071] Meanwhile, in an embodiment, the fourth sub-scan driver 34 may be omitted according to the pixel structure of the pixel PXnm.

[0072] The scan signal may be set to a gate-on voltage (e.g., a pulse of an on level) so that the transistors included in the pixel PXnm are turned on.

[0073] In an embodiment, the scan signal may be a signal of a pulse having a first polarity or a second polarity. In this case, the first polarity and the second polarity may be opposite polarities.

[0074] Hereinafter, the polarity may mean the logic level of the pulse. For example, when the pulse is of the first polarity, the pulse may have a high level. When a pulse of the first polarity is provided to the gate electrode of an N-type transistor, the N-type transistor may be turned on. That is, the pulse of the first polarity may be the on level of the N-type transistor. Here, it is assumed that a voltage sufficiently lower than the gate electrode is applied to the source electrode of the N-type transistor. For example, the N-type transistor may be an NMOS transistor.

[0075] In addition, when the pulse is of the second polarity, the pulse may have a low level. When a pulse of the second polarity is provided to the gate electrode of a P-type transistor, the P-type transistor may be turned on. That is, the pulse of the second polarity may be the on level of the P-type transistor. Here, it is assumed that a voltage sufficiently higher than the gate electrode is applied to the source electrode of the P-type transistor. For example, the P-type transistor may be a PMOS transistor.

[0076] Meanwhile, in an embodiment, the timing controller 10 may provide the emission start pulse ESP and the clock signal CLK to the emission driver 40 based on a plurality of timing signals Vsync, Hsync, DE, and CLK. The emission start pulse ESP may be used to control the first timing of the emission control signal, and the clock signal CLK may be used to shift the emission start pulse ESP.

[0077] The emission driver 40 can receive a clock signal CLK and an emission start pulse ESP from the timing controller 10 to generate emission control signals to be provided to a plurality of emission control lines EL1, EL2 to ELn. For example, the emission driver 40 can sequentially provide the emission control signals to the plurality of emission control lines EL1, EL2 to ELn. For example, the emission driver 40 can be configured in the form of a shift register.

[0078] In an embodiment, the plurality of emission control lines EL1, EL2 to ELn can be respectively electrically connected to a plurality of pixels PXnm included in a horizontal line (pixel row). This will be described later with reference to Figure 2 this.

[0079] In an embodiment, each of the plurality of emission control lines EL1, EL2 to ELn can include a first emission control line and a second emission control line, and the first emission control line and the second emission control line can be respectively electrically connected to a plurality of pixels PXnm included in a horizontal line (pixel row). This will be described later with reference to Figure 12 this.

[0080] When the emission control signals are sequentially provided to the plurality of emission control lines EL1, EL2 to ELn, the pixels PXnm may not emit light in units of horizontal lines. To this end, the emission control signals can be set to a gate-off voltage (e.g., a pulse of an off level) so that some transistors included in the pixels PXnm are turned off.

[0081] In an embodiment, the emission driver 40 can provide the emission control signals to the plurality of emission control lines EL1, EL2 to ELn at a constant first frequency regardless of the image refresh rate of the display device 1. Therefore, within one frame period, the emission control signals provided to each of the plurality of emission control lines EL1, EL2 to ELn can be repeatedly provided at predetermined time intervals. Therefore, when the image refresh rate is reduced, the number of repetitions of the operation of providing the emission control signals during one frame period can be increased.

[0082] The scan driver 30 and the emission driver 40 can be respectively formed on a substrate by a thin film process. In addition, the scan driver 30 and the emission driver 40 can be arranged on both sides with the display area 50 intervening therebetween. Meanwhile, when the scan driver 30 is divided into a first sub-scan driver 31 to a fourth sub-scan driver 34, the first sub-scan driver 31 to the fourth sub-scan driver 34 can also be arranged on both sides with the display area 50 intervening therebetween.

[0083] The display area 50 may include pixels PXnm. For example, each of the plurality of pixels PXnm may be connected to a corresponding data line DLm, a plurality of scan lines GILn, GWNLn, GWPLn, and GBLn, and an emission control line ELn. The pixel PXnm may be externally provided with a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT.

[0084] In an embodiment of the inventive concept, the plurality of signal lines GILn, GWNLn, GWPLn, GBLn, DLm, and ELn connected to the pixel PXnm may be differently arranged corresponding to the circuit structure of the pixel PXnm.

[0085] Meanwhile, according to the circuit structure of the pixel PXnm, the pixels PXnm arranged in the current horizontal line (or current pixel row) may be further connected to the scan line arranged in the previous horizontal line (or previous pixel row) and / or the scan line arranged in the next horizontal line (or next pixel row). To this end, a virtual scan line and / or a virtual emission control line (not shown) may be additionally formed on a region adjacent to the display area 50.

[0086] The initialization voltage providing circuit 60 may receive a control signal (not shown) from the timing controller 10 and provide the initialization voltage VINT to the display area 50. Specifically, the initialization voltage providing circuit 60 may provide the initialization voltage VINT to an initialization voltage line (not shown). The initialization voltage VINT may be provided to the plurality of pixels PXnm electrically connected to the initialization voltage line.

[0087] In an embodiment, the initialization voltage VINT may be a voltage for initializing the gate electrode of the first transistor included in the pixel PXnm, as will be described later.

[0088] In an embodiment, the initialization voltage VINT may be a bias voltage for bringing the first transistor included in the pixel PXnm into an on-bias state, as will be described later.

[0089] In an embodiment, the initialization voltage VINT may be a voltage for initializing the anode of the light-emitting diode included in the pixel PXnm, as will be described later.

[0090] Meanwhile, although Figure 1 not shown, the display device 1 may further include a memory.

[0091] Figure 2 is a circuit diagram of the pixel PXnm according to an embodiment of the inventive concept.

[0092] In Figure 2In order to facilitate the description, a pixel PXnm disposed on the n-th horizontal line and connected to the m-th data line DLm is shown.

[0093] Referring to Figure 2 , the pixel PXnm may include a plurality of transistors Tr1 to Tr7, a storage capacitor Cst, and a light emitting diode LD.

[0094] The first transistor Tr1 may control a driving current based on a data signal. The first transistor Tr1 may be referred to as a driving transistor. A first electrode of the first transistor Tr1 may be connected to a first node N1, a second electrode of the first transistor Tr1 may be connected to a third node N3, and a gate electrode of the first transistor Tr1 may be connected to a second node N2. According to the voltage of the second node N2, the first transistor Tr1 may control the amount of driving current flowing through a first power supply line ELVDDL having a first power supply voltage ELVDD, a fifth transistor Tr5, the first transistor Tr1, a sixth transistor Tr6, the light emitting diode LD, and a second power supply line ELVSSL having a second power supply voltage ELVSS. To this end, the first power supply voltage ELVDD may be set to a voltage higher than the second power supply voltage ELVSS.

[0095] The second transistor Tr2 may select the pixel PXnm to which a data signal is provided based on a third scan signal provided to the third scan line GWPLn. The second transistor Tr2 may be referred to as a scan transistor. The second transistor Tr2 may be connected between the data line DLm and the first node N1. That is, a first electrode of the second transistor Tr2 may be connected to the data line DLm, a second electrode of the second transistor Tr2 may be connected to the first node N1, and a gate electrode of the second transistor Tr2 may be connected to the third scan line GWPLn. When the third scan signal having a conductive level pulse is provided to the third scan line GWPLn, the second transistor Tr2 may be turned on to electrically connect the data line DLm and the first node N1.

[0096] The third transistor Tr3 may be connected between a second electrode (i.e., the third node N3) of the first transistor Tr1 and the second node N2. That is, a first electrode of the third transistor Tr3 may be connected to the second node N2, a second electrode of the third transistor Tr3 may be connected to the third node N3, and a gate electrode of the third transistor Tr3 may be connected to the second scan line GWNLn. When the second scan signal having a conductive level pulse is provided to the second scan line GWNLn, the third transistor Tr3 may be turned on to electrically connect the second electrode (i.e., the third node N3) of the first transistor Tr1 and the second node N2. Therefore, when the third transistor Tr3 is turned on, the first transistor Tr1 may be connected in the form of a diode. Accordingly, data writing and threshold voltage compensation for the first transistor Tr1 may be performed together.

[0097] The fourth transistor Tr4 may be connected between the third node N3 and the first initialization voltage line VINTL1. That is, the first electrode of the fourth transistor Tr4 may be connected to the third node N3, the second electrode of the fourth transistor Tr4 may be connected to the first initialization voltage line VINTL1, and the gate electrode of the fourth transistor Tr4 may be connected to the first scan line GILn. When a first scan signal having a conductive level pulse is provided to the first scan line GILn, the fourth transistor Tr4 may be turned on to supply the first initialization voltage applied through the first initialization voltage line VINTL1 to the third node N3.

[0098] Here, as will be described later with reference to Figure 3 and Figure 4 When the third transistor Tr3 and the fourth transistor Tr4 are turned on, the first initialization voltage applied to the third node N3 may be applied to the gate electrode of the first transistor Tr1. In this case, the first initialization voltage applied to the gate electrode of the first transistor Tr1 may be a low-level voltage. Therefore, the gate electrode of the first transistor Tr1 may be initialized.

[0099] Meanwhile, as will be described later with reference to Figure 3 and Figure 4 When the third transistor Tr3 is turned off and the fourth transistor Tr4 is turned on, the initialization voltage may be applied as a bias voltage to the drain electrode (and the source electrode) of the first transistor Tr1. At this time, the initialization voltage applied to the drain electrode (and the source electrode) of the first transistor Tr1 may be a high-level voltage. In this case, the first transistor Tr1 may be in a conductive bias state (i.e., the first transistor Tr1 may be in a conductive bias).

[0100] The fifth transistor Tr5 may be connected between the first power supply line ELVDDL and the first node N1. The gate electrode of the fifth transistor Tr5 may be connected to the emission control line ELn. When an emission control signal having a high level is provided to the emission control line ELn, the fifth transistor Tr5 may be turned off, and in other cases may be turned on.

[0101] The sixth transistor Tr6 may be connected between the second electrode of the first transistor Tr1 (i.e., the third node N3) and the first electrode of the light-emitting diode LD (i.e., the fourth node N4). The gate electrode of the sixth transistor Tr6 may be connected to the emission control line ELn. When an emission control signal having a high level is provided to the emission control line ELn, the sixth transistor Tr6 may be turned off, and in other cases may be turned on. Therefore, the fifth transistor Tr5 and the sixth transistor Tr6 may be controlled (turned on and off) simultaneously.

[0102] The seventh transistor Tr7 may be connected between a first electrode (i.e., the fourth node N4) of the light-emitting diode LD and the second initialization voltage line VINTL2. A gate electrode of the seventh transistor Tr7 may be connected to the fourth scan line GBLn. When a fourth scan signal having a conductive level pulse is provided to the fourth scan line GBLn, the seventh transistor Tr7 may be turned on to supply a second initialization voltage applied through the second initialization voltage line VINTL2 to the first electrode (i.e., the fourth node N4) of the light-emitting diode LD.

[0103] Here, as will be described later with reference to Figure 3 and Figure 4 When the seventh transistor Tr7 is turned on and the second initialization voltage is applied to the first electrode (i.e., the fourth node N4) of the light-emitting diode LD through the second initialization voltage line VINTL2, the first electrode of the light-emitting diode LD may be initialized.

[0104] In an embodiment, the second initialization voltage may be the same as the first initialization voltage. For example, the first initialization voltage and the second initialization voltage may be low-level voltages.

[0105] In an embodiment, the second initialization voltage may be the same as the first initialization voltage applied to the (n + 1)th pixel row.

[0106] The first electrode (i.e., the anode) of the light-emitting diode LD may be connected to the fourth node N4, and the second electrode (i.e., the cathode) of the light-emitting diode LD may be connected to the second power supply line ELVSSL of the second power supply voltage ELVSS. The light-emitting diode LD may emit light having a predetermined luminance corresponding to the amount of current supplied from the first transistor Tr1.

[0107] In an embodiment, the light-emitting diode LD may be an organic light-emitting diode including an organic light-emitting layer. In another embodiment, the light-emitting diode LD may be an inorganic light-emitting element formed of an inorganic material. Alternatively, the light-emitting diode LD may have a shape in which a plurality of inorganic light-emitting elements are connected in parallel and / or in series between the second power supply line ELVSSL and the fourth node N4.

[0108] Generally, the first power supply voltage ELVDD may be higher than the second power supply voltage ELVSS. However, in a special case such as when the light-emitting diode LD does not emit light, the second power supply voltage ELVSS may be set to be higher than the first power supply voltage ELVDD.

[0109] Meanwhile, when the second initialization voltage is provided to the first electrode of the light-emitting diode LD, a parasitic capacitor (not shown) of the light-emitting diode LD may be discharged. When the remaining voltage charged in the parasitic capacitor is discharged (removed), unintentional emission of weak light can be prevented. Therefore, the black display ability of the pixel PXnm can be improved.

[0110] The storage capacitor Cst can charge an amount of electric charge corresponding to a potential difference between the first power supply voltage ELVDD applied to the first power supply line ELVDDL and the voltage applied to the second node N2. The storage capacitor Cst can be connected between the first power supply line ELVDDL and the second node N2. Specifically, the first electrode of the storage capacitor Cst can be connected to the first power supply line ELVDDL, and the second electrode of the storage capacitor Cst can be connected to the second node N2.

[0111] In an embodiment, the first transistor Tr1 to the seventh transistor Tr7 can include a combination of N-type transistors and P-type transistors. Here, an N-type transistor generally refers to a transistor in which the amount of current to flow increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. A P-type transistor generally refers to a transistor in which the amount of current to flow increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction.

[0112] For example, the first transistor Tr1, the second transistor Tr2, the fourth transistor Tr4, the fifth transistor Tr5, the sixth transistor Tr6, and the seventh transistor Tr7 can be P-type transistors, and the third transistor Tr3 can be an N-type transistor. However, the inventive concept is not limited thereto. Meanwhile, when the transistors are formed on a substrate, the size of the N-type transistor can be larger than the size of the P-type transistor. Therefore, when the fourth transistor Tr4 is designed as a P-type transistor, integration of the pixel circuit can be achieved as compared with the case where the fourth transistor Tr4 is designed as an N-type transistor. In addition, the pixel including the fourth transistor Tr4 designed as a P-type transistor has the advantage of being applicable to the display device 1 having high resolution and a large screen.

[0113] In an embodiment, the N-type transistor can be an oxide semiconductor transistor, and the P-type transistor can be a polysilicon semiconductor transistor. For example, the third transistor Tr3 can include an active layer formed of an oxide such as indium-gallium-zinc-oxide (IGZO). That is, the third transistor Tr3 can be an oxide semiconductor transistor. In another embodiment, the first transistor Tr1, the second transistor Tr2, and the fourth transistor Tr4 to the seventh transistor Tr7 can include an active layer (channel) formed by a low temperature poly-silicon (LTPS) process. That is, the first transistor Tr1, the second transistor Tr2, and the fourth transistor Tr4 to the seventh transistor Tr7 can be polysilicon semiconductor transistors.

[0114] On the other hand, when the first transistor Tr1 is a P-type transistor, the luminance difference caused by the hysteresis change of the first transistor Tr1 in the corresponding frame period according to the change of the driving frequency can be visually recognized by the user. Specifically, in the low-frequency driving where the length of one frame period is long, when the first initialization voltage supplied to the second node N2 is too low, the hysteresis change of the first transistor Tr1 in the corresponding frame period may be increased. This hysteresis change may cause flicker in the low-frequency driving.

[0115] To improve this problem, the pixel PXnm according to an embodiment of the inventive concept and the display device 1 including the pixel PXnm may use the fourth transistor Tr4 to periodically apply a bias voltage of a constant voltage, for example, the first initialization voltage, to the drain electrode (and / or source electrode) of the first transistor Tr1. Accordingly, the hysteresis deviation caused by the difference in gray levels between adjacent pixels can be eliminated, and the screen smear caused thereby can be reduced (removed).

[0116] Hereinafter, a method of driving the pixel PXnm according to an embodiment of the inventive concept will be described in more detail with reference to a timing diagram.

[0117] Figure 3 and Figure 4 are timing diagrams for explaining a method of driving the Figure 2 pixel PXnm shown therein. Specifically, Figure 3 is a timing diagram for explaining a method of driving the pixel PXnm during a display scan period, and Figure 4 is a timing diagram for explaining a method of driving the pixel PXnm during a self-scan period.

[0118] As described above with reference to Figure 2 in Figure 3 and Figure 4 for ease of explanation, a method of driving the pixel PXnm arranged on the n-th horizontal line and connected to the m-th data line DLm will be described.

[0119] Referring to Figure 2 and Figure 3 , the pixel PXnm may be provided with signals for displaying an image during a display scan period. Here, the display scan period may include a period during which a plurality of data signals DV(n - 1), DV(n), and DV(n + 1) actually corresponding to the output image are written.

[0120] In an embodiment, the voltage of the conduction level of the second scan signal GWNn may be defined as a high-level voltage. The voltage of the conduction level of each of the first scan signal GIn, the third scan signal GWPn, and the fourth scan signal GBn may be defined as a low-level voltage. At the same time, the voltage of the conduction level of the emission control signal En may be defined as a low-level voltage. However, this is merely an example. The pulse widths and logic levels of the scan signal and the emission control signal are not limited thereto and may be changed according to pixel structures, transistor types, and similar attributes.

[0121] First, the emission control signal En may be provided to the emission control line ELn to interrupt the current flowing through the light-emitting diode LD. Here, the pulse width of the emission control signal En may be maintained from the first time point t1 to the twelfth time point t12. However, the inventive concept is not limited thereto. The fifth transistor Tr5 and the sixth transistor Tr6 may be turned off by the emission control signal En. During the period when the fifth transistor Tr5 and the sixth transistor Tr6 are turned off, the driving current supplied to the light-emitting diode LD may be stopped.

[0122] After the emission control signal En is provided, the first scan signal GIn may be provided. The pulse width of the first scan signal GIn may be maintained during a predetermined first period (for example, the period from the second time point t2 to the fifth time point t5). However, the inventive concept is not limited thereto. At the same time, the fourth transistor Tr4 may be turned on by the first scan signal GIn.

[0123] After the first scan signal GIn is provided, the second scan signal GWNn may be provided. The pulse width of the second scan signal GWNn may be maintained during a predetermined period (for example, the period from the third time point t3 to the eighth time point t8). However, the inventive concept is not limited thereto. At the same time, the third transistor Tr3 may be turned on by the second scan signal GWNn.

[0124] Here, when the third transistor Tr3 and the fourth transistor Tr4 are turned on simultaneously, as described above, the first initialization voltage VINT1 may be applied to the second node N2 through the first initialization voltage line VINTL1. Thus, the gate electrode of the first transistor Tr1 may be initialized. In this case, the first initialization voltage VINT1 applied to the gate electrode of the first transistor Tr1 may be the same as, for example, the second power supply voltage ELVSS. However, the inventive concept is not limited thereto.

[0125] After the second scan signal GWNn is provided, the supply of the first scan signal GIn is stopped at the fifth time point t5. That is, at the fifth time point t5, the first scan signal GIn at the conduction level (for example, low level) may change to the turn-off level (for example, high level). In this case, the fourth transistor Tr4 may be turned off.

[0126] At the sixth time point t6, a third scan signal GWPn and a fourth scan signal GBn may be provided. The pulse width of each of the third scan signal GWPn and the fourth scan signal GBn may be maintained during a predetermined period (e.g., the period from the sixth time point t6 to the seventh time point t7). However, the inventive concept is not limited thereto. Meanwhile, the second transistor Tr2 may be turned on by the third scan signal GWPn. When the second transistor Tr2 is turned on, the n-th data signal DV(n) may be provided to the first node N1 through the data line DLm. Since the third transistor Tr3 is turned on, the first transistor Tr1 may be connected in the form of a diode. When the first transistor Tr1 is diode-connected, the threshold voltage of the first transistor Tr1 may be compensated.

[0127] Meanwhile, the seventh transistor Tr7 may be turned on by the fourth scan signal GBn. When the seventh transistor Tr7 is turned on, a second initialization voltage VINT2 may be provided to the fourth node N4. In this case, the second initialization voltage VINT2 may be a low-level voltage. Accordingly, the voltage of the first electrode (e.g., anode) of the light-emitting diode LD may be initialized, and the voltage of the parasitic capacitor formed in the light-emitting diode LD may be discharged (removed). That is, the period from the sixth time point t6 to the seventh time point t7 may be a data writing and light-emitting diode initialization period.

[0128] The provision of each of the third scan signal GWPn and the fourth scan signal GBn may be stopped at the seventh time point t7. In this case, the second transistor Tr2 and the seventh transistor Tr7 may be turned off.

[0129] At the eighth time point t8, the provision of the second scan signal GWNn may be stopped. In this case, the third transistor Tr3 may be turned off.

[0130] After the provision of the second scan signal GWNn is stopped, a first scan signal GIn may be provided. In this case, the pulse width of the first scan signal GIn may be maintained during a predetermined second period (e.g., the period from the ninth time point t9 to the eleventh time point t11). Meanwhile, the first initialization voltage VINT1 may increase to a predetermined high-level voltage synchronously with the time point at which the first scan signal GIn is provided (e.g., the ninth time point t9). In an embodiment, at the ninth time point t9, the high level of the first initialization voltage VINT1 may increase to be equal to or higher than the level of the first power supply voltage ELVDD. The fourth transistor Tr4 may be turned on by the first scan signal GIn. When the third transistor Tr3 is turned off and the fourth transistor Tr4 is turned on, a predetermined high voltage (the increased first initialization voltage) may be applied as a bias voltage to the third node N3. In this case, the first transistor Tr1 may be in an on-bias state (i.e., the first transistor Tr1 may be in an on-bias).

[0131] Meanwhile, since the first transistors Tr1 of all the pixels arranged in the n-th pixel row are turned on and biased by the increased first initialization voltage, the bias difference can be eliminated. Therefore, the hysteresis difference of the pixels can be eliminated (reduced).

[0132] The conduction period of the fourth transistor Tr4 may not overlap with the conduction period of each of the second transistor Tr2 and the seventh transistor Tr7. That is, the initialization period and the bias period of the light-emitting diode LD may not overlap with each other, but are separated from each other.

[0133] Meanwhile, at the eleventh time point t11, the supply of the first scan signal GIn may be stopped. At this time, the fourth transistor Tr4 may be turned off. In addition, a predetermined high voltage (the increased first initialization voltage) may also be reduced to a predetermined low-level voltage synchronously with the time point (e.g., the twelfth time point t12) when the emission control signal En is stopped from being supplied. In this case, the first initialization voltage VINT1 may be the same voltage as the second power supply voltage ELVSS.

[0134] Thereafter, at the twelfth time point t12, the supply of the emission control signal En may be stopped, and the fifth transistor Tr5 and the sixth transistor Tr6 may be turned on. When the fifth transistor Tr5 and the sixth transistor Tr6 are turned on, the drive current generated based on the data signal DV(n) may be supplied to the light-emitting diode LD, and the light-emitting diode LD may emit light with a brightness corresponding to the drive current. That is, the period after the twelfth time point t12 may be the light-emitting period.

[0135] In an embodiment, one frame period may include a display scan period. The display scan period may include an initialization period (e.g., the period from the second time point t2 to the fifth time point t5), a data writing and light-emitting diode initialization period (e.g., the period from the sixth time point t6 to the seventh time point t7), a bias period (e.g., the period from the ninth time point t9 to the eleventh time point t11), and a light-emitting period (e.g., the period after the twelfth time point t12). Here, in the display scan period, the remaining periods (the initialization period, the data writing and light-emitting diode initialization period, and the bias period) except the light-emitting period may be the non-light-emitting periods of the pixels PXnm.

[0136] Meanwhile, referring to Figure 2 and Figure 4 , according to the image frame rate, one frame period may include at least one self-scan period.

[0137] In an embodiment, except for not providing the second scan signal GWNn and the data signal DV(n), the operation during the self-scan period may be substantially the same as the operation during the display scan period. During the self-scan period, the data driver 20 may not supply various data signals DV(n-1), DV(n), and DV(n+1) to the pixels PXnm in the display area 50. Therefore, power consumption can be further reduced.

[0138] For example, the self-scan period may include a light-emitting diode initialization period (e.g., the period from the sixth time point t6 to the seventh time point t7), a bias period (e.g., the period from the ninth time point t9 to the eleventh time point t11), and a light-emitting period (e.g., the period after the twelfth time point t12).

[0139] During the self-scan period, since the third transistor Tr3 remains in the off state, the voltage applied to the gate electrode of the first transistor Tr1 (i.e., the voltage applied to the second node N2) may not be affected by the driving of the self-scan period. That is, the data signal stored during the display scan period may maintain the voltage.

[0140] The emission control signal En, the first scan signal GIn, the third scan signal GWPn, and the fourth scan signal GBn may be provided at a first frequency regardless of the image refresh rate. The second scan signal GWNn may be provided at a second frequency corresponding to the image refresh rate.

[0141] In other words, the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 may be driven at the first frequency, and the third transistor Tr3 may be driven at a second frequency lower than the first frequency.

[0142] Therefore, even when the image refresh rate changes, the on-bias of the bias period can be continuously applied periodically. Therefore, the hysteresis change of the first transistor Tr1 for various image refresh rates can be minimized, and the flicker can be improved accordingly.

[0143] Refer to Figure 4 , the second scan signal GWNn may be a voltage at an off level (e.g., a low level). At the same time, the first scan signal GIn at a conductive level (e.g., a low level) may be provided from the second time point t2 to the fifth time point t5. When the third transistor Tr3 is off and the fourth transistor Tr4 is on, the first initialization voltage VINT1 may be applied to the third node N3 to initialize the third node N3.

[0144] On the other hand, after the fifth time point t5, the provision of the first scan signal GIn may be stopped, and a third scan signal GWPn and a fourth scan signal GBn at a conductive level (e.g., a low level) may be provided from the sixth time point t6 to the seventh time point t7. When the second transistor Tr2 is turned on, the reference voltage Vref may be provided to the first node N1 through the data line DLm. In this case, the reference voltage Vref may be a voltage provided by the data driver 20. When the seventh transistor Tr7 is turned on, the second initialization voltage VINT2 may be applied to the fourth node N4 through the second initialization voltage line VINTL2. Thus, the first node N1 and the fourth node N4 may be initialized. In this case, the second initialization voltage VINT2 may be a low-level voltage.

[0145] In Figure 4 it is shown that the third scan signal GWPn is provided from the sixth time point t6 to the seventh time point t7, but different from that shown in Figure 4 the third scan signal GWPn may not be provided during the self-scan period. In this case, the reference voltage Vref may also not be provided to the data line DLm.

[0146] Meanwhile, a first scan signal GIn at a conductive level (e.g., a low level) may be provided from the ninth time point t9 to the eleventh time point t11, and the first initialization voltage VINT1 may be increased to a predetermined high-level voltage synchronously with the ninth time point t9 at which the first scan signal GIn is provided. In an embodiment, the first initialization voltage VINT1 may be increased to a voltage greater than the first power supply voltage ELVDD at the ninth time point t9. When the third transistor Tr3 is turned off and the fourth transistor Tr4 is turned on, a predetermined high voltage (the increased first initialization voltage) may be applied as a bias voltage to the drain electrode (and the source electrode) of the first transistor Tr1 (i.e., the third node N3). In this case, the first transistor Tr1 may be in an on-bias state.

[0147] Figures 5 to 10 is a timing diagram showing embodiments of the first gate start pulse GSP1 to the fourth gate start pulse GSP4 and the emission start pulse ESP according to the image refresh rate. Figure 11 is a conceptual diagram for explaining a method of driving the display device 1 according to the image refresh rate.

[0148] Referring to Figures 5 to 10, for example, the output frequencies of the first gate start pulse GSP1, the third gate start pulse GSP3, and the fourth gate start pulse GSP4 for generating the first scan signal GIn, the third scan signal GWPn, and the fourth scan signal GBn, respectively, can be maintained at a constant frequency, for example, a first frequency, regardless of the image refresh rate RR (or the driving frequency). For example, the output frequencies of the first gate start pulse GSP1, the third gate start pulse GSP3, and the fourth gate start pulse GSP4 can be set to twice the maximum image refresh rate RR of the display device 1.

[0149] In addition, the output frequency of the emission start pulse ESP for generating the emission control signal En can also be maintained at a constant frequency, for example, at the first frequency, regardless of the image refresh rate RR (or the driving frequency). The output frequency of the emission start pulse ESP can be set to twice the maximum image refresh rate RR of the display device 1.

[0150] Meanwhile, the output frequency of the second gate start pulse GSP2 for generating the second scan signal GWNn can vary according to the image refresh rate RR.

[0151] In an embodiment, the timing controller 10 can output the second gate start pulse GSP2 at the same frequency (e.g., a second frequency) as the image refresh rate RR.

[0152] In an embodiment, the pulse width of the emission start pulse ESP can be greater than the pulse widths of the first gate start pulse GSP1 to the fourth gate start pulse GSP4.

[0153] In an embodiment, the emission start pulse ESP and the first gate start pulse GSP1 to the fourth gate start pulse GSP4 can all be output during the display scan period DSP. For example, each of the plurality of pixels PXnm can perform the Figure 3 driving shown therein. During the display scan period DSP, each of the plurality of pixels PXnm can store the data signal corresponding to the image to be displayed.

[0154] In an embodiment, the emission start pulse ESP, the first gate start pulse GSP1, the third gate start pulse GSP3, and the fourth gate start pulse GSP4 can be output during the self-scan period SSP. For example, each of the plurality of pixels PXnm can perform the Figure 4 driving shown therein.

[0155] During the display scan period DSP and the self-scan period SSP, a first transistor Tr1 for each of the plurality of pixels PXnm ( Figure 2 shown therein) can be provided. Figure 2Apply a predetermined high voltage (e.g., an increased first initialization voltage) as a bias to the first electrode and / or the second electrode (as shown in).

[0156] In an embodiment, the length of one display scan period DSP and the length of one self-scan period SSP may be substantially the same as each other. However, the number of self-scan periods SSP included in one frame period may be determined according to the image refresh rate RR.

[0157] Referring to Figure 5 and Figure 11 , for example, when the display device 1 is driven at an image refresh rate RR of 120 Hz, the number of second gate start pulses GSP2 provided during one frame period may be half the number of first gate start pulses GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, for an image refresh rate RR of 120 Hz, one frame period may include one display scan period DSP and one self-scan period SSP.

[0158] Meanwhile, the emission start pulse ESP may be provided at the same frequency as the first gate start pulse GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). When the display device 1 is driven at an image refresh rate RR of 120 Hz, each of the plurality of pixels PXnm may alternately repeat the light emission operation and the non-light emission operation twice during the frame period.

[0159] Referring to Figure 6 and Figure 11 , for example, when the display device 1 is driven at an image refresh rate RR of 80 Hz, the number of second gate start pulses GSP2 provided during one frame period may be 1 / 3 of the number of first gate start pulses GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, when driven at an image refresh rate RR of 80 Hz, one frame period may include one display scan period DSP and two consecutive self-scan periods SSP.

[0160] Meanwhile, the emission start pulse ESP may be provided at the same frequency as the first gate start pulse GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, each of the plurality of pixels PXnm may alternately repeat the light emission operation and the non-light emission operation three times during the frame period.

[0161] Referring to Figure 7 and Figure 11, for example, when the display device 1 is driven at an image refresh rate RR of 60 Hz, the number of second gate start pulses GSP2 provided during one frame period may be 1 / 4 of the number of first gate start pulses GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, when driven at an image refresh rate RR of 60 Hz, one frame period may include one display scan period DSP and three consecutive self-scan periods SSP.

[0162] Meanwhile, the emission start pulse ESP may be provided at the same frequency as the first gate start pulse GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Thus, each of the plurality of pixels PXnm may alternately repeat the light emission operation and the non-light emission operation four times during the frame period.

[0163] Refer to Figure 8 and Figure 11 , for example, when the display device 1 is driven at an image refresh rate RR of 48 Hz, the number of second gate start pulses GSP2 provided during one frame period may be 1 / 5 of the number of first gate start pulses GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, when driven at an image refresh rate RR of 48 Hz, one frame period may include one display scan period DSP and four consecutive self-scan periods SSP.

[0164] Meanwhile, the emission start pulse ESP may be provided at the same frequency as the first gate start pulse GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Thus, each of the plurality of pixels PXnm may alternately repeat the light emission operation and the non-light emission operation five times during the frame period.

[0165] Refer to Figure 9 and Figure 11 , for example, when the display device 1 is driven at an image refresh rate RR of 30 Hz, the number of second gate start pulses GSP2 provided during one frame period may be 1 / 8 of the number of first gate start pulses GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, when driven at an image refresh rate RR of 30 Hz, one frame period may include one display scan period DSP and seven consecutive self-scan periods SSP.

[0166] Meanwhile, the emission start pulse ESP may be provided at the same frequency as the first gate start pulse GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Thus, each of the plurality of pixels PXnm may alternately repeat the light emission operation and the non-light emission operation eight times during the frame period.

[0167] Refer toFigure 10 and Figure 11 For example, when the display device 1 is driven at an image refresh rate RR of 24 Hz, the number of second gate start pulses GSP2 provided during one frame period may be 1 / 10 of the number of first gate start pulses GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, when driven at an image refresh rate RR of 24 Hz, one frame period may include one display scan period DSP and nine consecutive self-scan periods SSP.

[0168] Meanwhile, the emission start pulse ESP may be provided at the same frequency as the first gate start pulse GSP1 (third gate start pulse GSP3 or fourth gate start pulse GSP4). Therefore, each of the plurality of pixels PXnm may alternately repeat the light emission operation and the non-light emission operation ten times during a frame period.

[0169] In a manner similar to the above-described manner, by adjusting the number of self-scan periods SSP included in one frame period, the display device 1 can be driven at a driving frequency of 60 Hz, 30 Hz, 24 Hz, 12 Hz, 8 Hz, 6 Hz, 5 Hz, 4 Hz, 3 Hz, 2 Hz, 1 Hz, or a similar frequency. In other words, the display device 1 can support various image refresh rates RR at frequencies corresponding to the common divisors of the first frequency.

[0170] In addition, since the number of self-scan periods SSP increases as the driving frequency decreases, a conduction bias having a constant magnitude can be periodically applied to the first transistor Tr1 included in the display area 50. Therefore, it is possible to improve the brightness reduction, flicker (strobing), and screen smear during low-frequency driving.

[0171] Figure 12 is a circuit diagram of the pixel PXnm according to another embodiment of the inventive concept.

[0172] As described above with reference to Figure 2 In Figure 12 for ease of explanation, the pixel PXnm disposed on the nth horizontal line and connected to the mth data line DLm is shown. Hereinafter, the description of the same components shown in Figure 2 will be omitted, and the inventive concept will be mainly described based on the differences.

[0173] Referring to Figure 12 , Figure 12The pixel PXnm shown in [Figure] can be connected to a first power supply line ELVDDL, a second power supply line ELVSSL, a first emission control line ELn1, a second emission control line ELn2, a first initialization voltage line VINTL1, a first scan line GILn, a second scan line GWNLn, a third scan line GWPLn, and a data line DLm.

[0174] The pixel PXnm may include transistors Tr1 to r6, a storage capacitor Cst, and a light emitting diode LD.

[0175] Since the first transistor Tr1, the second transistor Tr2, the third transistor Tr3, the storage capacitor Cst, and the light emitting diode LD are the same as those shown in [Figure], descriptions thereof are omitted. Figure 2 as shown in [Figure], descriptions thereof are omitted.

[0176] The fourth transistor Tr4 may be connected between the third node N3 and the first initialization voltage line VINTL1. That is, a first electrode of the fourth transistor Tr4 may be connected to the third node N3, a second electrode of the fourth transistor Tr4 may be connected to the first initialization voltage line VINTL1, and a gate electrode of the fourth transistor Tr4 may be connected to the first scan line GILn. When a first scan signal having a conductive level pulse is provided to the first scan line GILn, the fourth transistor Tr4 may be turned on to provide a first initialization voltage applied through the first initialization voltage line VINTL1 to the third node N3.

[0177] Here, as described above with reference to [Figure] Figures 2 to 4 When the third transistor Tr3 and the fourth transistor Tr4 are turned on, the gate electrode of the first transistor Tr1 may be initialized by the first initialization voltage applied to the third node N3.

[0178] Meanwhile, as described above with reference to [Figure] Figures 2 to 4 When the third transistor Tr3 is turned off and the fourth transistor Tr4 is turned on, a predetermined high voltage (increased first initialization voltage VINT1) may be applied as a bias voltage to the drain electrode (and source electrode) of the first transistor Tr1 (i.e., the third node N3). In this case, the first transistor Tr1 may be in a conductive bias state.

[0179] The fifth transistor Tr5 may be connected between the first power supply line ELVDDL and the first node N1. A gate electrode of the fifth transistor Tr5 may be connected to the first emission control line ELn1. When a first emission control signal is provided to the first emission control line ELn1, the fifth transistor Tr5 may be turned off, and may be turned on in other cases.

[0180] The sixth transistor Tr6 may be connected between the second electrode (i.e., the third node N3) of the first transistor Tr1 and the first electrode of the light-emitting diode LD. The gate electrode of the sixth transistor Tr6 may be connected to the second emission control line ELn2. When the second emission control signal is provided to the second emission control line ELn2, the sixth transistor Tr6 may be turned off, and may be turned on in other cases.

[0181] In an embodiment, the third transistor Tr3 and the fourth transistor Tr4 may include an active layer formed of an oxide such as In-Ga-Zn-oxide (IGZO). That is, the third transistor Tr3 and the fourth transistor Tr4 may be oxide semiconductor transistors. Additionally, the first transistor Tr1, the second transistor Tr2, the fifth transistor Tr5, and the sixth transistor Tr6 may include an active layer (channel) formed through a low-temperature polycrystalline silicon (LTPS) process. That is, the first transistor Tr1, the second transistor Tr2, the fifth transistor Tr5, and the sixth transistor Tr6 may be polycrystalline semiconductor transistors.

[0182] Hereinafter, a method of driving a pixel PXnm according to another embodiment of the present inventive concept will be described in detail with reference to a timing diagram.

[0183] Figure 13 and Figure 14 are timing diagrams for illustrating a method of driving Figure 12 the pixel PXnm shown in Figure 13 Specifically, Figure 14 is a timing diagram for illustrating a method of driving the pixel PXnm during a display scan period, and

[0184] As described above with reference to Figure 12 in Figure 13 and Figure 14 for ease of explanation, a method of driving a pixel PXnm arranged on the n-th horizontal line and connected to the m-th data line DLm will be described.

[0185] Referring to Figure 12 and Figure 13 the pixel PXnm may be provided with signals for displaying an image during a display scan period. Here, the display scan period may include a period during which a plurality of data signals DV(n - 1), DV(n), and DV(n + 1) actually corresponding to the output image are written.

[0186] In an embodiment, the voltage of the conduction level of each of the first scan signal GIn and the second scan signal GWNn may be defined as a high-level voltage, and the voltage of the conduction level of the third scan signal GWPn may be defined as a low-level voltage. At the same time, the voltage of the conduction level of the first emission control signal En1 and the second emission control signal En2 may be defined as a low-level voltage.

[0187] However, this is an example. The pulse widths and logic levels of the scan signal and the emission control signal are not limited thereto and may be changed according to pixel structures, transistor types, and similar attributes.

[0188] First, the first emission control signal En1 may be provided to the first emission control line ELn1. Here, the pulse width of the first emission control signal En1 may be maintained from the first time point t1 to the ninth time point t9. However, the inventive concept is not limited thereto. The fifth transistor Tr5 may be turned off by the first emission control signal En1. During the period when the fifth transistor Tr5 is turned off, the driving current supplied to the light-emitting diode LD may be stopped.

[0189] After the first emission control signal En1 is provided, the first scan signal GIn may be provided. The pulse width of the first scan signal GIn may be maintained during a predetermined period (for example, the period from the second time point t2 to the fourth time point t4). However, the inventive concept is not limited thereto. At the same time, the fourth transistor Tr4 may be turned on by the first scan signal GIn.

[0190] At the same time, the second scan signal GWNn may be provided synchronously with the time point at which the first scan signal GIn is provided (for example, the second time point t2). Here, the second scan signal GWNn may be maintained from the second time point t2 to the seventh time point t7. However, the inventive concept is not limited thereto. The third transistor Tr3 may be turned on by the second scan signal GWNn.

[0191] At the same time, the second emission control signal En2 may not be provided until a specific time point (for example, the third time point t3). In this case, the sixth transistor Tr6 may be turned on.

[0192] Here, when the third transistor Tr3, the fourth transistor Tr4, and the sixth transistor Tr6 are turned on, the gate electrode of the first transistor Tr1 and the first electrode of the light-emitting diode LD may be initialized by the first initialization voltage VINT1. In this case, for example, the first initialization voltage VINT1 may be the same as the second power supply voltage ELVSS. However, the inventive concept is not limited thereto. The period from the second time point t2 to the third time point t3 may be an initialization period.

[0193] The second emission control signal En2 may be provided at a third time point t3. The pulse width of the second emission control signal En2 may be maintained from the third time point t3 to the ninth time point t9. However, the inventive concept is not limited thereto. The sixth transistor Tr6 may be turned off by the second emission control signal En2.

[0194] After the time point at which the second emission control signal En2 is provided (e.g., the third time point t3), the provision of the first scan signal GIn may be stopped. In this case, the fourth transistor Tr4 may be turned off.

[0195] After the time point at which the provision of the first scan signal GIn is stopped (e.g., the fourth time point t4), the third scan signal GWPn may be provided. The pulse width of the third scan signal GWPn may be maintained for a predetermined period (e.g., the period from the fifth time point t5 to the sixth time point t6). However, the inventive concept is not limited thereto.

[0196] Meanwhile, the second transistor Tr2 may be turned on by the third scan signal GWPn. When the second transistor Tr2 is turned on, the n-th data signal DV(n) may be provided to the first node N1 through the data line DLm. Since the third transistor Tr3 is turned on, the first transistor Tr1 may be diode-connected. That is, the period from the fifth time point t5 to the sixth time point t6 may be a data writing and threshold voltage compensation period.

[0197] The provision of the third scan signal GWPn may be stopped at the sixth time point t6. In this case, the second transistor Tr2 may be turned off. Then, the provision of the second scan signal GWNn may be stopped at the seventh time point t7. In this case, the third transistor Tr3 may be turned off.

[0198] After the time point at which the provision of the second scan signal GWNn is stopped (e.g., the seventh time point t7), the first scan signal GIn may be provided. The first initialization voltage VINT1 may increase to a predetermined high-level voltage in synchronization with the time point at which the first scan signal GIn is provided (e.g., the eighth time point t8). In an embodiment, at the eighth time point t8, the high level of the first initialization voltage VINT1 may increase to a level equal to or higher than the level of the first power supply voltage ELVDD. Meanwhile, the fourth transistor Tr4 may be turned on by the first scan signal GIn. When the third transistor Tr3 is turned off and the fourth transistor Tr4 is turned on, a predetermined high voltage (the increased first initialization voltage) may be applied as a bias voltage to the third node N3. In this case, the first transistor Tr1 may be in an on-bias state.

[0199] Meanwhile, since the first transistors Tr1 of all the pixels arranged in the n-th pixel row are turned on and biased by the increased first initialization voltage, the bias difference can be eliminated. Therefore, the hysteresis difference of the pixels can be eliminated (reduced).

[0200] Meanwhile, at the ninth time point t9, the supply of the first emission control signal En1, the second emission control signal En2, the first scan signal GIn, and the second scan signal GWNn is stopped, and the predetermined high voltage (the increased first initialization voltage) can also be reduced to the predetermined low-level voltage. In this case, the first initialization voltage VINT1 can be the same voltage as the second power supply voltage ELVSS.

[0201] After the ninth time point t9, the fifth transistor Tr5 and the sixth transistor Tr6 can be turned on. When the fifth transistor Tr5 and the sixth transistor Tr6 are turned on, the drive current generated based on the data signal DV(n) can be supplied to the light-emitting diode LD, and the light-emitting diode LD can emit light with a brightness corresponding to the drive current. That is, the period after the ninth time point t9 can be the light-emitting period.

[0202] In an embodiment, one frame period can include a display scan period. The display scan period can include an initialization period (for example, the period from the second time point t2 to the third time point t3), a data writing and threshold voltage compensation period (for example, the period from the fifth time point t5 to the sixth time point t6), a bias period (for example, the period from the eighth time point t8 to the ninth time point t9), and a light-emitting period (for example, the period after the ninth time point t9). Here, in the display scan period, the remaining periods other than the light-emitting period (the initialization period, the data writing and threshold voltage compensation period, and the bias period) can be the non-light-emitting periods of the pixel PXnm.

[0203] Meanwhile, referring to Figure 12 and Figure 14 , according to the image frame rate, one frame period can include at least one self-scan period.

[0204] In an embodiment, except for not providing the second scan signal GWNn, the third scan signal GWPn, the reference voltage Vref ( Figure 4 shown in Figure 14 ), and the data signal DV(n), Figure 13 the operation of the self-scan period shown in

[0205] In Figure 14In [the above], the third scan signal GWPn is not provided. However, different from that shown in Figure 14 and similar to that shown in Figure 4 , the third scan signal GWPn at a conductive level (e.g., a low level) may be provided from the sixth time point t6 to the seventh time point t7. When the second transistor Tr2 is turned on by the third scan signal GWPn at a conductive level (e.g., a low level), as disclosed in Figure 4 , the reference voltage Vref may be applied to the first node N1 through the data line DLm. In this case, the reference voltage Vref may be a voltage provided by the data driver 20.

[0206] In an embodiment, the first emission control signal En1, the second emission control signal En2, the first scan signal GIn, and the third scan signal GWPn may be provided at a first frequency regardless of the image refresh rate, and the second scan signal GWNn may be provided at a second frequency corresponding to the image refresh rate.

[0207] In other words, the second transistor Tr2 and the fourth to sixth transistors Tr4 to Tr6 may be driven at the first frequency, and the third transistor Tr3 may be driven at a second frequency lower than the first frequency.

[0208] Accordingly, even when the image refresh rate changes, the on-bias of the bias period may always be periodically applied to the third node N3. Therefore, the hysteresis change of the first transistor Tr1 due to different image refresh rates may be minimized, and flicker may be improved accordingly.

[0209] As described above, the embodiments of the inventive concept are capable of minimizing the luminance difference even when the driving frequency changes.

[0210] In addition, the embodiments of the inventive concept may periodically apply a bias of a constant voltage to the driving transistor regardless of the data signal and the gray level of the image. Accordingly, it is possible to improve (remove) the hysteresis (the difference in threshold voltage shift) caused by the difference in on-bias (and the difference in gray level) between adjacent pixels and the screen smear (ghosting phenomenon) caused by the hysteresis deviation.

[0211] The effects according to the embodiments are not limited to the above description, and more different effects are included in this specification.

[0212] As described above, the exemplary embodiments of the inventive concept have been described with reference to the drawings. Those skilled in the art to which the inventive concept pertains will appreciate that various modifications and equivalent embodiments are possible without changing the technical spirit or basic features of the inventive concept. Therefore, it will be understood that the exemplary embodiments described above are disclosed for illustrative purposes only and are not intended to limit the scope of the inventive concept.

Claims

1. A display device, comprising: Pixels, connected to a first scan line, a second scan line, a third scan line, a data line, and an emission control line; And An initialization voltage providing circuit, configured to provide an initialization voltage to the pixels, Wherein, the pixels include: Light emitting diodes; A first transistor, including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, the first node being electrically connected to a first power supply line; A second transistor, connected between the data line and the first node, and including a gate electrode connected to the third scan line; A third transistor, connected between the second node and the third node, and including a gate electrode connected to the second scan line; and A fourth transistor, connected between the third node and a first initialization voltage line, and including a gate electrode connected to the first scan line, Wherein, the fourth transistor is turned on during a first period and a second period, Wherein, the initialization voltage providing circuit provides a first initialization voltage of a first level during the first period, and provides the first initialization voltage of a second level higher than the first level during the second period, and Wherein, the second level of the first initialization voltage is equal to or higher than the level of a first power supply voltage provided to the first power supply line.

2. The display device according to claim 1, wherein, The pixel further includes: A fifth transistor, connected between the first power supply line and the first node, and including a gate electrode connected to the emission control line; and A sixth transistor, connected between the third node and a fourth node, and including a gate electrode connected to the emission control line, the fourth node being connected to a first electrode of the light emitting diode.

3. The display device according to claim 2, Among them, During the first period after an emission control signal having an off level is provided to the fifth transistor and the sixth transistor, a first scan signal having a conductive level is provided to the first scan line, Wherein, during a period overlapping at least a part of the first period, a second scan signal having the conductive level is provided to the second scan line, and Wherein, during the period when the first scan signal and the second scan signal having the conductive level are provided, the first initialization voltage of the first level is applied to the second node.

4. The display device according to claim 3, wherein, During the period between the first period and the second period, a third scan signal having the conductive level is provided to the third scan line, and Wherein, during the period when the third scan signal having the conductive level is provided, a data signal is applied to the first node.

5. The display device according to claim 4, wherein, After the period when the third scan signal having the conductive level is provided, the second scan signal having the conductive level is stopped being provided, and Wherein, during the second period after the second scan signal having the conductive level is stopped being provided, the first scan signal having the conductive level is provided.

6. The display device according to claim 5, wherein, The first initialization voltage changes from the first level to the second level synchronously with the timing at which the first scan signal having the conductive level is provided.

7. The display device according to claim 2, wherein, The pixel further includes a seventh transistor connected between the fourth node and a second initialization voltage line and including a gate electrode connected to a fourth scan line.

8. The display device according to claim 7, wherein, A fourth scan signal having a conductive level is provided to the fourth scan line after the first period, and wherein, during the period in which the fourth scan signal having the conductive level is provided, a second initialization voltage is applied to the fourth node through the second initialization voltage line.

9. The display device according to claim 1, wherein, The emission control line includes a first emission control line and a second emission control line, and wherein the pixel further includes: a fifth transistor connected between the first power supply line and the first node and including a gate electrode connected to the first emission control line; and a sixth transistor connected between the third node and a first electrode of the light emitting diode and including a gate electrode connected to the second emission control line.

10. The display device according to claim 9, Among them, during the first period after a first emission control signal having a non-conductive level is provided to the fifth transistor, a first scan signal having a conductive level is provided to the first scan line, wherein, during a period overlapping at least a part of the first period, a second scan signal having the conductive level is provided to the second scan line, wherein, during a period overlapping at least a part of the first period, a second emission control signal having the non-conductive level is provided to the second emission control line, and wherein, during the period in which the first scan signal, the second scan signal, and the second emission control signal having the conductive levels are provided, the first initialization voltage having the first level is applied to the second node and the first electrode of the light emitting diode.

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