Includes integrated components for twisted pair digital line configuration

Abstract

The present application relates to an integrated component including a twisted pair digital line configuration. Some embodiments include an integrated component having a first stack and having a second stack above the first stack. A first real digital line has a first region along the first stack and has a second region along the second stack. A first complementary digital line has a first region along the first stack and has a second region along the second stack. The first real digital line is relatively compared to the first complementary digital line by a sense amplifier circuit. The second digital line has a first region along the first stack and laterally adjacent to the first region of the first complementary digital line, and the second digital line has a second region along the second stack and laterally adjacent to the second region of the first real digital line.

Description

Technical Field

[0001] A memory array (eg, a DRAM array). The integrated assembly includes a vertically stacked stack. The integrated assembly includes a twisted pair digital line configuration. Background Art

[0002] Memory is used in modern computing architectures to store data. One type of memory is dynamic random access memory (DRAM). Compared to alternative types of memory, DRAM can offer advantages of simplicity, low cost, and high speed.

[0003] DRAMs can utilize memory cells having one capacitor combined with one transistor (so-called 1T-1C memory cells), where the capacitor is coupled to the source / drain region of the transistor. An exemplary 1T-1C memory cell 2 is shown in FIG. 1 , where the transistor is labeled T and the capacitor is labeled C. One node of the capacitor is coupled to the source / drain region of the transistor, and the other node is coupled to the common plate CP. The common plate can be connected to any suitable voltage (such as a voltage in the range from greater than or equal to ground to less than or equal to VCC (i.e., ground ≤ CP ≤ VCC)). In some applications, the voltage of the common plate is about half of VCC (i.e., about VCC / 2). The gate of the transistor is coupled to the word line WL (i.e., access line, routing line, first linear structure, etc.), and the source / drain region is coupled to the bit line BL (i.e., digital line, sense line, second linear structure, etc.). In operation, during read / write operations, the electric field generated by the voltage along the word line can gate-couple the bit line to the capacitor.

[0004] FIG2 shows another prior art 1T-1C memory cell configuration. The configuration of FIG2 shows two memory cells 2a and 2b; memory cell 2a includes a transistor T1 and a capacitor C1, while memory cell 2b includes a transistor T2 and a capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. Memory cells 2a and 2b share a connection to a bit line BL.

[0005] The above-described memory cells may be incorporated into a memory array, and in some applications, the memory array may have an open bit line arrangement. FIG. 3 shows an exemplary integrated component 9 having an open bit line architecture. Component 9 includes two laterally adjacent memory arrays ("array 1" and "array 2"), each of which includes memory cells of the type described in FIG. 2 (not labeled in FIG. 3 to simplify the drawing). Word lines WL0 to WL7 extend across the arrays and are coupled to word line drivers. Digital lines D0 to D8 are associated with the first array (array 1), while digital lines D0* to D8* are associated with the second array (array 2). Sense amplifiers SA0 to SA8 are provided between the first array and the second array. Digital lines at the same height are paired with each other and compared by sense amplifiers (e.g., digital lines D0 and D0* are paired with each other and compared using sense amplifier SA0). In a read operation, one of the paired digital lines can be used as a reference for determining an electrical characteristic (e.g., voltage) of another of the paired digital lines.

[0006] Highly integrated memories have closely spaced memory cells and digit lines. Problems may be encountered due to undesirable capacitive coupling between closely spaced digit lines. Capacitive coupling may cause excessive noise during data read operations and becomes increasingly problematic as the level of integration increases. It is desirable to develop new architectures that can reduce or eliminate problematic capacitive coupling. Summary of the invention

[0007] Some embodiments include an integrated component having a first stack and having a second stack above the first stack. A first real digital line has a first region along the first stack and has a second region along the second stack. A first complementary digital line has a first region along the first stack and has a second region along the second stack. The first real digital line is relatively compared to the first complementary digital line by a sense amplifier circuit. The second digital line has a first region along the first stack and laterally adjacent to the first region of the first complementary digital line, and the second digital line has a second region along the second stack and laterally adjacent to the second region of the first real digital line.

[0008] Some embodiments include an integrated component having a substrate including a first sense amplifier circuit and a second sense amplifier circuit. A first stack is above the substrate. The first stack includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells. A second stack is above the first stack. The second stack includes a second portion of the first array of the first memory cells and includes a second portion of the second array of the second memory cells. A first real digital line is associated with the first array. The first real digital line has a first region associated with the first stack and has a second region associated with the second stack. A first complementary digital line is associated with the second array. The first complementary digital line has a first region associated with the first stack and has a second region associated with the second stack. The first real digital line is relatively compared to the first complementary digital line by a first sense amplifier circuit. A second real digital line is associated with the first array. The second real digital line has a first region that is laterally adjacent to the first region of the first complementary digital line and the second real digital line has a second region that is laterally adjacent to the second region of the first real digital line. A second complementary digital line is associated with the second array. The second complementary digit line has a first region laterally adjacent to the first region of the first real digit line, and the second complementary digit line has a second region laterally adjacent to the second region of the first complementary digit line.

[0009] Some embodiments include an integrated component having a substrate including sense amplifier circuits. A first stack is above the substrate. The first stack includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells. A second stack is above the first stack. The second stack includes a second portion of the first array of the first memory cells and includes a second portion of the second array of the second memory cells. A first set of real digital lines and complementary digital lines are associated with the first array and the second array. The real digital lines in the first set are relatively coupled to the complementary digital lines in the first set through the first set of sense amplifier circuits. A second set of real digital lines and complementary digital lines are associated with the first array and the second array. The real digital lines in the second set are relatively coupled to the complementary digital lines in the second set through the second set of sense amplifier circuits. The real digital lines in the second set have a first region and have a second region, the first region being laterally adjacent to the first region of the complementary digital lines in the first set and the second region being laterally adjacent to the second region of the real digital lines in the first set. The complementary digit lines in the second set have a first region that is laterally adjacent to the first region of the real digit lines in the first set and have a second region that is laterally adjacent to the second region of the complementary digit lines in the first set. A first opening passes through the first stack and a second opening passes through the second stack. An interconnect extends from a power supply to one of the sense amplifier circuits. The interconnect extends through the first opening and the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a schematic diagram of a prior art memory cell having 1 transistor and 1 capacitor.

[0011] 2 is a schematic diagram of a pair of prior art memory cells, each having 1 transistor and 1 capacitor and sharing a bit line connection.

[0012] FIG. 3 is a schematic diagram of a prior art integrated component having an open bit line architecture.

[0013] Figure 4 is a schematic diagram of an example integrated assembly having multiple stacks that are vertically displaced relative to each other.

[0014] Figure 5 yes Figure 4 Multi-dimensional schematic side view of an example layout of complementary digit lines within an example stackup of .

[0015] Figure 5A yes Figure 5 Alternative multidimensional views of the layout.

[0016] Figure 5B yes Figure 5 Schematic side view of one of the memory cells.

[0017] Figure 6 Yes Figure 5 A schematic side view of an area of ​​the layout of the components.

[0018] Figure 7 Yes Figure 5A A multi-dimensional view of an area of ​​an instantiated component of a layout.

[0019] Figure 8 yes Figure 7 A multi-dimensional view of an area of ​​instantiated component replacement.

[0020] Fig. 9 yes Figure 8 A multi-dimensional view of an area of ​​instantiated component replacement.

[0021] Fig.10 is a schematic top view of an example region of an example component.

[0022] Fig.11 yes Figure 4 Multi-dimensional schematic side view of an example layout of complementary digit lines within an example stackup of .

[0023] Fig.11A yes Fig.11 Alternative multidimensional views of the layout.

[0024] Fig.12 Yes Fig.11A A multi-dimensional view of an area of ​​a modified instantiated component of a layout.

[0025] Fig.13 yes Fig.12 A multi-dimensional view of an area of ​​instantiated component replacement.

[0026] Fig.14 is a schematic top view of an example region of an example component. DETAILED DESCRIPTION

[0027] Some embodiments include integrated components having a twisted pair digital line configuration (i.e., a twisted pair bit line configuration). The twisted pair digital line configuration can reduce or eliminate problematic capacitive coupling. Some conventional components can utilize shielding between adjacent digital lines to reduce problematic capacitive coupling. The embodiments described herein can eliminate problematic coupling without utilizing such shielding. Omitting shielding can simplify the manufacture of the architectures described herein compared to conventional architectures that include shielding, and can enable the architectures described herein to be formed to more tightly pack adjacent digital lines compared to architectures with shielding between adjacent digital lines. Reference Figures 4 to 14 Example embodiments are described.

[0028] refer to Figure 4 , integrated component 10 includes substrate 12, first stack 14 on substrate, and second stack 16 on first stack. Structures 12, 14, and 16 are stacked vertically on each other. Substrate 12, first stack 14, and second stack 16 can be considered as examples of levels (layers) stacked on each other. The levels can be in different semiconductor dies, or at least two of the two levels can be in the same semiconductor die.

[0029] The first stack 14 and the second stack 16 have memory areas 18 and 22, respectively. The first memory array and the second memory array (array 1 and array 2) are supported by the first stack 14 and the second stack 16, wherein each of the memory arrays has a first portion along the first (lower) stack 14 and a second portion along the second (upper) stack 16. The first memory array includes first memory cells 20a, and the second memory array includes second memory cells 20b. The memory cells are schematically illustrated as circles. The first memory array and the second memory array may include any suitable number of memory cells, and in some embodiments may include hundreds, thousands, millions, etc. of memory cells. The memory cells may be DRAM cells, and in some embodiments may be configured in an arrangement of the type described above with reference to prior art Figures 1 to 3 (i.e., array 1 and array 2 may be DRAM arrays). For simplicity Figure 4 , array 1 and array 2 are shown as being separated from each other. In some embodiments, an area of ​​array 1 may overlap an area of ​​array 2, as described below with reference to Figures 5 to 14 As shown in the described embodiments.

[0030] In some embodiments, the first stack 14 and the second stack 16 may be referred to as a first memory stack and a second memory stack, respectively.

[0031] Substrate 12 may include semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. Substrate 12 may be referred to as a semiconductor substrate. The term "semiconductive substrate" means any structure including semiconductor material, including but not limited to bulk semiconductive material such as a semiconductive wafer (alone or in an assembly including other materials) and a layer of semiconductive material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, substrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like. Each of stacks 14 and 16 may also include semiconductor material.

[0032] In the illustrated embodiment, substrate 12 includes a sense amplifier circuit (SA) and a word line driver circuit (WD).

[0033] The sense amplifier circuit includes an area labeled "SA-E" to identify it as being associated with the "even" portion of the circuit, and an area labeled "SA-O" to identify it as being associated with the "odd" portion of the circuit. The terms "even" and "odd" are arbitrary and are used to distinguish different sense amplifier circuits. The configuration shown has sense amplifier circuits SA-O and SA-E that are paired with each other and distributed as structures (blocks) 24. The sense amplifier circuits SA-E and SA-O may be referred to as first sense amplifier circuits and second sense amplifier circuits, respectively. In some embodiments, the sense amplifier circuit SA-E may be considered to correspond to a first set of sense amplifier circuits, while the sense amplifier circuit SA-O may be considered to correspond to a second set of sense amplifier circuits; and vice versa.

[0034] The word line driver circuit (i.e., row driver circuit) includes regions labeled SWD-L and SWD-U. The acronym SWD stands for sub-word line driver, and is used to emphasize that the components SWD-L and SWD-U are portions of a general word line driver circuit. The word line driver circuit SWD-L is utilized during operation of the memory cells associated with the lower stack 14, and the word line driver circuit SWD-U is utilized during operation of the memory cells associated with the upper stack 16.

[0035] The configuration shown has word line driver circuits SWD-L and SWD-U paired with each other and distributed as a structure (block) 30 .

[0036] Blocks 24 and 30 may be considered to form block regions. The block regions may be considered together to form a ridge-like arrangement of circuit subunits along substrate 12.

[0037] The first digital lines D0, D1, and D2 are associated with the first memory array (array 1). The first digital lines D0, D1, and D2 extend along the first memory array (array 1) and are coupled to the first memory cells 20a of the first memory array. The bit lines D0*, D1*, and D2* are laterally spaced apart from each other and may represent a large number of substantially identical bit lines extending across the first memory array. The term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. The first digital lines alternate between even first digital lines and odd first digital lines, where the digital lines D0* and D2* represent even first digital lines, and the digital line D1* represents an odd first digital line. The even first digital lines (e.g., D0*) are coupled to the first sense amplifier circuit 26 (i.e., SA-E), while the odd first digital lines (e.g., D1*) are coupled to the second sense amplifier circuit 28 (i.e., SA-O). The first digit lines D0 *, D1 *, and D2 * have a first portion along the first stack 14 , and have a second portion along the second stack 16 .

[0038] The second digital lines D0*, D1*, and D2* are associated with the second memory array (array 2). The second digital lines D0*, D1*, and D2* extend along the second memory array and are coupled to the second memory cells 20b of the second memory array (array 2). The bit lines D0*, D1*, and D2* are laterally spaced apart from each other and may represent a large number of substantially identical bit lines extending across the second memory array. The second digital lines alternate between even second digital lines and odd second digital lines, wherein the digital lines D0* and D2* represent even second digital lines and the digital line D1* represents odd second digital lines. The even second digital lines (e.g., D0*) are coupled to the second sense amplifier circuit 26 (i.e., SA-E), while the odd second digital lines (e.g., D1*) are coupled to the second sense amplifier circuit 28 (SA-O). The second digital lines D0*, D1*, and D2* have a first portion along the first stack 14 and have a second portion along the second stack 16.

[0039] Even first digital lines D0 and D2 are oppositely coupled to even second digital lines D0* and D2* through first sense amplifier circuit 26 (SA-E); and odd first digital line D1 is oppositely coupled to odd second digital line D1* through second sense amplifier circuit 28 (SA-O). For purposes of understanding the present disclosure and the appended claims, a first digital line is “oppositely coupled” to a second digital line through a sense amplifier circuit if the sense amplifier circuit is configured to compare electrical characteristics (e.g., voltages) of the first and second digital lines to each other.

[0040] Two digital lines coupled relative to each other through a sense amplifier circuit can be considered to include a true digital line and a complementary digital line. For example, digital lines D0 and D0* can be considered to be a true digital line and a complementary digital line, respectively; and similarly, digital lines D1 and D1* can be considered to be a true digital line and a complementary digital line, respectively. The terms "real" and "complementary" are arbitrary. During read / write operations of the memory cells (e.g., 20a, 20b) associated with the set, the electrical values ​​of the true digital lines and complementary digital lines of this set are utilized together. For the purpose of describing the embodiments herein, the true digital lines will be those without an asterisk indication in the label (e.g., D0, D1, D2, etc.), and the complementary digital lines will be those with an asterisk indication in the label (e.g., D0*, D1*, D2*, etc.).

[0041] Still reference Figure 4 , word lines 32 extend along the first memory array and the second memory array (array 1 and array 2).

[0042] Each of the first memory cells 20a within the first memory array (array 1) is uniquely addressed by one of the digit lines extending along the first memory array (e.g., one of the digit lines D0, D1, and D2 and one of the word lines 32). Similarly, each of the first memory cells 20b within the second memory array (array 2) is uniquely addressed by one of the digit lines extending along the second memory array (e.g., one of the digit lines D0*, D1*, and D2* and one of the word lines 32). In some embodiments, the digit lines along the first memory array (array 1) may be referred to as a first digit line set, while the digit lines along the second memory array (array 2) may be referred to as a second digit line set.

[0043] Figure 4 An advantage of the configuration is that all of the sense amplifier circuits and all of the word line driver circuits can be located directly beneath the memory arrays (array 1 and array 2), which can enable dense packaging of the memory array across the semiconductor substrate; or in other words, this can save valuable semiconductor space compared to a conventional configuration in which at least some of the sense amplifier circuits and / or at least some of the word line drivers are not located directly beneath the memory array. Vertical stacking of areas of the memory arrays (array 1 and array 2) can further save valuable semiconductor space. Figure 4 In the illustrated embodiment, digit lines D0, D0*, D1, D1*, D2, and D2* are all vertically shifted relative to first sense amplifier circuit SA-E and second sense amplifier circuit SA-0, and vertically shifted relative to word line driver circuits SWD-U and SWD-L.

[0044] Figure 4 The digital lines are not twisted to simplify the drawings. However, the embodiments described herein may include twisted pair digital line configurations. For example, Figure 5 An area of ​​an example integrated component 10 having a twisted pair digital line configuration according to an example embodiment is shown. The twisted pair digital lines include digital lines DL1 and DL1*. The digital lines DL1 and DL1* are coupled to each other via a sense amplifier circuit 28 identified as SA-O(1). -Digit line DL1 may be referred to as a true digital line, while digital line DL1* may be referred to as a complementary digital line. In some embodiments, digital lines DL1 and DL1* may be referred to as first digital lines to distinguish them from each other. Figure 5 The other digit lines shown are distinguished; and in such embodiments, digit line DL1 can be referred to as a first true digit line, while digit line DL1* can be referred to as a first complementary digit line.

[0045] The substrate 12, the first laminate 14 and the second laminate 16 are Figure 5 Schematically shown as having different heights. The real digital line DL1 is shown as having a first region 40a along the first stack (lower stack) 14 (associated therewith), a second region 40b along the second stack (upper stack) 16 (associated therewith), and a vertical extension 40c between the first segment 40a and the second segment 40b. The complementary digital line DL1* is shown as having a first region 42a along the first stack (lower stack) 14 (associated therewith), a second region 42b along the second stack (upper stack) 16 (associated therewith), and a vertical extension 42c between the first segment 40a and the second segment 40b. The vertical extensions 40c and 42c may be referred to as the first vertical extension and the second vertical extension, respectively. The region 44 including the vertical extensions 40c and 42c may be referred to as a twisting region.

[0046] Component 10 also includes a digit line DL0 on one side of twist region 44 and another digit line DL2* on the opposite side of twist region 44. Digit line DL0 may be referred to as a true digit line, and digit line DL2* may be referred to as a complementary digit line. In the illustrated embodiment, true digit line DL0 is not oppositely coupled to complementary digit line DL2*. Instead, digit line DL0 is coupled to first sense amplifier circuit 26a (SA-E(1)), and digit line DL2* is coupled to second sense amplifier circuit 26b (SA-E(2)).

[0047] The digit lines DL0 and DL2* may be referred to as second digit lines to distinguish them from the first digit lines DL1 and DL1*. And in some embodiments, the digit line DL0 may be referred to as a second true digit line, and the digit line DL2* may be referred to as a second complementary digit line.

[0048] The real digital line DL0 is shown as having a first region 46a along (associated with) the first stack (lower stack) 14, a second region 46b along (associated with) the second stack (upper stack) 16, and a vertical extension 46c between the first segment 46a and the second segment 46b. The complementary digital line DL2* is shown as having a first region 48a along (associated with) the first stack (lower stack) 14, a second region 48b along (associated with) the second stack (upper stack) 16, and a vertical extension 48c between the first segment 48a and the second segment 48b. The vertical extensions 46c and 48c may be referred to as third and fourth vertical extensions, respectively.

[0049] In some embodiments, regions 40a, 40b, 42a, 42b, 46a, 46b, 48a and 48b can be considered to be the ends of various digital lines (end regions), and vertically extending segments 40c, 42c, 46c and 48c can be considered to extend between the ends.

[0050] First region 46a of second real digit line DL0 is laterally adjacent to first region 42a of first complementary digit line DL1*, and in some embodiments may be considered a neighbor (in some applications, a nearest neighbor) of the first region of the first complementary digit line.

[0051] The second region 46b of the second real digit line DL0 is laterally adjacent to the second region 40b of the first real digit line DL1 , and in some embodiments may be considered a neighbor (in some applications, a nearest neighbor) of the second region of the first real digit line.

[0052] The first region 48a of the second complementary digit line DL2* is laterally adjacent to the first region 40a of the first real digit line DL1, and in some embodiments may be considered a neighbor (in some applications, a nearest neighbor) of the first region of the first real digit line.

[0053] Second region 48b of second complementary digit line DL2* is laterally adjacent to second region 42b of first complementary digit line DL1*, and in some embodiments may be considered a neighbor (in some applications, a nearest neighbor) of the second region of the first complementary digit line.

[0054] Sense amplifier circuits 26 a , 26 b , and 28 are associated with (along) substrate 12 .

[0055] Example memory cells 20a and 20b are shown along heights corresponding to stacks 14 and 16, and word lines 32 are also shown along heights corresponding to stacks 14 and 16. Each of the memory cells 20a of array 1 is uniquely addressed by a true digit line (DL0 or DL1) and word lines 32. Similarly, each of the memory cells 20b of array 2 is uniquely addressed by a complementary digit line (DL1* or DL2*) and word lines 32. The word lines extend along rows of memory cells 20a / 20b.

[0056] In the illustrated embodiment, the word line extends from memory cell 20a in a first region 46a along the second true digit line DL0 to memory cell 20b in a first region 42a along the first complementary digit line DL1*; the word line extends from memory cell 20a in a second region 46b along the second true digit line DL0 to memory cell 20a in a second region 40b along the first true digit line DL1; the word line extends from memory cell 20b in a first region 48a along the second complementary digit line DL2* to memory cell 20a along a first region 40a along the first true digit line DL1; and the word line extends from memory cell 20b in a second region 48b along the second complementary digit line DL2* to memory cell 20b along a second region 42b of the first complementary digit line DL1*.

[0057] The word line driver circuits (SWD-U and SWD-L) may be supported by substrate 12 and may be coupled to word lines 32. The word line driver circuits are not Figure 5 are shown in order to simplify the drawing.

[0058] Memory cells 20a and 20b may have any suitable configuration. Figure 5B 2 is shown in an enlarged view to simplify labeling of components of the memory cell. Memory cell 20 includes a transistor T coupled to a capacitor C. Transistor T includes a vertically extending column 70 of semiconductor material 72. Semiconductor material 72 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; the term III / V semiconductor material refers to semiconductor materials including elements selected from Groups III and V of the periodic table (wherein Groups III and V are old nomenclature and are now referred to as Groups 13 and 15).

[0059] A gate dielectric material (insulating material) 74 is along the sidewalls of pillar 70 , and a conductive gate material 76 is along the gate dielectric material.

[0060] The gate dielectric material 74 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0061] The conductive gate material 76 may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0062] Conductive gate material 76 forms a transistor gate of transistor T. The transistor includes a first source / drain region 86 within an upper region of pillar 70, a second source / drain region 88 within a lower region of pillar 70, and a channel region 90 between the first source / drain region 86 and the second source / drain region 88. In operation, an electric field generated by a voltage within gate material 76 (i.e., a voltage along word line 32 coupled to gate material 76) may gated couple source / drain regions 86 and 88 to each other through channel region 90. When the term "gated coupling" is utilized herein, this may refer to controlled coupling / decoupling of source / drain regions of a transistor, which may be caused by electrical activation / deactivation of a gate of the transistor.

[0063] Capacitor C includes a first conductive node 78, a second conductive node 80, and an insulating material (capacitor dielectric material) 82 between the first conductive node and the second conductive node.

[0064] The first conductive node 78 and the second conductive node 80 may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). The first conductive node and the second conductive node may include the same composition as each other, or may include different compositions relative to each other.

[0065] Insulating material 82 may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0066] In the illustrated embodiment, the lower conductive node 78 is configured as an upwardly open container. In other embodiments, the lower conductive node may have another suitable shape.

[0067] exist Figure 5B In the view of FIG. 1 , the word line 32 (gate material 76) is on both sides of the channel region 70, and Figure 5The word line (gate material) can be in any suitable configuration relative to the channel region of the transistor; and in some applications, the "transistor" can be on one side of the channel region, on both sides of the channel region, or can completely surround the channel region (i.e., can be a gate-all-around configuration).

[0068] Figure 5 The digital lines DL0, DL1, DL1*, and DL2* of the gate electrode include a conductive material 84. This conductive gate material may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0069] The second real digital line DL0 is configured as a first laterally opening container 50a, and the second complementary digital line DL2* is configured as a second laterally opening container 50b. The first laterally opening container 50a has a first closed end corresponding to the vertical extension section 46c, and has a first open end (opening edge) 51a in a relative relationship with the first closed end. The second laterally opening container 50b has a second closed end corresponding to the vertical extension section 48c, and has a second open end (opening edge) 51b in a relative relationship with the first closed end. The first laterally opening container and the second laterally opening container can be considered to have a first opening 52a and a second opening 52b therein. Figure 5 In the illustrated embodiment of FIG. 5 , the first opening 51 a and the second opening end 51 b face each other.

[0070] Figure 5An advantage of the configuration is that each of the odd digit lines (DL1 and DL1*) has a first portion adjacent to a region of one of the even digit lines (e.g., odd digit line DL1 has a first portion 40a adjacent to even digit line DL2*), and has a second portion adjacent to a region in a different one of the even digit lines (e.g., odd digit line DL1 has a second portion 40b adjacent to even digit line DL0). In addition, the even digit lines adjacent to the first portion of the odd digit lines will be different types of even digit lines (real or complementary) than the even digit lines adjacent to the second portion of the odd digit lines. For example, in the illustrated embodiment, the first portion 40a of the odd digit line DL1 is adjacent to a region of the complementary even digit line DL2*, while the second portion 40b of the odd digit line DL1 is adjacent to a region of the real even digit line DL0. This can enable the elimination of coupled noise along the adjacent digit lines DL1, DL0, and DL2* during differential sensing operations. Similarly, coupled noise along adjacent digit lines DL1*, DL0 and DL2* can be eliminated during differential sensing operations. Figure 5 The configuration can advantageously reduce problematic coupling noise between adjacent digital lines.

[0071] Figure 5A Shows Figure 5 1 is an alternative view of assembly 10 of FIG. 1. Specifically, each of stacks 14 and 16 is schematically shown, and regions of digit lines DL0, DL1, DL1*, and DL2* are schematically shown as being associated with the stacks. Additional digit lines are shown but not labeled.

[0072] Connections between regions along the digit lines of the upper stack 16 and regions along the digit lines of the lower stack 14 are schematically shown with dashed lines 53 (only one of which is labeled), and such dashed lines extend to connection regions 55 (only two of which are labeled) schematically shown in stippling.

[0073] refer to Figure 6 , which shows that with the above reference Figure 5 The various structures are depicted as larger portions of an integrated assembly 10 . Figure 6The view of FIG. 4 shows a pair of twist regions 44 that are laterally displaced relative to each other, and shows various digit lines DL0, DL0*, DL1, DL1*, DL2, DL2*, DL3, DL3*, DL4, and DL4* arranged in an oppositely paired configuration. It is noteworthy that the even pairing configuration (e.g., SA-E(1)) is laterally offset relative to the odd pairing configuration (e.g., SA-O(1)). Therefore, the last even digit line (DL4) of the even digit lines shown is only used for comparison pairing with digit line DL4* and has no noise cancellation relationship with any of the odd digit lines (e.g., DL3, DL3*).

[0074] Figure 7 Using the above reference Figure 5A A schematic diagram of the type described shows Figure 5 Component 10. Figure 7 Substrate 12 is also shown, and sense amplifier circuitry 28 (SA-O) is shown associated with substrate 12. A problem that may arise is that the illustrated configuration of digit lines may block areas that would otherwise be used to access interconnects extending to sense amplifier circuitry. For example, it may be desirable to route power to the sense amplifier circuitry. Regions 54 and 56 along stacks 14 and 16 are schematically illustrated, where such regions correspond to desired locations of windows to be formed to extend through stacks 14 and 16 to access sense amplifier circuitry 28.

[0075] refer to Figure 8 Describes the solution Figure 7 A solution to the problem shown is shown. Specifically, the digital lines are reconfigured to be free of window regions 54 and 56 so that interconnects can extend through window regions 54 and 56. An exemplary interconnect 58 is shown extending from a power supply 60 to the sense amplifier circuit 28. During operation of this sense amplifier circuit, power can be provided to the sense amplifier circuit using the power supply 60. Alternatively, the power supply 60 can correspond to an input / output extending to the sense amplifier circuit and / or any other structure / module that is desired to be electrically coupled to the sense amplifier circuit.

[0076] Figure 8 The window areas 54 and 56 are shown as corresponding to the first and second openings through the first and second stacks 14 and 16, respectively; and the interconnect 58 passes through such first and second openings. Figure 8 In the embodiment of FIG. 5 , the second opening 56 is located directly above the first opening 54 .

[0077] refer to Fig. 9 Describes the solution Figure 7 Another solution to the problem shown. Fig. 91 shows a digit line arranged such that the window 56 (second opening) in the upper stack 16 is laterally offset (i.e., not directly above the window 54) relative to the window 54 (first opening) in the lower stack 14. In some embodiments, an intermediate region 62 is located between the first stack 14 and the second stack 16, and the interconnect 58 is routed to extend laterally within this interconnect region such that the interconnect runs from a location 59 directly below the second opening 56 to another location 61 directly above the first opening 54.

[0078] Reference above Figures 5 to 9 The described configuration may have sense amplifier circuits and word line driver circuits associated with the base 12. The sense amplifier circuits and word line driver circuits may be provided in any suitable arrangement. Fig.10 An example arrangement is described. This example arrangement includes repeated blocks (where an example block is identified as block 63). Each block includes digit lines (where two example digit lines are identified as DL0 and DL1). As shown, some of the digit lines are coupled to the SA-E circuit, while other digit lines are coupled to the SA-O circuit. Each block also includes word lines (where example word lines are identified as WL1 and WL2). Some of the word lines extend from the word line driver circuit of the block containing the word lines, while other word lines extend from the word line driver circuit of an adjacent block.

[0079] The illustrated embodiment shows socket regions 64 along the edges of the tiles, where such socket regions enable interconnects to be routed along the edges of the circuitry associated with the tiles.

[0080] The twist region 44 is schematically shown relative to the tile. The twist region will be within the memory circuitry disposed above the tile, but is schematically shown within the tile to help the reader understand the possible relative locations of the sense amplifier circuitry and word line driver circuitry relative to the twist region. Fig.10 In the illustrated application, the even and odd sense amplifier circuits (SA-E and SA-O) within the block are along the same side of the twist region 44 and are laterally spaced apart from each other. Figure 5 As described, twist region 44 may include both first vertical extension 40c of real digit line DL1 and may include second vertical extension 42c of complementary digit line DL1*. Thus, first sense amplifier circuit and second sense amplifier circuit may be on the same side of first vertical extension 40c and second vertical extension 42c.

[0081] exist Fig.10In the illustrated embodiment of FIG. 1 , the word line driver circuit (SWD) is laterally offset relative to the sense amplifier circuit. In some embodiments, the word line driver circuit can be considered to be within a second region of the substrate 12, while the sense amplifier circuit can be considered to be within a first region of the substrate. The second region is laterally offset from the first region. In some embodiments, at least some of the first region and the second region can be directly below the first memory cell and the second memory cell of the first memory array and the second memory array, as described above with reference to FIG. Figure 4 described.

[0082] Fig.11 shows a similar Figure 5 However, the second digit line shown includes a second real digit line DL0 and a second complementary digit line DL0*, which are coupled to each other via the SA-E circuit 26. The first side opening container 50a and the second side opening container 50b are opposite to each other instead of facing each other as in Figure 5 facing each other as in the configuration of .

[0083] Fig.11A Similar to the above Figure 5A The view of the view utilized in the Fig.11 Component 10.

[0084] Fig.12 shows a method similar to that described above. Figure 8 The method described is modified Fig.11 10 to enable a pair of openings 54 and 56 to be formed in the stacks 14 and 16, with the opening 56 being directly above the opening 54. An interconnect 58 is shown passing through the openings 56 and 54 and coupling a power supply 60 with the sense amplifier circuit 28.

[0085] Fig.13 shows a method similar to that described above. Fig. 9 Modification of the described method Fig.11 10. The window 56 in the upper stack 16 is laterally offset relative to the window 54 in the lower stack 14. Thus, the interconnect 58 passes through the window 56 to a location 59 within the intermediate region 62 between the stacks, then extends laterally along this intermediate region to a location 57 directly above the opening 54, and then extends through the opening 54 to couple with the sense amplifier circuit 28.

[0086] Reference above Figures 11 to 13 The described configuration may have sense amplifier circuits and word line driver circuits associated with the base 12. The sense amplifier circuits and word line driver circuits may be provided in any suitable arrangement. Fig.14An example arrangement is described. This example arrangement includes repeated blocks (wherein an example block is identified as block 63). Each block includes digit lines (wherein two example digit lines are identified as DL1 and DL2). As shown, some of the digit lines are coupled to the SA-E circuit, while other digit lines are coupled to the SA-O circuit. Each block also includes word lines (wherein example word lines are identified as WL1 to WL4). Some of the word lines extend from the word line driver circuit of the block containing the word lines, while other word lines extend from the word line driver circuit of an adjacent block. The term "edge-only block" is used to schematically indicate areas where digit lines do not have a noise cancellation relationship with other digit lines, where such areas are used only for comparison purposes, rather than for comparison purposes and noise cancellation purposes.

[0087] The illustrated embodiment shows socket regions 64 along the edges of the tiles, where such socket regions enable interconnects to be routed along the edges of the circuitry associated with the tiles.

[0088] The twist region 44 is schematically shown relative to the tile. The twist region will be within the memory circuitry disposed above the tile, but is schematically shown within the tile to help the reader understand the possible relative locations of the sense amplifier circuitry and word line driver circuitry relative to the twist region. Fig.14 In the illustrated application of FIG. 4 , the even-numbered sense amplifier circuits (SA-E) within the block are along one side of the twist region 44, while the odd-numbered sense amplifier circuits (SA-O) within the block are along the opposite side of the twist region 44. In other words, Fig.14 The arrangement shown can be considered to correspond to the following application: Fig.11 The first sense amplifier circuit (eg, SA-O) is arranged along a first side of the twist region 44 in the block 63 below the twist region, and Fig.11 A second sense amplifier circuit (e.g., SA-E) is provided along a second side of the twist region 44 shown within the block 63 below the twist region; wherein the second side is in an opposing relationship to the first side. Fig.11 As described, the twist region 44 may include a first vertical extension 40c of the real digit line DL1 and may include a second vertical extension 42c of the complementary digit line DL1*. Thus, the first sense amplifier circuit and the second sense amplifier circuit may be on opposite sides of the first vertical extension 40c and the second vertical extension 42c relative to each other.

[0089] exist Fig.14In the illustrated embodiment of FIG. 1 , the word line driver circuit (SWD) is laterally offset relative to the sense amplifier circuit. In some embodiments, the word line driver circuit can be considered to be within a second region of the substrate 12, while the sense amplifier circuit can be considered to be within a first region of the substrate. The second region is laterally offset from the first region. In some embodiments, at least some of the first region and the second region can be directly below the first memory cell and the second memory cell of the first memory array and the second memory array, as described above with reference to FIG. Figure 4 described.

[0090] Used to form Figure 5 and 11 The various imprints (pattern etchings) of the digit lines shown may be along any suitable block, and in some embodiments, may be along the lines used to form Figure 5 and Fig.11 The word lines 32 are divided into blocks.

[0091] Although the embodiments described herein indicate two memory stacks (14, 16) above the substrate 12, it should be understood that in other embodiments there may be more than two memory stacks above the substrate.

[0092] The components and structures discussed above may be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a variety of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting devices, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0093] Unless otherwise stated, the various materials, substances, compositions, etc. described herein may be formed by any suitable method, now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0094] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In this disclosure, the terms are considered synonymous. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language changes in the disclosure to simplify the premise basis in the following claims and is not intended to indicate any significant chemical or electrical differences.

[0095] The terms "electrically connected" and "electrically coupled" may both be utilized in this disclosure. The terms are considered synonyms. The use of one term in some cases and the other in other cases may provide language variation in this disclosure to simplify the premise basis in the following claims. The terms "couple, coupling, coupled, etc." may refer to an electrical connection.

[0096] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the claims below are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0097] Unless otherwise indicated, cross-sectional views of the drawings only show features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0098] When a structure is referred to as being "on," "adjacent to," or "abutting against" another structure, it can be directly on the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly abutting against" another structure, there are no intervening structures present. The terms "directly below," "directly over," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0099] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may extend substantially orthogonally relative to an upper surface of the base, or may extend non-orthogonally.

[0100] In accordance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, since the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims should be given the full scope in a literal sense and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated component comprising: a substrate including a sense amplifier circuit; a first stack overlying the substrate; a second stack, the second stack being above the first stack; a first real digital line having a first region along the first stack and having a second region along the second stack; a first complementary digit line having a first region along the first stack and having a second region along the second stack; comparing the first true digit line with the first complementary digit line via the sense amplifier circuit; as well as a second digit line having a first region along the first stack and laterally adjacent to the first region of the first complementary digit line, and a second region along the second stack and laterally adjacent to the second region of the first true digit line.

2. An integrated component according to claim 1, wherein the second digital line is a second real digital line, and the integrated component also includes a second complementary digital line; the second complementary digital line has a first region, the first region is along the first stack and laterally adjacent to the first region of the first real digital line, and the second complementary digital line has a second region, the second region is along the second stack and laterally adjacent to the second region of the first complementary digital line.

3. The integrated component of claim 2, wherein the second complementary digit line is oppositely coupled to the second true digit line.

4. The integrated component of claim 2, wherein the second complementary digit line is not oppositely coupled to the second true digit line.

5. The integrated component of claim 2, wherein a word line extends from memory cells of the first region along the second true digit line to memory cells of the first region along the first complementary digit line.

6. The integrated component of claim 2, wherein a word line extends from memory cells of the second region along the second true digit line to memory cells of the second region along the first true digit line.

7. The integrated component of claim 2, wherein a word line extends from memory cells of the second region along the second complementary digit line to memory cells of the second region along the first complementary digit line.

8. The integrated component of claim 2, wherein a word line extends from memory cells of the first region along the second complementary digit line to memory cells of the first region along the first true digit line.

9. An integrated component according to claim 2, wherein the second real digital line and the second complementary digital line are configured as a first side opening container and a second side opening container, respectively; wherein the first side opening container and the second side opening container respectively have a first opening and a second opening extending therein.

10. The integrated assembly of claim 9, wherein the first opening and the second opening of the first side opening container and the second side opening container face each other.

11. The integrated assembly of claim 9, wherein the first opening and the second opening of the first side opening container and the second side opening container face away from each other.

12. An integrated assembly comprising: a substrate including a first sense amplifier circuit and a second sense amplifier circuit; a first stack of layers, the first stack of layers being over the substrate; The first stack includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells; a second stack, the second stack being above the first stack; the second stack including a second portion of the first array of the first memory cells and including a second portion of the second array of the second memory cells; a first real digital line associated with the first array, the first real digital line having a first region associated with the first stack and having a second region associated with the second stack; a first complementary digit line associated with the second array, the first complementary digit line having a first area associated with the first stack and having a second area associated with the second stack; and relatively comparing the first real digit line to the first complementary digit line via the first sense amplifier circuit; a second real digit line associated with the first array, the second real digit line having a first region laterally adjacent to the first region of the first complementary digit line, and the second real digit line having a second region laterally adjacent to the second region of the first real digit line; as well as A second complementary digit line associated with the second array has a first region laterally adjacent to the first region of the first real digit line and a second region laterally adjacent to the second region of the first complementary digit line.

13. The integrated component of claim 12, wherein a word line extends from memory cells of the first region along the second true digit line to memory cells of the first region along the first complementary digit line.

14. The integrated component of claim 12, wherein a word line extends from memory cells of the second region along the second true digit line to memory cells of the second region along the first true digit line.

15. The integrated component of claim 12, wherein a word line extends from memory cells of the second region along the second complementary digit line to memory cells of the second region along the first complementary digit line.

16. The integrated component of claim 12, wherein a word line extends from memory cells of the first region along the second complementary digit line to memory cells of the first region along the first true digit line.

17. The integrated assembly of claim 12, wherein: a vertically extending section extending from the first region of the first real digital line to the second region of the first real digital line; The first sense amplifier circuit is laterally offset to a first side of the vertically extending segment; and The second sense amplifier circuit is laterally offset to a second side of the vertically extending segment, wherein the second side is in opposing relationship to the first side.

18. The integrated assembly of claim 17, wherein: The vertical extension section is a first vertical extension section; a second vertically extending segment extending from the first region of the first complementary digit line to the second region of the first complementary digit line; the first sense amplifier circuit being laterally offset to a first side of the second vertically extending segment; and The second sense amplifier circuit is laterally offset to a second side of the second vertically extending segment.

19. The integrated assembly of claim 18, wherein: word lines extend from memory cells along the first true digit line and the first complementary digit line to memory cells along the second true digit line and the second complementary digit line; A word line driver circuit is coupled to the word line; the first sense amplifier circuit and the second sense amplifier circuit are along the first region of the substrate; the word line driver circuit being along a second region of the substrate, the second region being laterally offset from the first region of the substrate; and At least some of the first and second regions are located directly below the first and second memory cells of the first and second arrays.

20. The integrated assembly of claim 12, wherein: a first vertically extending segment extending from the first region of the first real digital line to the second region of the first real digital line; a second vertically extending segment extending from the first region of the first complementary digit line to the second region of the first complementary digit line; and The first sense amplifier circuit and the second sense amplifier circuit are each laterally offset to a first side of the second vertically extending segment.

21. The integrated assembly of claim 20, wherein: word lines extend from memory cells along the first true digit line and the first complementary digit line to memory cells along the second true digit line and the second complementary digit line; A word line driver circuit is coupled to the word line; The first sense amplifier circuit and the second sense amplifier circuit are along a first region of the substrate; the word line driver circuit being along a second region of the substrate, the second region being laterally offset from the first region of the substrate; and At least some of the first and second regions are located directly below the first and second memory cells of the first and second arrays.

22. The integrated component of claim 12, wherein the second complementary digit line is oppositely coupled to the second true digit line.

23. The integrated component of claim 12, wherein the second complementary digit line is not oppositely coupled to the second true digit line.

24. The integrated assembly of claim 12, wherein: The first region of the second real number line is along a first end portion of the second real number line; the second region of the second real number line is along an opposite second end of the second real number line; a first vertically extending segment extending between the first end and the second end of the second real digital line; The first region of the second complementary digit line is along a first end portion of the second complementary digit line; The second region of the second complementary digit line is along an opposing second end of the second complementary digit line; and A second vertically extending segment extends between the first end and the second end of the second complementary digit line.

25. The integrated assembly of claim 24, wherein: The second real number line is shaped as a first laterally open container, wherein the first laterally open container has a first closed end corresponding to the first vertically extending section and has a first open end in opposing relationship to the first closed end; and The second complementary digit line is shaped as a second laterally open container, wherein the second laterally open container has a second closed end corresponding to the second vertically extending segment and has a second open end in opposing relationship to the second closed end.

26. The integrated assembly of claim 25, wherein the first open end and the second open end face each other.

27. The integrated assembly of claim 25, wherein the first open end and the second open end face away from each other.

28. An integrated assembly comprising: a substrate including a sense amplifier circuit; a first stack of layers, the first stack of layers being over the substrate; The first stack includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells; a second stack, the second stack being above the first stack; the second stack including a second portion of the first array of the first memory cells and including a second portion of the second array of the second memory cells; a first set of real digit lines and complementary digit lines, the first set being associated with the first array and the second array; the real digit lines in the first set being oppositely coupled to the complementary digit lines in the first set through the first set of sense amplifier circuits; a second set of true digit lines and complementary digit lines, the second set being associated with the first array and the second array; the true digit lines in the second set being oppositely coupled to the complementary digit lines in the second set through the second set of sense amplifier circuits; The real digit lines in the second set have a first region laterally adjacent to the first region of the complementary digit lines in the first set and have a second region laterally adjacent to the second region of the real digit lines in the first set; The complementary digit lines in the second set have a first region laterally adjacent to the first region of the real digit lines in the first set and have a second region laterally adjacent to the second region of the complementary digit lines in the first set; a first opening through the first laminate and a second opening through the second laminate; as well as An interconnect extends from a power source to one of the sense amplifier circuits; the interconnect extends through the first opening and the second opening.

29. The integrated assembly of claim 28, wherein: The real number lines in the second set are configured as laterally open first containers, wherein the first containers have a first open edge; The complementary digit lines in the second set are configured as a laterally open second container, wherein the second container has a second open edge; and The first opening edge and the second opening edge face each other.

30. The integrated assembly of claim 28, wherein: The real number lines in the second set are configured as laterally open first containers, wherein the first containers have a first open edge; The complementary digit lines in the second set are configured as a laterally open second container, wherein the second container has a second open edge; and The first opening edge and the second opening edge face away from each other.

31. The integrated assembly of claim 28, wherein the second opening is located directly above the first opening.

32. The integrated assembly of claim 28, wherein the second opening is not located directly above the first opening.

33. An integrated component according to claim 32, wherein an intermediate region is located between the first stack and the second stack, and wherein the interconnect extends laterally along this intermediate region to travel from a position directly below the second opening to another position directly above the first opening.

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