Circuitry for verifying the contents of a register

Abstract

Embodiments of the present disclosure relate to circuits for verifying the contents of a register. According to an embodiment, a method verifies the contents of a plurality of registers having two first registers, wherein each register in the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether the value of the verification bit of each corresponding register in the plurality of registers corresponds to the data word of its corresponding register. The data words stored in the two first registers are selected so that the bits of the same column of the two registers include two complementary bits, each bit of a common binary word is associated with a corresponding register in the plurality of registers, and the value of the verification bit of each corresponding register depends on the data word of the corresponding register and the bit of the common binary word associated with the corresponding register.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Patent Application No. 2003541, filed on April 8, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly to devices including circuitry for verifying the contents of a register. Background Art

[0004] A register is a volatile memory, usually located inside a digital processor. A register is usually used to temporarily store a word of data. It can be an instruction (operator), a variable (operand), or a control signal.

[0005] For example, in the case of a vehicle, the registers may contain information such as a value representing the level of closure of a window or information related to the operation of the vehicle (speed, motor temperature, etc.).

[0006] Therefore, it is important to ensure that this information is correct and reliable and has not been accidentally modified (e.g. by cosmic radiation), particularly in order to ensure the safety of users. Summary of the invention

[0007] One embodiment provides a device comprising: at least two first registers, each of which contains a data word and a verification bit; and a first circuit configured to determine whether the verification bit of each register corresponds to the data word of the register, the data word of the first register being selected so that bits in the same column of the first register include two complementary bits.

[0008] Another embodiment provides a method, for each register between at least two first registers, each first register includes a data word and a verification bit, wherein a step is for the circuit to determine whether the verification bit of each register corresponds to the data word of the register, and the data word of the first register is selected so that bits in the same column of the first register include two complementary bits.

[0009] According to an embodiment, the device comprises at least one second register, each second register containing a data word and a validation bit.

[0010] According to an embodiment, the device comprises a second circuit configured to periodically transfer the contents of all registers to the first circuit one after the other.

[0011] According to an embodiment, each verification bit is obtained when written into the corresponding register by applying a first function to a data word of said register.

[0012] According to an embodiment, the first circuit is configured to apply a first function to the data word contained in each register and to compare the result with a validation bit contained in said register.

[0013] According to an embodiment, a common binary word is associated with all registers, the common word comprising bits associated with each register, the value of a validation bit of each register depending on the data word of said register and on the value of the bits of the common word associated with said register.

[0014] According to an embodiment, the first function includes a second function and a third function, and the second function is applied to a result of the third function.

[0015] According to an embodiment, each register is coupled to a circuit configured to perform a write into the register through a third circuit configured to apply a second function to the value of the verification bit, the second function depending on the value of the bit of the common word associated with the register.

[0016] According to an embodiment, the second function is an XOR type function.

[0017] According to an embodiment, if the bit associated with the register has a first value, the third bit is a direct electrical connection, and if the bit associated with the register has a second value, the third circuit is an inverter.

[0018] According to an embodiment, the first circuit is configured to: apply a functional inverse of a second function to a verification bit; apply the first function to a data word contained in the register; and compare the results.

[0019] According to an embodiment, the first circuit includes a fourth circuit configured to apply a third function to a data word contained in a register; a fifth circuit configured to apply an XOR-type function to receive as input a verification bit of the register and a bit of a common word associated with the register; and a sixth circuit configured to apply an XOR-type function to receive as input an output of the fourth circuit and an output of the fifth circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above features and advantages as well as other features and advantages will be described in detail in the following description of specific embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 illustrates schematically and partially an embodiment of an electronic device including circuitry for verifying the contents of a register; and

[0022] Figure 2 Further details are shown Figure 1 part of. DETAILED DESCRIPTION

[0023] Similar features are designated by similar reference numerals in the various drawings. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions and material properties.

[0024] For the sake of clarity, only the operations and elements that are helpful for understanding the embodiments described herein are described and illustrated in detail.

[0025] Unless otherwise specified, when referring to two elements being connected together, this refers to a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this refers to the two elements may be connected or may be coupled via one or more other elements.

[0026] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "up", "down", "high", "low", etc.) or direction qualifiers (such as "horizontal", "vertical", etc.), reference is made to the direction shown in the accompanying drawings.

[0027] Unless otherwise specified, "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0028] Figure 1 Schematically and partially illustrated is an embodiment of an electronic device 100 comprising circuitry for verifying the contents of a register. The device 100 is, for example, a vehicle control system.

[0029] According to an embodiment, the device 100 comprises an authentication register 16. The register 16 is a register dedicated to the authentication process and its content has no influence on the functions controlled by the device 100. The device 100 comprises at least two authentication registers 16, preferably exactly two registers 16, such as Figure 1 shown.

[0030] Each register 16 comprises a first portion 16a in which a binary word VIR1, VIR2 is stored. For example, each word VIR1, VIR2 has a size greater than or equal to 8 bits, for example equal to 32 bits.

[0031] Preferably, the binary words VIR1 , VIR2 do not change value during operation of the device 100 and form a reference word in some way.

[0032] The binary words of register 16 are preferably selected so that each position of first portion 16a has all possible values ​​in at least one of binary words VIR1, VIR2. In other words, the binary words of register 16 are selected so that bits of the same column of register 16 comprise at least two complementary bits.

[0033] Thus, each position or each column of bits of the first portion 16 a has a value of '1' in at least one verification register 16 and a value of '0' in at least one verification register 16 .

[0034] For example, one of the registers 16 contains a word consisting entirely of '0's in the first portion 16a, while the other register 16 contains a word consisting entirely of '1's in the first portion 16a.

[0035] Preferably, one of the registers 16 contains an alternation of '1' and '0' starting from '0' in the first portion 16a, and the other of the registers 16 contains an alternation of '1' and '0' starting from '1' in the first portion 16a.

[0036] Each register 16 comprises a second portion 16b in which verification bits VPAR1, VPAR2, for example parity verification bits, are stored.

[0037] Each verification bit VPAR1, VPAR2 is obtained by applying a function f to the binary word written in the first part of the corresponding register. For example, function f comprises a first function f1 applied to the data word we wish to store in the register and a second function f2 applied to the result of function f1.

[0038] Function f1 is, for example, a common function enabling verification bits to be obtained from a data word. Function f1 is, for example, a function enabling parity bits to be obtained. According to another example, function f1 is an error correction code (e.g., a Hamming code), a signature function or more generally any function whose result depends on the state of a bit of a data word.

[0039] The information contained in the register 16, ie the data words VIR1, VIR2 and the verification bits VPAR1, VPAR2, are preferably hard-coded during formation of the device, meaning fixed in an immutable manner.

[0040] The device 100 further comprises a central processing unit (CPU) 12 or processor 12. The unit 12 is, for example, configured to control functions of the device 100 (not shown).

[0041] The device 100 further comprises at least one register 14. The three registers 14 are as follows: Figure 1 as shown in .

[0042] Each register 14 includes a first portion 14a in which data words REG1, REG2, REG3 are stored. Each data word REG1, REG2, REG3 forms a piece of information stored in the register. Each data word forms a piece of information that needs to be verified. Each data word REG1, REG2, REG3 is a binary word. For example, each data word has a size greater than or equal to 8 bits (for example, equal to 32 bits). Preferably, all data words REG1, REG2, REG3 have the same size. Preferably, the binary words VIR1, VIR2 of register 16 have the same size as the data words of register 14.

[0043] Each register 14 includes a second portion 14b in which verification bits PAR1, PAR2, PAR3 (eg, parity bits) are stored.

[0044] The verification bits are typically obtained by applying a function f to the data word that is desired to be stored in the register.

[0045] Function f means that the combination of functions f1 and f2 is applied, for example, by a logic circuit. For example, functions f1 and f2 are applied by the same circuit 24. For example, one circuit 24 is coupled between each register 14 and unit 12.

[0046] Alternatively, the function f is applied, for example by the unit 12, to the data word that needs to be stored in the register.

[0047] Thus, during writing to one of the registers 14, the unit 12 provides the data word, for example, to the circuit 24 associated with the register, and the circuit 24 applies the function f1 to the data word and then applies the function f2 to the data word. The result of the function f2 is the verification bit and is written to the second part 14b of the register. In parallel, the data word is preferably written to the first part of the register without modification.

[0048] According to an embodiment, the information contained in the register 14, i.e. the data words REG1, REG2, REG3 and the verification bits PAR1, PAR2, PAR3, is at least partially generated by the unit 12 and written into the register 14. The contents of the register are written, for example, based on the contents of a non-volatile memory or are generated by a circuit (not shown).

[0049] A common binary word is associated with the assembly formed by the registers 14 and 16 of the device 100. The binary word preferably comprises at least as many bits as the device 100 comprises registers 14 and 16. Each register 14 and 16 is associated with a bit of the common word. Figure 1In the example of , the common word includes 5 bits, which are associated with registers REG1, REG2, REG3, VIR1 and VIR2 respectively. The common word is, for example, quasi-random. The common word is, for example, continuously generated or transmitted by circuit 22. Circuit 22 is, for example, a linear feedback shift register (LSFR). The common word includes at least one value '1' and at least one value '0'. Therefore, the common word is not completely formed by bits with the same value.

[0050] The device 100 comprises an error detection circuit (COMP) 20. Preferably, the device 100 comprises a unique error detection circuit 20. Thus, the contents of the registers 14 and 16 are checked by the same circuit 20.

[0051] The contents of registers 14 and 16 are sequentially passed to circuit 20 via circuit 18 (MUX). Circuit 18 is, for example, a multiplexer. Circuit 18 is coupled (preferably connected) to all registers 14 and 16 at its input. Circuit 18 is coupled (preferably connected) to circuit 20 at its output. Circuit 18 comprises, for example, an output having a data word of a selected register passed to the output, and another output having a bit contained in a second portion of the selected register passed to the other output. The information (i.e., the data word and the verification bit) is passed to circuit 20 to be verified.

[0052] The circuit 18 is also coupled (preferably connected) at its input to a circuit 19 (CNT). The circuit 19 is configured to pass a control signal to the circuit 18, which determines to which register the content to be passed to the circuit 20 belongs. The circuit 19 receives as input a clock signal CLK. The circuit 19 is, for example, a counter. The circuit 19 is configured so that the content of all registers is cyclically passed to the circuit 20.

[0053] The order in which the registers are associated with the bits of the common word is the same as the order in which the contents of the registers are transferred by circuit 18 to circuit 20 .

[0054] Circuit 22 is synchronized by the same clock signal CLK as circuit 19. Thus, circuit 19 delivers a signal controlling the transfer of the contents of one of the registers, and circuit 22 delivers the bits of the common word corresponding to that register before (e.g., during the same edge of signal CLK) delivering a signal controlling the transfer of the contents of the next register.

[0055] The function f2 of each circuit 24 or the result of function f2 depends on the value of the bit of the common word associated with the register corresponding to the circuit 24. Therefore, the value contained in the second part of each register represents the associated bit of the data word and the common word. For example, if the bit of the common word has a first value, function f2 corresponds to the first operation, and if the bit of the common word has a second value, function f2 corresponds to the second operation. For example, if the bit of the common word has a first value, function f2 is an identity function, that is, the result of function f2 is equal to the result of function f1; if the bit of the common word has a second value, function f2 is a function inversion, that is, the result of function f2 is the function inversion or complement of the result of function f1. The inverse of a bit with a value of '1' is a bit with a value of '0', and the inverse of a bit with a value of '0' is a bit with a value of '1'.

[0056] In other words, function f2 corresponds, for example, to an exclusive-OR type function applied to the associated bits of the common word and to the value generated by function f1.

[0057] Function f2 has a function inverse f2'. The value to which the function is applied is a binary value and function f2' is a complement function, in other words, according to the following function:

[0058]

[0059]

[0060] Thus, the result of function f2' applied to the result of function f2 is the value (x) to which the function is applied. The application of function f2' to function f2 corresponds to the identity function, in other words to f2'(f2(x))=x.

[0061] Preferably, the common word is known at the manufacture of the device 100. The circuit 24 can then be different depending on the value associated with each register, so that the function f2 is also different. For example, if the bit associated with the register has a first value, the corresponding circuit 24 is a circuit (e.g., electrically connected) that outputs the same binary value as the binary value at the input, and if the bit associated with the register has a second value, the corresponding circuit 24 is an inverter.

[0062] According to certain standards, such as the ISO 26262 standard on functional safety of road vehicles, register verification comprises two levels. The first level corresponds to the verification of the register content. The second level corresponds to the verification of the operation of the verification element. In practice, if the data word is correct, but the error detection circuit comprises a fault, the error may be detected incorrectly. In another more problematic case, if the data word comprises a fault, for example caused by cosmic radiation, and the detection circuit comprises a complementary fault, the two faults may compensate each other. As a result, the error in the data word will not be detected. It is therefore important to be able to detect faults, regardless of whether they originate from another level.

[0063] Figure 2 An example of circuit 20 is shown in further detail in . Circuit 20 is coupled (preferably connected) at its input to the output of circuit 18 and to circuit 22. Circuit 20 is coupled (preferably connected) at its output to memory 26 (MEM), for example.

[0064] The circuit 20 is configured such that, when it receives via the circuit 18 the contents of the first and second parts of the register 14 or 16 and, via the circuit 22, the bits of the common word associated with said register:

[0065] a') applies the function f1 to the contents of the first part of the register,

[0066] b') applying a function f2' to the contents of the second part of the register, the function f2' depending on the bits of the common word associated with the register, and

[0067] c') comparing the results of steps a') and b').

[0068] Steps a') and b') are, for example, performed in parallel.

[0069] If the result of step c') indicates that the results are identical, in other words, if the verification bit corresponds to the data word, the output signal of the circuit 20 takes a first value. If the result of step c') indicates that the results are different, in other words, if the verification bit does not correspond to the data word, the output signal of the comparator takes a second value. The first value of the output signal indicates that the data word corresponds to the stored word, and therefore the stored information is correct. The second value of the output signal indicates that the data word does not correspond to the expected original value, and therefore there is an error.

[0070] Thus, during operation of device 100, at a first time, circuit 19 passes a signal associated with one of registers 14 or 16 to circuit 18. Circuit 18 obtains the contents of the first and second parts of the register (e.g., data word REG1 and verification bit PAR1). The contents are passed at the output of circuit 18. Thus, circuit 20 receives the contents of the first and second parts of the register as input. Circuit 20 further receives the bits of the common word associated with the register at its input. Circuit 20 performs steps a'), b') and c') described previously. The output signal generated by circuit 20 can determine whether the data word of the register is correct. If not, the system of the integrated device will take measures that are applicable to the case where invalid data is not considered. For example, system reset, entry into degraded mode, etc.

[0071] At a second time, circuit 19 passes the signal associated with the next register 14 or 16 to circuit 18. Circuit 18 obtains the content of the first and second parts of the register (e.g., data word ReG2 and verification bit PAR2). The output signal of circuit 20 is generated in the same way as in the case of the previous register. For the output signal of circuit 20 associated with the first register to be generated before the second time, the second time is preferably far enough from the first time. The second time corresponds, for example, to an edge (e.g., a rising edge) of the clock signal CLK after the first time.

[0072] Similarly, the same verification method is applied to all registers one by one. For example, during each edge (e.g., rising edge) of the clock signal, the verification method is applied to the following registers. Thus, the registers are checked at each clock cycle. Once all registers are verified, the method is executed again on the first register. Thus, the contents of the registers are continuously verified.

[0073] The application of the verification method for each register is preferably fast. The duration between the verification of two consecutive registers is, for example, shorter than 200ms (preferably shorter than 50ms). Preferably, the duration between the verification of two consecutive registers is such that all registers can be verified within a fault-tolerant time interval. For example, this time interval is 200ms, which corresponds to the requirements of the ISO 26262 standard.

[0074] The continuous verification of the registers, in particular the register 14 , makes it possible to determine errors that occur in a data word when writing the word or during storage.

[0075] Verification of the contents of register 16 enables determination of whether the circuits located downstream of the register (i.e., on the path between the register and circuit 20) are functioning properly, which corresponds to a second verification level. For example, verification of register 16 enables determination of whether there are potential faults in the circuits downstream of the register. The term potential fault refers, for example, to one of the circuits or connections that transmit the contents of the register not sending one or more bits correctly. For example, a potential fault in circuit 18 may cause the output signal to always have one bit (e.g., the third bit) at the same value (e.g., value '0'). Therefore, in this example, the third bit of the word received by circuit 20 has a value of '0' regardless of what the word is that is sent.

[0076] Assuming that each bit of the reference word to be transmitted has a value of '1' in a register 16 and a value of '0' in another register 16, it can be determined whether the bits of the reference word are blocked at the same value.

[0077] For example, consider the case where the bits of a given column of the first register 16 have a value of '1' and the bits of the same column of the second register 16 have a value of '0'. If an error in the device causes the bits of the column to still have a value of '1' when the contents of the register are transferred to the circuit 20, then when verifying the second register 16, the circuit 20 will detect that the value of the bits of the given column does not have a value of '0', but has a value of '1'. If an error in the device causes the bits of the column to still have a value of '0' when the contents of the register are transferred to the circuit 20, then when verifying the first register 16, the circuit 20 will detect that the value of the bits of the given column does not have a value of '1', but has a value of '0'.

[0078] When an error is detected, circuit 19 can, for example, pass the value of a control signal of circuit 18 to unit 12. It is thus known in which register the error occurred. The reaction of device 100 when an error is detected can, for example, differ depending on the register in which the error was detected.

[0079] The use of the common word in content verification can determine whether circuits 18, 19, and 22 are functioning properly and whether all registers 14 and 16 are verified in a prescribed order. In practice, circuits 19 and 22 are configured to generate control signals of circuit 18 corresponding to a register and bits of the common word corresponding to the register, respectively, so that circuit 20 can verify the contents of the register using bits of the common word associated with the register.

[0080] Circuits 18, 19, and 22 may not function properly. For example, circuit 19 may skip values. In other words, circuit 18 may not pass the content of one of the registers in the loop. Therefore, the register whose content is transferred to circuit 20 does not correspond to the bits of the common word transferred by circuit 22. Therefore, there will be an offset between the content transferred and the bits of the common word transferred to circuit 20. If two consecutive bits of the common word are equal, this offset will not be detected. However, if two consecutive bits of the common word are different, circuit 20 will detect an error.

[0081] For example, it can be considered that Figure 2 The common word associated with registers 14 and 16 is 00110. Therefore, the bits of the common word associated with the first register, the second register, the third register, the fourth register and the fifth register, respectively, contain the words REG1, REG2, REG3, VIR1, VIR2, respectively, with the values ​​'0', '0', '1', '1', '0'. It can be further considered that circuit 19 erroneously does not pass the signal controlling the transmission of the contents of the first register, but passes the signal controlling the transmission of the contents of the second register. Therefore, circuit 20 receives the contents of the second register and the bits of the common word of the first register. Since the bits of the common words associated with the first register and the second register are equal, the error is not detected. Thereafter, circuit 19 passes the signal controlling the transmission of the contents of the next register (i.e., the third register) to circuit 20. Circuit 22 passes the next bit of the common word (i.e., the bit associated with the second register) to circuit 20. Therefore, circuit 20 receives the contents of the third register and the bits of the common word associated with the second register. Since the bits of the common word associated with the second and third registers are different, circuit 20 detects an error.

[0082] According to an embodiment, the bits of the common word associated with the verification register are equal, preferably equal to the value for which the function f2 is an identity function. Each verification bit VPAR1, VPAR2 is then obtained by applying the function f1 to the binary word written into the first part 16a of the register. The function f2 is not applied. Therefore, the second part 16b is not coupled to the unit 12 via the circuit 24.

[0083] The described device 100 can be easily associated with other elements of data verification. For example, the circuit 100 may include a circuit 28 (CRC, Figure 1 ), the circuit 28 is configured to detect transmission or transfer errors. The circuit 28 is, for example, a cyclic redundancy check.

[0084] Figure 2 Further details are shown Figure 1 part of.

[0085] Circuit 20 comprises circuit 50 configured to apply function f1. Circuit 50 receives as input the contents of first part 14a or 16a of register 14 or 16. Circuit 50 performs a bit-by-bit summation of bits of a data word, for example using circuitry applying an exclusive-OR type function.

[0086] Circuit 20 further includes a circuit 52 for applying function f2' according to the bit of the common word. Circuit 52 receives as input the verification bit of the register and the bit of the common word associated with the register. For example, the circuit is an XOR gate. Therefore, if the bit of the common word has a first value ('0'), function f2' is an identity function, and the output has the value of the verification bit. If the bit of the common word has a second value ('1'), function f2' is an inversion function or a complementary function.

[0087] Circuit 20 includes circuit 54 configured to determine whether the outputs of circuits 50 and 52 are the same. Circuit 54 is, for example, a circuit that applies an XOR-type function. Circuit 54 is, for example, an XOR-type logic gate.

[0088] An advantage of the described embodiments is that they allow detecting the content of registers and verifying errors in the operation of components.

[0089] Another advantage of the described embodiments is that they are able to ensure that all registers have been verified.

[0090] Another advantage of the described embodiments is that they include a single error detection circuit 20 for all registers 14 and 16. In some embodiments, all or part of the disadvantages of known circuits for verifying the contents of registers are addressed or mitigated.

[0091] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined and other variations will readily occur to those skilled in the art.

[0092] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. An electronic device, comprising: a plurality of registers, including two first registers, each register of the plurality of registers being configured to store a data word and a validation bit; a first circuit configured to determine whether the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register, wherein the data words stored in the two first registers are selected such that bits of the same column of the two first registers include two complementary bits; and a common word circuit coupled to the first circuit, the common word circuit being configured to output a common binary word, wherein each bit of the common binary word is associated with a corresponding register of the plurality of registers, and a value of the verification bit of each corresponding register depends on the data word of the corresponding register and the bit of the common binary word associated with the corresponding register. 2 . The electronic device according to claim 1 , wherein the plurality of registers further comprises at least one second register.

3. The electronic device according to claim 2, further comprising: A second circuit has an input coupled to the outputs of the plurality of registers and an output coupled to the first circuit, wherein the second circuit is configured to periodically couple the output of each of the plurality of registers to the input of the first circuit. The electronic device of claim 3 , wherein the second circuit comprises a multiplexer. 5 . The electronic device of claim 3 , wherein the value of the validation bit of each respective register is based on applying a first function to the data word of its respective register.

6. The electronic device according to claim 5, wherein the first circuit comprises: The function verification circuit is configured to determine whether the verification bit of the corresponding register is related to the data word of the corresponding register according to the first function.

7. The electronic device of claim 6, wherein the first function comprises: A third function of the data word for the respective register, a second function for a result of the third function, and the bits of the common binary word associated with the respective register.

8. The electronic device according to claim 7, wherein the function verification circuit comprises: a second function circuit configured to apply the third function to the data word of the corresponding register to produce a first value; a third function circuit configured to apply an inverse of the second function to the verification bit of the corresponding register to produce a second value; as well as A comparator has an input coupled to the output of the second function circuit and the output of the third function circuit.

9. The electronic device according to claim 7, further comprising: A third circuit is coupled to an input of the at least one second register, the third circuit being configured to apply the second function and the third function to the data word of the at least one second register.

10. An electronic device according to claim 7, wherein the third function is a parity verification function, which is applied to the data word of the corresponding register, and the second function is an exclusive OR function, which is applied to the result of the parity verification function and the bits of the common binary word associated with the corresponding register.

11. The electronic device of claim 2, wherein the data words of the two first registers are permanently stored and the at least one second register is writable.

12. A method of verifying the contents of a plurality of registers, the plurality of registers comprising two first registers, each register of the plurality of registers being configured to store a data word and a verification bit, the method comprising: determining whether the value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register, wherein the data words stored in the two first registers are selected such that bits of the same column of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register. The method of claim 12 , wherein the plurality of registers further comprises at least one second register.

14. The method of claim 13, wherein determining whether the value of the validation bit of each respective one of the plurality of registers corresponds to the data word of its respective register is performed periodically on each of the plurality of registers.

15. The method of claim 13, wherein the value of the validation bit of each respective register is based on applying a first function to the data word of its respective register.

16. The method of claim 15, wherein the first function comprises: A third function of the data word for the respective register, a second function for a result of the third function, and the bits of the common binary word associated with the respective register.

17. The method of claim 16, further comprising determining whether the value of the validation bit of each respective register of the plurality of registers corresponds to the data word of its respective register, comprising: applying the third function to the data word of the corresponding register to produce a first value; applying the inverse of the second function to the validation bit of the corresponding register to produce a second value; and The first value is compared to the second value.

18. The method of claim 16, wherein the second function is an XOR function and the third function is a parity check function.

19. The method according to claim 16, further comprising: applying the first function to a first data word and bits of the common binary word associated with the at least one second register to produce a verification bit value; as well as The first data word and the verification bit value are written to the at least one second register.

20. A circuit comprising: A plurality of registers, including two first registers and at least one second register, wherein Each register of the plurality of registers is configured to store a data word and a corresponding verification bit, each bit of a data word stored in a first register of the two first registers is complementary to each bit of a data word stored in a second register of the two first registers, the value of the validation bit of each respective one of the plurality of registers being related to the data word of the respective register and to a bit of a common binary word, the bit of the common binary word being associated with the respective register, according to a first function; a multiplexer coupled to outputs of the plurality of registers; a control circuit coupled to the multiplexer, the control circuit configured to cause the multiplexer to cyclically select each output of the plurality of registers; as well as a verification circuit coupled to the output of the multiplexer, wherein the verification circuit is configured to verify, according to the first function, that the value of the verification bit for each respective one of the plurality of registers is related to the data word of the respective register and the bit of the common binary word associated with the respective register.

21. The circuit of claim 20, further comprising: A verification bit determination circuit is coupled to the input of the at least one second register, the verification bit determination circuit being configured to apply a parity verification function to the data word input of the at least one second register and to apply an XOR function to an output of the parity verification function, wherein The verification circuit is configured to apply the parity verification function to the data word output by the corresponding register to obtain a first value, apply the XOR function to the first value to produce a second value, and compare the first value to the second value.

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