Memory device and method of testing the same

Abstract

A memory device comprising a plurality of sense amplifier circuits to sense data bits in response to parallel test signals from a plurality of memory banks, a plurality of comparators to compare the data bits from each of the plurality of sense amplifier circuits to a test bit, and a logic circuit to receive output signals of the plurality of comparators and output a test result, wherein each of the plurality of comparators receives the test bit, an evolving parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bits and the test bit in response to the evolving parallel bit test (PBT) signal, at least one logic state test set signal, and the test pass signal, and passes through the respective memory bank in response to the test pass signal regardless of the test operation.

Description

[0001] Cross-references to related applications

[0002] The entire contents of Korean Patent Application No. 10-2020-0039785, entitled "Memory Device and Test Method Thereof," filed on April 1, 2020, with the Korean Intellectual Property Office, are incorporated herein by reference. Technical Field

[0003] This disclosure relates to memory devices and methods for testing them. Background Technology

[0004] Generally, Dynamic Random Access Memory (DRAM) includes Parallel Bit Test (PBT) circuitry for performing parallel tests on multiple bits. In Parallel Bit Test mode, after the same data is written to N (two or more natural numbers) memory cells, N bits of data are read simultaneously. A comparator compares the read N bits of data to determine whether the N bits pass (or "match") or fail (or "mismatch"). Based on this pass / fail result, a "1" or "0" is output as the test result data. Parallel Bit Test mode reduces the number of cycles required to access all bits to 1 / N, thus shortening the test time compared to serial testing. Summary of the Invention

[0005] The embodiment relates to a memory device, including: a plurality of sense amplifier circuits that sense data bits in response to parallel test signals from a plurality of banks; a plurality of comparators that compare data bits from each of the plurality of sense amplifier circuits with test bits; and logic circuitry that receives output signals from the plurality of comparators and outputs test results, wherein each of the plurality of comparators receives a test bit, an evolved parallel bit test (PBT) signal, at least one logic state test set signal, and a test pass signal, compares the data bits and the test bits in response to the evolved parallel bit test (PBT) signal, at least one logic state test set signal, and the test pass signal, and passes through the corresponding bank in response to the test pass signal, regardless of the test operation.

[0006] The embodiment also relates to a memory device, comprising: a first inverter connected to a first input terminal for receiving data bits read from a memory bank; a second inverter that inverts an evolved parallel bit test signal; a third inverter; a fourth inverter; a fifth inverter; a first NOR gate circuit that performs a first NOR operation on the output signal of the second inverter and the test bit, and outputs the result of the first NOR operation to the third inverter; a second NOR gate circuit that performs a second NOR operation on a first test ignore signal and a test pass signal, and outputs the result of the second NOR operation to the fourth inverter; a third NOR gate circuit that performs a third NOR operation on a second test ignore signal and a test pass signal, and outputs the result of the third NOR operation to the fifth inverter; a first NAND gate circuit that performs a first NAND operation on the output signal of the fourth inverter and the output signal of the first NOR gate circuit, and outputs the result of the first NAND operation to the second input terminal; and a second NAND gate circuit that performs a second NAND operation on the output signals of the third inverter and the fifth inverter, and outputs the result of the second NAND operation to the second inverting input terminal. AND gate circuit; a first PMOS transistor connected between a power supply terminal and a first node and having a gate connected to a first input terminal; a second PMOS transistor connected between a power supply terminal and a first node and having a gate connected to a second input terminal; a third PMOS transistor connected between a first node and a second node and having a gate connected to the output terminal of a first inverter, the second node being connected to an output terminal for outputting the result of a parallel bit test operation; a fourth PMOS transistor connected between a first node and a second node and having a gate connected to a second inverting input terminal; a first NMOS transistor connected between a second node and a third node and having a gate connected to the output terminal of a first inverter; a second NMOS transistor connected between a second node and a third node and having a gate connected to a second input terminal; a third NMOS transistor connected between a third node and a ground terminal and having a gate connected to a first input terminal; and a fourth NMOS transistor connected between a third node and a ground terminal and having a gate connected to a second inverting input terminal.

[0007] The embodiments also relate to a memory device including: a plurality of memory banks having a plurality of memory cells connected to word lines and bit lines; a row decoder that selects any word line in response to a row address; a column decoder that selects any bit line in response to a column address; a sense amplifier circuit that senses data bits from memory cells connected to selected bit lines during a parallel bit test operation; a repair control circuit that replaces faulty memory cells with redundant cells during the parallel bit test operation; and a parallel bit test circuit that receives test commands and test bits from an external device and performs the parallel bit test operation by comparing the data bits received from the plurality of sense amplifier circuits of each of the plurality of memory banks with the test bits, wherein the parallel bit test circuit passes through at least one of the plurality of memory banks, regardless of the parallel bit test operation.

[0008] The embodiments also relate to a method for testing a memory device, the method comprising: receiving a test command, test data, and bank-independent (DON'T CARE) information; performing a test operation by comparing the test data with data read from each of the plurality of banks in response to a test command in each of the plurality of banks; performing a repair operation on the banks that fail in the test operation; and, in the repair operation, using the DON'T CARE information to pass through the unrepairable banks. Attached Figure Description

[0009] The features will become clear to those skilled in the art from the detailed description of the exemplary embodiments with reference to the accompanying drawings, wherein:

[0010] Figure 1 This is a graphical example illustrating a test system 10 for testing a memory device 100 according to an exemplary embodiment;

[0011] Figure 2 This is a diagram example illustrating a memory device 100 according to an example embodiment;

[0012] Figure 3 This is a conceptual illustration of a test operation of a memory device 100 according to an example embodiment;

[0013] Figure 4 This is a schematic example illustrating a PBT circuit 190 according to an exemplary embodiment;

[0014] Figure 5 This is a diagram example illustrating a general comparator (CMP) used to perform parallel bit test operations;

[0015] Figure 6A and Figure 6B This is an example diagram illustrating the process of parallel bit testing operations on a general-purpose memory device;

[0016] Figure 7 This is a diagram example illustrating a comparator according to an example embodiment;

[0017] Figure 8A and Figure 8B This is an example diagram illustrating the process of a parallel bit test operation of a memory device 100 according to an example embodiment;

[0018] Figure 9 This is a flowchart example illustrating a test operation of a memory device 100 according to an example embodiment;

[0019] Figure 10 This is a flowchart example illustrating a test operation of a memory device 100 according to another exemplary embodiment of the present disclosure;

[0020] Figure 11A and Figure 11B This is a diagram illustrating an example of using the PBTPASS test pass signal;

[0021] Figure 12 This is a diagram example illustrating a memory chip according to an example embodiment;

[0022] Figure 13 This is a graphical example illustrating a computing system 2000 according to an example embodiment;

[0023] Figure 14 This is a diagram example illustrating a car system 3000 according to an example embodiment;

[0024] Figure 15 This is a diagram example illustrating a mobile device 4000 according to an example embodiment;

[0025] Figure 16 This is a graphical example illustrating a computing system 5000 according to an example embodiment; and

[0026] Figure 17 This is a graphical example illustrating a data center 7000 with a memory device applied according to an example embodiment. Detailed Implementation

[0027] Figure 1 This is a graphical example illustrating a test system 10 for testing a memory device 100 according to an example embodiment.

[0028] refer to Figure 1 The test system 10 may include a memory device 100 and a tester 200.

[0029] Memory device 100 can be implemented to store data. According to an example embodiment, memory device 100 may include a plurality of memory banks. According to an example embodiment, each of the plurality of memory banks may include a plurality of memory cells connected to word lines and bit lines. According to an example embodiment, each of the memory cells may be a volatile memory cell or a non-volatile memory cell. For example, a memory cell may be a dynamic random access memory (DRAM) cell, a flash memory cell, a magnetoresistive random access memory (MRAM) cell, or a phase-change random access memory (PRAM) cell. According to an example embodiment, memory device 100 may be a DRAM memory device 100.

[0030] Memory device 100 may include parallel bit test (PBT) circuitry 190 for performing parallel bit test (PBT) operations. The parallel bit test operation may include a test operation for determining whether memory device 100 is good or faulty (defective) by comparing data read from memory cells after test data has been written to memory cells of memory device 100.

[0031] According to an example embodiment, in a parallel bit test operation, in response to a test pass signal PBTPASS, the PBT circuit 190 can be implemented to pass through a predetermined memory region (e.g., a memory bank) of the memory device 100, regardless of whether the predetermined memory region is faulty. According to an example embodiment, the test pass signal PBTPASS can be generated by a mode register set (MRS). According to another example embodiment, the test pass signal PBTPASS can be received from the tester 200.

[0032] The tester 200 can be implemented to send commands / addresses (CMD / ADDR), clock (CLK), and test data (TDATA) related to the test operation to the memory device 100 during the test operation, and to receive the result value (RSLT) of the test operation from the memory device 100.

[0033] According to the example embodiment, the test system 10 can use the test pass signal PBTPASS to process the test pass of a predetermined area of ​​the memory device 100. Therefore, the test system 10 according to this example embodiment can overcome the statistical limitation of reliability assessment sample size by skipping the test operation on specific areas of the memory device 100, and greatly shorten the development cycle of the memory device 100.

[0034] Figure 2 This is a diagram illustrating a memory device 100 according to an example embodiment.

[0035] refer to Figure 2The memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, a sense amplifier circuit 140, an address register 150, a memory bank control logic 152, a refresh counter 154, a row address multiplexer 156, a column address latch 158, control logic 160, a repair control circuit 166, a timing control circuit 164, an input / output gate circuit 170, an error correction circuit 180, a data input / output buffer 182, and a PBT circuit 190.

[0036] The memory cell array 110 may include a first memory bank 111 to an eighth memory bank 118, although it should be understood that the number of memory banks in the memory cell array 110 may vary.

[0037] The line decoder 120 may include first storage line decoders 121 to eighth storage line decoders 128, which are respectively connected to the first storage bank 111 to the eighth storage bank 118.

[0038] The column decoder 130 may include first storage column decoders 131 to eighth storage column decoders 138, which are respectively connected to the first storage bank 111 to the eighth storage bank 118.

[0039] The sensing amplifier circuit 140 may include a first sensing amplifier 141 to an eighth sensing amplifier 148 respectively connected to a first memory bank 111 to an eighth memory bank 118.

[0040] The first memory bank 111 to the eighth memory bank 118, the first memory bank row decoder 121 to the eighth memory bank row decoder 128, the first memory bank column decoder 131 to the eighth memory bank column decoder 138, and the first sense amplifier 141 to the eighth sense amplifier 148 can be configured with the first memory bank to the eighth memory bank respectively. Each of the first memory bank 111 to the eighth memory bank 118 may include a plurality of memory cells MC formed at the intersection of word line WL and bit line BL.

[0041] Address register 150 can receive and store address ADDR, which has bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the external memory controller. Address register 150 can provide the received bank address BANK_ADDR to the bank control logic 152, the received row address ROW_ADDR to the row address multiplexer 156, and the received column address COL_ADDR to the column address latch 158.

[0042] The memory bank control logic 152 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the memory bank row decoders corresponding to the memory bank address BANK_ADDR among the first memory bank row decoders 121 to the eighth memory bank row decoders 128 can be activated. Similarly, in response to the memory bank control signal, the memory bank column decoders corresponding to the memory bank address BANK_ADDR among the first memory bank column decoders 131 to the eighth memory bank column decoders 138 can be activated.

[0043] The row address multiplexer 156 can receive the row address ROW_ADDR from the address register 150 and the refresh row address REF_ADDR from the refresh counter 154. The row address multiplexer 156 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 156 can be applied to the first memory bank row decoder 121 to the eighth memory bank row decoder 128, respectively.

[0044] The bank row decoders 121 through 128, activated by the bank control logic 152, can decode the row address RA output from the row address multiplexer 156 to activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address. Furthermore, the activated bank row decoder can activate the word line corresponding to the row address and simultaneously activate the redundant word line corresponding to the redundant row address output from the repair control circuit 166.

[0045] Column address latch 158 can receive column address COL_ADDR from address register 150 and temporarily store the received column address COL_ADDR. Furthermore, in burst mode, column address latch 158 can incrementally increment the received column address COL_ADDR. Column address latch 158 can apply the temporarily stored or incrementally incremented column address COL_ADDR to column decoders 131 through 138 of the first memory bank, respectively.

[0046] The memory bank column decoders 131 through 138, activated by the memory bank control logic 152, can decode the sense amplifiers corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR via the input / output gate circuit 170. Furthermore, the activated memory bank column decoders can perform column repair operations in response to the column repair signal CRP output from the repair control circuit 166.

[0047] Control logic 160 can be implemented to control the operation of memory device 100. For example, control logic 160 can generate control signals that cause memory device 100 to perform write or read operations. Control logic 160 may include a command decoder 161 for decoding commands CMD received from the memory controller and a mode register group 162 for setting the operating mode of memory device 100.

[0048] For example, command decoder 161 can generate operation control signals ACT, PCH, WE, and RD corresponding to command CMD by decoding write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, and chip select signal / CS. Control logic 160 can provide operation control signals ACT, PCH, WE, and RD to timing control circuit 164. Control signals ACT, PCH, WR, and RD may include active signal ACT, precharge signal PCH, write signal WR, and read signal RD. Timing control circuit 164 can generate a first control signal CTL1 for controlling the voltage level of word line WL and a second control signal CTL2 for controlling the voltage level of bit line BL in response to operation control signals ACT, PCH, WR, and RD, and can provide the first control signal CTL1 and the second control signal CTL2 to memory cell array 110.

[0049] Repair control circuit 166 can generate repair control signals CRP and SRP, which control the repair operations of at least one first cell region and a second cell region in the memory bank based on the fuse information of the row address ROW_ADDR, column address COL_ADDR, and word lines of address ADDR (or access address). Repair control circuit 166 can provide redundant row addresses to the corresponding memory bank row decoder, provide column repair signals CRP to the corresponding memory bank column decoder, and provide selection signals and enable signals SRA to the block control circuits associated with the corresponding redundant array blocks.

[0050] Furthermore, in the hPPR mode stored in mode register group 162, the repair control circuit 166 can generate an hPPR word line activation signal in response to address ADDR. Furthermore, in the sPPR mode stored in mode register group 162, the repair control circuit 166 can generate an sPPR word line activation signal sPPR_WL_EN in response to address ADDR. Furthermore, in the sPPR_OFF mode stored in mode register group 162, the repair control circuit 166 can disable the sPPR logic and generate a normal word line activation signal to access previous data. According to the example embodiment, the repair control circuit 166 can change the repair unit based on address ADDR and fuse information. For example, the repair control circuit 166 can change the type and number of repair address bits based on address ADDR and fuse information.

[0051] Each of the input / output gates in the input / output gate circuit 170 may include input data masking logic, a read data latch for storing data output from the first memory bank 111 to the eighth memory bank 118, a write driver for writing data to the first memory bank 111 to the eighth memory bank 118, and circuitry for strobing input / output data.

[0052] The codeword to be read from one of the first to eighth memory banks 111 can be sensed by a sense amplifier corresponding to a memory bank and stored in a read data latch. After ECC decoding is performed by the error correction circuit 180, the codeword CW stored in the read data latch can be provided to the memory controller through the data input / output buffer 182. The data DQ to be written to one of the first to eighth memory banks 111 can be written to a memory bank through a write driver after ECC encoding is performed by the error correction circuit 180.

[0053] The data input / output buffer 182 can provide data DQ to the error correction circuit 180 based on the clock signal CLK provided from the memory controller during a write operation, and provide data DQ provided from the error correction circuit 180 to the memory controller during a read operation.

[0054] Error correction circuit 180 can generate parity bits based on the data bits of data DQ provided from data input / output buffer 182 during a write operation, and provide codeword CW including data DQ and parity bits to input / output gate 170, and input / output gate 170 can write codeword CW into memory.

[0055] Furthermore, the error correction circuit 180 can receive the codeword CW read from a memory bank during a read operation from the input / output gate circuit 170. The error correction circuit 180 can correct at least one erroneous bit included in the data DQ by performing ECC decoding on the data DQ using the parity bit included in the read codeword CW, thereby providing the corrected erroneous bit to the data input / output buffer 182.

[0056] PBT circuit 190 can be implemented to work with slave tester 200 (see...) Figure 1 The test performs parallel testing operations on each received test data TDATA in the storage, performs repair operations when error correction is possible, and outputs the result value based on the results.

[0057] Furthermore, in response to the test pass signal PBTPASS, the PBT circuit 190 can be implemented to pass through the memory bank regardless of the result of the test operation on the corresponding memory bank. According to another example embodiment, the test pass signal PBTPASS can be output from the mode register group 162 during a parallel bit test operation.

[0058] Even if an unrepairable memory bank is provided, the memory device 100 according to the example embodiment can still use the repair control circuit 166 to shield the output terminals of such memory bank in response to the test pass signal PBTPASS. Therefore, the memory device 100 according to this example embodiment can make a failure chip operable as a good chip by controlling the output terminals of each memory bank.

[0059] Figure 3 This is a conceptual diagram illustrating test operation of a memory device 100 according to an example embodiment. (See reference...) Figure 3 The data input terminal can select input data (DI) in either normal mode or test mode. Input data (DI) can be sent to, stored in, and output to multiple memory banks.

[0060] The PBT circuit 190 can be implemented to compare the outputs of multiple memory banks and output the result value using a comparison output signal and a test pass signal PBTPASS corresponding to the result.

[0061] The data output terminal can select normal mode or test mode, and output data DQ to the outside or output the result value of the test operation according to the selected mode.

[0062] According to an example embodiment, the operating modes may include a normal mode for writing data to or reading data from each memory bank, and a parallel test mode in which multiple memory banks are simultaneously written to and read from. In normal mode, to access cells in the same manner as general-purpose memory operation, a word line and a bit line corresponding to the number of input / output bits of a memory bank can be selected by combining row and column addresses. Data in the selected memory cell can be written to or read from as described above.

[0063] In test mode, the same data can be written to multiple memory banks. During a read operation used for testing, the data for each memory bank can be received by the PBT circuit 190 through a sense amplifier. When the data B1, B2, B3, or B4 of each memory bank are all "low" or all "high", the PBT circuit 190 can output a result value corresponding to normal as the result of the test operation. Furthermore, even if the data B1, B2, B3, or B4 of each memory bank are not all "low" or all "high", in response to the test pass signal PBTPASS, even if the result for a particular memory bank is a failure, the PBT circuit 190 can still output a result value corresponding to normal.

[0064] At the same time, it should be understood that, although Figure 3 The number of storage units shown is 4, but the number of storage units can vary.

[0065] Figure 4 This is a diagram illustrating an example embodiment of the PBT circuit 190.

[0066] refer to Figure 4 The PBT circuit 190 may include a first parallel test circuit 191 to a fourth parallel test circuit 194 and a logic circuit 195. Here, the first parallel test circuit 191 to the fourth parallel test circuit 194 may be referred to as PBT1 to PBT4, respectively.

[0067] The first parallel test circuit 191 to the fourth parallel test circuit 194 may include corresponding first comparators CMP1 to fourth comparators CMP4, which can be implemented to compare inputs to the tester 200 (see [link]). Figure 1 The test data and the data read from the corresponding memory are used to output the corresponding test results B1_PASS to B4_PASS of the memory using the test pass signal PBTPASS and the comparison result.

[0068] The first comparator CMP1 (of the first parallel test circuit 191) can be implemented to receive data bit FDO1, test bit WDI1, evolved PBT signal ePBT, test ignore (or irrelevant (DON'T CARE)) signal iePBT 1 / 0, and test pass signal PBTPASS, and output the first memory bank test result signal B1_PASS. Data bit FDO1 can be received from the first input / output sense amplifier circuit IOSA1. The first input / output sense amplifier circuit IOSA1 can receive the parallel bit test signal PBT and sense the data bit FDO1 from the first memory bank BANK1. Test bit WDI1 can be received from the tester 200, and the received test bit WDI1 can be buffered in an internal latch. The mode register group MRS ( Figure 2 162) receives the parallel bit test signal PBT, the evolved PBT signal ePBT, the test ignore signal iePBT 1 / 0, and the test pass signal PBTPASS.

[0069] Each of the second comparators CMP2 to the fourth comparator CMP4 in the corresponding second parallel test circuit 192 to the fourth parallel test circuit 194 can be implemented in the same way as the first comparator CMP1 in the first parallel test circuit 191. Figure 4 The number of comparators CMP1 to CMP4 shown is 4, but this number can vary.

[0070] Logic circuit 195 can be implemented to receive the output signals B1_PASS, B2_PASS, B3_PASS, and B4_PASS of each comparator CMP1 to CMP4, and output the result value PBT_RSLT of the PBT test operation. For example, logic circuit 195 may include an OR gate circuit that performs an OR operation. It should be understood that, although Figure 4 The logic circuit 195 shown is illustrated as an OR gate circuit, but the logic circuit according to this example embodiment may include, for example, an XOR gate circuit that performs an XOR operation.

[0071] Figure 5 This is a graphical example illustrating a general comparator CMP used to perform parallel bit test operations.

[0072] refer to Figure 5 The comparator CMP may include PMOS transistors PM1 to PM4, NMOS transistors NM1 to NM4, inverters INV1 to INV3, NAND gates NAND1 and NAND2, and NOR gate NOR1.

[0073] The first PMOS transistor PM1 can be connected between the power supply terminal VDD and the first node N1, and can have a gate connected to the first input terminal FDOx. The first input terminal FDOx can receive data connected to the memory cell through a corresponding sense amplifier.

[0074] The second PMOS transistor PM2 can be connected between the power supply terminal VDD and the first node N1, and can have a gate connected to the second input terminal CIN1. The second input terminal CIN1 can be connected to the output terminal of the first NAND gate circuit NAND1. The first NAND gate circuit NAND1 can be implemented to perform a first NAND operation on the first test ignore signal iePBT_D0 and the output signal of the NOR gate circuit NOR1. The NOR gate circuit NOR1 can be implemented to perform a first NAND operation on the slave tester 200 (see...). Figure 1 The received test data WDIx and the output signal of the second inverter INV2 are subjected to a first NOR operation. The second inverter INV2 can be implemented to invert the evolved PBT signal ePBT.

[0075] The third PMOS transistor PM3 can be connected between the first node N1 and the second node N2, and can have a gate connected to the output terminal of the first inverter INV1. The first inverter INV1 can be implemented to invert the data at the first input terminal FDOx.

[0076] A fourth PMOS transistor, PM4, can be connected between the first node N1 and the second node N2, and can have a gate connected to the second inverting input terminal CIN2. The inverted second input terminal CIN2 can be connected to the output terminal of the second NAND gate circuit NAND2. The second NAND gate circuit NAND2 can be implemented to perform a second NAND operation on the second test ignore signal iePBT_D1 and the output signal of the third inverter INV3. The third inverter INV3 can be implemented to invert the output signal of the NOR gate circuit NOR1. The second node N2 may include the output terminal Dout of the comparator CMP.

[0077] The first NMOS transistor NM1 can be connected between the second node N2 and the third node N3, and can have a gate connected to the output terminal of the first inverter INV1.

[0078] The second NMOS transistor NM2 can be connected between the second node N2 and the third node N3, and can have a gate connected to the second input terminal CIN1.

[0079] The third NMOS transistor NM3 can be connected between the third node N3 and the ground terminal GND, and can have a gate connected to the first input terminal FDOx.

[0080] The fourth NMOS transistor NM4 can be connected between the third node N3 and the ground terminal GND, and can have a gate connected to the second inverting input terminal CIN2.

[0081] A general-purpose comparator can perform test operations when the data at a specific data input / output terminal is processed in a non-careful manner or when the data at a specific logic terminal is processed in a non-careful manner.

[0082] Figure 6A and Figure 6B This is an example diagram illustrating the process of parallel bit testing operations on a general-purpose memory device.

[0083] refer to Figure 6A Assuming that the third memory bank BANK3 and the twelfth memory bank BANK12 are unrepairable as a result of testing and repair operations, then... Figure 6B As shown, since irreparability was confirmed during the test operation on the third memory bank BANK3 when parallel test operations were performed on each memory bank, the memory device will be immediately treated as a faulty chip.

[0084] When any unrepairable memory bank appears, the general-purpose memory device is treated as a faulty chip. For example... Figure 6A and Figure 6B As shown, there is no problem driving a memory device with 14 non-faulty memory banks (memory bank 1, memory bank 2, memory banks 4 to 11, and memory banks 13 to 16), but the corresponding memory device is still treated as faulty or bad. Conversely, the memory device according to the example embodiment can be implemented to pass the faulty memory bank in a parallel bit test operation.

[0085] Figure 7 This is a graphical example illustrating a comparator in a parallel test circuit according to an example embodiment.

[0086] refer to Figure 7 ,and Figure 5 Compared to the comparator CMP shown, the example of comparator CMP1 in the first parallel test circuit 191 according to this example embodiment may also include a second NOR gate circuit NOR2, a third NOR gate circuit NOR3, a fourth inverter INV4, and a fifth inverter INV5.

[0087] The second NOR gate circuit NOR2 can be implemented to perform a NOR operation on the first test ignore signal iePBT_D0 and the test pass signal PBTPASS. The output terminal of the second NOR gate circuit NOR2 can be connected to the input terminal of the fourth inverter INV4. The first NAND gate circuit NAND1 can be implemented to perform a first NAND operation on the output signal of the fourth inverter INV4 and the output signal of the first NOR gate circuit NOR1.

[0088] The third NOR gate circuit, NOR3, can be implemented to perform a NOR operation on the second test ignore signal iePBT_D1 and the test pass signal PBTPASS. The output terminal of the third NOR gate circuit, NOR3, can be connected to the input terminal of the fifth inverter, INV5. The second NAND gate circuit, NAND2, can be implemented to perform a second NAND operation on the output signals of the third inverter, INV3, and the fifth inverter, INV5. Here, the input terminal of the third inverter, INV3, can be connected to the output terminal of the first NOR gate circuit, NOR1.

[0089] The memory device 100 according to an example embodiment may include: circuitry for passing a failure determination to an ePBT circuit when processing data resulting from an actual failure by applying a test pass signal PBTPASS, the ePBT circuitry being configured to compare data read from the output terminal of the PBT circuit 190 with a write expectation value and output the data read from the output terminal of the PBT circuit 190; and iePBT circuitry for performing don't care processing on specific data and outputting the specific data. For each memory bank, the test pass signal PBTPASS may be controlled together with iePBT D0 / D1.

[0090] When comparing the value FDOx output from the PBT path via the input / output sense amplifier circuit IOSA with the test expectation value WDIx, if the phase of the test pass signal PBTPASS is "high", the pass / fail determination of the corresponding data can be treated as irrelevant (DON'T CARE).

[0091] According to the example embodiment, the test pass signal PBTPASS can be applied to each memory bank. Therefore, when performing data-independent (DON'T CARE) testing on a specific memory bank (e.g., G0_A), the data processing result can be passed by applying the test memory bank signal PBTPASS for the corresponding memory bank (e.g., G0_A).

[0092] The memory device 100 according to the example embodiment can shield the data output terminals of some unrepairable areas by controlling the data processing results of each memory bank. Therefore, the memory device 100 according to the example embodiment can make a faulty chip operable as a pass chip. As a result, the parameters of the test die can be ensured. For example, when the initial yield is not ensured due to process generation conversion, the test die ensured by applying the test pass signal PBTPASS can be used for wafer-level evaluation, stress evaluation, reliability evaluation, etc. Furthermore, the test die can also be used for stress evaluation and reliability evaluation in the post-assembly back-end stages.

[0093] Furthermore, the memory device according to the example embodiment can overcome statistical limitations caused by the lack of an evaluable sample size. As a result, the development cycle of memory chips can be shortened, and memory chips can be ramped up earlier.

[0094] Figure 8A and Figure 8B This is an example diagram illustrating the process of a parallel bit test operation of a memory device 100 according to an example embodiment.

[0095] like Figure 8A As shown, even if the third memory bank BANK3 and the twelfth memory bank BANK12 are irreparable, the memory device 100 according to the example embodiment can still complete the test operation, while treating specific memory banks BANK3 and BANK12 as irrelevant (DON'T CARE) in the parallel bit test operation, and memory banks BANK3 and BANK12 can be processed as good chips.

[0096] Figure 9 This is a flowchart example illustrating a test operation of a memory device 100 according to an example embodiment.

[0097] refer to Figures 1 to 9 The parallel bit test operation of memory device 100 can be performed as follows.

[0098] Memory device 100 can be accessed from tester 200 (see...) Figure 1 The memory device 100 receives test commands and test data and stores don't care information (S110). In response to the test command, the memory device 100 can perform a test operation in each of the plurality of memory banks (S120). The memory device 100 can perform a repair operation in each of the memory banks (S130). The memory device 100 can process unrepairable memory banks as passable memory banks based on the don't care information (S140).

[0099] According to an example embodiment, a test pass signal can be generated for at least one of a plurality of memory banks using bank-independent (DON'T CARE) information. According to an example embodiment, the repair operation can include identifying an unrepairable memory bank among the plurality of memory banks. According to an example embodiment, in response to the test pass signal, the output terminal of the unrepairable memory bank can be masked. According to an example embodiment, the repair operation can be performed after skipping the row address RA of the unrepairable memory bank. According to an example embodiment, the test pass signal can be sent to at least one group of memory banks among the plurality of memory banks.

[0100] Figure 10 This is a flowchart example illustrating a test operation of a memory device 100 according to another example embodiment of the present disclosure.

[0101] refer to Figures 1 to 10 The test operation of memory device 100 can be performed as follows.

[0102] The memory device 100 can determine during a test operation whether there is an unrepairable region (e.g., a specific memory cell) (S210). The memory device 100 can shield the output terminal of the faulty region (S220). Thereafter, the memory device 100 can perform a repair operation after skipping the faulty region (RA) (S230). Even if a faulty region exists, the memory device 100 can perform a pass process (S240).

[0103] Figure 11A and Figure 11B This is a diagram illustrating an example of using the PBTPASS test pass signal.

[0104] like Figure 11A and Figure 11B As shown, the test pass signal PBTPASS applies to the first memory bank groups G0A, G0B, G0C, and G0D.

[0105] Figure 11A The iePBT circuit shown can perform don't care processing on specific data by using the first test ignore signal TMRS_IEPBT_D0 and the test pass signals TMRSF_PBTPASS_G0A, TMRSF_PBTPASS_G0B, TMRSF_PBTPASS_G0C and TMRSF_PBTPASS_G0D.

[0106] Figure 11BThe iePBT circuit shown can perform don't care processing by using the PBT signal TRMS_IEPBT and the test pass signals TMRSF_PBTPASS_G0A, TMRSF_PBTPASS_G0B, TMRSF_PBTPASS_G0C and TMRSF_PBTPASS_G0D.

[0107] As described below, the memory device according to the example embodiment can be implemented in a stacked type.

[0108] Figure 12 This is a diagram example illustrating a memory chip according to an example embodiment.

[0109] refer to Figure 12 The memory chip 1000 may include a first memory die 1100 to a third memory die 1300 and through silicon vias (TSVs) stacked vertically on a substrate. The number of stacked memory dies may differ. Figure 12 The quantities shown. In the example embodiment, the first memory die 1100 and the second memory die 1200 may be slave dies, and the third memory die 1300 may be a master die or a buffer die.

[0110] The first memory die 1100 may include a first memory cell array 1110 and a first through-silicon via (TSV) region 1120 for accessing the first memory cell array 1110. The second memory die 1200 may include a second memory cell array 1210 and a second TSV region 1220 for accessing the second memory cell array 1210.

[0111] The first through-silicon via (TSV) region 1120 may be a region in the first memory die 1100 in which a TSV for communication between the first memory die 1100 and the third memory die 1300 is provided. Similarly, the second TSV region 1220 may be a region in the second memory die 1200 in which a TSV for communication between the second memory die 1200 and the third memory die 1300 is provided. TSVs can provide an electrical path between the first memory die 1100 and the third memory die 1300.

[0112] The first memory die 1100 to the third memory die 1300 can be electrically connected to each other via through-silicon vias (TSVs). In an example embodiment, the number of TSVs can be hundreds to thousands, and the TSVs can be arranged in a matrix.

[0113] The third memory die 1300 may include a first peripheral circuit 1310 and a second peripheral circuit 1320. The first peripheral circuit 1310 may include circuitry for accessing the first memory die 1100, and the second peripheral circuit 1320 may include circuitry for accessing the second memory die 1200. According to an example embodiment, each of the first peripheral circuit 1310 and the second peripheral circuit 1320 can be accessed via… Figures 1 to 1 The method and apparatus for performing parallel bit test operations described in section 1 are implemented.

[0114] As described below, the memory device according to the example embodiment can be applied to a computing system.

[0115] Figure 13 This is a graphical example illustrating a computing system 2000 according to an example embodiment.

[0116] refer to Figure 13 The computing system 2000 may include at least one volatile memory module (such as DIMM(s)) 2100, at least one non-volatile memory module (such as NVDIMM(s)) 2200 and at least one central processing unit (such as a processor) 2300.

[0117] The Computing System 2000 can be used as a computer, portable computer, ultra-mobile PC (UMPC), workstation, data server, netbook, personal digital assistant (PDA), tablet computer, cordless phone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), digital camera, digital audio recorder / player, digital camera / digital video recorder / player, portable game console, navigation system, set-top box, wearable device, 3D TV, device for receiving and transmitting information in a wireless environment, any of the various electronic devices configured for home networks, any of the various electronic devices configured for computer networks, any of the various electronic devices configured for telematics networks, radio frequency identification (RFID), or any of the various electronic devices configured for the computing system.

[0118] At least one non-volatile memory module 2200 may include at least one non-volatile memory. According to an example embodiment, the at least one non-volatile memory may include NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), thyristor random access memory (TRAM), etc.

[0119] According to an example embodiment, at least one of memory modules 2100 and 2200 can be implemented to perform... Figures 1 to 1 The parallel bit test operation described in 1.

[0120] According to an example embodiment, memory modules 2100 and 2200 can be connected to processor 2300 via a DDRx interface (x is an integer of 1 or greater).

[0121] At least one processor 2300 may be implemented to control the volatile memory module 2100 and the non-volatile memory module 2200. According to an example embodiment, the processor 2300 may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof.

[0122] As described below, the memory device according to the example embodiment can be applied to an automotive system.

[0123] Figure 14 This is a diagram example illustrating a car system 3000 according to an example embodiment.

[0124] refer to Figure 14 The automotive system 3000 may include an electronic control unit (ECU) 3100, a memory device 3200, a dynamic range sensor (DVS) 3300, a display 3400, and a communication processor 3500.

[0125] The electronic control unit (ECU) 3100 can be implemented to control the overall operation. The ECU 3100 can process image data received from the DVS 3300. The ECU 3100 may include a neural processing unit (NPU). The NPU can quickly derive the optimal image for driving by comparing the images received from the DVS 3300 with a learned model.

[0126] The memory device 3200 can be implemented to store the operation-related learning model of the NPU. The memory device 3200 can include volatile or non-volatile memory devices. For example, the memory device 3200 can be DRAM or PRAM. The memory device 3200 can be, for example... Figures 1 to 1 Operate in the parallel bit test mode described in 1.

[0127] The Dynamic Range Sensor (DVS) 3300 can be implemented to sense the external environment of a vehicle. The DVS 3300 can output event signals in response to changes in the relative intensity of light. The DVS 3300 may include a pixel array with multiple DVS pixels and an address event processor.

[0128] The display 3400 can be implemented to display images processed by the ECU 3100 or images transmitted by the communication processor 3500.

[0129] The communication processor 3500 can be implemented to send processed images to an external device (e.g., an external vehicle) or to receive images from an external vehicle. The communication processor 3500 can be implemented to perform wired or wireless communication with the external device.

[0130] As described below, the memory device according to the example embodiment can be applied to a mobile device.

[0131] Figure 15 This is a diagram example illustrating a mobile device 4000 according to an example embodiment.

[0132] refer to Figure 15 The mobile device 4000 may include an application processor 4100, at least one DRAM 4200, at least one storage device 4300, at least one sensor 4400, a display device 4500, an audio device 4600, a network processor 4700, and at least one input / output device 4800. For example, the mobile device 4000 may be implemented as a laptop computer, mobile phone, smartphone, tablet PC, or wearable computer.

[0133] Application processor 4100 can be implemented to control the overall operation of mobile device 4000. Application processor 4100 can execute applications that provide internet browsers, games, and videos. According to example embodiments, application processor 4100 may include single-core or multi-core processors. For example, application processor 4100 may include multi-core processors, such as dual-core, quad-core, and hexa-core processors. According to example embodiments, application processor 4100 may also include internal or external cache memory.

[0134] Application processor 4100 may include controller 4110, neural processing unit (NPU, such as an artificial intelligence processor) 4120, and interface 4130. According to an example embodiment, the NPU may optionally be provided.

[0135] According to an example embodiment, the application processor 4100 can be implemented as a system-on-a-chip (SoC). The kernel of the operating system running on the SoC may include an I / O scheduler and a device driver for controlling the storage device 4300. The device driver can control the access performance to the storage device 4300 by referring to the number of synchronization queues managed by the I / O scheduler, or control the CPU mode and DVFS level in the SoC.

[0136] DRAM 4200 can be connected to controller 4110. DRAM 4200 can store data necessary for the operation of application processor 4100. For example, DRAM 4200 can temporarily store operating system (OS) and application data, or it can be used as execution space for various software codes.

[0137] DRAM 4200 can perform an sPPR shutdown operation upon request from application processor 4100. DRAM 4200 can be connected to NPU 4120. DRAM 4200 can store data related to artificial intelligence operations.

[0138] Compared to I / O devices or flash memory, DRAM 4200 can offer relatively low latency and high bandwidth (BW). DRAM 4200 can be initialized when the mobile device is powered on, and can load OS and application data. It can be used as temporary storage for OS and application data, or as execution space for various software code. Mobile systems can multitask to load multiple applications simultaneously, and the switching and execution speed between applications can be used as performance metrics for the mobile system.

[0139] In addition, the DRAM 4200 may include the ability to perform test operations to pass, for example... Figures 1 to 1 The PBT circuit of the unrepairable memory as described in 1.

[0140] Storage device 4300 can be connected to interface 4130. According to an example embodiment, interface 4130 can operate via any of the following communication protocols: DDR, DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), Non-volatile Memory Express (NVMe), Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Universal Storage Bus (USB) Attached SCSI (UAS), Internet Small Computer System Interface (iSCSI), and Fiber Channel over Ethernet (FCoE). According to an example embodiment, any storage device 4300 can be included in a mobile device 4000 in an embedded form. According to another example embodiment, any storage device 4300 can be included in a removable form in the mobile device 4000.

[0141] Storage device 4300 can be implemented to store user data. For example, storage device 4300 can store data collected from sensor 4400 or data network data, augmented reality (AR) / virtual reality (VR) data, and high-definition (HD) 4K content. Storage device 4300 may include at least one non-volatile storage device. For example, storage device 4300 may include a solid-state drive (SSD), an embedded multimedia card (eMMC), etc.

[0142] According to the example embodiment, the storage device 4300 may be implemented as a stand-alone chip of the application processor 4100, or it may be implemented as a single package having the application processor 4100.

[0143] According to the example embodiment, the storage device 4300 can be installed using various types of packaging. For example, the storage device 4300 can use packages on packages (PoP), ball grid arrays (BGA), chip scale packages (CSP), plastic leaded chip carriers (PLCC), plastic dual in-line packages (PDIP), die in waffle packs, chip on board (COB), ceramic dual in-line packages (CERDIP), metric quad flat packs (MQFP), thin quad flat packs (TQFP), small outlines (SOIC), shrink small outline packages (SSOP), thin small outlines (TSOP), system in package (SIP), multi-chip packages (MCP), and wafer-level fabricated packages. It is installed using WFP (Wafer-Plug-in Package) and wafer-level processed stack package (WSP).

[0144] Sensor 4400 can be implemented to sense the external environment of mobile device 4000. According to an example embodiment, sensor 4400 may include an image sensor that senses images. Sensor 4400 can send the generated image information to application processor 4100. According to another example embodiment, sensor 4400 may include a biosensor that senses biometric information. For example, sensor 4400 can sense fingerprints, iris patterns, vascular patterns, heart rate, blood glucose, etc., and generate sensing data corresponding to the sensed information. It should be understood that sensor 4400 may include any suitable sensor, such as an illuminance sensor, an acoustic sensor, and an accelerometer.

[0145] The display device 4500 can be implemented to output data. For example, the display device 4500 can output image data sensed by the sensor 4400, or data calculated by the application processor 4100.

[0146] The audio device 4600 can be implemented to output voice data to the outside or sense external voice.

[0147] The network processor 4700 can be implemented to connect and communicate with external devices via wired or wireless communication methods.

[0148] Input / output device 4800 can be implemented to input data to mobile device 4000 or output data from mobile device 4000. Input / output device 4800 may include devices that provide digital input and output functions, such as USB or storage, digital camera, SD card, touch screen, DVD, modem, and network adapter.

[0149] As described below, the memory device according to the example embodiment can be applied to various types of computing systems (e.g., CPU / GPU / NPU platforms).

[0150] Figure 16 This is a graphical example illustrating a computing system 5000 according to an example embodiment.

[0151] refer to Figure 16 The computing system may include a central processing unit (CPU) 5110, a graphics processing unit (GPU) 5120 or a neural processing unit (NPU) (or dedicated processing unit) connected to the system bus 5001; a memory device 5210 or a storage device 5220 connected to the system bus 5001; and an input / output device 5310, a modem 5320, a network device 5330 or a storage device 5340 connected to the expansion bus 5002. The expansion bus 5002 may be connected to the system bus 5001 via an expansion bus interface 5003.

[0152] According to the example embodiment, each of the CPU 5110 and GPU 5120 may include on-chip caches 5111 and 5121.

[0153] According to an example embodiment, CPU 5110 may include off-chip cache 5112. Although in Figure 16 Not shown, but GPU 5120 may also include an off-chip cache. According to an example embodiment, off-chip cache 5112 may be internally connected to CPU 5110 and GPU 5120 via different buses.

[0154] According to example embodiments, on-chip / off-chip caches may include volatile memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM), or non-volatile memory, such as NAND flash memory, phase random access memory (PRAM), or resistive random access memory (RRAM).

[0155] According to an example embodiment, main memories 5114 and 5124 can be connected to CPU 5110 and GPU 5120 via corresponding memory controllers 5113 and 5123. According to an example embodiment, memories 5116 and 5126 can be connected to CPU 5110 and GPU 5120 via bridges 5115 and 5125. Bridges 5115 and 5125 may include memory controllers that control the corresponding memories 5116 and 5126. According to an example embodiment, each of bridges 5115 and 5125 can be implemented as a network device, wireless network device, switch, bus, cloud, or optical channel.

[0156] According to the example embodiment, memories 5124 and 5126 may include GPU memory. GPU memory can store commands and data that can interact with the GPU. Commands and data can be copied from main memory or memory. GPU memory can store image data and can have a larger bandwidth than memory. GPU memory can have its clock separate from the CPU. The GPU can read image data from GPU memory, process the image data, and then write the image data back to GPU memory. GPU memory can be configured to accelerate graphics processing.

[0157] According to an example embodiment, memories 5124 and 5126 may include NPU memory. The NPU memory can store commands and data that may interact with the NPU. Commands and data can be copied from main memory or other memory. The NPU memory can store weight data for the neural network. The NPU memory can have a larger bandwidth than regular memory. The NPU memory can have its clock separate from the CPU. The NPU can read and update weight data from the NPU memory during training, and then write the weight data back to the NPU memory. The NPU memory can be configured to accelerate machine learning, such as neural network training and inference.

[0158] According to the example embodiment, each of the main memories 5114, 5116, 5124, and 5126 can be implemented to execute... Figures 1 to 1 The memory chip for the test operation described in 1.

[0159] According to example embodiments, the main memory may include volatile memory, such as DRAM and SRAM, or non-volatile memory, such as NAND flash memory, PRAM, and RRAM. The main memory may have lower latency and lower capacity than the secondary memories 5210 and 5220.

[0160] CPU 5110 and GPU 5120 can access secondary memories 5210 and 5220 via system bus 5001. Memory device 5210 can be controlled by memory controller 5211. Memory controller 5211 can be connected to system bus 5001. Memory device 5220 can be controlled by memory controller 5221. Memory controller 5221 can be connected to system bus 5001.

[0161] Storage device 5220 can be implemented to store data. Storage controller 5221 can be implemented to read data from storage device 5220 and send the read data to the host. Storage controller 5221 can be implemented to store the sent data in storage device 5220 in response to a request from the host. Each of storage device 5220 and storage controller 5221 may include storage metadata, a read cache to store frequently accessed data, or a storage cache to improve write efficiency. For example, a write cache can receive and process a specific number of write requests.

[0162] Storage device 5220 may include volatile memory, such as hard disk drives (HDDs), and non-volatile memory, such as NVRAM, SSDs, SCMs, and newer types of memory.

[0163] As described below, the memory device according to the example embodiment can be applied to a data server system.

[0164] Figure 17 This is a diagram example illustrating a data center with a memory device applied according to an example embodiment.

[0165] refer to Figure 17 Data center 7000 is a facility that collects various types of data and provides services, and may be referred to as a data storage center. Data center 7000 may be a system used to operate search engines and databases, or it may be a computing system used by companies such as storage entities or government agencies. Data center 7000 may include application servers 7100 to 7100n and storage servers 7200 to 7200m. According to an example embodiment, the number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m may be different and may vary from one another.

[0166] Application server 7100 or storage server 7200 may include at least one of processors 7110 and 7210 and memories 7120 and 7220. Taking storage server 7200 as an example, processor 7210 can control the overall operation of storage server 7200 and can access memory 7220 and execute instructions and / or data loaded in memory 7220. Memory 7220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVMDIMM). According to example embodiments, the number of processors 7210 and the number of memories 7220 included in storage server 7200 may be selected differently. In example embodiments, processors 7210 and memories 7220 may provide processor-memory pairs. In example embodiments, the number of processors 7210 and memories 7220 may be different. Processor 7210 may include a single-core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. According to an example embodiment, application server 7100 may not include storage device 7150. Storage server 7200 may include one or more storage devices 7250. According to an example embodiment, the number of storage devices 7250 included in storage server 7200 may be selected differently.

[0167] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300. Network 7300 can be implemented using Fibre Channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission and can utilize optical switching that provides high performance / high availability. Depending on the access method to network 7300, storage servers 7200 to 7200m can be provided as file storage, block storage, or object storage.

[0168] In an example embodiment, network 7300 can be a storage-only network, such as a storage area network (SAN). For example, the SAN can be an FC-SAN implemented using an FC network and according to the FC Protocol (FCP). As another example, the SAN can be an IP-SAN implemented using a TCP / IP network and according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In another example embodiment, network 7300 can be a general-purpose network, such as a TCP / IP network. For example, network 7300 can be implemented according to protocols such as Ethernet FC (FCoE), Network Attached Storage (NAS), and Fibre Channel NVMe (NVMe over Fabrics, NVMe-oF).

[0169] The following text will primarily describe application server 7100 and storage server 7200. The description of application server 7100 can be applied to another application server 7100n, and the description of storage server 7200 can be applied to another storage server 7200m.

[0170] Application server 7100 can store data requested by users or clients and stored in one of storage servers 7200 to 7200m via network 7300. Furthermore, application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be implemented as a web server or a database management system (DBMS).

[0171] Application server 7100 can access memory 7120n or storage device 7150n included in another application server 7100n via network 7300, or access memory 7220 to 7220m or storage device 7250 to 7250m included in storage servers 7200 to 7200m via network 7300. Therefore, application server 7100 can perform various operations on data stored in application servers 7100 to 7100n and / or storage servers 7200 to 7200m. For example, application server 7100 can execute instructions for moving or copying data between application servers 7100 to 7100n and / or storage servers 7200 to 7200m. At this point, data can be moved from storage devices 7220 to 7220m of storage servers 7200 to 7200m, or directly from storage devices 7250 to 7250m of storage servers 7200 to 7200m, to storage devices 7120 to 7120n of application servers 7100 to 7100n. For security or privacy reasons, data moved over network 7300 can be encrypted.

[0172] Taking storage server 7200 as an example, interface 7254 can provide physical connection between processor 7210 and controller 7251, as well as physical connection between NIC 7240 and controller 7251. For example, interface 7254 can be implemented using direct attached storage (DAS) method, which directly connects storage device 7250 and dedicated cable. Furthermore, for example, the 7254 interface can be implemented through various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD), Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Storage (UFS), Embedded Universal Flash Storage (eUFS), and Compact Flash (CF) card interfaces.

[0173] The storage server 7200 may also include a switch 7230 and a NIC 7240. The switch 7230 can selectively connect the processor 7210 and the storage device 7250, or selectively connect the NIC 7240 and the storage device 7250, under the control of the processor 7210.

[0174] In an example embodiment, NIC 7240 may include a network interface card, network adapter, etc. NIC 7240 can connect to network 7300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 7240 may include internal memory, DSP, host bus interface, etc., and can connect to processor 7210 and / or switch 7230 via the host bus interface. The host bus interface can be implemented as one of the examples of interface 7254 described above. In an example embodiment, NIC 7240 can be integrated with at least one of processor 7210, switch 7230, and storage device 7250.

[0175] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can program or read data by sending commands to storage devices 7150 to 7150n and 7250 to 7250m or memories 7120 to 7120n and 7220 to 7220m. In this case, the data can be data corrected by an error correction code (ECC) engine. This data is data bus inversion (DBI) or data masking (DM) processed, and may include cyclic redundancy check (CRC) information. For security or privacy reasons, the data can be encrypted.

[0176] Storage devices 7150 to 7150n and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 7252 to 7252m, the read enable (RE) signal is input as a data output control signal and can be used to output data to the DQ bus. The data strobe (DQS) can be generated using the RE signal. Command and address signals can be latched in the page buffer based on the rising or falling edge of the writing enable (WE) signal.

[0177] Controller 7251 can control the overall operation of storage device 7250. In an example embodiment, controller 7251 may include static random access memory (SRAM). Controller 7251 can write data to NAND flash memory 7252 in response to a write command, or can read data from NAND flash memory 7252 in response to a read command. For example, write and / or read commands may be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100n. DRAM 7253 can temporarily store (buffer) data to be written to or read from NAND flash memory 7252. Furthermore, DRAM 7253 can store metadata. Metadata may be user data or data generated by controller 7251 to manage NAND flash memory 7252. Storage device 7250 may include a secure element (SE) for security or privacy.

[0178] The memory chip according to the example embodiment may include: circuitry for passing a failure determination to an ePBT circuit when processing data due to an actual failure by applying a PBT pass signal, the ePBT circuitry for comparing data read from the output terminal of the PBT circuit with a write expectation value and outputting the data read from the output terminal of the PBT circuit 190; and an iePBT circuitry for performing don't-treaty processing on specific data and outputting the specific data. In the example embodiment, for each memory bank, the PBT pass signal may be controlled together with the iePBT D0 / D1.

[0179] If the phase of the PBT pass signal is "high" when comparing the value (FDOx) output from the PBT path via the IO S / A output with the expected value (WDIx), then the memory chip according to the example embodiment can perform DON'T CARE processing to determine the pass / fail of the data.

[0180] In the memory chip according to the example embodiment, the PBT is applied to each memory bank, and when performing data-independent (DON'T CARE) operation on a particular memory bank (e.g., G0_A), the PBT signal of the corresponding memory bank (e.g., G0_A) can be used to process the data processing results.

[0181] According to the example embodiment, the memory chip can control the data processing results of each memory bank to shield the data output terminals of some unrepairable areas, which allows the faulty chip to be operated through the chip, thereby ensuring the parameters of the test die.

[0182] Furthermore, when the initial yield cannot be guaranteed due to process generation transition, the test die secured by applying the PBT pass signal can be used for wafer-level evaluation, stress evaluation, reliability evaluation, etc., and can also be used for stress evaluation and reliability evaluation of the post-assembly back-end stage.

[0183] The memory chip according to the example embodiment can overcome the statistical limitations caused by the lack of an evaluable sample size, and as a result, the development cycle of the memory chip can be shortened and the memory chip can be increased earlier.

[0184] As described above, according to the example embodiment, the memory device and its testing method can shield the data output terminals of some unrepairable areas by controlling the data processing results of each memory bank.

[0185] According to an example embodiment, the memory device and its testing method can make a faulty or bad chip operable as a passable chip.

[0186] According to the example embodiment, the memory device and its testing method can ensure the parameters of the test die.

[0187] According to an example embodiment, the memory device and its testing method can be used for stress assessment and reliability assessment of the assembled back-end stage.

[0188] As described above, the memory device according to the example embodiment may include test circuitry (e.g., PBT circuitry) that controls the shielding of the output terminals of each memory bank. For example, the memory device may use repair logic to shield the output terminals of unrepairable memory banks. Therefore, the memory device can operate the product as a normal chip, which can be driven by only outputting the repairable memory banks correctly. The memory device can recover evaluation quantity losses due to initial low yield / low quality of the product and maximize evaluation quantity by controlling the output terminals of each memory bank to convert faulty chips into good chips. As a result, the memory device can overcome the statistical limitations of reliability evaluation sample size and significantly shorten the development cycle.

[0189] As described above, the embodiments can provide memory devices and testing methods for improving yield. The embodiments can also provide memory devices and testing methods for shielding output terminals of unrepairable memory cells.

[0190] This document has disclosed exemplary embodiments. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A memory device, comprising: Multiple sense amplifier circuits are configured to sense data bits in response to parallel test signals from multiple memory banks; Multiple comparators are configured to compare data bits from each of the multiple sense amplifier circuits with test bits; as well as The logic circuit is configured to receive the output signals of the plurality of comparators and output the test results. Each of the plurality of comparators receives the test bit, an evolved parallel bit test signal (ePBT), at least one logic state test setting signal, and a test pass signal. In response to the evolved parallel bit test signal, the at least one logic state test setting signal, and the test pass signal, the data bit and the test bit are compared. In response to the test pass signal provided for at least one predetermined memory bank of the plurality of memory banks, the data bit and the test bit are passed through the corresponding memory bank, regardless of the test operation.

2. The memory device according to claim 1, wherein, Each of the plurality of comparators, in response to the at least one logic state test setting signal, performs data-independent (DON'TCARE) processing.

3. The memory device according to claim 1, wherein, Each of the plurality of comparators receives a test pass signal from the mode register group for the memory bank to be passed, regardless of the parallel bit test operation.

4. The memory device according to claim 3, wherein, For each memory bank, the test pass signal is controlled together with at least one test ignore signal.

5. The memory device according to claim 3, wherein, When comparing the test bit and the data bit, if the test pass signal is logic "high", the parallel bit test circuit makes a pass / fail determination for the corresponding data bit.

6. The memory device according to claim 3, wherein, The test is performed by independently applying a signal to each of the plurality of memory cells.

7. The memory device according to claim 1, wherein, The logic circuit includes an OR gate circuit, which outputs the result of a parallel bit test operation by performing an OR operation on the output signals of the plurality of comparators.

8. The memory device according to claim 7, wherein, Each of the plurality of comparators includes: A first inverter is connected to a first input terminal, which receives data bits read from a corresponding memory bank among the plurality of memory banks; The second inverter is configured to invert the evolved parallel bit test signal; Third inverter; Fourth inverter; Fifth inverter; A first NOR gate circuit is configured to perform a first NOR operation on the output signal of the second inverter and the test bit, and output the result of the first NOR operation to the third inverter; The second NOR gate is configured to perform a second NOR operation on the first test ignore signal and the test pass signal, and output the result of the second NOR operation to the fourth inverter. The third NOR gate is configured to perform a third NOR operation on the second test ignore signal and the test pass signal, and output the result of the third NOR operation to the fifth inverter. The first NAND gate circuit is configured to perform a first NAND operation on the output signal of the fourth inverter and the output signal of the first NOR gate circuit, and output the result of the first NAND operation to the second input terminal. The second NAND gate circuit is configured to perform a second NAND operation on the output signal of the third inverter and the output signal of the fifth inverter, and output the result of the second NAND operation to the second inverting input terminal. A first PMOS transistor is connected between a power supply terminal and a first node, and has a gate connected to the first input terminal; A second PMOS transistor is connected between the power supply terminal and the first node, and has a gate connected to the second input terminal; A third PMOS transistor is connected between the first node and the second node, and has a gate connected to the output terminal of the first inverter, the second node being connected to the output terminal of the parallel bit test operation. A fourth PMOS transistor is connected between the first node and the second node and has a gate connected to the second inverting input terminal; A first NMOS transistor is connected between the second node and the third node and has a gate connected to the output terminal of the first inverter; A second NMOS transistor is connected between the second node and the third node, and has a gate connected to the second input terminal; A third NMOS transistor is connected between the third node and the ground terminal, and has a gate connected to the first input terminal; and A fourth NMOS transistor is connected between the third node and the ground terminal, and has a gate connected to the second inverting input terminal.

9. A memory device, comprising: A first inverter is connected to a first input terminal for receiving data bits read from the memory. The second inverter inverts the evolved parallel bit test signal; Third inverter; Fourth inverter; Fifth inverter; A first NOR gate circuit is configured to perform a first NOR operation on the output signal and test bit of the second inverter, and output the result of the first NOR operation to the third inverter; The second NOR gate is configured to perform a second NOR operation on the first test ignore signal and the test pass signal, and output the result of the second NOR operation to the fourth inverter. The third NOR gate is configured to perform a third NOR operation on the second test ignore signal and the test pass signal, and output the result of the third NOR operation to the fifth inverter. The first NAND gate circuit is configured to perform a first NAND operation on the output signal of the fourth inverter and the output signal of the first NOR gate circuit, and output the result of the first NAND operation to the second input terminal. The second NAND gate circuit is configured to perform a second NAND operation on the output signal of the third inverter and the output signal of the fifth inverter, and output the result of the second NAND operation to the second inverting input terminal. A first PMOS transistor is connected between a power supply terminal and a first node, and has a gate connected to the first input terminal; A second PMOS transistor is connected between the power supply terminal and the first node, and has a gate connected to the second input terminal; A third PMOS transistor is connected between the first node and the second node, and has a gate connected to the output terminal of the first inverter, the second node being connected to the output terminal of the parallel bit test operation. A fourth PMOS transistor is connected between the first node and the second node and has a gate connected to the second inverting input terminal; A first NMOS transistor is connected between the second node and the third node and has a gate connected to the output terminal of the first inverter; A second NMOS transistor is connected between the second node and the third node, and has a gate connected to the second input terminal; A third NMOS transistor is connected between the third node and the ground terminal, and has a gate connected to the first input terminal; as well as A fourth NMOS transistor is connected between the third node and the ground terminal, and has a gate connected to the second inverting input terminal.

10. The memory device according to claim 9, wherein, The first test ignore signal corresponds to data bit "0", and the second test ignore signal corresponds to data bit "1".

11. The memory device according to claim 9, wherein, The evolved parallel bit test signal, the test pass signal, the first test ignore signal, and the second test ignore signal are generated from the mode register group in the parallel bit test operation.

12. The memory device according to claim 9, wherein, In the parallel bit test operation, the test pass signal is received independently according to the memory bank.

13. The memory device according to claim 9, wherein, In the parallel bit test operation, the same test pass signal is received in either memory bank group.

14. The memory device according to claim 13, wherein, Any memory bank group is the first memory bank group.

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