Display device

Abstract

A display device is provided, including: a first transistor including a gate electrode; a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor; a lower gate signal line extending in a first direction; an upper gate signal line provided over the lower gate signal line and extending in the first direction; and a first connection pattern provided over the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. In an overlapping region in which the lower gate signal line or the upper gate signal line overlaps with the first connection pattern, an entirety of the upper gate signal line overlaps with a portion of the lower gate signal line.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a display device. BACKGROUND

[0002] A display device is a device that displays an image for providing visual information to a user. The display device can include pixels, and each of the pixels can include a light emitting element that generates light and a pixel circuit that provides a driving current to the light emitting element. The pixel circuit can include stacked conductive layers.

[0003] In a process of forming the conductive layers to form the pixel circuit, the conductive layers can be misaligned due to misalignment of a mask. In this case, capacitances between the conductive layers of a pixel row can not be consistent, and thus, flyback voltages of the pixel row can not be consistent. Accordingly, a stain can be recognized in the display device, and display quality of the display device can be reduced.

[0004] It will be understood that this Background of the Technology section of the Specification is, in part, intended to provide useful background information to facilitate a better understanding of the Technology. However, it also can include ideas, concepts, or recognitions that were not SUMMARY

[0005] Embodiments provide a display device having improved display quality.

[0006] A display device according to an embodiment can include a first transistor including a gate electrode disposed on a substrate, a second transistor including a lower gate electrode disposed on the substrate, an upper gate electrode disposed on the lower gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode, an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end portion of the second transistor, and crossing the lower gate signal line and the upper gate signal line. In an overlapping area in which the lower gate signal line or the upper gate signal line can be overlapped with the first connection pattern, an entirety of the upper gate signal line can overlap with a portion of the lower gate signal line.

[0007] In an embodiment, in the overlapping area, a width of the upper gate signal line in a second direction can be smaller than a width of the lower gate signal line in the second direction.

[0008] In an embodiment, a difference between the width of the lower gate signal line in the second direction and the width of the upper gate signal line in the second direction can be greater than about 1 µm.

[0009] In an embodiment, the first connection pattern can extend in the second direction in the overlapping region.

[0010] In an embodiment, the first lower gate signal line can have a width along the second direction which is substantially equal inside and outside the overlapping region, and the first upper gate signal line can have a width along the second direction which is substantially equal inside and outside the overlapping region.

[0011] In an embodiment, in a plan view, the lower gate signal line can protrude in the second direction in the overlapping region.

[0012] In an embodiment, in a plan view, the upper gate signal line can be recessed in the second direction in the overlapping region.

[0013] In an embodiment, the first transistor can include a first active layer provided between the base and the gate electrode, and the second transistor can include a second active layer provided between the lower gate electrode and the upper gate electrode. A first end portion of the second active layer can be electrically connected to an end portion of the first active layer.

[0014] In an embodiment, the first active layer of the first transistor can include polycrystalline silicon, and the second active layer of the second transistor can include an oxide semiconductor.

[0015] In an embodiment, the first connection pattern can electrically connect the gate electrode of the first transistor and a second end portion of the second active layer of the second transistor.

[0016] In an embodiment, the display device can further include a second connection pattern electrically connecting an end portion of the first active layer and a first end portion of the second active layer, wherein the first connection pattern and the second connection pattern can be provided on the same layer.

[0017] A display device according to an embodiment can include a first transistor including a gate electrode provided over a base; a second transistor including a lower gate electrode provided over the base, an upper gate electrode provided over the lower gate electrode, and a first end portion electrically connected to an end portion of the first transistor; a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line provided over the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern provided over the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end portion of the second transistor, and crossing the lower gate signal line and the upper gate signal line. In an overlapping region in which the lower gate signal line or the upper gate signal line can overlap with the first connection pattern, an entirety of the lower gate signal line can overlap with a portion of the upper gate signal line.

[0018] In an embodiment, in the overlapping region, the width of the upper gate signal line in the second direction can be greater than the width of the lower gate signal line in the second direction.

[0019] In an embodiment, the difference between the width of the upper gate signal line in the second direction and the width of the lower gate signal line in the second direction can be greater than about 1 μm.

[0020] In an embodiment, the first connection pattern can extend in the second direction in the overlapping region.

[0021] In an embodiment, the width of the first lower gate signal line in the second direction both inside and outside the overlapping region can be substantially equal, and the width of the first upper gate signal line in the second direction both inside and outside the overlapping region can be substantially equal.

[0022] In an embodiment, in a plan view, the lower gate signal line can be recessed in the second direction in the overlapping region.

[0023] In an embodiment, in a plan view, the upper gate signal line can protrude in the second direction in the overlapping region.

[0024] In an embodiment, the first transistor can include a first active layer provided between a substrate and a gate electrode, and the second transistor can include a second active layer provided between a lower gate electrode and an upper gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer.

[0025] In an embodiment, the first active layer of the first transistor can include polysilicon, and the second active layer of the second transistor can include an oxide semiconductor.

[0026] In an embodiment, the first connection pattern can electrically connect the gate electrode of the first transistor and a second end portion of the second active layer of the second transistor.

[0027] In an embodiment, the display device can further include a second connection pattern electrically connecting an end portion of the first active layer and a first end portion of the second active layer, wherein the first connection pattern and the second connection pattern can be provided on the same layer.

[0028] In the display device according to the embodiment, in the stacking region where the lower gate signal line or the upper gate signal line can overlap with the first connection pattern, the entire upper gate signal line can overlap with a portion of the lower gate signal line, or the entire lower gate signal line can overlap with a portion of the upper gate signal line, thereby constantly maintaining the capacitance between the lower gate signal line and the first connection pattern, as well as the capacitance between the upper gate signal line and the first connection pattern. Therefore, the flyback voltage of the first connection pattern caused by the gate signals applied to the lower and upper gate signal lines can be constant. Furthermore, no blemishes appear in the display device, thus improving the display quality. Attached Figure Description

[0029] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a plan view showing a display device according to an embodiment;

[0031] Figure 2 This is an equivalent circuit diagram showing the pixels according to an embodiment;

[0032] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 It is shown Figure 2 A layout diagram of example pixels in the image;

[0033] Figure 16 It is along Figure 13 A schematic cross-sectional view taken by line I-I' in the middle;

[0034] Figure 17 It is shown Figure 13 A layout diagram of an example of region A in the diagram;

[0035] Figure 18 It is along Figure 17 A schematic cross-sectional view taken from line II-II' in the middle;

[0036] Figure 19 It is shown Figure 13 A layout diagram of an example of region A in the diagram;

[0037] Figure 20 It is shown Figure 13a layout diagram of an example of region A in FIG. 1;

[0038] Figure 21 is a graph illustrating a flyback voltage of the third node based on the second gate signal;

[0039] Figure 22 is a graph illustrating Figure 13 a layout diagram of an example of region A in FIG. 1;

[0040] Figure 23 is a schematic cross-sectional view taken along line III-III' in Figure 22

[0041] Figure 24 is a graph illustrating a flyback voltage of the third node based on the second gate signal; Figure 13 a layout diagram of an example of region A in FIG. 1;

[0042] Figure 25 is a graph illustrating Figure 13 a layout diagram of an example of region A in FIG. 1; and

[0043] Figure 26 is a graph illustrating Figure 2 a layout diagram of an example of pixel in FIG. 1. DETAILED DESCRIPTION

[0044] Hereinafter, a display device according to an embodiment will be explained in detail with reference to the accompanying drawings.

[0045] Some of the parts not associated with the description can not be provided in order to describe the disclosed embodiments, and the same reference numerals refer to the same elements throughout the specification.

[0046] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0047] The terms "and" and "or" can be used in an inclusive and exclusive sense and can be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of" for the purpose of its meaning and explanation. For example, "at least one of A and B" can be understood to mean "A, B, or both A and B"

[0048] ​It will be understood that, although the terms“first,”“second,” etc. can be used herein to describe various components, these components should not be limited by these terms. These components are only called such for the purpose of distinguishing between one component and another component. For example, a component called a first element in one embodiment can also be referred to as a second element in another embodiment without departing from the scope of the claims.

[0049] As used herein, the singular forms“a,”“an,” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] It will be further understood that the terms“comprises” and / or“comprising,”“includes” and / or“including” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0051] When a layer, film, region, substrate, area, or element is referred to as being“on” another layer, film, region, substrate, area, or element, it can be directly on the other layer, film, region, substrate, area, or element or intervening layers, films, regions, substrates, areas, or elements can also be present. In contrast, when an element is referred to as being“directly on” another element, there are no intervening layers, films, regions, substrates, areas, or elements between them. Also, when a layer, film, region, substrate, area, or element is referred to as being“under” or“beneath” another layer, film, region, substrate, area, or element, it can be directly under the other layer, film, region, substrate, area, or element, or intervening layers, films, regions, substrates, areas, or elements can also be present. In contrast, when a layer, film, region, substrate, area, or element is referred to as being“directly under” or“directly beneath” another layer, film, region, substrate, area, or element, there are no intervening layers, films, regions, substrates, areas, or elements between them. Also,“over” or“on” can include positioned above or below, and does not necessarily imply a gravity-based orientation.

[0052] For ease of description, spatially relative terms, such as "below", "under", "lower", "above", "upper", and the like, can be used herein for the purpose of illustrating one element or component's relationship to another element or component as

[0053] For ease of illustration, the dimensions of components in the drawings can be exaggerated. In other words, the following embodiments are not limited to the dimensions of components and thicknesses of components shown in the drawings, since the dimensions and thicknesses of components in the drawings are arbitrarily shown for ease of illustration.

[0054] In addition, the term "overlying" or "overlie" means that a first object can be on a second object or below the second object or to the side of the second object, and vice versa. In addition, the term "overlying" can include layered, stacked, facing or facing toward, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by one of ordinary skill in the art. The terms "facing" and "facing toward" mean that a first element can be directly or indirectly opposite a second element. In the case where a third element is interposed between the first element and the second element, the first element and the second element can be understood to indirectly oppose each other, even though the first element and the second element still face each other. When an element is described as "not overlying" or "not overlying" another element, this can include the element being spaced apart from, offset from, or disposed apart from the other element, or any other suitable term as will be appreciated and understood by one of ordinary skill in the art.

[0055] In the specification, expressions such as "A and / or B" mean A, B, or A and B. In addition, expressions such as "at least one of A and B" mean A, B, or A and B.

[0056] In the following embodiments, when a component is referred to as being "on a plane", it is understood that the component is viewed from the top, and when a component is referred to as being "on a schematic cross-section", it is understood that the component is cut vertically and viewed from the side.

[0057] It will be understood that when a layer, region, or element is referred to as being "connected" or "coupled" to another layer, region, or element, it can be "directly connected" or "directly coupled" to the other layer, region, or element or it can be "indirectly connected" or "indirectly coupled" to the other layer, region, or element with other layers, regions, or elements intervening therebetween. For example, it will be understood that when a layer, region, or element is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or element, it can be "directly electrically connected" or "directly electrically coupled" to the other layer, region, or element or it can be "indirectly electrically connected" or "indirectly electrically coupled" to the other layer, region, or element with other layers, regions, or elements intervening therebetween

[0058] Also, when an element is referred to as being "connected" or "in contact with" another element, it can be "electrically connected" or "in electrical contact with" the other element, or "indirectly connected" or "in indirect contact with" the other element with other elements interposed therebetween.

[0059] "about" or "approximately" as used herein includes the recited value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0060] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that can not be perpendicular to each other.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0062] Figure 1 is a plan view showing a display device according to an embodiment.

[0063] Referring to Figure 1According to an embodiment, a display device can include pixels PX. Each pixel PX can refer to a single area defined by dividing a display area for displaying a color in a plan view, and one pixel PX can display one predetermined primary color. In other words, one pixel PX can be a minimum unit that can display a color independent of another pixel PX. The pixels PX can be arranged or disposed along a first direction DR1 and a second direction DR2 intersecting or crossing the first direction DR1.

[0064] Figure 2 is an equivalent circuit diagram illustrating a pixel according to an embodiment.

[0065] Referring to Figure 2 According to an embodiment, a pixel PX can include a pixel circuit PC and a light emitting element EL. The pixel circuit PC can provide a driving current to the light emitting element EL. The light emitting element EL can emit light based on the driving current provided from the pixel circuit PC. The pixel circuit PC can include at least one transistor and at least one capacitor to generate the driving current.

[0066] In an embodiment, the pixel circuit PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor CAP. However, the disclosure is not limited thereto, and in an embodiment, the pixel circuit PC can include two to six transistors or eight or more transistors and / or two or more capacitors.

[0067] The first transistor T1 can be electrically connected between a first node N1 and a second node N2. A gate electrode of the first transistor T1 can be electrically connected to a third node N3. The first transistor T1 can generate a driving current based on a voltage between the first node N1 and the third node N3.

[0068] The second transistor T2 can be electrically connected between a data line 171 and the first node N1. A gate electrode of the second transistor T2 can receive a first gate signal GS1. The second transistor T2 can transmit a data voltage DV to the first node N1 based on the first gate signal GS1.

[0069] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. A gate electrode of the third transistor T3 can receive a second gate signal GS2. The third transistor T3 can electrically connect the second node N2 and the third node N3 based on the second gate signal GS2 to compensate for a threshold voltage of the first transistor T1.

[0070] The fourth transistor T4 can be electrically connected between the first initialization voltage line 133 and the third node N3. A gate electrode of the fourth transistor T4 can receive a third gate signal GS3. In an embodiment, in a case where the pixel PX is included in an Nth (N is a positive integer equal to or greater than 2) pixel row, the third gate signal GS3 can be a first gate signal applied to an (N-1)th pixel row. The fourth transistor T4 can receive the first initialization voltage IV1 from the first initialization voltage line 133, and can transmit the first initialization voltage IV1 to the third node N3 based on the third gate signal GS3 to initialize the gate electrode of the first transistor T1.

[0071] The fifth transistor T5 can be electrically connected between the power voltage line 172 and the first node N1. A gate electrode of the fifth transistor T5 can receive an emission control signal EM. The power voltage line 172 can transmit a first power voltage VDD from a first power supply.

[0072] The sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4. A gate electrode of the sixth transistor T6 can receive the emission control signal EM. The fifth transistor T5 and the sixth transistor T6 can transmit the driving current generated from the first transistor T1 to the light emitting element EL based on the emission control signal EM.

[0073] The seventh transistor T7 can be electrically connected between the second initialization voltage line 161 and the fourth node N4. A gate electrode of the seventh transistor T7 can receive a fourth gate signal GS4. In an embodiment, in a case where the pixel PX is included in an Nth pixel row, the fourth gate signal GS4 can be a first gate signal applied to an (N+1)th pixel row. The seventh transistor T7 can receive the second initialization voltage IV2 from the second initialization voltage line 161, and can transmit the second initialization voltage IV2 to the fourth node N4 based on the fourth gate signal GS4 to initialize the light emitting element EL.

[0074] In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a transistor having a single gate structure, and each of the third transistor T3 and the fourth transistor T4 can be a transistor having a double gate structure. However, the disclosure is not limited thereto. In such an embodiment, a gate electrode of each of the third transistor T3 and the fourth transistor T4 can include a lower gate electrode and an upper gate electrode, and the lower gate electrode and the upper gate electrode can be electrically connected to each other.

[0075] In an embodiment, the active layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be formed of polysilicon, and the active layer of each of the third transistor T3 and the fourth transistor T4 can be formed of an oxide semiconductor. In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be PMOS, and each of the third transistor T3 and the fourth transistor T4 can be NMOS. However, the disclosure is not limited thereto.

[0076] The capacitor CAP can be electrically connected between the power voltage line 172 and the third node N3. In the case where the second transistor T2 is off, the capacitor CAP can hold the voltage between the first node N1 and the third node N3, so that the light emitting element EL can emit light.

[0077] The light emitting element EL can be electrically connected between the fourth node N4 and the second power supply. The second power supply can supply a second power voltage VSS. In an embodiment, the second power voltage VSS can be less than the first power voltage VDD. The light emitting element EL can emit light based on a driving current transmitted from the pixel circuit PC.

[0078] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 is a layout diagram illustrating an example of the pixel PX in Figure 2 . Figure 16 is a schematic cross-sectional view taken along the line I-I' in Figure 13 .

[0079] Referring to Figures 2 to 16 , the pixel PX can include a first active layer 110, a first conductive layer 120, a second conductive layer 130, a second active layer 140, a third conductive layer 150, a fourth conductive layer 160, a fifth conductive layer 170, a first electrode 180, an emission layer 190, and a second electrode 200, which can be disposed on a substrate 100.

[0080] The substrate 100 can be an insulating substrate including glass, quartz, plastic, or the like, within the spirit and scope of the disclosure. In an embodiment, the substrate 100 can include a first flexible layer, a first barrier layer disposed on the first flexible layer, a second flexible layer disposed on the first barrier layer, and a second barrier layer disposed on the second flexible layer. Within the spirit and scope of the disclosure, the first flexible layer and the second flexible layer can include an organic insulating material such as polyimide (PI) or the like. Within the spirit and scope of the disclosure, the first barrier layer and the second barrier layer can include an inorganic insulating material such as silicon oxide, silicon nitride, amorphous silicon, or the like.

[0081] The first active layer 110 can be disposed on the substrate 100. In an embodiment, the first active layer 110 can include polysilicon. However, the disclosure is not limited thereto, and in an embodiment, the first active layer 110 can include amorphous silicon, an oxide semiconductor, or the like, within the spirit and scope of the disclosure.

[0082] A buffer layer can be disposed between the substrate 100 and the first active layer 110. The buffer layer can block impurities from penetrating through the substrate 100 toward above the substrate 100. The buffer layer can provide a planarized upper surface above the substrate 100. Within the spirit and scope of the disclosure, the buffer layer can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. The buffer layer can be omitted.

[0083] The first conductive layer 120 can be disposed on the first active layer 110. Within the spirit and scope of the disclosure, the first conductive layer 120 can include a conductive material such as molybdenum (Mo), copper (Cu), or the like.

[0084] The first insulating layer 101 can be disposed between the first active layer 110 and the first conductive layer 120. Within the spirit and scope of the disclosure, the first insulating layer 101 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0085] The first conductive layer 120 can include a first gate signal line 121, an emission control signal line 122, and a conductive pattern 123. The first gate signal line 121 can extend in a first direction DR1. The emission control signal line 122 can be spaced apart from the first gate signal line 121 and can extend in the first direction DR1. The conductive pattern 123 can be positioned or disposed between the first gate signal line 121 and the emission control signal line 122.

[0086] The first portion of the first gate signal line 121 which overlaps the first active layer 110 can form a gate electrode of the second transistor T2, and the second portion of the first gate signal line 121 which overlaps the first active layer 110 can form a gate electrode of the seventh transistor T7. The portion of the first active layer 110 which overlaps the gate electrode of the second transistor T2 can be a channel region of the second transistor T2, and the portion of the first active layer 110 which overlaps the gate electrode of the seventh transistor T7 can be a channel region of the seventh transistor T7. Thus, the first portion of the first gate signal line 121 and the first active layer 110 can form the second transistor T2, and the second portion of the first gate signal line 121 and the first active layer 110 can form the seventh transistor T7.

[0087] The first portion of the emission control signal line 122 which overlaps the first active layer 110 can form a gate electrode of the fifth transistor T5, and the second portion of the emission control signal line 122 which overlaps the first active layer 110 can form a gate electrode of the sixth transistor T6. The portion of the first active layer 110 which overlaps the gate electrode of the fifth transistor T5 can be a channel region of the fifth transistor T5, and the portion of the first active layer 110 which overlaps the gate electrode of the sixth transistor T6 can be a channel region of the sixth transistor T6. Thus, the first portion of the emission control signal line 122 and the first active layer 110 can form the fifth transistor T5, and the second portion of the emission control signal line 122 and the first active layer 110 can form the sixth transistor T6.

[0088] The portion of the conductive pattern 123 which overlaps the first active layer 110 can form a gate electrode of the first transistor T1. The portion of the first active layer 110 which overlaps the gate electrode of the first transistor T1 can be a channel region of the first transistor T1. Thus, the portion of the conductive pattern 123 and the first active layer 110 can form the first transistor T1.

[0089] The second conductive layer 130 can be disposed on the first conductive layer 120. Within the spirit and scope of the disclosure, the second conductive layer 130 can include a conductive material such as molybdenum (Mo), copper (Cu), etc.

[0090] The second insulating layer 102 can be disposed between the first conductive layer 120 and the second conductive layer 130. Within the spirit and scope of the disclosure, the second insulating layer 102 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0091] The second conductive layer 130 can include a first lower gate signal line 131, a second lower gate signal line 132, a first initialization voltage line 133, and a conductive line 134. The first lower gate signal line 131 can extend in the first direction DR1. The second lower gate signal line 132 can be spaced apart from the first lower gate signal line 131 and can extend in the first direction DR1. The first initialization voltage line 133 can be spaced apart from the second lower gate signal line 132 and can extend in the first direction DR1. The conductive line 134 can be spaced apart from the first lower gate signal line 131 and can extend in the first direction DR1.

[0092] The conductive line 134 can overlap the conductive pattern 123. The conductive pattern 123 and the conductive line 134 can form a capacitor CAP.

[0093] The second active layer 140 can be provided over the second conductive layer 130. The second active layer 140 can not overlap the first active layer 110. In an embodiment, the second active layer 140 can include an oxide semiconductor. However, the disclosure is not limited thereto, and in an embodiment, the second active layer 140 can include amorphous silicon, polysilicon, or the like, within the spirit and scope of the disclosure.

[0094] The third insulating layer 103 can be provided between the second conductive layer 130 and the second active layer 140. The third insulating layer 103 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon nitride oxide, or the like, within the spirit and scope of the disclosure.

[0095] The third conductive layer 150 can be provided over the second active layer 140. The third conductive layer 150 can include a conductive material such as molybdenum (Mo), copper (Cu), or the like, within the spirit and scope of the disclosure.

[0096] The fourth insulating layer 104 can be provided between the second active layer 140 and the third conductive layer 150. The fourth insulating layer 104 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon nitride oxide, or the like, within the spirit and scope of the disclosure.

[0097] The third conductive layer 150 can include a first upper gate signal line 151 and a second upper gate signal line 152. The first upper gate signal line 151 can extend in the first direction DR1. The second upper gate signal line 152 can be spaced apart from the first upper gate signal line 151 and can extend in the first direction DR1.

[0098] The portion of the first lower gate signal line 131 which overlaps the second active layer 140 can form a lower gate electrode of the third transistor T3, and the portion of the first upper gate signal line 151 which overlaps the second active layer 140 can form an upper gate electrode of the third transistor T3. The portion of the second active layer 140 which overlaps the lower gate electrode and the upper gate electrode of the third transistor T3 can be a channel region of the third transistor T3. Accordingly, the portion of the first lower gate signal line 131, the second active layer 140, and the portion of the first upper gate signal line 151 can form the third transistor T3. The third transistor T3 can be a transistor having a dual gate structure.

[0099] The portion of the second lower gate signal line 132 which overlaps the second active layer 140 can form a lower gate electrode of the fourth transistor T4, and the portion of the second upper gate signal line 152 which overlaps the second active layer 140 can form an upper gate electrode of the fourth transistor T4. The portion of the second active layer 140 which overlaps the lower gate electrode and the upper gate electrode of the fourth transistor T4 can be a channel region of the fourth transistor T4. Accordingly, the portion of the second lower gate signal line 132, the second active layer 140, and the portion of the second upper gate signal line 152 can form the fourth transistor T4. The fourth transistor T4 can be a transistor having a dual gate structure.

[0100] The fourth conductive layer 160 can be disposed on the third conductive layer 150. In the disclosed spirit and scope, the fourth conductive layer 160 can include a conductive material such as aluminum (Al), titanium (Ti), copper (Cu), etc. In an embodiment, the fourth conductive layer 160 can have a multi-layer structure including a Ti layer, an Al layer, and a Ti layer which can be stacked.

[0101] The fifth insulating layer 105 can be disposed between the third conductive layer 150 and the fourth conductive layer 160. In the disclosed spirit and scope, the fifth insulating layer 105 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. and / or an organic insulating material such as polyimide (PI), etc.

[0102] The fourth conductive layer 160 can include a second initialization voltage line 161, a first connection pattern 162, a second connection pattern 163, a third connection pattern 164, a first contact pattern 165, a second contact pattern 166, and a third contact pattern 167. The second initialization voltage line 161 can extend in the first direction DR1. The second initialization voltage line 161 can be electrically connected to the first active layer 110 through the first contact hole CH1. Accordingly, the second initialization voltage line 161 can be electrically connected to the seventh transistor T7.

[0103] The first connection pattern 162 can be spaced apart from the second initialization voltage line 161. The first connection pattern 162 can be electrically connected to the conductive pattern 123 through the second contact hole CH2, and can be electrically connected to the second active layer 140 through the third contact hole CH3. Accordingly, the first connection pattern 162 can electrically connect the gate electrode of the first transistor T1 and the second end portion of the third transistor T3. For example, the first connection pattern 162 can electrically connect the gate electrode of the first transistor T1 and the second end portion 142 of the second active layer 140.

[0104] The second connection pattern 163 can be spaced apart from the first connection pattern 162. The second connection pattern 163 can be electrically connected to the first active layer 110 through the fourth contact hole CH4, and can be electrically connected to the second active layer 140 through the fifth contact hole CH5. Accordingly, the second connection pattern 163 can electrically connect the end portion of the first transistor T1 and the first end portion of the third transistor T3. As an example, the second connection pattern 163 can electrically connect the end portion 111 of the first active layer 110 and the first end portion 141 of the second active layer 140.

[0105] The third connection pattern 164 can be spaced apart from the second connection pattern 163. The third connection pattern 164 can be electrically connected to the first initialization voltage line 133 through the sixth contact hole CH6, and can be electrically connected to the second active layer 140 through the seventh contact hole CH7. Accordingly, the third connection pattern 164 can electrically connect the first initialization voltage line 133 and the second active layer 140. The first initialization voltage line 133 can be electrically connected to the fourth transistor T4 through the third connection pattern 164.

[0106] The first contact pattern 165 can be spaced apart from the third connection pattern 164. The first contact pattern 165 can be electrically connected to the first active layer 110 through the eighth contact hole CH8. Accordingly, the first contact pattern 165 can be electrically connected to the second transistor T2.

[0107] The second contact pattern 166 can be spaced apart from the first contact pattern 165. The second contact pattern 166 can be electrically connected to the first active layer 110 through the ninth contact hole CH9, and can be electrically connected to the conductive line 134 through the tenth contact hole CH10. Accordingly, the second contact pattern 166 can be electrically connected to the fifth transistor T5 and the capacitor CAP.

[0108] The third contact pattern 167 can be spaced apart from the second contact pattern 166. The third contact pattern 167 can be electrically connected to the first active layer 110 through the eleventh contact hole CH11. Accordingly, the third contact pattern 167 can be electrically connected to the sixth transistor T6.

[0109] A fifth conductive layer 170 can be disposed on the fourth conductive layer 160. In the disclosed spirit and scope, the fifth conductive layer 170 can include a conductive material such as aluminum (Al), titanium (Ti), copper (Cu), etc. In an embodiment, the fifth conductive layer 170 can have a multi-layer structure including a Ti layer, an Al layer, and a Ti layer which can be stacked.

[0110] A sixth insulating layer 106 can be disposed between the fourth conductive layer 160 and the fifth conductive layer 170. In the disclosed spirit and scope, the sixth insulating layer 106 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. and / or an organic insulating material such as polyimide (PI), etc.

[0111] The fifth conductive layer 170 can include a data line 171, a power voltage line 172, and a fourth contact pattern 173. The data line 171 can extend in the second direction DR2. The data line 171 can be electrically connected to the first contact pattern 165 through a twelfth contact hole CH12. Accordingly, the data line 171 can be electrically connected to the second transistor T2 through the first contact pattern 165.

[0112] The power voltage line 172 can be spaced apart from the data line 171 and can extend in the second direction DR2. The power voltage line 172 can be electrically connected to the second contact pattern 166 through a thirteenth contact hole CH13. Accordingly, the power voltage line 172 can be electrically connected to the fifth transistor T5 and the capacitor CAP through the second contact pattern 166.

[0113] The fourth contact pattern 173 can be spaced apart from the power voltage line 172. The fourth contact pattern 173 can be electrically connected to the third contact pattern 167 through a fourteenth contact hole CH14.

[0114] A first electrode 180 can be disposed on the fifth conductive layer 170. In the disclosed spirit and scope, the first electrode 180 can include a conductive material such as a metal, an alloy, a transparent conductive oxide, etc. For example, in the disclosed spirit and scope, the first electrode 180 can include silver (Ag), indium tin oxide (ITO), etc. In an embodiment, the first electrode 180 can have a multi-layer structure including an ITO layer, an Ag layer, and an ITO layer which can be stacked.

[0115] A seventh insulating layer 107 can be disposed between the fifth conductive layer 170 and the first electrode 180. In the disclosed spirit and scope, the seventh insulating layer 107 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. and / or an organic insulating material such as polyimide (PI), etc.

[0116] The first electrode 180 can be electrically connected to the fourth contact pattern 173 through the contact hole. Accordingly, the first electrode 180 can be electrically connected to the sixth transistor T6 through the third contact pattern 167 and the fourth contact pattern 173.

[0117] The eighth insulating layer 108 can be disposed on the first electrode 180. The eighth insulating layer 108 can cover or be stacked with the first electrode 180, and can be disposed on the seventh insulating layer 107. The eighth insulating layer 108 can have a pixel opening exposing at least a portion of the first electrode 180. In an embodiment, the pixel opening can expose a central portion of the first electrode 180, and the eighth insulating layer 108 can cover or be stacked with a peripheral portion of the first electrode 180. Within the spirit and scope of the disclosure, the eighth insulating layer 108 can include an organic insulating material such as polyimide (PI), etc.

[0118] The emission layer 190 can be disposed on the first electrode 180. The emission layer 190 can be disposed on the first electrode 180 exposed by the pixel opening. The emission layer 190 can include at least one of an organic light emitting material and a quantum dot.

[0119] In an embodiment, the organic light emitting material can include a low molecular organic compound or a high molecular organic compound. For example, within the spirit and scope of the disclosure, the low molecular organic compound can include copper phthalocyanine, diphenyl benzidine (N,N'-diphenylbenzidine), tris-hydroxyquinoline aluminum (tris-(8-hydroxyquinoline) aluminum), etc. Within the spirit and scope of the disclosure, the high molecular organic compound can include polyethylenedioxythiophene (poly(3,4-ethylenedioxythiophene)), polyaniline, polyphenylenevinylene, polyfluorene, etc.

[0120] In an embodiment, the quantum dot can include a core including a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and combinations thereof. In an embodiment, the quantum dot can have a core-shell structure including a core and a shell surrounding the core. The shell can prevent chemical degeneration of the core, thereby functioning as a protective layer for maintaining a semiconductor property and a charging layer for imparting an electrophoretic property to the quantum dot.

[0121] The second electrode 200 can be disposed on the emission layer 190. In an embodiment, the second electrode 200 can also be disposed on the eighth insulating layer 108. Within the spirit and scope of the disclosure, the second electrode 200 can include a conductive material such as a metal, an alloy, a transparent conductive oxide, etc. For example, within the spirit and scope of the disclosure, the second electrode 200 can include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. The first electrode 180, the emission layer 190, and the second electrode 200 can form a light emitting element EL.

[0122] Figure 17 is a layout diagram illustrating an example of a region A in Figure 13 Figure 18 is a schematic cross-sectional view taken along line II-II' in Figure 17

[0123] Referring to Figure 17 and Figure 18 , the first upper gate signal line 151 can be disposed on the first lower gate signal line 131, and the first connection pattern 162 can be disposed on the first upper gate signal line 151. The first connection pattern 162 can intersect or cross the first lower gate signal line 131 and the first upper gate signal line 151, which can extend in the first direction DR1. The area in which the first lower gate signal line 131 or the first upper gate signal line 151 can be overlapped with the first connection pattern 162 can be defined as an overlap area OA. The first connection pattern 162 can extend in the second direction DR2 in the overlap area OA.

[0124] In the overlap area OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be smaller than the width 131W of the first lower gate signal line 131 in the second direction DR2. The entirety of the first upper gate signal line 151 can overlap a portion of the first lower gate signal line 131 in the overlap area OA. In other words, a portion of the first lower gate signal line 131 can overlap the first upper gate signal line 151 in the overlap area OA, and another portion of the first lower gate signal line 131 can not overlap the first upper gate signal line 151 in the overlap area OA. For example, a central portion of the first lower gate signal line 131 in the second direction DR2 can overlap the first upper gate signal line 151 in the overlap area OA, and side portions of the first lower gate signal line 131 in the second direction DR2 can not overlap the first upper gate signal line 151 in the overlap area OA.

[0125] ​​In the comparative example, in a case where the first lower gate signal line and the first upper gate signal line partially overlap each other in the overlap region, the capacitance between the first lower gate signal line and the first upper gate signal line can change due to a tolerance in the process of forming the first upper gate signal line on the first lower gate signal line. However, in the embodiment, in the overlap region OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be smaller than the width 131W of the first lower gate signal line 131 in the second direction DR2, and the entirety of the first upper gate signal line 151 can overlap a portion of the first lower gate signal line 131 in the overlap region OA. Thus, the capacitance between the first lower gate signal line 131 and the first connection pattern 162 and the capacitance between the first upper gate signal line 151 and the first connection pattern 162 can be constantly maintained despite the tolerance in the process of forming the first upper gate signal line 151 on the first lower gate signal line 131 being taken into account.

[0126] In the embodiment, in the overlap region OA, a value obtained by subtracting the width 151W of the first upper gate signal line 151 in the second direction DR2 from the width 131W of the first lower gate signal line 131 in the second direction DR2 can be greater than about 1 pm. In other words, in the overlap region OA, a difference between the width 131W of the first lower gate signal line 131 in the second direction DR2 and the width 151W of the first upper gate signal line 151 in the second direction DR2 can be greater than about 1 pm. A tolerance of less than about 0.5 pm in the second direction DR2 can occur in the process of forming the first upper gate signal line 151 on the first lower gate signal line 131. Because the value obtained by subtracting the width 151W of the first upper gate signal line 151 in the second direction DR2 from the width 131W of the first lower gate signal line 131 in the second direction DR2 can be greater than about 1 pm in the overlap region OA, the entirety of the first upper gate signal line 151 can overlap a portion of the first lower gate signal line 131 in the overlap region OA despite the tolerance of less than about 0.5 pm in the second direction DR2 that can occur in the process of forming the first upper gate signal line 151 on the first lower gate signal line 131.

[0127] In the embodiment, each of the width of the first lower gate signal line 131 in the second direction DR2 and the width of the first upper gate signal line 151 in the second direction DR2 can be constant. For example, the width of the first lower gate signal line 131 in the second direction DR2 outside the overlap region OA can be substantially equal to the width 131W of the first lower gate signal line 131 in the second direction DR2 inside the overlap region OA, and the width of the first upper gate signal line 151 in the second direction DR2 outside the overlap region OA can be substantially equal to the width 151W of the first upper gate signal line 151 in the second direction DR2 inside the overlap region OA.

[0128] Figure 19 is a layout view illustrating an example of the region A in Figure 13 . Figure 20 is a layout view illustrating an example of the region A in Figure 13 .

[0129] Referring to Figure 19 , in an embodiment, the first lower gate signal line 131 can protrude in the plan view in the second direction DR2 in the overlap region OA. In such an embodiment, a portion of the first upper gate signal line 151 outside the overlap region OA can not overlap with the first lower gate signal line 131, and the first lower gate signal line 131 can have a protruding portion 131P that protrudes in the second direction DR2 in the overlap region OA. For example, a width of the first lower gate signal line 131 in the second direction DR2 outside the overlap region OA can be smaller than a width 131W of the first lower gate signal line 131 in the second direction DR2 inside the overlap region OA, and a width of the first upper gate signal line 151 in the second direction DR2 outside the overlap region OA can be substantially equal to a width 151W of the first upper gate signal line 151 in the second direction DR2 inside the overlap region OA.

[0130] Referring to Figure 20 , in an embodiment, the first upper gate signal line 151 can be recessed in the plan view in the second direction DR2 in the overlap region OA. In such an embodiment, a portion of the first upper gate signal line 151 outside the overlap region OA can not overlap with the first lower gate signal line 131, and the first upper gate signal line 151 can have a recessed portion 151R that is recessed in the second direction DR2 in the overlap region OA. For example, a width of the first lower gate signal line 131 in the second direction DR2 outside the overlap region OA can be substantially equal to a width 131W of the first lower gate signal line 131 in the second direction DR2 inside the overlap region OA, and a width of the first upper gate signal line 151 in the second direction DR2 outside the overlap region OA can be larger than a width 151W of the first upper gate signal line 151 in the second direction DR2 inside the overlap region OA.

[0131] Figure 21 is a graph illustrating a flyback voltage of the third node N3 based on the second gate signal GS2.

[0132] Referring to Figure 2 , Figure 18 and Figures 22 to 25In a case where the second gate signal GS2 applied to the gate electrode of the third transistor T3 changes from a low level to a high level, the second node N2 and the third node N3 can be electrically connected to each other so that the first transistor T1 can be diode-connected. Then, in a case where the second transistor T2 is turned on based on the first gate signal GS1, the data voltage DV can be applied to the first node N1, and thus a voltage V_N3 in which the threshold voltage of the first transistor T1 can be compensated from the data voltage DV can be applied to the third node N3. Then, in a case where the second gate signal GS2 changes from the high level to the low level, the voltage V_N3 of the third node N3 can increase or decrease by as much as the kickback voltage V_KB.

[0133] Because the capacitance can be formed between the first lower gate signal line 131 and the first connection pattern 162 and between the first upper gate signal line 151 and the first connection pattern 162 in the overlapping area OA, the first lower gate signal line 131 and the first upper gate signal line 151 can electrically affect the first connection pattern 162. In a case where the second gate signal GS2 transmitted through the first lower gate signal line 131 and the first upper gate signal line 151 changes from a high level to a low level, the voltage V_N3 of the first connection pattern 162, which can be the third node N3, can increase or decrease by as much as the kickback voltage V_KB.

[0134] In a comparative example, in a case where the kickback voltages V_KB occurring in the pixel rows can be different from each other, a stain can occur in the display device. However, in the embodiment, because the capacitance between the first lower gate signal line 131 and the first connection pattern 162 and the capacitance between the first upper gate signal line 151 and the first connection pattern 162 can be constantly maintained, the kickback voltages V_KB occurring in the pixel rows can be substantially equal to each other, and thus a stain can not occur in the display device, and the display quality of the display device can be improved.

[0135] Hereinafter, a description of elements which can be substantially the same or similar to those of the display device described with reference to Figures 17 to 20 described with reference to Figure 22 described with reference to the display device will not be repeated.

[0136] Figure 13 is a layout view illustrating an example of an area A in Figure 23 is a layout view illustrating an example of an area A in Figure 22 is a schematic cross-sectional view taken along line III-III' in Figure 22 is a schematic cross-sectional view taken along line III-III' in

[0137] described with reference to Figure 23 and Figure 24In the overlapping region OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be larger than the width 131W of the first lower gate signal line 131 in the second direction DR2. The entirety of the first lower gate signal line 131 can overlap with a portion of the first upper gate signal line 151 in the overlapping region OA. In other words, a portion of the first upper gate signal line 151 can overlap with the first lower gate signal line 131 in the overlapping region OA, and another portion of the first upper gate signal line 151 can not overlap with the first lower gate signal line 131 in the overlapping region OA. For example, a central portion of the first upper gate signal line 151 in the second direction DR2 can overlap with the first lower gate signal line 131 in the overlapping region OA, and side portions of the first upper gate signal line 151 in the second direction DR2 can not overlap with the first lower gate signal line 131 in the overlapping region OA.

[0138] In an embodiment, in the overlapping region OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be larger than the width 131W of the first lower gate signal line 131 in the second direction DR2, and the entirety of the first lower gate signal line 131 can overlap with a portion of the first upper gate signal line 151 in the overlapping region OA. Thus, the first upper gate signal line 151 can shield the first lower gate signal line 131 from the first connection pattern 162, despite tolerances in the process of forming the first upper gate signal line 151 on the first lower gate signal line 131. Thus, the capacitance between the first lower gate signal line 131 and the first connection pattern 162 and the capacitance between the first upper gate signal line 151 and the first connection pattern 162 can be consistently maintained.

[0139] In an embodiment, in the overlap region OA, a value of the width 151W of the first upper gate signal line 151 in the second direction DR2 minus the width 131W of the first lower gate signal line 131 in the second direction DR2 can be greater than about 1 pm. In other words, in the overlap region OA, a difference between the width 151W of the first upper gate signal line 151 in the second direction DR2 and the width 131W of the first lower gate signal line 131 in the second direction DR2 can be greater than about 1 pm. A tolerance of less than about 0.5 pm in the second direction DR2 can occur in a process of forming the first upper gate signal line 151 on the first lower gate signal line 131. In the overlap region OA, because the value of the width 151W of the first upper gate signal line 151 in the second direction DR2 minus the width 131W of the first lower gate signal line 131 in the second direction DR2 is greater than about 1 pm, the entirety of the first lower gate signal line 131 can overlap with a portion of the first upper gate signal line 151 in the overlap region OA despite the tolerance of less than about 0.5 pm in the second direction DR2 that can occur in the process of forming the first upper gate signal line 151 on the first lower gate signal line 131.

[0140] In an embodiment, each of the width of the first lower gate signal line 131 in the second direction DR2 and the width of the first upper gate signal line 151 in the second direction DR2 can be constant. For example, the width of the first lower gate signal line 131 in the second direction DR2 outside the overlap region OA can be substantially equal to the width 131W of the first lower gate signal line 131 in the second direction DR2 inside the overlap region OA, and the width of the first upper gate signal line 151 in the second direction DR2 outside the overlap region OA can be substantially equal to the width 151W of the first upper gate signal line 151 in the second direction DR2 inside the overlap region OA. In other words, the width of the first lower gate signal line 131 in the second direction DR2 both inside and outside the overlap region OA can be substantially equal. Similarly, the width of the first upper gate signal line 151 in the second direction DR2 both inside and outside the overlap region OA can be substantially equal.

[0141] Figure 13 is a layout diagram illustrating an example of a region A in Figure 25 . Figure 13 is a layout diagram illustrating an example of a region A in Figure 24 .

[0142] Referring to Figure 25In an embodiment, in the overlapping region OA, the first lower gate signal line 131 can be recessed in the plan view in the second direction DR2. In such an embodiment, a portion of the first lower gate signal line 131 outside the overlapping region OA can not overlap with the first upper gate signal line 151, and the first lower gate signal line 131 can have a recessed portion 131R recessed in the second direction DR2 in the overlapping region OA. For example, a width of the first lower gate signal line 131 in the second direction DR2 outside the overlapping region OA can be greater than a width 131W of the first lower gate signal line 131 in the second direction DR2 inside the overlapping region OA, and a width of the first upper gate signal line 151 in the second direction DR2 outside the overlapping region OA can be substantially equal to a width 151W of the first upper gate signal line 151 in the second direction DR2 inside the overlapping region OA.

[0143] Referring to Figure 26 In an embodiment, in the overlapping region OA, the first upper gate signal line 151 can be protruded in the plan view in the second direction DR2. In such an embodiment, a portion of the first lower gate signal line 131 outside the overlapping region OA can not overlap with the first upper gate signal line 151, and the first upper gate signal line 151 can have a protruded portion 151P protruded in the second direction DR2 in the overlapping region OA. For example, a width of the first lower gate signal line 131 in the second direction DR2 outside the overlapping region OA can be substantially equal to a width 131W of the first lower gate signal line 131 in the second direction DR2 inside the overlapping region OA, and a width of the first upper gate signal line 151 in the second direction DR2 outside the overlapping region OA can be smaller than a width 151W of the first upper gate signal line 151 in the second direction DR2 inside the overlapping region OA.

[0144] Figure 2 is a layout diagram illustrating an example of the pixel PX in Figures 3 to 16 . The pixel PX described with reference to Figure 26 may be substantially the same as or similar to the pixel PX described with reference to ​ . Thus, a description of the repeated elements will be omitted.

[0145] Referring to ​In an embodiment, the third contact hole CH3 electrically connecting the second active layer 140 and the first connection pattern 1162 can not overlap the first gate signal line 121. In other words, the third contact hole CH3 and the first gate signal line 121 can be spaced apart from each other in a plan view. Accordingly, a path for compensating for the threshold voltage of the first transistor T1 through the second active layer 140, the third contact hole CH3, and the first connection pattern 1162 can not overlap the first gate signal line 121 transmitting the first gate signal.

[0146] In a case where the third contact hole CH3 overlaps the first gate signal line 121 (in other words, in a case where the path for compensating for the threshold voltage of the first transistor T1 overlaps the first gate signal line 121), the resistance of the second active layer 140 can increase due to the first gate signal transmitted by the first gate signal line 121, and thus the on-current of the third transistor T3 can decrease. However, in an embodiment, the third contact hole CH3 electrically connecting the second active layer 140 and the first connection pattern 1162 can not overlap the first gate signal line 121, and thus the first gate signal transmitted by the first gate signal line 121 can substantially not affect the path for compensating for the threshold voltage of the first transistor T1. Accordingly, a decrease in the on-current of the third transistor T3 due to an increase in the resistance of the second active layer 140 can be prevented.

[0147] The display device according to an embodiment can be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like, within the spirit and scope of the disclosure.

[0148] Although the display device according to an embodiment has been described with reference to the accompanying drawings, the illustrated embodiment is an example, and modifications and changes can be made without departing from the technical spirit described in the claims.

Claims

1. A display device comprising: a first transistor including a gate electrode provided over a substrate; a second transistor including a lower gate electrode provided over the substrate, an upper gate electrode provided over the lower gate electrode, and a first end portion electrically connected to an end portion of the first transistor; a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line provided over the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern provided over the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line, wherein, in a superposition region where the lower gate signal line or the upper gate signal line is superposed with the first connection pattern, an entirety of the upper gate signal line overlaps with a portion of the lower gate signal line.

2. The display device according to claim 1, wherein In the superposition region, a width of the upper gate signal line in a second direction is smaller than a width of the lower gate signal line in the second direction.

3. The display device according to claim 2, wherein A difference between the width of the lower gate signal line in the second direction and the width of the upper gate signal line in the second direction is greater than 1 μm.

4. The display device according to claim 2, wherein The first connection pattern extends in the second direction in the superposition region.

5. The display device according to claim 2, wherein the width of the lower gate signal line in the second direction is equal both inside and outside the superposition region, and the width of the upper gate signal line in the second direction is equal both inside and outside the superposition region.

6. The display device according to claim 2, wherein In a plan view, the lower gate signal line protrudes in the second direction in the superposition region.

7. The display device according to claim 2, wherein In a plan view, the upper gate signal line is recessed in the second direction in the superposition region.

8. The display device according to claim 1, wherein the first transistor includes a first active layer provided between the substrate and the gate electrode, and the second transistor includes a second active layer provided between the lower gate electrode and the upper gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer.

9. The display device according to claim 8, wherein the first active layer of the first transistor includes polycrystalline silicon, and the second active layer of the second transistor includes an oxide semiconductor.

10. The display device of claim 8, wherein, The first connection pattern electrically connects the gate electrode of the first transistor and a second end portion of the second active layer of the second transistor.

11. The display device according to claim 8, further comprising: a second connection pattern electrically connecting the end portion of the first active layer and the first end portion of the second active layer, wherein the first connection pattern and the second connection pattern are provided over the same layer.

12. A display device comprising: a first transistor including a gate electrode provided over a substrate; a second transistor including a lower gate electrode provided over the substrate, an upper gate electrode provided over the lower gate electrode, and a first end portion electrically connected to an end portion of the first transistor; a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line provided over the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern provided over the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line, wherein in a superposition region in which the lower gate signal line or the upper gate signal line is superposed with the first connection pattern, an entirety of the lower gate signal line overlaps with a portion of the upper gate signal line.

13. The display device of claim 12, wherein, In the superposition region, a width of the upper gate signal line in a second direction is larger than a width of the lower gate signal line in the second direction.

14. The display device of claim 13, wherein, A difference between the width of the upper gate signal line in the second direction and the width of the lower gate signal line in the second direction is greater than 1 μm.

15. The display device of claim 13, wherein, The first connection pattern extends in the second direction in the superposition region.

16. The display device according to claim 13, wherein the width of the lower gate signal line in the second direction is equal both inside and outside the superposition region, and the width of the upper gate signal line in the second direction is equal both inside and outside the superposition region.

17. The display device of claim 13, wherein, In a plan view, the lower gate signal line is recessed in the second direction in the superposition region.

18. The display device of claim 13, wherein, In a plan view, the upper gate signal line is protruded in the second direction in the superposition region.

19. The display device according to claim 12, wherein the first transistor includes a first active layer provided between the substrate and the gate electrode, and the second transistor includes a second active layer provided between the lower gate electrode and the upper gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer.

20. The display device according to claim 19, wherein the first active layer of the first transistor includes polycrystalline silicon, and the second active layer of the second transistor includes an oxide semiconductor.

21. The display device of claim 19, wherein, The first connection pattern electrically connects the gate electrode of the first transistor and a second end portion of the second active layer of the second transistor.

22. The display device according to claim 19, further comprising: a second connection pattern electrically connecting the end portion of the first active layer and the first end portion of the second active layer, wherein the first connection pattern and the second connection pattern are provided over the same layer.

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