Method and apparatus for supporting source line configuration of a memory device

Abstract

The present application relates to a source line configuration for a memory device. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled to the floating gate of the first transistor. The memory cell may be coupled to a word line, a digit line, and a source line. During a write operation, one or more memory cells in the memory device may be used to clamp the source line to the digit line. During a read operation, one or more memory cells in the memory device may be used to ground the source line.

Description

[0001] Cross Reference

[0002] This patent application claims priority to PCT Application No. PCT / US2020 / 017734, filed by Fackenthal on February 11, 2020, entitled “SOURCE LINE CONFIGURATIONS FOR A MEMORY DEVICE,” which claims priority to U.S. Patent Application No. 16 / 282,749, filed by Fackenthal on February 22, 2019, entitled “SOURCE LINE CONFIGURATIONS FOR AMEMORY DEVICE,” each of which is assigned to the assignee herein and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] TECHNICAL FIELD The field relates to source line configurations for memory devices. Background Art

[0004] The following generally relates to a system including at least one memory device and more particularly to source line configurations for memory cells having floating gates and techniques for using the same.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states in the memory device. For example, binary devices most commonly store one of two states, typically represented by a logical 1 or a logical 0. Other devices can store more than two states. To access stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state into the memory device.

[0006] Some types of memory devices may bias (e.g., apply voltages to) various access lines during read and write operations of memory cells. These access lines may include word lines, digit lines, and / or other types of conductive lines that may be coupled to memory cells. Summary of the Invention

[0007] A method is described. In some embodiments, the method may include: receiving a command to perform a write operation on a memory cell, the memory cell including a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor connected to the floating gate of the first transistor; coupling a source line connected to the first transistor and a digit line connected to the second transistor based at least in part on receiving the command; applying a first voltage to the digit line as part of the write operation; activating the second transistor to apply a second voltage to the floating gate of the first transistor, the second voltage being based at least in part on the first voltage; and deactivating the second transistor to cause the first transistor to store the logic state based at least in part on the second voltage applied to the floating gate of the first transistor.

[0008] A method is described. In some embodiments, the method may include: receiving a command to perform a read operation on a memory cell, the memory cell including a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled to the floating gate of the first transistor; grounding a source line coupled to the first transistor of the memory cell; applying a first voltage to a digit line connected to the second transistor of the memory cell as part of the read operation; and determining the logic state stored by the memory cell based at least in part on a signal on the digit line during at least a portion of a duration that the source line is grounded.

[0009] An apparatus is described. In some embodiments, the apparatus may include: an array of memory cells, each memory cell of the array including a first transistor including a control gate and a floating gate and a second transistor connected to the floating gate of the first transistor, wherein each memory cell is configured to store a logic state using the first transistor and the second transistor; a set of word lines, each word line connected to the control gate of the first transistor and the gate of the second transistor of a memory cell in a row of the array; a set of digit lines, each digit line connected to a first node of the first transistor and a second node of the second transistor of a memory cell in a column of the array; and a set of source lines, each source line corresponding to one digit line of the set of digit lines and connected to the second node of the first transistor of a corresponding memory cell connected to the one digit line, each source line configured to be biased based on performing an operation using the one digit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Examples of systems supporting methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein are described.

[0011] Figure 2 Examples of memory dies supporting methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein are illustrated.

[0012] Figure 3A and 3B Examples of access line biasing of a memory device are described in support of methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0013] Figure 4 Examples of access line biasing of a memory device are described in support of methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0014] Figure 5 Examples of memory devices are described that support methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0015] Figure 6 An example of a timing diagram is illustrated to support methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0016] Figure 7 An example of a timing diagram is illustrated to support methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0017] Figure 8 A block diagram showing a memory device supporting methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0018] Figure 9 and 10

[0014] Flowcharts are shown illustrating a method or methods supporting methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein. DETAILED DESCRIPTION

[0019] A memory device may include one or more memory cells that are programmable to store different logic states. For example, a memory cell may store one bit of digital logic (eg, a logic 1 state and a logic 0 state) during operation.

[0020] A memory cell can store a logic state using two transistors, one of which can be associated with a floating gate. A floating gate can be an electrical node that is in close proximity to a transistor's control gate but separated from the control gate by a dielectric material. The voltage or charge stored on the floating gate can affect the threshold voltage of the transistor associated with the floating gate and, therefore, can also affect the amount of current flowing through the transistor when a voltage is applied to the control gate. The amount of current flowing through the transistor can be "sensed" to determine the logic state stored by the memory cell. This type of memory cell, which may be referred to as a floating gate memory cell, may not use a capacitor to store a logic state. Instead, a memory cell with a floating gate can store a logic state based on the voltage of the floating gate.

[0021] A floating gate memory cell may include two transistors: a first transistor for storing a logic state and a second transistor for selectively accessing the floating gate of the first transistor. The description herein refers to the first transistor associated with the floating gate as a read transistor because it can be activated during a read operation to read the state of the memory cell. The second transistor in the memory cell may be referred to as a write transistor because it can be activated during a write operation to apply a voltage to the floating gate of the first transistor.

[0022] Floating gate memory cells can be coupled to various access lines. These access lines can include word lines and digit lines, such as those used with other types of memory cells. Floating gate memory cells can also be coupled to an access line called a source line.

[0023] Floating gate memory cells can be read or written by biasing (e.g., applying voltage to) access lines associated with the memory cell, such as a word line, a digit line, and a source line. For example, a word line can be coupled to the control gates of a read transistor and a write transistor and can be biased to select a target memory cell during a read or write operation. A digit line can be coupled to the drains of the read transistor and the write transistor and can be biased to apply a voltage to the floating gate during a write operation (via the write transistor) or to cause current to flow between the digit line and the source line during a read operation (via the read transistor). The source line can be biased to a relatively low voltage (e.g., ground) during a read operation to enable current to flow from the digit line to the source line via the read transistor.

[0024] In some cases, if the source line is biased to a low voltage during a write operation while the digit line is biased to a higher voltage to write a logic state to a selected memory cell, the voltage difference between the digit line and the source line can cause current to flow through unselected memory cells coupled to the same digit line and source line. This accumulated leakage current can cause undesirable effects in the memory device. Therefore, it may be desirable to bias the source line to the digit line voltage during a write operation to eliminate or mitigate undesirable current flow through unselected memory cells. That is, the source line may need to be biased differently depending on whether it is used for a read operation or a write operation.

[0025] In some cases, the source line can be biased by coupling the source line with a controller or voltage regulator that drives the source line to the appropriate voltage depending on the access operation. However, using this approach, the source line may be derived from a block of memory cells associated with the memory device (e.g., from a tile or slice of memory cells), which can be expensive.

[0026] To avoid leading the source line out of the corresponding block of memory cells, in some cases, other floating gate memory cells fabricated on the same die as the memory cell array can be used to bias the source line. These other floating gate memory cells can be coupled to the source lines of the memory cells in the array and can be configured to bias the source line to the appropriate voltage depending on the operation (read or write).

[0027] For example, in some cases, a memory die may include memory cells coupled to a source line and a digit line and configured to clamp (e.g., couple) the source line and the corresponding digit line during a write operation. In some cases, a memory die may include memory cells coupled to a source line and a ground node and configured to ground the source line during a read operation. In this way, memory cells present on a block of memory cells can be used instead of appropriately biasing the source line by bringing the source line out of the block of memory cells.

[0028] Initially in reference Figure 1 and 2 Features of the present invention are described in the context of the memory system and memory die described in FIG. Features of the present invention are described in the context of the memory device and timing diagrams described with reference to FIG. 3 to 7. Figures 8 to 10 The device diagrams and flow charts described for use with source line management further illustrate and describe these and other features of the present invention.

[0029] Figure 1An example of a system 100 utilizing one or more memory devices according to examples as disclosed herein is described. The system 100 can include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110. The system 100 can include one or more memory devices, but for ease of description, the one or more memory devices can be described as a single memory device 110.

[0030] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be a computer, a laptop, a tablet, a smartphone, a cellular phone, a wearable device, an Internet-connected device, or the like. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100. In some examples, system 100 is configured for bidirectional wireless communication with other systems or devices using a base station or access point. In some examples, system 100 may be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0031] At least a portion of system 100 may be an example of a host device. This host device may be an example of a device that uses memory to execute processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, or the like. In some cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some cases, the host device may be an example of a graphics processing unit (GPU).

[0032] In some cases, memory device 110 may be a standalone device or component that is configured to communicate with other components of system 100 and provide a physical memory address / space for potential use or reference by system 100. In some examples, memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may operate to support modulation schemes used to modulate signals, different pin designs for communicating signals, disparate packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0033] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified data storage capacity. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package device).

[0034] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may electronically communicate with each other using a bus 140.

[0035] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In such cases, the processor 120 may be an example of a central processing unit (CPU), a GPU, a general-purpose graphics processing unit (GPGPU), or a system-on-a-chip (SoC), among other examples.

[0036] BIOS component 125 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100 (e.g., peripheral components 130, I / O components 135, etc.). BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0037] Peripheral component 130 can be any input or output device, or an interface for such a device, that can be integrated into or with system 100. Examples can include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral component 130 can be other components that one skilled in the art would understand to be a peripheral device.

[0038] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0039] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or interfacing with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or that may be managed by I / O controller 135.

[0040] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or that may be managed by I / O controller 135.

[0041] The components of system 100 may be composed of general-purpose or special-purpose circuits designed to perform their functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein.

[0042] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are described in more detail.

[0043] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of or adjacent to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a level, tier, layer, or die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., up to two, up to three, up to four, up to five, up to six, up to seven, up to eight). This may increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn may reduce production costs or increase the performance of the memory array, or both. In a certain 3D memory device, different levels may share at least one common access line, such that some levels may share at least one of a word line, a digit line, and / or a plate line.

[0044] The device memory controller 155 may include circuitry or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command instructing the memory device 110 to store certain data on behalf of a component of the system 100 (e.g., the processor 120) or a read command instructing the memory device 110 to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, or the like.

[0045] A local memory controller 165 (e.g., local to the memory die 160) can be configured to control the operation of the memory die 160. Furthermore, the local memory controller 165 can be configured to communicate with the device memory controller 155 (e.g., to receive and transmit data and / or commands). The local memory controller 165 can support the device memory controller 155 in controlling the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 can perform the various functions described herein. Thus, the local memory controller 165 can be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0046] The external memory controller 105 can be configured to facilitate communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 can act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 do not need to know the details of the operation of the memory device. The components of the system 100 can present requests to the external memory controller 105 (e.g., read commands or write commands) that the external memory controller 105 satisfies. The external memory controller 105 can convert or translate the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 can include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 can include a common data clock that generates a common (source) data clock signal.

[0047] In some cases, the external memory controller 105 or other components of the system 100, or the functionality thereof described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or the functionality thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controllers 165. Likewise, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may in some cases be performed by an external memory controller 105 (separate from or included in the processor 120).

[0048] In some cases, memory device 110 may receive a command to perform a write operation on a memory cell having a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled to the floating gate. In some cases, external memory controller 105, device memory controller 155, and / or local memory controller 165 may be configured to cause the memory device to: couple a source line and a digit line based on receiving the command, the source line being coupled to the first transistor and the digit line being coupled to the second transistor; apply a first voltage to the digit line; apply a second voltage to the floating gate of the first transistor by activating the second transistor, the second voltage being based at least in part on the first voltage; and store the logic state in the memory cell by deactivating the second transistor. In some cases, the logic state is based on the second voltage.

[0049] In some cases, memory device 110 may receive a command to perform a read operation on a memory cell having a first transistor with a floating gate for storing a logic state of the memory cell and a second transistor coupled to the floating gate. In some cases, external memory controller 105, device memory controller 155, and / or local memory controller 165 may be configured to: ground a source line coupled to the first transistor; apply a first voltage to a digit line coupled to the second transistor of the memory cell; and determine the logic state stored in the memory cell based on applying the first voltage to the digit line and grounding the source line.

[0050] Components of system 100 can exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 can enable communication between external memory controller 105 and memory device 110. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 can include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin can be an example of an electrically conductive input or output point of a device of system 100, and a pin can be configured to function as part of a channel. In some cases, the pins or pads of a terminal can be part of a signal path of channel 115. Additional signal paths can be coupled to the terminals of a channel to route signals within the components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or components thereof, such as internal to memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0051] Lanes 115 (and associated signal paths and terminals) can be dedicated to conveying specific types of information. In some cases, lanes 115 may be aggregated lanes and, therefore, may include multiple individual lanes. For example, data lanes 190 may be x4 (e.g., comprising four signal paths), x8 (e.g., comprising eight signal paths), x16 (comprising sixteen signal paths), and so on. Signals conveyed through the lanes may utilize a double data rate (DDR) timing scheme. For example, some symbols of a signal may be registered on the rising edge of a clock signal, and other symbols of the signal may be registered on the falling edge of the clock signal. Signals conveyed through the lanes may utilize single data rate (SDR) signaling. For example, one symbol of a signal may be registered for each clock cycle.

[0052] In some cases, channels 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to communicate commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channels 186 may include a read command with the address of the desired data. In some cases, CA channels 186 may be registered on rising and / or falling clock signal edges. In some cases, CA channels 186 may include any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0053] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to pass one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., a CK_t signal and a CK_c signal), and the signal paths of CK channels 188 may be configured accordingly. In some cases, the clock signals may be single-ended. CK channels 188 may include any number of signal paths. In some cases, clock signals CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for commands and addressing operations or other system-wide operations for memory device 110. Clock signal CK may therefore be variously referred to as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, an oscillator, a crystal, logic gates, transistors, or the like).

[0054] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to communicate data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may communicate information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110.

[0055] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0056] Channel 115 can use a variety of different architectures to couple external memory controller 105 and memory device 110. Examples of various architectures can include a bus, a point-to-point connection, a crossbar, a high-density interposer (e.g., a silicon interposer), or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path can at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0057] The signals communicated through the channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme where M is equal to 2. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0058] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. A multi-symbol modulation scheme may be an example of an M-ary modulation scheme where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal, or PAM4 signal, may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0059] Figure 2 An example of a memory die 200 according to an example as disclosed herein is illustrated. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205 that are programmable to store different logical states. Each memory cell 205 may be programmable to store two or more states. For example, a memory cell 205 may be configured to store one bit of digital logic at a time (e.g., a logic 0 and a logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic at a time (e.g., a logic 00, a logic 01, a logic 10, or a logic 11).

[0060] Memory cell 205 can store a state representing digital data. In a dynamic random access memory (DRAM) architecture or a ferroelectric random access memory (FeRAM) architecture, memory cell 205 can include a capacitor comprising a dielectric material to store a charge representing a programmable state. In a floating gate memory architecture, memory cell 205 can include two transistors, one of which is associated with a floating gate. The floating gate can be configured to store a charge representing a programmable state.

[0061] Operations such as reading and writing can be performed on floating gate memory cell 205 by activating, selecting, or biasing access lines, such as word line 210, digit line 215, and / or source line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, source lines, or the like may be interchangeable without loss of understanding or operation. Activating, selecting, or biasing word line 210, digit line 215, or source line 220 may include applying a voltage to the corresponding line.

[0062] Memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and source lines 220) arranged in a grid-like pattern. Memory cells 205 may be located at the intersections of word lines 210, digit lines 215, and / or source lines 220. By biasing word lines 210, digit lines 215, and source lines 220 (e.g., applying a voltage to word lines 210, digit lines 215, or source lines 220), a single memory cell 205 may be accessed at their intersections.

[0063] Access to memory cells 205 may be controlled by row decoder 225 and column decoder 230. For example, row decoder 225 may receive a row address from local memory controller 265 and activate word lines 210 based on the received row address. Column decoder 230 may receive a column address from local memory controller 265 and activate digit lines 215 based on the received column address.

[0064] For example, memory die 200 may include a plurality of word lines 210 (labeled WL_1 through WL_M), a plurality of digit lines 215 (labeled DL_1 through DL_N), and a plurality of source lines (labeled SL_1 through SL_N), where M and N depend on the size of the memory array. In some cases, the number N of source lines corresponds to the number N of digit lines, such that each digit line 215 has a corresponding source line 220 associated with the same memory cell 205 as the digit line 215. Thus, by activating or biasing a word line 210, a digit line 215, and a source line 220 (e.g., WL_1, DL_2, and SL_2), the memory cell 205 at its intersection can be accessed. The intersection of a word line 210 and a digit line 215 (in a two-dimensional or three-dimensional configuration) can be referred to as the address of a memory cell 205. In some cases, the intersection of a word line 210, a digit line 215, and a source line 220 can be referred to as the address of a memory cell 205.

[0065] Memory cell 205 can include a read transistor 235 and a write transistor 245 associated with a floating gate 240. Read transistor 235 and write transistor 245 can be used together to read and write logic states to memory cell 205.

[0066] The floating gate 240 can be used to store a charge or voltage representing the logical state of the memory cell 205. The floating gate 240 can be an electrical node positioned near the control gate 275 of the read transistor 235, such that the charge or voltage on the floating gate 240 can affect the threshold voltage associated with the read transistor 235. For example, the control gate 275 can be the gate of a transistor that is used to activate or deactivate the transistor. The read transistor 235 can be associated with the floating gate 240 at least because the threshold voltage of the read transistor 235 can be affected by the charge or voltage on the floating gate 240. The threshold voltage can be the minimum voltage that must be applied to the control gate of the transistor to fully activate the transistor and couple the source node of the transistor with the drain node of the transistor.

[0067] In some cases, the read transistor 235 may include a floating gate 240. That is, the read transistor 235 may be a floating gate transistor that includes a floating gate 240. In some cases, the read transistor 235 may be a transistor that does not include a floating gate 240 (e.g., is not a floating gate transistor). In this case, the floating gate 240 may be an electrical node that is fabricated in close proximity to the control gate of the read transistor 235 but is not included within the read transistor 235. The floating gate 240 may be coupled to the drain node 295 of the write transistor 245.

[0068] In some cases, the read transistor 235 may be a first type of transistor (p-type, n-type) and the write transistor 245 may be a second type of transistor (n-type, p-type). For example, the read transistor 235 may be a p-type transistor and the write transistor may be an n-type transistor, or vice versa. For simplicity, in the disclosure herein, the read transistor 235 is assumed to be a p-type transistor and the write transistor 245 is assumed to be an n-type transistor, but the reverse may also be used. Similarly, references to the source and drain nodes of the read transistor 235 and the write transistor 245 may be reversed. In some cases, the read transistor 235 and the write transistor 245 may be the same type of transistor (e.g., both p-type or both n-type).

[0069] Word line 210 can be a conductive line coupled to memory cell 205 for performing access operations on memory cell 205. In some architectures, word line 210 can be coupled to control gate 275 of read transistor 235 and to control gate 270 of write transistor 245. In some cases, word line 210 can be configured to control activation of read transistor 235 and write transistor 245 during memory cell access by applying voltages to control gates 275 and 270. In some cases, because read transistor 235 and write transistor 245 are different types of transistors, applying a voltage to word line 210 can activate either read transistor 235 or write transistor 245, but not both. In some cases, word line 210 can be biased to a voltage that activates read transistor 235 but not write transistor 245 during a read operation. In some cases, word line 210 can be biased to a voltage that activates write transistor 245 but not read transistor 235 during a write operation.

[0070] The digit line 215 may be a conductive line connecting the memory cell 205 and the sensing element 250 and used to perform access operations on the memory cell 205. The digit line 215 may be connected to the source node 280 of the write transistor 245 and to the drain node 290 of the read transistor 235.

[0071] Source line 220 may be a conductive line coupled to memory cell 205 for performing access operations on memory cell 205. Source line 220 may be coupled to source node 285 of read transistor 235. In some memory devices, a common source line (e.g., a source plate) may be coupled to each memory cell. In such memory devices, access operations (e.g., read operations or write operations) may cause interference to other rows or columns. Some memory devices may not include a common source line or source plate, but may instead include source lines associated with digit lines. In such examples, a single source line may be associated with a single digit line. This architecture may reduce or mitigate interference during access operations, but may increase components associated with the source line (e.g., drivers, etc.). Source line configurations that include source lines associated with digit lines are described herein.

[0072] During a write operation, word line 210 can be biased to a write voltage that activates write transistor 245, and digit line 215 can be biased to a state voltage based on the logic state to be stored by memory cell 205. For example, digit line 215 can be biased to a higher voltage to store a logic state "1" and to a lower voltage to store a logic state "0." Activating write transistor 245 can couple source node 280 of write transistor 245 with drain node 295 of write transistor 245, thereby causing a voltage based on the voltage of digit line 215 to be applied to floating gate 240. After the voltage has been applied to floating gate 240, word line 210 can be biased to a voltage that deactivates write transistor 245, thereby isolating floating gate 240 and storing the applied voltage on floating gate 240. In some cases, read transistor 235 can remain inactive during a write operation.

[0073] During a read operation, word line 210 can be biased to a read voltage that can activate read transistor 235, and write transistor 245 can remain inactive. Activating read transistor 235 can couple the drain node 290 of read transistor 235 with the source node 285 of read transistor 235, thereby coupling digit line 215 and source line 220. During a read operation, digit line 215 can be biased to a small positive voltage and source line 220 can be grounded so that when read transistor 235 is activated, current can flow from digit line 215 to source line 220. The amount of current flowing from digit line 215 to source line 220 can be affected by the state stored by memory cell 205. That is, the voltage or charge stored on floating gate 240 can affect the threshold voltage associated with read transistor 235, thereby affecting the activation level of read transistor 235 in response to the read voltage. The activation level of read transistor 235 may in turn affect the amount of current flowing between digit line 215 and source line 220 .

[0074] Sense component 250 can be configured to detect a state (e.g., charge or voltage) stored on floating gate 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. In some cases, sense component 250 can detect the state by detecting the amount of current flowing between digit line 215 and source line 220 during a read operation (which can be considered a signal output by memory cell 205).

[0075] In some cases, sensing component 250 may include one or more sense amplifiers to amplify the signal output of memory cell 205. The sense amplifiers can detect small changes in current along digit line 215 during a read operation and can generate a signal corresponding to a logic 0 or logic 1 based on the detected current.

[0076] Sense component 250 can be configured to compare a signal received from memory cell 205 across digit line 215 with a reference signal 255 (e.g., a reference voltage or current). Sense component 250 can determine the stored state of memory cell 205 based on the comparison. For example, in binary signaling, if digit line 215 has a voltage or current higher than reference signal 255, sense component 250 can determine that the stored state of memory cell 205 is a logic 1, and if digit line 215 has a voltage or current lower than reference signal 255, sense component 250 can determine that the stored state of memory cell 205 is a logic 0. Sense component 250 can include various transistors or amplifiers to detect and amplify differences in the signals. The detected logic state of memory cell 205 can be output as output 260 by row decoder 230. In some cases, sense component 250 can be part of another component (e.g., column decoder 230, row decoder 225). In some cases, sensing component 250 may be in electronic communication with row decoder 255 and / or column decoder 230 .

[0077] The local memory controller 265 may control the operation of the memory cell 205 through various components such as the row decoder 225, the column decoder 230, and the sensing component 250. The local memory controller 265 may be a reference Figure 1 105 (or a reference to an external memory controller 105). Figure 1The local memory controller 265 receives one or more commands and / or data from the external memory controller 105 (or the device memory controller 155 described herein); translates the commands and / or data into information that can be used by the memory die 200; performs one or more operations on the memory die 200; and, in response to performing the one or more operations, passes data from the memory die 200 to the external memory controller 105 (or the device memory controller 155). The local memory controller 265 can generate row, column, and / or source line address signals to bias or activate the target word lines 210, target digit lines 215, and target source lines 220. The local memory controller 265 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents described herein can be adjusted or varied and can be different for the various operations described in operating the memory die 200.

[0078] In some cases, the local memory controller 265 can be configured to perform a precharge operation on the memory die 200. The precharge operation can include precharging one or more components and / or access lines of the memory die 200 to one or more predetermined voltage levels. In some examples, the memory cells 205 and / or portions of the memory die 200 can be precharged between different access operations. In some examples, the digit lines 215 and / or other components can be precharged prior to a read operation.

[0079] In some cases, the local memory controller 265 can be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 can be programmed during a single write operation. The local memory controller 265 can identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 265 can identify a target word line 210, a target digit line 215, and / or a target source line 220 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 can activate the target word line 210, the target digit line 215, and / or the target source line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the source line 220) to access the target memory cell 205. The local memory controller 265 can apply a particular signal (eg, voltage) to the digit line 215 during a write operation to store a particular state on the floating gate 240 of the memory cell 205, the particular state indicating a desired logic state.

[0080] In some cases, the local memory controller 265 can be configured to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in the memory cells 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 265 can identify the target memory cell 205 on which the read operation is performed. The local memory controller 265 can identify the target word line 210, target digit line 215, and / or target source line 220 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 can activate the target word line 210, target digit line 215, and / or target source line 220 (e.g., apply a voltage to the word line 210, digit line 215, or source line 220) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sensing component 250 in response to a biased access line. The sensing component 250 can amplify the signal. The local memory controller 265 can trigger the sensing component 250 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 255. Based on the comparison, the sensing component 250 can determine the logic state stored on the memory cell 205. As part of a read operation, the local memory controller 265 can communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller).

[0081] In some memory architectures, accessing a memory cell 205 can degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed on a floating gate memory cell can destroy the logic state stored on the floating gate. The local memory controller 265 can perform a rewrite operation or a refresh operation to return the memory cell 205 to its original logic state. The local memory controller 265 can rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation can be considered part of the read operation. In addition, activating a single access line (such as word line 210) can disturb the state stored in some memory cells coupled to that access line. Therefore, a rewrite operation or a refresh operation can be performed on one or more memory cells that have not been accessed.

[0082] Figure 3A and 3B Examples of access line biasing of a memory device 300 during write and read operations, respectively, are illustrated in support of methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0083] The memory device 300 includes a plurality of memory cells, including a target memory cell 205-a. The target memory cell 205-a may be a reference Figure 2 1. An example of a floating gate memory cell 205 is depicted. Target memory cell 205-a includes a read transistor 235-a and a write transistor 245-a associated with floating gate 240-a. In this example, read transistor 235-a is a p-type transistor and write transistor 245-a is an n-type transistor. In some cases, write transistor 245 in memory device 300 can be activated when a first voltage is applied to its control gate, and read transistor 235 in memory device 300 can be activated when a second (different) voltage is applied to its control gate. In this example, write transistor 245-a can be activated when a voltage of three (3) volts is applied to its control gate, and read transistor 235 can be activated when a voltage of negative (-1) volt is applied to its control gate. Figure 3A and 3B The values ​​of the voltages described in are to be considered as examples. The voltages may be any value or combination of values ​​that performs the functions described herein.

[0084] Figure 3A An example of access line biasing of the memory device 300 during a write operation is depicted. During a write operation to a target memory cell 205-a, the word line 210-a associated with the target memory cell 205-a can be biased to a write voltage that activates the write transistor 245-a but does not activate the read transistor 235-a. For example, the write voltage can be applied to the control gate of the write transistor 245-a via the word line 210-a and can be a voltage that exceeds the threshold voltage associated with the write transistor 245-a. In this example, the write voltage can be three (3) volts. Other word lines associated with unselected memory cells in the memory device 300, such as word line 210-b, can be biased to zero (0) volts (e.g., ground voltage).

[0085] During a write operation, the digit line 215-a associated with the target memory cell 205-a can be biased to a state voltage based on the logic state to be written to the target memory cell 205-a. For example, to write a logic state "1," the digit line 215-a can be biased to two (2) volts. To write a logic state "0," the digit line 215-a can be biased to zero (0) volts. Other digit lines associated with unselected memory cells in the memory device 300, such as the digit line 215-b, can be biased to zero (0) volts (e.g., ground voltage).

[0086] As reference Figure 2As described above, the source node of write transistor 245-a can be coupled to digit line 215-a and the drain node of write transistor 245-a can be coupled to floating gate 240-a. Thus, when write transistor 245-a is activated by applying a write voltage to word line 210-a, a voltage based on the state voltage applied to digit line 215-a can be applied to floating gate 240-a. In some cases, the voltage applied to floating gate 240-a can be substantially the same as the state voltage on digit line 215-a minus any voltage drop across write transistor 245-a.

[0087] After applying a voltage to floating gate 240-a, word line 210-a can be set to zero (0) volts to deactivate write transistor 245-a, thereby decoupling floating gate 240-a from digit line 215-a. Floating gate 240-a can be floating (e.g., decoupled from any voltage source or rail) and can thus store a voltage representing a logic state.

[0088] During a write operation, the source line 220-a associated with the target memory cell 205-a may not be used and may be biased to zero (0) volts (e.g., ground). To simplify manufacturing and source line biasing, in this example, multiple source lines 220 may be coupled to a single conductive source plate 310, which may be biased to zero (0) volts.

[0089] Figure 3B An example of access line biasing of the memory device 300 during a read operation of a target memory cell 205-a is depicted. During a read operation on the target memory cell 205-a, the word line 210-a associated with the target memory cell 205-a can be biased to a read voltage that activates the read transistor 235-a but does not activate the write transistor 245-a. For example, the read voltage can be applied to the control gate of the read transistor 235-a via the word line 210-a and can be a voltage that exceeds the nominal threshold voltage associated with the read transistor 235-a. The nominal threshold voltage can be the threshold voltage of the read transistor 235-a when the floating gate 240-a is uncharged. In this example, the read voltage can be negative (-1) volt. Other word lines associated with unselected memory cells in the memory device 300, such as word line 210-b, can be biased to zero (0) volts (e.g., ground).

[0090] During a read operation, the digit line 215-a associated with the target memory cell 205-a can be biased to a read voltage. In this example, the read voltage can be 0.5 volts and can be the same voltage regardless of the logic state stored by the target memory cell 205-a. Other digit lines associated with unselected memory cells in the memory device 300, such as digit line 215-b, can be biased to zero (0) volts.

[0091] As reference Figure 2 2. A memory cell 205-a is described in detail below. A drain node of read transistor 235-a may be coupled to digit line 215-a and a source node of read transistor 235-a may be coupled to source line 220-a. During a read operation, digit line 215-a is biased to a voltage (e.g., 0.5V) higher than source line 220-a. Thus, when read transistor 235-a is activated by applying a read voltage to word line 210-a, current may flow between digit line 215-a and source line 220-a via read transistor 235-a. The amount of current conducted by read transistor 235-a may depend on the voltage stored on floating gate 240-a. Thus, the amount of current flowing from digit line 215-a to source line 220-a may be sensed by a sense amplifier to determine the logic state stored by target memory cell 205-a.

[0092] In some cases, during a write operation to a logic state "1" (e.g., when the write voltage applied to digit line 215-a is a relatively high voltage (e.g., two (2) volts)), read transistors 235-a, 235-b associated with digit line 215-a and source line 220-a may not activate but may still conduct a small amount of current (e.g., leakage current) due to the voltage difference between digit line 215-a and source line 220-a. Although Figure 3A Two memory cells are depicted coupled to digit line 215-a and source line 220-a, but in practice there may be hundreds or thousands of memory cells coupled to these access lines.Thus, the accumulated leakage current that may be conducted through read transistor 235 during a write operation may be significant.

[0093] Therefore, in some cases, it may be desirable to bias the source line 220 associated with the target memory cell 205 to the same voltage as the digit line 215 associated with the target memory cell 205 during a write operation to avoid voltage differences between the digit line 215 and the source line 220, and thereby reduce or eliminate leakage current through the read transistor.

[0094] Figure 4 An example of access line biasing for a memory device 400 is illustrated in support of methods and apparatus for supporting source line configuration for a memory device according to examples as disclosed herein. Figure 4Depicted is an example of access line biasing for memory device 400 during a write operation. Figure 4 The values ​​of the voltages described in are to be considered as examples. The voltages may be any value or combination of values ​​that performs the functions described herein.

[0095] Memory device 400 is similar to memory device 300, but in this case, memory device 400 includes transistors that can be independently biased rather than with a single source plate (e.g., Figure 3A and 3B 3. The memory device 100 includes a plurality of source lines 220-c, 220-d coupled to a source plate 310 (depicted in FIG). Isolating the source lines 220-c, 220-d from one another can allow the memory device to bias the source line 220-c associated with the target memory cell 205-c to the voltage of the digit line 215-c associated with the target memory cell 205 during a write operation, thereby reducing or eliminating leakage current through the read transistors associated with the source line 220-c and the digit line 215-c. For example, if the digit line 215-c is biased to two (2) volts (e.g., to write a logic state "1" to the target memory cell 205-c), the source line 220-c can also be biased to two (2) volts. If digit line 215-c is biased to zero (0) volts (e.g., to write a logic state "0" to target memory cell 205-c), source line 220-c may also be biased to zero (0) volts. In some cases, a single source line (e.g., source line 220-c) may be associated with a single digit line (e.g., digit line 215-c). Memory device 400 may include digit line 215-d.

[0096] Source lines in the memory device 400 that are not associated with the target memory cell 205-c, such as source line 220-d, may remain biased at zero (0) volts to reduce power consumption.

[0097] In some cases, source lines 220-c, 220-d can be individually biased by leading each source line 220-c, 220-d out of the corresponding memory cell block and coupling each source line to a voltage supply or voltage regulator so that each source line can be individually biased. However, this approach may not be suitable for some applications. Therefore, alternative methods of source line biasing may be useful.

[0098] Figure 5 An example of a memory device 500 is illustrated that supports methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein.

[0099] The memory device 500 includes a memory array 505, which may be a reference Figure 11. Memory array 505 includes floating gate memory cells 205-e, 205-f, 205-g, and 205-h. For example, each memory cell 205 in memory array 505 can be coupled to a word line 210, a digit line 215, and a source line 220, as described with reference to FIG. Figure 2 The digit line 215 may be coupled to a digit line receptacle 545 , which may be coupled to a digit line driver for biasing (applying voltage to) the digit line 215 .

[0100] The memory array 505 can be organized into rows and columns of memory cells 205. For example, the memory array 505 has a first row including memory cells 205-e, 205-f and an Nth row including memory cells 205-g, 205-h. The memory array 505 has a first column including memory cells 205-e, 205g and a second column including memory cells 205-f, 205-h.

[0101] The memory array 505 includes at least one row of clamped memory cells, including clamped memory cells 205-i, 205-j. The clamped memory cells 205-i, 205-j may be as shown in FIG. Figure 2 3 and 4, and can be associated with access lines including a clamp line 515, a source line 220, and a digit line 215. The memory cells in a row of clamped memory cells 510 can be coupled to the source line 220 and the digit line 215 of the memory array 505. The clamp line 515 can serve as a word line for the clamped memory cells 205-i, 205-j. The clamp line 515 can be coupled to and controlled by a word line decoder. The clamped memory cells 205-i, 205-j may not be used to store a logic state; instead, the clamped memory cells 205-i, 205-j can be used to bias the source line 220 of the memory array 505 during a write operation of the memory cells 205 in the memory array 505.

[0102] The memory array 505 includes at least one row of grounded memory cells 520, including grounded memory cells 205-k, 205-1. The grounded memory cells 205-k, 205-1 may be as shown in FIG. Figure 2 3 and may be associated with access lines including a ground line 525 and a source line 220. The memory cells in a row of grounded memory cells 520 may be coupled to the source line 220 of the memory array 505. The ground line 525 may serve as a word line for the grounded memory cells 205-k, 205-1. The ground line 525 may be coupled to and controlled by a word line decoder.

[0103] Unlike the memory cells in the memory array 505 and the clamped memory cells in the row of clamped memory cells 510, the grounded memory cells 205-k, 205-1 may not be coupled to the digit line 215. Instead, the grounded memory cells 205-k, 205-1 may be coupled to a ground node 560 that is biased to a ground voltage (e.g., zero (0) volts). That is, the source of the write transistor and the drain of the read transistor in each grounded memory cell 205-k, 205-1 may be coupled to the ground node 560 rather than to the digit line 215. The grounded memory cells 205-k, 205-1 may not be used to store a logic state; instead, the grounded memory cells 205-k, 205-1 may be used to bias the source line 220 of the memory array 505 during a read operation of the memory cells 205 in the memory array 505.

[0104] During a write operation of a target memory cell 205 in the memory array 505, the clamp line 515 can be biased to a read voltage that activates the read transistors in the clamped memory cells 205-i, 205-j, and the ground line 525 can be biased to a voltage that keeps the read and write transistors in the grounded memory cells 205-k, 205-1 inactive. For example, the clamp line 515 can be biased to negative two (-2) volts, and the ground line 525 can be biased to zero (0) volts.

[0105] Activating the read transistors in the clamped memory cells 205-i, 205-j during a write operation can couple the digit line 215 associated with the target memory cell 205 and the source line 220 associated with the target memory cell 205, thereby clamping the source line 220 and the digit line 215 and biasing the source line 220 to the voltage of the digit line 215. As previously described, biasing the source line 220 to the same voltage as the digit line 215 during a write operation can reduce or eliminate leakage current that can flow between the digit line 215 and the source line 220 during the write operation.

[0106] During a read operation of a target memory cell 205 in the memory array 505, the ground line 525 can be biased to a read voltage that activates the read transistors in the grounded memory cells 205-k, 205-1, and the clamp line 515 can be biased to a voltage that keeps the read and write transistors in the clamped memory cells 205-i, 205-j inactive. For example, the ground line 525 can be biased to negative two (-2) volts, and the clamp line 515 can be biased to zero (0) volts, which can be opposite to the bias used during a write operation.

[0107] Activating the read transistor in the grounded memory cell 205-k, 205-1 can couple the source line 220 associated with the target memory cell 205 to the ground node 560 biased to the ground voltage, thereby biasing the source line 220 to the ground voltage. Figure 2 and 3B As depicted, the digit line 215 associated with the target memory cell 205 can be biased to a voltage such that current can flow from the digit line 215 to the source line 220 via the read transistor in the target memory cell 205 .

[0108] For example, if memory cell 205-g is the target memory cell during a read operation, current may flow along current path 540 (not shown) from a digit line driver associated with digit line receptacle 545, through digit line 215-e, through memory cell 205-g (e.g., through a read transistor of memory cell 205-g), to source line 220-e, and then back through grounded memory cell 205-k (e.g., through a read transistor of grounded memory cell 205-k) to ground node 560.

[0109] As described above, one or more rows of clamped memory cells 510 and one or more rows of grounded memory cells 520, each of which is coupled to the memory array 505, can enable a memory device to bias the source lines associated with the floating gate memory cells using on-die circuitry that can be manufactured and controlled in the same manner as floating gate memory cells. This technique can reduce or eliminate the need to bring source lines out of a block of memory cells associated with the memory device for biasing the source lines (e.g., out of a tile or slice of memory cells). Although Figure 5 A single row of clamped memory cells 510 and a single row of grounded memory cells 520 are depicted, but in practice, there may be multiple rows of each. In some cases, the clamped memory cells and the grounded memory cells may each be implemented using multiple rows operated in parallel. The number of rows may be chosen for sufficient drive strength.

[0110] In some cases, it may be desirable to have all read transistors of the clamped and grounded memory cells operate in a high current (e.g., low threshold) state. In some cases, this state can be achieved by including a clamp line and a ground line in the refresh scheme. That is, the clamped and grounded memory cells can be refreshed during operation of the memory device. During a refresh of the row, the digit line can be held at zero (0) volts and the clamp line and ground line can be raised to a high voltage. This technique can use the write transistors in the clamped and grounded memory cells to hold the floating gates in these cells at zero (0) volts, which can be similar to writing a zero to the floating gate. In some cases, one or more clamped rows and one or more grounded rows can also be initialized in a similar manner after power-on.

[0111] Figure 6 An example of a timing diagram 600 is illustrated to support methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein. The timing diagram 600 may depict voltages on various access lines associated with a target memory cell during a write operation. The timing diagram includes a word line voltage V WL 605, digital line voltage V DL 610, source line voltage V SL 615, clamping line voltage V CL 620 and ground line voltage V GL 625. The timing diagram 600 also includes the floating gate voltage V FG 630. Figure 6 The values ​​of the voltages described in are to be considered as examples. The voltages may be any value or combination of values ​​that performs the functions described herein.

[0112] At time t0, the target memory cell and the corresponding access line may be idle, and the floating gate may be storing state "0." Therefore, V WL 605、V DL 610, V SL 615、V CL 620 and V GL 625 can be biased to zero (0) volts, and V FG 630 can store a voltage of zero (0) volts.

[0113] At time t1, a write operation can be performed. WL 605 may be biased to a write voltage of three (3) volts to activate the write transistor in the target memory cell. V DL 610 can be biased to two (2) volts to write a logic state "1" or to zero (0) volts to write a logic state "0." CL620 may be set to negative (-1) volts to activate the read transistor in the clamp memory cell, thereby clamping the source line associated with the target memory cell to the digit line associated with the target memory cell, as shown in FIG. Figure 5 Therefore, V SL 615 can be equal to V DL 610. Since the write transistor is activated, thereby coupling the digit line and the floating gate and applying a voltage to the floating gate, V FG 630 can generate V based DL 610 is the voltage of the voltage. For example, V FG 630 can be used in V DL 610 generates a higher voltage (e.g., approximately two (2) volts) when biased to two (2) volts and at V DL 610 generates a lower voltage (eg, zero (0) volts) when biased to zero (0) volts. During a write operation, V GL 625 can be held inactive at zero (0) volts.

[0114] At some time after time t1, V WL 605 can be biased to zero (0) volts (not shown) to deactivate the read transistor and store the logic state on the floating gate.

[0115] Figure 7 An example of a timing diagram 700 is illustrated to support methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein. The timing diagram 700 may depict voltages of various access lines associated with a target memory cell during a read operation. The timing diagram includes a word line voltage V WL 705, digital line voltage V DL 710, source line voltage V SL 715, clamping line voltage V CL 720 and ground line voltage V GL 725. The timing diagram 700 also includes the floating gate voltage V FG 730. Figure 6 The values ​​of the voltages described in are to be considered as examples. The voltages may be any value or combination of values ​​that performs the functions described herein.

[0116] At time t0, the target memory cell and the corresponding access line may be idle, and the floating gate may be storing a state of "0" or "1". Thus, V WL 705, V DL 710, V SL 715, V CL 720 and V GL 725 can be biased to zero (0) volts, and V FG730 can store a voltage of approximately two (2) volts or zero (0) volts.

[0117] At time t1, a read operation can be performed. WL 705 can be biased to a read voltage of negative (-1) volt to activate the read transistor in the target memory cell. DL 710 can be biased to a small positive voltage, such as 0.5 volts. GL 725 may be set to negative (-1) volts to activate the read transistor in the grounded memory cell, thereby grounding the source line associated with the target memory cell, as shown in FIG. Figure 5 Therefore, during a read operation, V SL 715 may be held at zero (0) volts.

[0118] Since the read transistor of the target memory cell is activated to couple the source line (biased to zero (0) volts) with the digit line (biased to 0.5 volts), current can flow from the digit line through the read transistor to the source line. The amount of current that can flow through the read transistor can be affected by the floating gate V FG 730V voltage. If V FG 730 is about two (2) volts (indicating a logic state "1") at the start of a read operation, then V FG 730 is zero (0) volts (indicating a logic state "0") at the start of the read operation, more current can flow. In the former case, V FG 730 may be slightly reduced during a read operation. During a read operation, V CL 720 can be held inactive at zero (0) volts.

[0119] Figure 8 A block diagram 800 is shown of a memory device 805 supporting methods and apparatus for supporting source line configuration of a memory device according to examples as disclosed herein. For example, the memory device 805 may be a reference Figures 1 to 5 Memory device 805 may include a command module 810, a coupling module 815, a bias module 820, a transistor activation module 825, a refresh module 830, and a determination module 835. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0120] The command module 810 may receive a command to perform a write operation on a memory cell including a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor connected to the floating gate of the first transistor.

[0121] The command module 810 may receive a command to perform a read operation on a memory cell including a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor connected to the floating gate of the first transistor.

[0122] The coupling module 815 may couple the source line connected to the first transistor and the digit line connected to the second transistor based on receiving the command. In some examples, the coupling module 815 may decouple the source line from the digit line.

[0123] As part of a write operation, bias module 820 can apply a first voltage to a digit line. In some examples, bias module 820 can ground a source line coupled to a first transistor of a memory cell. In some examples, as part of a read operation, bias module 820 can apply a first voltage to a digit line coupled to a second transistor of a memory cell.

[0124] In some examples, bias module 820 may apply a fourth voltage to a word line associated with the memory cell, the word line being connected to the control gate of the first transistor and to the gate of the second transistor, based on receiving the command.

[0125] In some examples, the bias module 820 may apply a fourth voltage to the word line to activate the second transistor without activating the first transistor.

[0126] In some examples, as part of a read operation, bias module 820 may apply a second voltage to a word line connected to the control gate of the first transistor to activate the first transistor. In some cases, the word line is connected to the gate of the second transistor, and applying the second voltage to the word line does not activate the second transistor.

[0127] The transistor activation module 825 may activate the second transistor to apply a second voltage to the floating gate of the first transistor, the second voltage being based on the first voltage.

[0128] In some examples, the transistor activation module 825 may deactivate the second transistor to cause the first transistor to store a logic state based on a second voltage applied to the floating gate of the first transistor. In some examples, the command module 810 may receive a second command to perform a read operation on the memory cell after deactivating the second transistor. In some examples, the refresh module 830 may refresh the second memory cell after deactivating the second transistor. In some examples, the refresh module 830 may refresh the second memory cell by applying a third voltage to the control gate of the third transistor. In some cases, refreshing the second memory cell occurs after determining the logic state stored by the memory cell.

[0129] In some examples, transistor activation module 825 can activate a third transistor in the second memory cell, the third transistor having a first node connected to the digit line, a second node connected to the source line, and a floating gate. In some examples, activating the third transistor includes applying a third voltage to a control gate of the third transistor, the third transistor having a floating gate.

[0130] In some examples, as part of a read operation, transistor activation module 825 can activate a fourth transistor in the third memory cell to couple the source line to a ground voltage.

[0131] In some examples, transistor activation module 825 can activate a third transistor in the second memory cell, the third transistor having a first node connected to a source line, a second node connected to a ground voltage, and a floating gate. In some examples, activating the third transistor includes applying the second voltage to a control gate of the third transistor.

[0132] The determination module 835 may determine the logic state stored by the memory cell based on the signal on the digit line during at least a portion of the duration when the source line is grounded. In some examples, the determination module 835 may determine the second logic state of the memory cell when the source line is coupled to a ground voltage. In some examples, the determination module 835 may determine that the logic state stored by the memory cell is based on activating the first transistor, the signal on the digit line being based on the voltage of the floating gate of the first transistor.

[0133] In some examples, determining the state stored by the floating gate of the first transistor includes determining a current associated with a signal on the digit line.

[0134] Figure 9 A flow chart illustrating a method or methods 900 for supporting methods and apparatus for supporting source line configuration of a memory device according to aspects of the present invention is shown. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory device as described herein. Figure 8 The memory device described herein performs the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0135] At 905, a memory device may receive a command to perform a write operation on a memory cell comprising a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor connected to the floating gate of the first transistor. The operations of 905 may be performed according to the methods described herein. In some examples, aspects of the operations of 905 may be performed as described with reference to Figure 8 Describes the commands a module executes.

[0136] At 910, a memory device may couple a source line connected to a first transistor and a digit line connected to a second transistor based on receiving a command. The operations of 910 may be performed according to the methods described herein. In some examples, aspects of the operations of 910 may be implemented as described in reference to Figure 8 The described coupling module is implemented.

[0137] As part of the write operation, at 915, the memory device may apply a first voltage to the digit line. The operation of 915 may be performed according to the methods described herein. In some examples, aspects of the operation of 915 may be performed as described in reference to Figure 8 The described bias module is implemented.

[0138] At 920, the memory device may activate the second transistor to apply a second voltage to the floating gate of the first transistor, the second voltage being based on the first voltage. The operation of 920 may be performed according to the methods described herein. In some examples, aspects of the operation of 920 may be performed as described in reference to Figure 8 Describes the transistor activation module implementation.

[0139] At 925, the memory device may deactivate the second transistor to cause the first transistor to store a logic state based on a second voltage applied to the floating gate of the first transistor. The operations of 925 may be performed according to the methods described herein. In some examples, aspects of the operations of 925 may be described by referring to Figure 8 Describes the transistor activation module implementation.

[0140] In some examples, an apparatus as described herein may perform a method or methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for each of: receiving a command to perform a write operation on a memory cell, the memory cell including a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor connected to the floating gate of the first transistor; coupling a source line connected to the first transistor and a digit line connected to the second transistor based on receiving the command; applying a first voltage to the digit line as part of the write operation; activating the second transistor to apply a second voltage to the floating gate of the first transistor, the second voltage being based on the first voltage; and deactivating the second transistor to cause the first transistor to store a logic state based on the second voltage applied to the floating gate of the first transistor.

[0141] In some examples of method 900 and apparatus described herein, coupling the source line and the digit line may include operations, features, means, or instructions for activating a third transistor in the second memory cell, the third transistor having a first node connected to the digit line, a second node connected to the source line, and a floating gate.

[0142] In some examples of method 900 and apparatus described herein, activating the third transistor may include operations, features, means, or instructions for applying a third voltage to a control gate of the third transistor, the third transistor having a floating gate.

[0143] Some examples of method 900 and apparatus described herein may further include operations, features, means, or instructions for refreshing the second memory cell after deactivating the second transistor.

[0144] Some examples of method 900 and apparatus described herein may further include operations, features, means, or instructions for applying a fourth voltage to a word line associated with the memory cell based on receiving the command, the word line being connected to the control gate of the first transistor and to the gate of the second transistor.

[0145] Some examples of method 900 and apparatus described herein may further include operations, features, means, or instructions for applying a fourth voltage to the word line to activate the second transistor without activating the first transistor.

[0146] Some examples of method 900 and the apparatus described herein may further include operations, features, components, or instructions for each of: receiving a second command to perform a read operation on the memory cell after deactivating the second transistor; decoupling the source line from the digit line; activating a fourth transistor in the third memory cell to couple the source line to a ground voltage as part of the read operation; and determining a second logic state of the memory cell when the source line may be coupled to the ground voltage.

[0147] Figure 10 A flow chart illustrating a method or methods 1000 for supporting methods and apparatus for supporting source line configuration of a memory device according to aspects of the present invention is shown. The operations of the method 1000 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 1000 may be implemented by a memory device as described herein. Figure 8 The memory device described herein performs the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0148] At 1005, a memory device may receive a command to perform a read operation on a memory cell comprising a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled to the floating gate of the first transistor. The operations of 1005 may be performed according to the methods described herein. In some examples, aspects of the operations of 1005 may be performed as described with reference to Figure 8 Describes the commands a module executes.

[0149] At 1010, a memory device may ground a source line coupled to a first transistor of a memory cell. The operations of 1010 may be performed according to the methods described herein. In some examples, aspects of the operations of 1010 may be performed as described in reference to Figure 8 The described bias module is implemented.

[0150] At 1015, as part of a read operation, the memory device may apply a first voltage to a digit line coupled to a second transistor of the memory cell. The operations of 1015 may be performed according to the methods described herein. In some examples, aspects of the operations of 1015 may be described by referring to Figure 8 The described bias module is implemented.

[0151] At 1020, the memory device may determine the logic state stored by the memory cell based on the signal on the digit line during at least a portion of the duration the source line is grounded. The operations of 1020 may be performed according to the methods described herein. In some examples, aspects of the operations of 1020 may be described by reference to Figure 8 Determine module execution as described.

[0152] In some examples, an apparatus as described herein may perform a method or methods, such as method 1000. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for each of: receiving a command to perform a read operation on a memory cell, the memory cell including a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled to the floating gate of the first transistor; grounding a source line coupled to the first transistor of the memory cell; applying a first voltage to a digit line connected to the second transistor of the memory cell as part of the read operation; and determining a logic state stored by the memory cell based on a signal on the digit line during at least a portion of the duration that the source line is grounded.

[0153] In some examples of method 1000 and apparatus described herein, grounding the source line may include operations, features, means, or instructions for activating a third transistor in the second memory cell, the third transistor having a first node connected to the source line, a second node connected to a ground voltage, and a floating gate.

[0154] In some examples of method 1000 and apparatus described herein, activating the third transistor may include operations, features, means, or instructions for applying the second voltage to a control gate of the third transistor.

[0155] Some examples of method 1000 and apparatus described herein may further include operations, features, means, or instructions of refreshing the second memory cell by applying a third voltage to a control gate of the third transistor.

[0156] In some examples of method 1000 and apparatus described herein, the refreshing of the second memory cell occurs after determining the logic state stored by the memory cell.

[0157] Some examples of method 1000 and apparatus described herein may further include an operation, feature, component, or instruction for applying a second voltage to a word line connectable to a control gate of the first transistor to activate the first transistor as part of a read operation.

[0158] Some examples of method 1000 and apparatus described herein may further include an operation, feature, component, or instruction for determining a logic state stored by a memory cell may be based on activating a first transistor, a signal on a digit line based on a voltage of a floating gate of the first transistor.

[0159] In some examples of method 1000 and apparatus described herein, a word line may be connected to a gate of the second transistor, and wherein applying the second voltage to the word line does not activate the second transistor.

[0160] In some examples of method 1000 and apparatus described herein, determining the state stored by the floating gate of the first transistor may include operations, features, means, or instructions for determining a current associated with a signal on a digit line.

[0161] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified so that other implementations are possible. Furthermore, aspects from two or more of the methods may be combined.

[0162] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0163] As used herein, the term "virtual ground" refers to a node in a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly coupled to ground. Thus, the voltage of the virtual ground can temporarily fluctuate and return to approximately 0V in a steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. "Virtual ground" or "virtual grounding" means connecting to approximately 0V.

[0164] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact with, or connected to, or coupled to, each other) if any conductive path exists between the components that can support signal flow between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with, or connected to, or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or an indirect conductive path between the connected components may include intermediate components, such as switches, transistors, or other components. In some cases, the signal flow between the connected components may be interrupted for a period of time using one or more intermediate components, such as switches or transistors.

[0165] The term "coupled" refers to moving from an open-circuit relationship between components (where signals cannot currently pass between the components via conductive paths) to a closed-circuit relationship between the components (where signals can pass between the components via conductive paths). When a component (e.g., a controller) is coupled with other components, the component initially changes to allow signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0166] The term "isolated" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller isolates two components from one another, it creates a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0167] As used herein, the term "substantially" means that the modified property (eg, the verb or adjective modified by the term substantially) need not be absolute, but is close enough to achieve the advantage of the property.

[0168] The devices described herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0169] The switching element or transistor described herein may represent a field-effect transistor (FET) and include a three-terminal device comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via a conductive material (e.g., metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "turned off" or "deactivated."

[0170] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0171] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar component. When only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the second reference label.

[0172] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0173] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0174] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features that implement the functions can also be physically located at various locations, including parts that are distributed so that the functions are implemented at different physical locations. Moreover, as used herein (included in the claims), the "or" used in a list of items (e.g., a list of items starting with a phrase such as "at least one" or "one or more") indicates an inclusion list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a conditional closed set. For example, without departing from the scope of the present invention, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0175] The description herein is provided to enable one skilled in the art to make or use the present invention. Various modifications to the present invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present invention. Therefore, the present invention is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: receiving a command to perform a write operation on a first memory cell, the first memory cell including a first transistor having a floating gate for storing a logic state of the first memory cell and a second transistor connected to the floating gate of the first transistor; coupling a source line connected to the first transistor with a digit line connected to the second transistor based at least in part on receiving the command, wherein the source line is further coupled to a second memory cell and a third memory cell, wherein coupling the source line with the digit line comprises applying a first voltage to activate the second memory cell and applying a second voltage to deactivate the third memory cell, the first voltage being different from the second voltage, wherein the second memory cell comprises a clamped memory cell and the third memory cell comprises a grounded memory cell; applying a third voltage to the digit line as part of the write operation; activating the second transistor to apply a fourth voltage to the floating gate of the first transistor, the fourth voltage being based at least in part on the third voltage; and The second transistor is deactivated to cause the first transistor to store the logic state based at least in part on the fourth voltage applied to the floating gate of the first transistor.

2. The method of claim 1 , wherein coupling the source line and the digit line comprises: A third transistor in the second memory cell is activated, the third transistor having a first node connected to the digit line, a second node connected to the source line, and a floating gate.

3. The method according to claim 2, wherein: Activating the third transistor includes applying a fifth voltage to a control gate of the third transistor, the third transistor having a floating gate.

4. The method according to claim 3, further comprising: The second memory cell is refreshed after deactivating the second transistor.

5. The method according to claim 1, further comprising: Based at least in part on receiving the command, a sixth voltage is applied to a word line associated with the first memory cell, the word line being connected to the control gate of the first transistor and to the gate of the second transistor.

6. The method according to claim 5, wherein: Applying the sixth voltage to the word line activates the second transistor without activating the first transistor.

7. The method according to claim 1, further comprising: receiving a second command to perform a read operation on the first memory cell after deactivating the second transistor; decoupling the source line from the digit line; activating a fourth transistor in the third memory cell to couple the source line to a ground voltage as part of the read operation; and A second logic state of the first memory cell is determined when the source line is coupled to the ground voltage.

8. A method comprising: receiving a command to perform a read operation on a first memory cell, the first memory cell including a first transistor having a floating gate for storing a logic state of the first memory cell and a second transistor coupled to the floating gate of the first transistor; grounding a source line coupled to the first transistor of the first memory cell, a second memory cell, and a third memory cell, wherein grounding the source line comprises applying a first voltage to deactivate the second memory cell and applying a second voltage to activate the third memory cell, the first voltage being different from the second voltage, wherein the second memory cell comprises a clamped memory cell and the third memory cell comprises a grounded memory cell; applying a third voltage to a digit line connected to the second transistor of the first memory cell as part of the read operation; and The logic state stored by the first memory cell is determined based at least in part on a signal on the digit line during at least a portion of the duration the source line is grounded.

9. The method of claim 8, wherein grounding the source line comprises: A third transistor in the third memory cell is activated, the third transistor having a first node connected to the source line, a second node connected to a ground voltage, and a floating gate.

10. The method according to claim 9, wherein: Activating the third transistor includes applying a fourth voltage to a control gate of the third transistor.

11. The method according to claim 10, further comprising: The third memory cell is refreshed by applying a fifth voltage to the control gate of the third transistor.

12. The method of claim 11, wherein refreshing the third memory cell occurs after determining the logic state stored by the first memory cell.

13. The method of claim 8, further comprising: A sixth voltage is applied to a word line connected to the control gate of the first transistor as part of the read operation to activate the first transistor.

14. The method according to claim 13, wherein: Determining the logic state stored by the first memory cell is based at least in part on activating the first transistor, the signal on the digit line being based at least in part on a voltage of the floating gate of the first transistor. 15 . The method of claim 13 , wherein the word line is connected to a gate of the second transistor, and wherein applying the sixth voltage to the word line does not activate the second transistor.

16. The method of claim 8, wherein: Determining the logic state stored by the floating gate of the first transistor includes determining a current associated with the signal on the digit line.

17. An apparatus comprising: a memory cell array, each memory cell of the memory cell array comprising a first transistor including a control gate and a floating gate and a second transistor connected to the floating gate of the first transistor, wherein each memory cell is configured to store a logic state using the first transistor and the second transistor; a plurality of word lines, each word line connected to the control gate of the first transistor and the gate of the second transistor of the memory cells of a row of the array; a plurality of digit lines, each digit line connected to a first node of the first transistor and a second node of the second transistor of a memory cell of a column of the array; and a plurality of source lines, each source line corresponding to one digit line of the plurality of digit lines and connected to the second node of the first transistor of a corresponding memory cell connected to the one digit line, each source line connected to the first transistor of the corresponding memory cell being further coupled to a clamped memory cell and a grounded memory cell, each source line being configured to be biased based on performing an operation using the one digit line by applying a first voltage to activate one of the clamped memory cell and the grounded memory cell and applying a second voltage to deactivate the other of the clamped memory cell and the grounded memory cell, the first voltage being different from the second voltage.

18. The apparatus of claim 17, further comprising: a row of clamp memory cells coupled to the memory cell array, each memory cell of the row of clamp memory cells comprising a third transistor including a floating gate and a fourth transistor connected to the floating gate of the third transistor, wherein a first node of each of the third transistors is connected to a corresponding source line of the plurality of source lines; and A clamp line is connected to the control gate of each of the third transistors and is configured to bias the corresponding source line to a voltage of the one digit line based on the operation being a write operation.

19. The apparatus of claim 18, wherein the second node of each of the third transistors is connected to the corresponding one of the digit lines.

20. The apparatus of claim 18, wherein the clamp line is configured to bias the corresponding source line to the voltage of the one digit line by activating each of the third transistors to couple the corresponding source line and the one digit line.

21. The apparatus of claim 18, wherein a third node of each of the fourth transistors is connected to the corresponding one of the digit lines and a gate of each of the fourth transistors is connected to the clamp line.

22. The apparatus of claim 17, further comprising: a row of grounded memory cells coupled to the memory cell array, each memory cell of the row of grounded memory cells comprising a fifth transistor including a floating gate and a sixth transistor coupled to the floating gate of the fifth transistor, wherein a first node of each of the fifth transistors is connected to a corresponding source line of the plurality of source lines; and A ground line is connected to the control gate of each of the fifth transistors and is configured to bias the corresponding source line to a ground voltage based on the operation being a read operation.

23. The apparatus of claim 22, wherein the second node of each of the fifth transistors is connected to the ground voltage.

24. The apparatus of claim 22, wherein the ground line is configured to bias the corresponding source line to the ground voltage by activating each of the fifth transistors to couple the corresponding source line with the ground voltage.

25. The apparatus of claim 17, wherein the first transistor of each memory cell is a p-type transistor and the second transistor of each memory cell is an n-type transistor.

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