Semiconductor structure and method of manufacturing the same

Abstract

The semiconductor structure and the manufacturing method thereof are provided in the present disclosure. The positioning of the electronic component is assisted by a correction mold. In order to avoid damage to the electronic component during the correction process, a corresponding chamfer is made on the correction mold and the electronic component respectively. The electronic component can be moved and corrected along the chamfer to improve the positioning accuracy.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor structures and their manufacturing methods. Background Technology

[0002] Currently, when embedding electronic components, pick-and-place devices are mostly used to control the positioning accuracy of the components. If the electronic components are misaligned, it will affect the yield of subsequent circuits or other processes. The main technical solution at present is to improve the pick-and-place accuracy of the pick-and-place device. Summary of the Invention

[0003] This disclosure provides semiconductor structures and methods for manufacturing them.

[0004] In a first aspect, this disclosure provides a semiconductor structure comprising: a first electronic component having opposing first and second surfaces, the second surface having a chamfer; and a first circuit layer disposed on the first surface and electrically connected to the first electronic component.

[0005] In some alternative implementations, the chamfer extends from the second surface to the side surface between the second surface and the first surface.

[0006] In some alternative implementations, the chamfer angle is between 30 and 85 degrees.

[0007] In some alternative implementations, the semiconductor structure further includes a second electronic component adjacent to the first electronic component, wherein the horizontal distance between the first and second electronic components is greater than the length of the right-angle side projected onto the horizontal direction by the chamfer.

[0008] In some alternative embodiments, the semiconductor structure further includes a molding layer that encapsulates the first electronic component, the molding layer having opposing third and fourth surfaces.

[0009] In some alternative implementations, the molding layer exposes the chamfer of the first electronic component.

[0010] In some alternative implementations, the molding layer covers the chamfer of the first electronic component.

[0011] In some alternative implementations, the semiconductor structure further includes a substrate electrically connected to a first circuit layer.

[0012] In some alternative embodiments, the substrate has a through-hole, a first electronic component is disposed in the through-hole, and a molding layer fills the gap between the first electronic component and the through-hole.

[0013] In some alternative implementations, the chamfer is a rounded chamfer.

[0014] In some alternative embodiments, the semiconductor structure further includes: a first solder resist layer disposed on the first circuit layer, the first solder resist layer having a plurality of first openings, the first circuit layer exposed from the first openings forming a first conductive pad.

[0015] In some alternative embodiments, the semiconductor structure further includes: a second circuit layer disposed on the fourth surface, the second circuit layer being electrically connected to the substrate; and a second solder resist layer disposed on the second circuit layer, the second solder resist layer having a plurality of second openings, the second circuit layer exposed from the second openings forming a second conductive pad.

[0016] In a second aspect, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing a first carrier having an upper surface; disposing a first electronic component on the upper surface; and applying force to the first electronic component using a calibration mold to calibrate the horizontal position of the first electronic component.

[0017] In some alternative implementations, the first electronic component and the calibration mold each have corresponding chamfers.

[0018] In some alternative implementations, the upper surface is a vacuum suction stage or tape.

[0019] In some alternative embodiments, the method further includes: providing a substrate; providing a through-hole in the substrate; and placing the substrate on an upper surface such that a first electronic component is placed in the through-hole.

[0020] In some alternative embodiments, the method further includes forming a molding layer that covers the substrate and the first electronic component and fills the gap between the via and the first electronic component.

[0021] In some alternative embodiments, the chamfer of the first electronic component is formed by the following steps: placing a wafer on a second carrier, the wafer having an active side and a back side; using a first cutter to half-cut the active side to disconnect the electrical connection; flipping the wafer over and fixing it on a third carrier; using a second cutter with a chamfer to cut the back side to separate the wafer and form a chamfer on the back side, thereby obtaining a chamfered first electronic component.

[0022] In some alternative implementations, the sealing layer has opposing third and fourth surfaces.

[0023] In some optional embodiments, the method further includes: forming a first circuit layer on a third surface, the first circuit layer being electrically connected to a first electronic component and a substrate respectively; forming a first solder resist layer on the first circuit layer; forming a plurality of openings on the first solder resist layer, the first circuit layer exposed from the openings forming a first conductive pad.

[0024] In some alternative embodiments, the method further includes: forming a second circuit layer on a fourth surface, the second circuit layer being electrically connected to a substrate; forming a second solder resist layer on the second circuit layer; and forming a plurality of openings in the second solder resist layer, the second circuit layer exposed from the openings forming a second conductive pad.

[0025] To address the technical problem of reduced yield in subsequent circuitry or other processes due to electronic component misalignment, the semiconductor structure and manufacturing method disclosed herein utilize a calibration mold to assist in electronic component positioning. Furthermore, to prevent damage to the electronic component during calibration, chamfers are fabricated on both the calibration mold and the electronic component. The electronic component can move and be calibrated along these chamfers, thereby improving positioning accuracy. Additionally, the semiconductor structure and manufacturing method disclosed herein can simultaneously calibrate two or more electronic components. Attached Figure Description

[0026] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0027] Figures 1-6 These are the first to sixth structural schematic diagrams of the semiconductor structure according to this disclosure;

[0028] Figures 7A to 7O This is a schematic diagram of the manufacturing process of the semiconductor structure according to the present disclosure.

[0029] Symbol explanation:

[0030] 1-First electronic component, 11-Chamfer, 12-First surface, 13-Second surface, 121-Side surface, 2-Second electronic component, 21-Second chamfer, 3-First circuit layer, 31-First conductive pad, 4-Molding layer, 41-Molding material, 42-Third surface, 43-Fourth surface, 5-Substrate, 51-Through hole, 52-Reconnection layer, 6-Second circuit layer, 61-Second conductive pad, 7-First solder resist layer, 8-Second solder resist layer, 9-Correction mold, 91-Mold chamfer, 10-Bottom filler, 141-Second carrier, 14-Third carrier, 15-Wafer, 16-First cutting tool, 17-Second cutting tool, 171-Cutting tool chamfer, 18-First carrier, 181-Top surface, 19-Punching mold, 20-Fourth carrier, θ-Chamfer angle. Detailed Implementation

[0031] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0032] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0033] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. Figures 1-6 The first to sixth structural schematic diagrams of the semiconductor structures disclosed herein are shown. Reference will be made below. Figures 1-6 This disclosure will be described in detail with reference to the embodiments.

[0034] Figure 1 A first structural schematic diagram of the semiconductor structure of this disclosure is shown. Figure 1 The semiconductor structure shown may include a first electronic component 1, a first circuit layer 3, a molding layer 4, a substrate 5, a second circuit layer 6, a first solder resist layer 7, and a second solder resist layer 8.

[0035] In this embodiment, the first electronic component 1 may have opposing first surfaces 12 and second surfaces 13. The first electronic component 1 may be, for example, a chip with various functions.

[0036] The first circuit layer 3 may be disposed on the first surface 12 and electrically connected to the first electronic component 1. The first circuit layer 3 may contain conductive materials such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0037] The substrate 5 can be electrically connected to the first circuit layer 3. The substrate 5 can have a through-hole 51, in which the first electronic component 1 can be disposed. The substrate 5 can include a redistribution layer 52. The substrate 5 can contain polyimide (PI), ABF substrate (Ajinomoto build-up film, ABF), molding compounds, pre-impregnated composite fibers (e.g., prepreg material), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), and combinations thereof, or other similar materials. The substrate 5 can contain conductive materials such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0038] The molding layer 4 can cover the first electronic component 1. The molding layer 4 can fill the gap between the first electronic component 1 and the through hole 51. This structure is not easily deformed or expanded under temperature changes and can maintain the original shape of the object under conditions of large temperature differences. The molding layer 4 can be made of molding materials such as epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, and ion trapping agent. The molding layer 4 can have opposing third surfaces 42 and fourth surfaces 43.

[0039] A first solder mask layer 7 may be disposed on a first circuit layer 3. The first solder mask layer 7 may have multiple first openings. The first circuit layer 3 exposed from the first openings may form a first conductive pad 31.

[0040] The second circuit layer 6 can be disposed on the fourth surface 43. The second circuit layer 6 can be electrically connected to the substrate 5. The second solder mask layer 8 can be disposed on the second circuit layer 6. The second solder mask layer 8 can have a plurality of second openings. The second circuit layer 6 exposed from the second openings can form a second conductive pad 61.

[0041] The second surface 13 of the first electronic component 1 may have a chamfer 11. The chamfer 11 may extend from the second surface 13 to the side 121 between the second surface 13 and the first surface 12. The chamfer angle θ may be between 30 degrees and 85 degrees. In the manufacturing process, setting the chamfer 11 can provide higher alignment accuracy.

[0042] Figure 2 A second structural schematic diagram of the semiconductor structure disclosed herein is shown. (As shown...) Figure 2 As shown, with Figure 1 The difference in the semiconductor structures shown is that, Figure 1 The chamfer 11 shown can be a bevel chamfer. Figure 2 The chamfer 11 shown can be a rounded chamfer. That is, the shape of the chamfer can be various, such as a beveled chamfer, a rounded chamfer, or different angles / radians, such as a 45-degree beveled chamfer.

[0043] Figure 3 A third structural schematic diagram of the semiconductor structure of this disclosure is shown. (As shown) Figure 3 As shown, with Figure 1 The difference in the semiconductor structures shown is that, Figure 1 The molded sealing layer 4 shown can cover the first electronic component 1. Figure 3 The molding layer 4 shown can expose the chamfer 11 of the first electronic component 1. That is, the molding layer 4 can cover or not completely cover the first electronic component 1.

[0044] Figure 4 A fourth structural schematic diagram of the semiconductor structure of this disclosure is shown. (As shown) Figure 4 As shown, with Figure 1 The difference in the semiconductor structures shown is that, Figure 4 The semiconductor structure shown may also include a second electronic component 2.

[0045] In this embodiment, the second electronic component 2 may be adjacent to the first electronic component 1. The horizontal distance between the first electronic component 1 and the second electronic component 2 may be greater than the length of the right-angled side projected onto the horizontal direction by the chamfer 11. The second component 2 may have a second chamfer 21.

[0046] Figure 5 A fifth schematic diagram of the semiconductor structure of this disclosure is shown. (As shown) Figure 5 As shown, with Figure 1 The difference in the semiconductor structures shown is that, Figure 1 The first electronic component 1 shown is positioned closer to the center. Figure 5 The first electronic component 1 shown is located closer to the edge.

[0047] Figure 6 A sixth structural schematic diagram of the semiconductor structure of this disclosure is shown. (As shown) Figure 6 As shown, with Figure 1 The difference in the semiconductor structures shown is that, Figure 6 The semiconductor structure shown may also include a bottom filler 10.

[0048] In this embodiment, the underfill material 10 can be used to protect the pins of the first electronic component 1 and to fill the gaps between the pins of the first electronic component 1. The underfill material 10 can fill the gaps, thereby achieving the purpose of reinforcement. The underfill material 10 can be, for example, capillary underfill (CUF), molded underfill (MUF), non-conductive paste (NCP), etc.

[0049] The semiconductor structure disclosed herein first includes a calibration mold 9 for calibrating the first electronic component 1 (e.g., ...). Figure 7I and Figure 7J As shown), by setting a chamfer 11 corresponding to the chamfer 91 of the correction mold 9 in the first electronic component 1, and / or setting a second chamfer 21 corresponding to the chamfer 91 of the correction mold 9 in the second electronic component 2, the first electronic component 1 and / or the second electronic component 2 can realize movement correction along the chamfer 91 of the mold to improve positioning accuracy.

[0050] Figures 7A to 7O A schematic diagram of the manufacturing process of the semiconductor structure according to the present disclosure is shown. The figures have been simplified for better understanding of the aspects of the present disclosure.

[0051] Please refer to Figures 7A-7E The chamfer 11 of the first electronic component 1 can be formed by the following steps: Please refer to Figure 7A A wafer 15 is disposed on the second carrier 141. The wafer 15 may have an active side and a back side. Please refer to [reference needed]. Figure 7B The first cutting tool 16 is used to half-cut the active face of wafer 15 to disconnect the electrical connection. Please refer to [reference needed]. Figure 7C Flip the wafer 15 over and fix it onto the third carrier 14, then remove the second carrier 141. Please refer to... Figure 7D A second tool 17 with a chamfer 171 is used to cut the back side of the wafer 15 to separate the wafer 15 and form a chamfer 11 on the back side. Please refer to... Figure 7E Thus, a first electronic component 1 with a chamfer of 11 is obtained.

[0052] Please refer to Figure 7F Substrate 5 is provided.

[0053] Please refer to Figure 7G and Figure 7HThrough holes 51 are formed on substrate 5 using a punching die 19 (e.g., a puncher). Substrate 5 with through holes 51 is obtained.

[0054] Please refer to Figure 7I , Figure 7I The calibration mold 9 shown can be used to calibrate an electronic component (first electronic component 1). First, a first carrier 18 is provided, having an upper surface 181. Then, the first electronic component 1 can be placed on the upper surface 181. Finally, the calibration mold 9 can be used to apply force to the first electronic component 1 to correct its horizontal position.

[0055] Please refer to Figure 7J , Figure 7J The calibration mold 9 shown can be used to simultaneously calibrate two or more electronic components (first electronic component 1 and second electronic component 2). First, a first carrier 18 is provided, having an upper surface 181. Then, the first electronic component 1 and the second electronic component 2 can be disposed on the upper surface 181. Finally, the calibration mold 9 can be used to apply force to the first electronic component 1 and the second electronic component 2 to calibrate their horizontal positions.

[0056] Specifically, a chamfer 91 can be provided on the pressing head to obtain a correction mold 9. The correction mold 9 can not only be used to transport the first electronic component 1 and / or the second electronic component 2 onto the upper surface 181, but also the chamfer 91 of the correction mold 9 can be used to correct and position the first electronic component 1 and / or the second electronic component 2.

[0057] The upper surface 181 may be provided with a fixing stage, such as a vacuum suction stage, an electrostatic suction stage, or tape. This can be used to fix the first electronic component 1 and / or the second electronic component 2, providing a restraining force. Therefore, the first electronic component 1 and / or the second electronic component 2 can be moved and corrected along the mold chamfer 91.

[0058] Please refer to Figure 7K The substrate 5 is placed on the upper surface 181 so that the first electronic component 1 is placed in the through hole 51.

[0059] Please refer to Figure 7L and Figure 7M A molding compound 41 is disposed on the fourth carrier 20, and the substrate 5 and the first electronic component 1 are bonded to the molding compound 41 to form a molding layer 4 that covers the substrate 5 and the first electronic component 1 and fills the gap between the through hole 51 and the first electronic component 1. The molding layer 4 may have a third surface 42 and a fourth surface 43 opposite to each other.

[0060] Please refer to Figure 7N A first circuit layer 3 is disposed on the third surface 42. The first circuit layer 3 can be electrically connected to the first electronic component 1 and the substrate 5 respectively. A second circuit layer 6 is disposed on the fourth surface 43. The second circuit layer 6 can be electrically connected to the substrate 5.

[0061] Please refer to Figure 7O A first solder resist layer 7 is provided on the first circuit layer 3. Multiple first openings are provided on the first solder resist layer 7. The first circuit layer 3 exposed through the first openings can form a first conductive pad 31. A second solder resist layer 8 is provided on the second circuit layer 6. Multiple second openings are provided on the second solder resist layer 8. The second circuit layer 6 exposed through the second openings can form a second conductive pad 61.

[0062] The method for manufacturing a semiconductor structure disclosed herein utilizes a calibration mold 9 to assist in the positioning of a first electronic component 1 and / or a second electronic component 2. To prevent damage to the first electronic component 1 and / or the second electronic component 2 during the calibration process, a mold chamfer 91 is provided on the calibration mold 9, a corresponding chamfer 11 is formed on the first electronic component 1, and a corresponding second chamfer 21 is formed on the second electronic component 2. A fixing stage (e.g., a vacuum stage, an electrostatic stage, or tape) on the upper surface 181 can assist in providing constraint force, thus allowing the first electronic component 1 and / or the second electronic component 2 to move and be calibrated along the mold chamfer 91 to improve positioning accuracy.

[0063] The method for manufacturing semiconductor structures disclosed herein can achieve similar technical effects to the aforementioned semiconductor structures, and will not be described in detail here.

[0064] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A first carrier is provided, the first carrier having an upper surface; The first electronic component is disposed on the upper surface; A calibration mold is used to apply force to the first electronic component to correct its horizontal position. The first electronic component and the calibration mold each have corresponding chamfers. The first electronic component is corrected and positioned using the chamfer of the calibration mold. The first electronic component moves and is corrected along the chamfer of the calibration mold. The angle of the chamfer is between 30 degrees and 85 degrees.

2. The method according to claim 1, wherein, The upper surface is a vacuum suction table or tape.

3. The method according to claim 1, wherein, The method further includes: Provide substrate; Through holes are provided in the substrate; A substrate is placed on the upper surface so that the first electronic component is placed in the through hole.

4. The method according to claim 3, wherein, The method further includes: A molding layer is formed that covers the substrate and the first electronic component and fills the gap between the through-hole and the first electronic component.

5. The method according to claim 1, wherein, The chamfer of the first electronic component is formed through the following steps: A wafer is disposed on a second carrier, the wafer having an active side and a back side; The active surface is cut in half using the first cutting tool to disconnect the electrical connection; The wafer is flipped over and fixed onto the third carrier. The back side is cut using a second tool with a chamfer to separate the wafer and form a chamfer on the back side, resulting in a first electronic component with a chamfer.

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