Circuit and method for multimode filter

Abstract

An integrated circuit provided in an embodiment includes a variable capacitor. The variable capacitor includes: a first capacitor element, wherein the first capacitor element includes a first capacitor of a metal oxide semiconductor structure; a second capacitor element connected in parallel with the first capacitor element, wherein the second capacitor element includes a second capacitor of a metal oxide semiconductor structure; a third capacitor element connected in parallel with the first capacitor element and the second capacitor element, wherein the third capacitor element includes a third capacitor of a metal insulator metal structure; and a fourth capacitor element connected in parallel with the first capacitor element, the second capacitor element and the third capacitor element, wherein the fourth capacitor element includes a fourth capacitor of a metal insulator metal structure.

Description

[0001] The present invention claims the priority of the prior application of U.S. non-provisional patent application No. 13 / 872,727, filed on April 29, 2013, entitled “Circuit and Method for a Multi-Mode Filter”, which claims the priority of the prior application of U.S. provisional patent application No. 61 / 780,513, filed on March 13, 2013, entitled “Circuit and Method for a Multi-Mode Filter”, the contents of the above prior applications are incorporated into this text by reference. Technical Field

[0002] The present invention relates generally to electronic circuits and methods, and more particularly to circuits and methods for multimode filters. Background Art

[0003] A cellular communication device includes a transceiver, such as an RF transceiver for receiving and transmitting radio frequency (RF) signals. The RF transceiver may include a baseband filter designed to filter the baseband bandwidth of the received RF signal. An example of a baseband filter is a differential biquad filter coupled to a single pole filter. The transceiver may be integrated on a single chip capable of receiving and transmitting RF signals of multiple communication standards, including Global System for Mobile Communications (GSM), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), Time Division Synchronous Code Division Multiple Access (TDSCDMA), Enhanced GSM Data Rate Evolution (EDGE), and Institute of Electrical and Electronics Engineering (IEEE) Wi-Fi 802.11a / b / g / n. These different communication standards support different broadband bandwidths, and therefore have different requirements for filters. Summary of the invention

[0004] According to an embodiment, an integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, wherein the second capacitive element includes a second MOS capacitor. The integrated circuit also includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, wherein the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, wherein the fourth capacitive element includes a second MIM capacitor.

[0005] According to another embodiment, a circuit includes a first operational amplifier (op-amp) having a first input, a second input, and a first output, wherein the first input is coupled to a first node, the second input is coupled to a second node, and the first output is coupled to a third node. The circuit also includes a first resistor coupled to the first node and a fourth node and a first capacitive element coupled to the fourth node and a fifth node, wherein the first capacitive element includes a first MOS capacitor and a first MIM capacitor coupled in parallel with the first MOS capacitor. In addition, the circuit also includes a second capacitive element coupled to the first node and the third node, wherein the second capacitive element includes a second MOS capacitor and a second MIM capacitor coupled in parallel with the second MOS capacitor. The circuit also includes a second resistor coupled to the third node and a sixth node and a second operational amplifier, wherein the second operational amplifier includes a third input coupled to the sixth node, a fourth input coupled to the seventh node, and a second output coupled to the eighth node. In addition, the circuit also includes a third capacitive element coupled to the sixth node and the eighth node, wherein the third capacitive element includes a third MOS capacitor and a third MIM capacitor coupled in parallel with the third MOS capacitor.

[0006] According to an additional embodiment, a method for selecting the capacitance of a capacitance structure includes determining whether a first capacitance element of the capacitance structure is selected, wherein the first capacitance element includes a first MOS capacitor; and determining whether a second capacitance element of the capacitance structure is selected, wherein the second capacitance element includes a second MOS capacitor, and the second capacitance element is coupled in parallel with the first capacitance element. The method also includes determining whether a third capacitance element of the capacitance structure is selected, wherein the third capacitance element includes a first MIM capacitor, and the third capacitance element is coupled in parallel with the first capacitance element and the second capacitance element; and determining whether a fourth capacitance element of the capacitance structure is selected, wherein the fourth capacitance element includes a second MIM capacitor, and the fourth capacitance element is coupled in parallel with the first capacitance element, the second capacitance element, and the third capacitance element. In addition, the method also includes selecting one or more of the first, second, third, and fourth capacitance elements based on the determination result.

[0007] According to another embodiment, a method for manufacturing an integrated circuit includes forming a first capacitor element on a surface of a semiconductor substrate, forming a second capacitor element on the surface of the semiconductor substrate, and coupling the first capacitor element in parallel with the second capacitor element. The method also includes forming a third capacitor element in a metal layer covering the surface of the semiconductor substrate, and forming a fourth capacitor element in the metal layer covering the surface of the semiconductor substrate. In addition, the method also includes coupling the third capacitor element in parallel with the first capacitor element and the second capacitor element, and coupling the fourth capacitor element in parallel with the first capacitor element, the second capacitor element, and the third capacitor element.

[0008] The above is a rather broad overview of the features of embodiments of the present invention in order to better understand the detailed description of the present invention below. Additional features and advantages of embodiments of the present invention will be described below, which form the subject matter of the claims of the present invention. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments may be readily used as a basis for modifying or designing other structures or processes for achieving the same purposes of the present invention. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 An embodiment baseband filter is shown;

[0011] Figure 2 An embodiment differential baseband filter is shown;

[0012] Figure 3 An embodiment capacitor circuit is shown;

[0013] Figure 4 Another embodiment capacitor circuit is shown;

[0014] Figure 5 An embodiment metal oxide semiconductor (MOS) capacitor circuit is shown;

[0015] Figure 6 Another embodiment MOS capacitor circuit is shown;

[0016] Figure 7 An embodiment metal insulator metal (MIM) capacitor circuit is shown;

[0017] Figure 8 An embodiment MIM capacitor circuit is shown;

[0018] Fig. 9 Embodiment MOS and MIM capacitor circuits are shown;

[0019] Fig.10 Example MOS and MIM capacitor layouts are shown;

[0020] Fig.11 Embodiment MOS and MIM capacitor integrated circuits are shown;

[0021] Fig.12 Another embodiment MOS capacitor circuit is shown;

[0022] Fig.13 An embodiment tracking oscillator circuit is shown; and

[0023] Fig.14 An embodiment method of selecting a capacitor is shown.

[0024] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0025] Initially it should be understood that although an illustrative implementation of one or more embodiments is provided below, the disclosed systems and / or methods may be implemented using any number of currently known or existing techniques. The present invention should in no way be limited to the illustrative implementations, drawings, and techniques described below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0026] For 3G and 4G cellular transceivers, several wireless standards can be implemented on a single chip. The various standards have different requirements for baseband filter bandwidths, ranging from 200KHz for Global System for Mobile Communications (GSM) to 20MHz for Long Term Evolution (LTE)-40. Typically, large capacitors are used for low-bandwidth filters and small capacitors are used for high-bandwidth filters.

[0027] The biquad filter or biquad plus real pole filter is the main filter in cellular baseband receivers. Figure 1 Circuit 100 is shown, which is an example of a current driven biquad filter that can be used as a single pole before a baseband filter in a transceiver. A biquad filter (biquad filter or biquadratic filter) is a linear filter that implements a transfer function (the ratio of two quadratic functions). Circuit 100 shows a low-pass Tow-Thomas biquad filter. The natural frequency of the biquad portion in circuit 100 is given by:

[0028]

[0029] Where R 116 is the resistance of resistor 116, R 118 is the resistance of resistor 118, C 112 is the capacitance of capacitor 112, C 122 is the capacitance of capacitor 122. Therefore, the capacitance of capacitor 112 and the capacitance of capacitor 122 affect the critical frequency of circuit 100. For circuit 100 to be implemented as a multi-mode filter, capacitor 112 and capacitor 122 may be variable capacitors. The voltage gain (Vout / Vin) of filter 100 is given by:

[0030]

[0031] The quality factor of the biquad portion of circuit 100 is given by:

[0032] Where R 114 is the resistance of resistor 114. The second order transfer function of circuit 100 is given by:

[0033]

[0034] Circuit 100 includes three operational amplifiers: operational amplifier 110, operational amplifier 120, and operational amplifier 126. Operational amplifier 126 inverts the output of operational amplifier 120, while operational amplifier 110 and operational amplifier 120 perform a filtering function. The positive input of operational amplifier 110 is coupled to ground 104, while the negative input of operational amplifier 110 is coupled to resistor 106, which is coupled to current source 102 and capacitor 108. In an example, current source 102 is an AC current source of 1 ampere. Capacitor 112 and resistor 114 are coupled in parallel between the negative input and output of operational amplifier 110. Resistor 118 is coupled between the output of operational amplifier 110 and the negative input of operational amplifier 120, while the positive input of operational amplifier 120 is connected to ground 104. Capacitor 122 is coupled between the negative input and output of operational amplifier 120. Capacitor 124 is coupled between the output of operational amplifier 120 and the negative input of operational amplifier 126. The positive input of operational amplifier 126 is coupled to ground 104, and resistor 128 is coupled between the negative input and the output of operational amplifier 126. Resistor 116 is coupled between the output of operational amplifier 126 and the negative input of operational amplifier 110. In order to adjust the frequency and Q of circuit 100, various resistors and capacitors may be implemented as variable resistors and capacitors that may be adjusted to change the frequency and Q of circuit 100.

[0035] The baseband filters in an RF receiver may be implemented as differential filters. Figure 2 Circuit 130 is shown, which is a current driven differential biquad filter with a single pole. Circuit 130 includes two fully differential op amps: differential op amp 142 and differential op amp 156. Only two op amps are used in circuit 130, compared to three in circuit 100, due to the inherent inversion in the fully differential op amps. The natural frequency of the biquad portion in circuit 130 is given by:

[0036]

[0037] Where R 162 is the resistance of resistor 162, R 152 is the resistance of resistor 152, C 158 is the capacitance of capacitor 158, C 146 is the capacitance of capacitor 146. The gain of circuit 130 is given by:

[0038]

[0039] Where R 162 is the resistance of resistor 162, R 138is the resistance of resistor 138 .

[0040] Circuit 130 may be symmetrical, i.e., the upper half of the circuit corresponds to the lower half of the circuit. In an example, the capacitance of capacitor 146 and capacitor 150 is equal, and the capacitance of capacitor 158 and capacitor 160 is equal, and these capacitances may be adjusted to change the natural frequency and Q of the low pass filter. The resistance of the resistor and the capacitance of the capacitor are adjustable, so the natural frequency of circuit 130 may be adjusted to make circuit 130 a multi-mode filter. In one embodiment, the capacitors may be switched in to compensate for the effect on the cut-off frequency tolerance of the filter, and the resistors may be swapped to select the operating mode of the filter (e.g., LTE-40, LTE-20, GSM, etc.).

[0041] Resistor 138 is coupled between negative input terminal 132 and a negative input terminal of differential operational amplifier 142, and resistor 140 is coupled between positive input terminal 134 and a positive input terminal of differential operational amplifier 142. Capacitor 136 is coupled between negative input terminal 132 and positive input terminal 134. Resistor 144 and capacitor 146 are coupled in parallel between the negative input terminal and a positive output terminal of differential operational amplifier 142, and resistor 148 and capacitor 150 are coupled in parallel between the positive input terminal and a negative output terminal of differential operational amplifier 142. Resistor 152 is coupled between the positive output terminal of differential operational amplifier 142 and a negative input terminal of differential operational amplifier 156, and resistor 154 is coupled between the negative output terminal of differential operational amplifier 142 and a positive input terminal of differential operational amplifier 156. Capacitor 158 is coupled between the negative input terminal of differential operational amplifier 156 and the positive output terminal of differential operational amplifier 156, and capacitor 160 is coupled between the positive input terminal of differential operational amplifier 156 and the negative output terminal of differential operational amplifier 156. Resistor 162 is coupled between the negative output terminal of differential operational amplifier 156 and the negative input terminal of differential operational amplifier 142, and resistor 164 is coupled between the positive output terminal of differential operational amplifier 156 and the positive input terminal of differential operational amplifier 142. Negative output terminal 166 is coupled to the positive output terminal of operational amplifier 156, and positive output terminal 168 is coupled to the negative output terminal of operational amplifier 156.

[0042] Figure 3Circuit 170 is shown, which can be used as a variable capacitor (e.g., in circuit 130). Switch 182 connects and disconnects capacitor 172, switch 184 connects and disconnects capacitor 174, switch 186 connects and disconnects capacitor 176, and switch 188 connects and disconnects capacitor 180. In the example, switch 182 is omitted. The capacitance of capacitor 172 can be fixed (Cfix), which can be connected all the time. The capacitance of capacitor 174 is the least significant bit (Clsb) capacitance, while the capacitance of capacitor 176 is a multiple of Clsb, and the capacitance of capacitor 180 is also a multiple of Clsb. For example, the capacitance of capacitor 176 is twice that of capacitor 174, and the capacitance of capacitor 180 is four times that of capacitor 174. Capacitor 174, capacitor 176, and capacitor 180 are connected or disconnected in parallel with capacitor 172 to obtain the capacitance required by circuit 170. Although only four capacitors are shown in circuit 170, additional capacitors may be connected in parallel with capacitor 172, with each successive capacitor having a capacitance that is a multiple of the capacitance of the previous capacitor. As the filter moves from a wider bandwidth filtering mode (i.e., LTE-40) to a narrower bandwidth filtering mode (i.e., GSM), the values ​​of Cfix and Clsb are increased by adding additional capacitors to obtain appropriate values ​​for a given mode. Thus, all capacitors deployed in a high bandwidth mode may be reused in a low bandwidth mode.

[0043] In a multimode filter of an RF transceiver, the two bandwidths are so close that the capacitor required to implement Clsb in circuit 170 is too small to be practical. Figure 4 Circuit 190 is shown, and the capacitance of circuit 190 can be adjusted so that the capacitance is close without requiring the capacitance of a certain capacitor to be Clsb. As in circuit 170, circuit 190 has four capacitors, one end of each capacitor (capacitor 192, capacitor 194, capacitor 196 and capacitor 198) is connected to a switch (switch 200, switch 202, switch 204, switch 206), and the switch is connected in series with each capacitor so that the capacitor can be connected independently to obtain the required capacitance. In the example, switch 200 is omitted. However, circuit 190 is configured so that only one capacitor can be connected at a time. The capacitance of capacitor 192 is Cfix, the capacitance of capacitor 194 is Cfix+Clsb, the capacitance of capacitor 196 is Cfix+N*Clsb, and the capacitance of capacitor 198 is Cfix+M*Clsb, where N and M are integers. In the example, N is 2 and M is 3. The structure can be expanded to include more capacitors according to the required filter cutoff frequency accuracy. In the example, we use 16 capacitors and a 4-bit binary tuning word.

[0044] The variable capacitors used in circuits 170 and 190 can be implemented as metal oxide semiconductor (MOS) capacitors. MOS capacitors have a small area and can be very small in capacitance, which facilitates small steps in capacitance, which are very useful in implementing high bandwidth filters. In high bandwidth filters, we need small capacitance steps. However, MOS capacitors, especially large capacitors with large capacitance, have linearity and leakage issues. These capacitors can cause problems if used in low bandwidth modes (i.e., GSM) where the capacitor values ​​are large. Figure 5 A circuit 210 is shown with a MOS capacitor configuration. To reduce the nonlinear effects of the MOS capacitor, a pair of capacitors (capacitor 218 and capacitor 220) are connected back-to-back with the center terminal 216 biased to the supply voltage. The two differential paths are biased to half the supply voltage. This differential operation compensates for the nonlinearity of a single capacitor.

[0045] The back-to-back MOS capacitors may be configured as a binary tree, such as the binary trees shown in circuits 170 and 190 . Figure 6 Circuit 230 is shown having back-to-back MOS capacitors connected in a parallel configuration with a switch in series with the pair of MOS capacitors. Capacitor 218 and capacitor 220 are biased using bias 236 and switched on and off using switch 232, capacitor 238 and capacitor 240 are biased using bias 246 and controlled by switch 242, capacitor 248 and capacitor 250 are biased using bias 256 and controlled by switch 252, and capacitor 258 and capacitor 260 are biased using bias 266 and controlled by switch 262.

[0046] Metal-Insulator-Metal (MIM) capacitors can also be used as variable capacitors. MIM capacitors are very linear and have low leakage, but they are large in area and difficult to implement for small capacitors. However, MIM capacitors are useful in implementing low bandwidth modes. In low bandwidth modes, we use large capacitance values ​​and large capacitance steps. To balance the parasitic capacitance between two different paths of the MIM capacitor, an anti-parallel connection can be implemented, such as Figure 7 2. MIM capacitor 276 is connected to MIM capacitor 278 in anti-parallel. Switch 280 and switch 284 are connected to opposite ends of the anti-parallel configuration. Circuit 270 does not include a bias network. In another example, capacitor 276 and capacitor 278 are MOS capacitors. When MOS capacitors are used, the area of ​​the capacitors in circuit 270 is smaller than that of the capacitors in circuit 210.

[0047] Figure 8Circuit 290 is shown, which shows multiple pairs of MIM capacitors in an anti-parallel configuration, which form a capacitor tree. MIM capacitor 276 and MIM capacitor 278 are connected to switch 280 and switch 284. MIM capacitor 292 and MIM capacitor 294 are connected to switch 296 and switch 300, MIM capacitor 304 and MIM capacitor 306 are connected to switch 308 and switch 312, and MIM capacitor 316 and MIM capacitor 318 are connected to switch 320 and switch 324.

[0048] Since leakage is not a major concern, MOS capacitors are suitable for high bandwidth filters with small capacitors, which have a small capacitance. MIM capacitors are suitable for small bandwidth filters with large capacitors, which have a large capacitance step. Table 1 shows the capacitance values ​​of capacitors 108, capacitors 112, and capacitors 122 in circuit 100 for various communication transceivers in pico-farads. The capacitance is dominated by GSM / EDGE filters and LTE-1.4 filters.

[0049]

[0050] Table 1

[0051] In an embodiment, a large capacitor is implemented as a MIM capacitor connected in parallel with a small capacitor implemented as a MOS capacitor. Fig. 9 A circuit 330 is shown, which includes MOS capacitors and MIM capacitors arranged in parallel. MOS capacitors 218, 220, 238 and 240 are connected in parallel with MIM capacitors 276, 278, 292 and 294. The MOS capacitors are turned on in the large bandwidth mode and the MIM capacitors are turned on in the low bandwidth mode. Therefore, the best properties of each capacitor can be utilized, so that we can have better filter shape accuracy.

[0052] In the example, the MIM capacitors are physically located above the MOS capacitors and active devices, which saves additional area on the die. Since the MIM capacitors are close to the top of the stack, they rarely interact with the MOS capacitors or the active circuits described below. Fig.10 A layout 340 is shown including a MIM capacitor 342 , a MOS capacitor 346 , and a switch 344 , with the MIM capacitor 342 being above the MOS capacitor 346 . Fig.11A cross-sectional view of an integrated circuit 350 is shown, the integrated circuit 350 including a MIM capacitor and a MOS capacitor, the MIM capacitor being on top of the MOS capacitor. A substrate 352 includes MOS capacitor bottom plates 354 and 358, which may be n-well regions. An oxide layer 364 is on the MOS capacitor bottom plate 354, and an oxide layer 368 is on the MOS capacitor bottom plate 358. A MOS capacitor top plate 366 is on the oxide layer 364, and a MOS capacitor top plate 370 is on the oxide layer 368. In an example, the MOS capacitor top plate 366 and the MOS capacitor top plate 370 are gate polysilicon layers. In addition, the MOS capacitor top plate 366 is connected to the metal interconnect layer 380 via 374, and the MOS capacitor top plate 370 is connected to the metal interconnect layer 380 via 378. The contact layer 356 is embedded in the MOS capacitor bottom plate 354, and the contact layer 360 is embedded in the MOS capacitor bottom plate 358. In addition, contact layer 356 is connected to metal interconnect layer 381 via 372, and contact layer 360 is connected to metal interconnect layer 383 via 376. In addition, metal interconnect layer 382 and metal interconnect layer 384 are above metal interconnect layer 380. In addition, dielectric layer 362 (e.g., silicon dioxide) is interposed between the layers. MIM capacitor bottom plate 386 is above these metal interconnect layers. Insulating layer 389, which can be another dielectric such as silicon dioxide or hafnium dioxide, is placed between MIM capacitor bottom plate 386 and MIM capacitor top plate 388. MIM capacitor bottom plate 386 is connected to metal interconnect layer 396 via 392, and MIM capacitor top plate 388 is connected to metal interconnect layer 394 via 390. Ultra-thick metal layer 398 is above dielectric layer 362.

[0053] Fig.12 A circuit 400 is shown, which includes a circuit that can be used at the filter input ( Figure 2The capacitor 136 in the circuit 400 implements a MOS capacitor array with real poles. At the filter input, a differential signal is applied to the adjustable capacitor. In the specific case where the bandwidths of the two filters are very close, for example, for an LTE-10 filter with a bandwidth of 5MHz and a 3G2C filter with a bandwidth of 5.3MHz, we need to use a new method. Since these frequencies are very close, Clsb is very small, for example, 0.02741×CFix. In circuit 400, only one branch is connected at a time. The capacitor is implemented as a back-to-back MOS capacitor. For clarity, the bias blocks at the connections of multiple pairs of back-to-back MOS capacitors are omitted.In the example, the capacitance of capacitors 408 and 410 is Cfix and switches 406 and 412 control capacitors 408 and 410, the capacitance of capacitors 416 and 418 is Cfix+Clsb and switches 414 and 420 control capacitors 416 and 418, the capacitance of capacitors 424 and 426 is Cfix+2×Clsb and switches 422 and 428 control capacitors 424 and 426, the capacitance of capacitors 432 and 434 is Cfix+3×Clsb and switches 430 and 436 control capacitors 432 and 434, and the capacitance of capacitors 440 and 442 is Cfix+3×Clsb. x+4×Clsb and switches 438 and 444 control capacitors 440 and 442, the capacitance of capacitors 448 and 450 is Cfix+5×Clsb and switches 446 and 452 control capacitors 448 and 450, the capacitance of capacitors 456 and 458 is Cfix+6×Clsb and switches 454 and 460 control capacitors 456 and 458, the capacitance of capacitors 464 and 466 is Cfix+7×Clsb and switches 462 and 468 control capacitors 464 and 466, the capacitance of capacitors 472 and 474 is Cfix+8×Clsb and switches 4 470 and 476 control capacitors 472 and 474, the capacitance of capacitors 480 and 482 is Cfix+9×Clsb and switches 478 and 484 control capacitors 480 and 482, the capacitance of capacitors 488 and 490 is Cfix+10×Clsb and switches 486 and 492 control capacitors 488 and 490, the capacitance of capacitors 496 and 498 is Cfix+11×Clsb and switches 494 and 500 control capacitors 496 and 498, the capacitance of capacitors 504 and 506 is Cfix+12×Clsb and switches 502 and 508 control capacitors 4. The capacitance of capacitors 504 and 506 is Cfix+12×Clsb and switches 502 and 508 control capacitors 504 and 506, the capacitance of capacitors 512 and 514 is Cfix+13×Clsb and switches 510 and 516 control capacitors 512 and 514, the capacitance of capacitors 520 and 522 is Cfix+14×Clsb and switches 518 and 524 control capacitors 520 and 522, and the capacitance of capacitors 528 and 530 is Cfix+15×Clsb and switches 526 and 532 control capacitors 528 and 530. For example, the value of Cfix can be as low as 1 pF, so using a conventional binary tuning array we can end up with an LSB of a 4-bit tuning control word of 62.5 pF4, which is very close to the parasitic capacitance of the switches and is therefore difficult to implement accurately.

[0054] To adjust both types of capacitors, the circuit containing the tracking oscillator will provide two different control words, one for the MIM capacitor branch and the other for the MOS capacitor branch. The circuit is essentially a phase-locked loop (PLL) that locks the frequency of the RC oscillator to an exact external frequency, typically on the order of several MHz, by adjusting the adjustable capacitors in the oscillator. Since the adjustable capacitors in the oscillator use the same topology as used in the filter, the filter can also be tuned when tuning the RC oscillator. In one embodiment, two separate tracking oscillators are used, with one tracking circuit controlling the MIM capacitors and the other tracking circuit controlling the MOS capacitors, so that the branch using either type of capacitor can be accurately tuned. The code can be stored in digital form and provided to the appropriate capacitor.

[0055] Alternatively, a single tracking oscillator may be used to control both the MIM capacitors and the MOS capacitors. Fig.13 Circuit 540 is shown, which includes a single tracking oscillator that controls MOS capacitors and MIM capacitors. Tracking oscillator 542 receives a reference frequency 564. Switches 552 and 554 connect back-to-back MOS capacitors 548 and 550 to track capacitor 542. In addition, capacitor 546 connects the centers of MOS capacitors 548 and 550 to provide voltage 544. In addition, switches 560 and 562 connect anti-parallel MIM capacitors 556 and 558 to track oscillator 542. N bits are read out, and the N bits enter the MOS capacitor tree in phase 1 and enter the MIM capacitor tree in phase 2. The operation is similar to the case of two tracking oscillators. The two types of capacitors are interleaved in time. In Fig.13 During phase 2 of the filter, the MIM capacitor tree is turned on and tuned for a number of reference frequency cycles. Afterwards, the MOS capacitors are turned on and tuned during phase 1. The binary words are stored in registers so that no matter what type of capacitor is calibrated at any time, the binary word is always available to the filter. The width of the controller will depend on the accuracy of the filter. For a more accurate response, more steps, more bits, and more capacitors are needed.

[0056] Fig.14A flow chart 570 is shown illustrating a method of selecting capacitors from a capacitor bank, which may include MOS capacitors and MIM capacitors. First, at step 572, it is determined whether a MOS capacitor is selected. When a MOS capacitor is selected, at step 574, one or more MOS capacitors are selected. The selection of the connected MOS capacitor is determined by the binary word of the tracking oscillator. The tracking oscillator, essentially a PLL, operates in a closed loop and will attempt to adjust the adjustable capacitor outside the RC oscillator until the frequency of the RC oscillator is locked to a stable reference frequency. If a MOS capacitor is not selected in step 572, or after a MOS capacitor is selected in step 574, it is determined at step 576 whether a MIM capacitor is selected. Only MOS capacitors may be selected, only MIM capacitors may be selected, or both MOS capacitors and MIM capacitors may be selected. If a MIM capacitor is not selected in step 576, the method ends at step 580. If a MIM capacitor is selected in step 576, then one or more MIM capacitors are selected in step 578. Thereafter, the method ends at step 580.

[0057] Advantages of embodiments include small die area for circuits including MOS and MIM capacitors. Additionally, embodiments enable accurate filter corner implementation.

[0058] Although several embodiments have been provided in the present invention, it should be understood that the systems and methods disclosed herein may be embodied in many other specific forms without departing from the spirit or scope of the present invention. The examples of the present invention should be considered illustrative rather than restrictive, and the present invention is not limited to the details given in this text. For example, various elements or components may be combined or merged in another system, or certain features may be omitted or not implemented.

[0059] In addition, without departing from the scope of the present invention, the techniques, systems, subsystems and methods described and illustrated as discrete or separate in the various embodiments may be combined or merged with other systems, modules, techniques or methods. Other items shown or discussed as coupled or directly coupled or communicating with each other may also be coupled or communicated indirectly through an interface, device or intermediate component, either electrically, mechanically or otherwise. Other variations, substitutions and altered examples may be determined by those skilled in the art without departing from the spirit and scope of the disclosure herein.

Claims

1. An integrated circuit, characterized in that: include: An operational amplifier, and a first variable capacitor connected between an input terminal and an output terminal of the operational amplifier, wherein the first variable capacitor comprises: A first capacitive element, wherein the first capacitive element comprises a first capacitor of a metal oxide semiconductor structure; a second capacitive element connected in parallel with the first capacitive element, wherein the second capacitive element comprises a second capacitor of a metal oxide semiconductor structure; a third variable capacitor, the third variable capacitor being coupled to the positive input terminal and the negative input terminal of the operational amplifier, the third variable capacitor comprising: a fifth capacitive element, wherein the fifth capacitive element comprises a fifth capacitor of a metal oxide semiconductor structure; a sixth capacitive element connected in parallel with the fifth capacitive element, wherein the sixth capacitive element comprises a sixth capacitor of a metal oxide semiconductor structure; a seventh capacitive element connected in parallel with the fifth capacitive element and the sixth capacitive element, wherein the seventh capacitive element comprises a seventh capacitor of a metal oxide metal structure; an eighth capacitive element connected in parallel with the fifth capacitive element, the sixth capacitive element and the seventh capacitive element, wherein the eighth capacitive element comprises an eighth capacitor of a metal oxide metal structure; a fifth switch coupled in series with the fifth capacitor, and a sixth switch coupled in series with the sixth capacitor, the fifth switch being used to independently connect or disconnect the fifth capacitor, and the sixth switch being used to independently connect or disconnect the sixth capacitor; A ninth capacitor of a metal oxide semiconductor structure is connected back-to-back with the fifth capacitor, and terminals of the back-to-back connection are coupled to a bias voltage.

2. The integrated circuit according to claim 1, characterized in that Also includes: a third capacitive element connected in parallel with the first capacitive element and the second capacitive element, wherein the third capacitive element comprises a third capacitor of a metal oxide metal structure; and a fourth capacitive element connected in parallel with the first capacitive element, the second capacitive element and the third capacitive element, wherein the fourth capacitive element comprises a fourth capacitor of a metal oxide metal structure; It also includes a second switch coupled in series with the second capacitor and a fourth switch coupled in series with the fourth capacitor, wherein the second switch is used to independently connect or disconnect the second capacitor, and the fourth switch is used to independently connect or disconnect the fourth capacitor.

3. The integrated circuit according to claim 2, characterized in that It also includes a first switch coupled in series with the first capacitor and a third switch coupled in series with the third capacitor, the first switch is used to independently connect or disconnect the first capacitor, and the third switch is used to independently connect or disconnect the third capacitor.

4. The integrated circuit according to claim 2 or 3, characterized in that: The first capacitor and the second capacitor are formed on a surface of a semiconductor substrate, and the third capacitor and the fourth capacitor are formed in a metal layer covering the surface of the semiconductor substrate.

5. The integrated circuit according to any one of claims 1 to 3, characterized in that: The integrated circuit is applied to a multimode filter; The multi-mode filter is used for passing a 200KHz signal including a global system for mobile communications and a 20MHz signal of long term evolution.

6. The integrated circuit according to claim 5, characterized in that The input end of the operational amplifier includes a positive input end and a negative input end, and the output end of the operational amplifier includes a positive output end and a negative output end; The multimode filter includes a first resistor coupled in parallel with the first variable capacitor between the positive input terminal and the negative output terminal of the operational amplifier.

7. The integrated circuit according to claim 6, characterized in that The multimode filter also includes a second variable capacitor and a second resistor, the second resistor and the second variable capacitor are coupled in parallel between the negative input terminal and the positive output terminal of the operational amplifier, and the circuit formed by the second resistor and the second variable capacitor is symmetrical to the circuit formed by the first capacitor and the first resistor.

8. The integrated circuit according to claim 4, characterized in that The oxide in the metal oxide metal structure is silicon dioxide or hafnium dioxide.

9. The integrated circuit according to claim 4, characterized in that: The top plate of the first capacitor is gate polysilicon.

10. The integrated circuit according to claim 9, characterized in that The integrated circuit includes a first through hole; The first via connects the top plate of the first capacitor to a first metal interconnect layer overlying a surface of a semiconductor substrate.

11. The integrated circuit according to claim 1, characterized in that: It also includes a seventh switch coupled in series with the seventh capacitor and an eighth switch coupled in series with the eighth capacitor, the seventh switch is used to independently connect or disconnect the seventh capacitor, and the eighth switch is used to independently connect or disconnect the eighth capacitor.

12. The integrated circuit according to claim 1, characterized in that: The third variable capacitor further includes a ninth switch, and the ninth switch and the fifth switch are coupled in series with the fifth capacitor and the ninth capacitor for connecting or disconnecting the fifth capacitor and the ninth capacitor.

13. The integrated circuit according to claim 1, characterized in that: The capacitance value of the seventh capacitor is greater than the capacitance value of the fifth capacitor.

14. The integrated circuit according to claim 13, characterized in that: The capacitance value of the eighth capacitor is greater than the capacitance value of the sixth capacitor.

15. The integrated circuit according to claim 1, characterized in that: The signals of bandwidths of multiple communication standards are signals of different bandwidths under the same communication standard.

16. The integrated circuit according to claim 1, characterized in that: The signals of bandwidths of multiple communication standards are signals of different bandwidths under different communication formats.

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