Method for writing into non-volatile memory and corresponding integrated circuit

Abstract

A method of writing to a non-volatile memory and a corresponding integrated circuit are disclosed. A semiconductor well of the non-volatile memory accommodates memory cells. Each memory cell has a floating gate and a control gate. Erasing the memory cells includes biasing the semiconductor well with a first erase voltage, the absolute value of the first erase voltage being greater than the breakdown voltage level of a bipolar junction of a control gate switch circuit of the memory. The absolute value of the first erase voltage is based on a comparison of a value of a wear indication of the memory cell with a wear threshold.

Description

Technical Field

[0001] Embodiments and implementations relate to integrated circuits, and more particularly to nonvolatile memory and writing in nonvolatile memory. Background Art

[0002] Writing in a non-volatile memory such as an electrically erasable and programmable type "EEPROM" (Electrically Erasable Programmable Read-Only Memory) generally consists of an erase cycle followed by a programming cycle. For example, the erase cycle is collective in so-called selected memory cells belonging to a so-called selected full page (or row), while programming is selective according to the data ("0" or "1") to be written into the different memory cells of the selected memory.

[0003] During erase and program cycles, the floating gate transistor belonging to each memory cell is biased with a sufficiently high write voltage to inject charge (positive or negative, depending on the erase and programming specifications adopted) into the floating gate of the transistor either by the Fowler-Nordheim effect or by the effect of injected hot carriers.

[0004] Therefore, the threshold value (the value of the threshold voltage) of the floating gate transistor in the erased state is different from the threshold value of the floating gate transistor in the programmed state that allows the stored data to be read.

[0005] The write voltage is approximately 10 to 15 volts in absolute value and is applied between the control gate and the body (substrate or well housing the transistor) of the floating gate transistor, such as during erase, or between the control gate and a conductive terminal of the floating gate transistor, such as during programming.

[0006] In order to generate a high write voltage, a voltage division technique is used to apply a medium-amplitude positive voltage on the one hand and a medium-amplitude negative voltage on the other hand.

[0007] This allows in particular to reduce the size of the transistors of the memory, in particular the transistors delivering the write voltages, taking into account that the voltage limitations in these transistors are alleviated by the voltage division technique.

[0008] Charge injection is particularly prone to degrading the dielectric layer through which the injected charge tunnels over many erase and program cycles.

[0009] This degradation results in a shift in the threshold of the transistor in both the erased and programmed states.

[0010] This drift is particularly high in erase involving charge injected between the semiconductor body and the floating gate. For example, after hundreds of thousands of write cycles (e.g., 500,000 cycles), the threshold in the erased state may be about 2 to 4 volts greater than the threshold in the erased state resulting from the first erase cycle.

[0011] Therefore, after a large number of write cycles, the distinction between the erased state and the programmed state becomes indeterminate.

[0012] This aging phenomenon results in a limited endurance of the memory. Memory endurance is a characteristic that defines the number of write cycles that guarantee normal operation of the memory (in other words, the "lifetime" of the memory). From a commercial point of view, endurance is an important characteristic.

[0013] This aging phenomenon becomes more pronounced as the size of transistors in memory decreases.

[0014] Furthermore, the techniques used to increase the lifetime of the erase cycle to limit the drift of the threshold in the erased state have the direct disadvantage of slowing down the write operation. From a commercial point of view, the speed of the write cycle is also an important characteristic.

[0015] Therefore, conventional techniques for increasing the erase voltage to limit threshold drift are often limited by the breakdown level of the junction of the transistor that transmits the control gate voltage. Summary of the invention

[0016] Therefore, there is a need to propose a compact non-volatile memory with longer endurance without limiting other characteristics of the memory.

[0017] According to one aspect, the present disclosure provides a method for writing a non-volatile memory, the non-volatile memory including memory cells contained in a semiconductor well, each memory cell including a state transistor having a floating gate and a control gate. The method includes an erase cycle, the erase cycle including biasing the semiconductor well with a first erase voltage (e.g., positive), and in response to an increase in the wear value of the memory cell being greater than a wear threshold, increasing the level of the first erase voltage in absolute value form to a level greater than a breakdown level of a bipolar junction of a control gate switch circuit of the memory.

[0018] In a method according to this aspect, the erase cycle can include biasing the control gates of the selected memory cells with a second erase voltage (eg, negative) via the control gate switching circuit.

[0019] It goes without saying that the wear value of a memory cell is a value representing the aging of the memory cell, which can be determined at a given moment by a circuit provided for this purpose. For example, the number of erase cycles performed can be counted and this count can be used as an indication of the wear of the memory cell; the difference between the storage voltage level and the threshold voltage level of the memory cell can be used as an indication of the wear; etc.; and combinations thereof.

[0020] The wear threshold may be a value representing the aging of the memory cell due to which the maximum voltage level in the control gate switch circuit (breakdown level of the bipolar junction) is no longer sufficient to prevent a drift (e.g., a drift of about 2 volts) of the threshold of the state transistor in the erased state. Such aging of the memory cell (corresponding to the wear threshold) may be illustrated, for example, by 500,000 write cycles implemented in the memory.

[0021] The first erase voltage and the second erase voltage are mutually configured to erase the selected memory cell, such as by injecting charge into the floating gate of the state transistor of the selected memory cell, typically via the Fowler-Nordheim effect.

[0022] In other words, the method according to this aspect proposes to increase the magnitude of the erase voltage by increasing the component of the erase voltage (first erase voltage) applied in the well of the memory cell in absolute value in the voltage division technique.

[0023] However, the first erase voltage does not pass through the control gate switch circuit.

[0024] Therefore, the level of the first erase voltage is not limited by the breakdown level of the bipolar junction of the control gate switching circuit.

[0025] This therefore allows limiting the drift of the threshold value while strengthening the erasure in aged memory cells beyond the limit imposed by the breakdown of the bipolar junction controlling the gate switching circuit and thus allows increasing the overall endurance of the memory.

[0026] The memory may include a peripheral circuit, a buffer transistor housed in a buffer semiconductor well, the memory cell being coupled to the peripheral circuit via a conductive terminal of the buffer transistor, and, according to one implementation, biasing the buffer semiconductor well and the gate of the buffer transistor with a buffer isolation voltage suitable for isolating the peripheral circuit from a first erase voltage.

[0027] For example, the bit line is coupled to a conductive terminal of a state transistor of a memory cell, and the bit line is coupled to the peripheral circuit through a conductive terminal of a buffer transistor.

[0028] This allows the first erase voltage not to be transmitted to the peripheral circuit when the level of the first erase voltage is greater than the breakdown level of the control gate switch circuit, which is generally destructive to the peripheral circuit.

[0029] More specifically, since the bit line is not used during the erase cycle, the bit line is at a floating potential. Therefore, the potential of the bit line may rise to the level of the first erase voltage, potentially rising to a voltage level that can degrade the peripheral circuit.

[0030] However, since the gate of the buffer transistor is biased with the buffer isolation voltage, the peripheral circuit is protected from the first erase voltage present on the bit line during writing. In addition, since the buffer semiconductor well is also biased with the buffer isolation voltage, the buffer transistor will not be damaged by the first erase voltage of the bit line.

[0031] In this regard, when the wear value is greater than the wear threshold, the buffered isolation voltage may be at least equal to a difference between a level of the first erase voltage and a breakdown level of a bipolar junction of the control gate switch circuit.

[0032] According to one implementation, the semiconductor isolation region is biased with a first erase voltage, and in a triple-well type structure, the conductor isolation region surrounds a semiconductor well and a buffer semiconductor well, wherein the semiconductor well accommodates a memory cell.

[0033] In one aspect, the semiconductor region of the memory is allowed to be electrically isolated from the first erase voltage. More specifically, the bipolar junction between the substrate and the semiconductor isolation region is generally capable of supporting a voltage greater than the breakdown voltage of the control gate switching circuit.

[0034] On the other hand, the semiconductor isolation region shared by the triple-well type structure for both the well for accommodating the memory cell and the buffer well is advantageously compact. The sharing is obtained in particular by buffering the isolation voltage, preventing the breakdown of the bipolar junction between the buffer semiconductor well and the semiconductor isolation region biased with the first erase voltage.

[0035] According to one implementation, the erase cycle further includes biasing the control gates of unselected memory cells with a neutralizing voltage via the control gate switching circuit.

[0036] The neutralization voltage is configured relative to the first erasing voltage applied to the well that also accommodates the unselected memory cells to neutralize the pseudo-erasure phenomenon of the unselected memory cells. This is advantageous in terms of data retention.

[0037] For example, the neutralization voltage is selected such that it is equal to the first erase voltage. However, the neutralization voltage is limited by the breakdown level of the bipolar junction of the control gate switch circuit.

[0038] According to one implementation, when the wear value is less than the wear threshold, the method comprises increasing the level of the neutralization voltage in absolute value so as to maintain a constant initial deviation relative to said level of the first erase voltage. In the case where the neutralization voltage is selected so that it is equal to the first erase voltage, maintaining the constant initial deviation is a zero deviation.

[0039] This advantageously allows pseudo-erasure phenomena of unselected memory cells to be neutralized while the first erase voltage increases as the memory cells age.

[0040] According to one implementation, when the wear value is greater than the wear threshold, the method includes shifting the level of the neutralization voltage to an offset neutralization voltage level and increasing the level of the offset neutralization voltage in absolute value to keep the offset constant relative to the level of the first erase voltage.

[0041] Furthermore, advantageously, when the wear value is greater than the wear threshold, the level of the first erase voltage remains unchanged when the level of the neutralization voltage reaches the breakdown level of the bipolar junction of the control gate switch circuit.

[0042] In other words, when the first erase voltage exceeds the breakdown voltage of the control gate switch circuit, the level of the neutralization voltage is offset so as not to exceed the level of the breakdown voltage. Then, as a result of the offset, the neutralization voltage follows the evolution of the first erase voltage without exceeding the breakdown voltage. When the neutralization voltage reaches the level of the breakdown voltage of the bipolar junction of the control gate switch circuit closest to the safety margin, the first erase voltage is no longer increased.

[0043] Maintaining a constant offset when increasing the first erase voltage beyond the wear threshold is advantageous in regulating the generated voltage and allows good control of the pseudo-erasure phenomenon caused by this constant difference. In this regard, the method can compensate for pseudo-erasure by conventional mechanisms (e.g., so-called "refresh" algorithms).

[0044] According to another implementation, when the wear value is greater than the wear threshold, the level of the first erase voltage remains unchanged at a level equal to a tolerance margin taken for the breakdown level of the bipolar junction of the control gate switch circuit.

[0045] In this other implementation, the level of the neutralization voltage does not shift and remains constant beyond the wear threshold. Therefore, the deviation between the level of the first erase voltage and the level of the neutralization voltage increases as the level of the first erase voltage evolves. Therefore, the pseudo-erasure phenomenon in the unselected memory cells may not be well controlled, but for the time period starting after the wear threshold, it is lower at the beginning than at the end.

[0046] According to another aspect, the present disclosure provides a non-volatile memory integrated circuit, comprising:

[0047] memory cells housed in the semiconductor well and each memory cell including a state transistor having a floating gate and a control gate; and

[0048] An erase device is configured to bias the semiconductor well with a first erase voltage (e.g., positive) during an erase cycle, the erase device being configured to increase the level of the first erase voltage to a level greater than a breakdown level of the bipolar junction of the control gate switch circuit in absolute value form in response to the wear value of the memory cell increasing to be greater than a wear threshold.

[0049] According to one embodiment, the erase apparatus is configured during an erase cycle to bias the control gates of selected memory cells with a second erase voltage (eg, negative) through the control gate switch circuit.

[0050] According to one embodiment, the integrated circuit further includes peripheral circuitry, a buffer transistor housed in a buffer semiconductor well, and the memory cell is coupled to the peripheral circuitry via a conductive terminal of the buffer transistor, the buffer semiconductor well and a gate of the buffer transistor to be biased with a buffer isolation voltage adapted to isolate the peripheral circuitry from the first erase voltage.

[0051] According to one embodiment, when the wear value is greater than the wear threshold, the distribution circuit is configured to generate a buffered isolation voltage at least equal to a difference between a level of the first erase voltage and a breakdown level of a bipolar junction of the control gate switch circuit.

[0052] According to one embodiment, the semiconductor well accommodating the memory cell is surrounded by a semiconductor isolation region in a triple-well type structure, and in the triple-well type structure, the buffer semiconductor well is also surrounded by the same semiconductor isolation region, and the semiconductor isolation region is biased with a first erase voltage.

[0053] According to one embodiment, the erase apparatus is further configured during the erase cycle to bias the control gates of the unselected memory cells with a neutralizing voltage via the control gate switching circuit.

[0054] According to one embodiment, when the wear value is less than the wear threshold, the erasing device is configured to increase the level of the neutralization voltage in absolute value so as to maintain a constant initial deviation relative to said level of the first erasing voltage.

[0055] According to one embodiment, when the wear value is greater than the wear threshold, the erase device is configured to shift the level of the neutralization voltage to an offset neutralization voltage level and increase the level of the offset neutralization voltage in absolute value form so that the offset remains constant relative to the level of the first erase voltage.

[0056] According to one embodiment, when the wear value is greater than the wear threshold, the erasing device is configured to keep the level of the first erasing voltage unchanged when the level of the neutralization voltage reaches the breakdown level of the bipolar junction of the control gate switch circuit.

[0057] According to one embodiment, when the wear value is greater than the wear threshold, the erasing device is configured to keep the level of the first erasing voltage unchanged when the level of the first erasing voltage is equal to a tolerance margin taken for the breakdown level of the bipolar junction of the control gate switch circuit.

[0058] In an embodiment, a method includes: erasing memory cells contained in a semiconductor well of a nonvolatile memory, each memory cell having a floating gate and a control gate, erasing including biasing the semiconductor well with a first erase voltage, the first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switch circuit of the memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell with a wear threshold; and writing to one or more of the memory cells. In an embodiment, in response to the comparison indicating that the value of the wear indication is greater than the wear threshold, the absolute value of the erase voltage is increased. In an embodiment, erasing includes biasing a control gate of a selected memory cell with a second erase voltage using the control gate switch circuit. In an embodiment, the memory includes peripheral circuitry and a buffer transistor contained in a buffer semiconductor well; the memory cell is coupled to the peripheral circuitry through a conductive terminal of the buffer transistor; and biasing the buffer semiconductor well and the gate of the buffer transistor with a buffer isolation voltage to isolate the peripheral circuitry from the first erase voltage. In an embodiment, when the value of the wear indication is less than the wear threshold, the buffer isolation voltage is at least equal to a difference between the level of the first erase voltage and the breakdown voltage level of the bipolar junction of the control gate switch circuit. In an embodiment, a semiconductor isolation region is biased with a first erase voltage, the semiconductor isolation region surrounding a semiconductor well and a buffer semiconductor well housing a memory cell, the memory having a triple well type structure. In an embodiment, an erase cycle includes biasing the control gates of unselected memory cells with a neutralization voltage via a control gate switch circuit. In an embodiment, when the value of the wear indication is less than a wear threshold, the method includes increasing the level of the neutralization voltage in absolute value form so as to maintain a constant initial deviation relative to the level of the first erase voltage. In an embodiment, when the value of the wear indication is greater than the wear threshold, the method includes shifting the level of the neutralization voltage to an offset neutralization voltage level, and increasing the level of the offset neutralization voltage in absolute value form so as to maintain a constant deviation relative to the level of the first erase voltage. In an embodiment, when the value of the wear indication is greater than the wear threshold, the level of the first erase voltage remains unchanged after the level of the neutralization voltage reaches a breakdown voltage level of a bipolar junction of the control gate switch circuit. In an embodiment, when the value of the wear indication is greater than the wear threshold, the level of the first erase voltage remains unchanged, the level being equal to a tolerance margin taken for the breakdown voltage level of the bipolar junction of the control gate switch circuit.

[0059] In an embodiment, a non-volatile memory integrated circuit includes: memory cells housed in a semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; and a control circuit device that controls reading, writing and erasing of the memory cells in operation, wherein erasing includes biasing the semiconductor well with a first erase voltage, the absolute value of the first erase voltage being greater than a breakdown voltage level of a bipolar junction of a control gate switch circuit of the non-volatile memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell with a wear threshold. In an embodiment, in response to the comparison indicating that the value of the wear indication is greater than the wear threshold, the absolute value of the erase voltage is increased. In an embodiment, the control circuit device biases the control gate of a selected memory cell with a second erase voltage using the control gate switch circuit in operation. In an embodiment, the integrated circuit includes peripheral circuitry and a buffer transistor housed in a buffer semiconductor well, wherein the memory cell is coupled to the peripheral circuitry through a conductive terminal of the buffer transistor, and the control circuit device biases the buffer semiconductor well and the gate of the buffer transistor with a buffer isolation voltage in operation to isolate the peripheral circuitry from the first erase voltage. In an embodiment, in operation, when the value of the wear indication is greater than the wear threshold, the control circuit generates a buffer isolation voltage at least equal to the difference between the level of the first erase voltage and the breakdown voltage level of the bipolar junction of the control gate switch circuit. In an embodiment, the semiconductor well accommodating the memory cell is surrounded by a semiconductor isolation region in a triple well type structure, the buffer semiconductor well is surrounded by the semiconductor isolation region, and the control circuit biases the semiconductor isolation region with the first erase voltage in operation. In an embodiment, the control circuit biases the control gates of the unselected memory cells with the neutralization voltage via the control gate switch circuit during the erase cycle. In an embodiment, during the erase cycle, when the value indicating the wear is less than the wear threshold, the control circuit device sets the level of the neutralization voltage to an initial deviation that remains constant relative to the level of the first erase voltage in absolute value form. In an embodiment, during the erase cycle, when the value indicating the wear is greater than the wear threshold, the control circuit shifts the level of the neutralization voltage to the offset neutralization voltage level in operation, and increases the level of the offset neutralization voltage in absolute value form so as to keep the offset constant relative to the level of the first erase voltage. In an embodiment, when the value indicating wear is greater than a wear threshold, the control circuit device maintains the level of the first erase voltage unchanged when the level of the neutralization voltage reaches a breakdown level of the bipolar junction of the control gate switch circuit. In an embodiment, when the value indicating wear is greater than the wear threshold, the control circuit device maintains the level of the first erase voltage unchanged when the level of the first erase voltage is equal to a tolerance margin taken for the breakdown level of the bipolar junction of the control gate switch circuit.

[0060] In an embodiment, a system includes: one or more processing cores; and a non-volatile memory coupled to the one or more processing cores, the non-volatile memory including: memory cells contained in a semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; and a control circuit device that controls reading, writing, and erasing of the memory cells in operation, wherein erasing includes biasing the semiconductor well with a first erase voltage, the absolute value of the first erase voltage being greater than a breakdown voltage level of a bipolar junction of a control gate switch circuit of the non-volatile memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell with a wear threshold. In an embodiment, the system includes an integrated circuit, the integrated circuit including the non-volatile memory. In an embodiment, the integrated circuit includes the one or more processing cores. In an embodiment, the absolute value of the first erase voltage is increased in response to a comparison indicating that the value of the wear indication is greater than the wear threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Other advantages and features of the present disclosure will become apparent by reviewing the detailed description of non-limiting embodiments and implementations, and from the accompanying drawings, in which:

[0062] Figure 1 A cross-sectional view showing one example of a memory cell of an integrated circuit of a nonvolatile memory NVM of an embodiment.

[0063] Figure 2 shows the implementation reference Figure 1 An exemplary embodiment of an erase cycle of a memory NVM is described.

[0064] Figure 3 An example of an embodiment of a control gate switch circuit GCSW for transmitting a negative erase voltage -VNN or a positive neutralization voltage +VPP in a control gate line of a memory cell is shown.

[0065] Figure 4 and Figure 5 As shown in the reference Figures 1 to 3 Two exemplary embodiments of a writing method implemented in a memory NVM are described.

[0066] Figure 6 An exemplary embodiment of a memory is shown. DETAILED DESCRIPTION

[0067] Figure 1A cross-sectional view of an example of a memory cell of an integrated circuit of a non-volatile memory NVM is shown. The integrated circuit shown also includes a control circuit device 102, which controls the writing, reading and erasing of the memory cells of the non-volatile memory NVM. In some embodiments, a separate circuit device can be used to control the reading, writing and erasing of the memory cells. The non-volatile memory can be included in a system including one or more processing cores, which can, for example, be coupled to the non-volatile memory and can store data in the non-volatile memory and retrieve data from the non-volatile memory.

[0068] The memory cell includes a state transistor TE (TEsel or TEnsel, depending on whether the state transistor TE is selected or unselected) and an access transistor TA coupled in series.

[0069] The memory cell is accommodated in and above the semiconductor well PW1 , which is typically P-type doped.

[0070] Well PW1 accommodates the memory array PM (see Figure 6 ) in the memory cells of the memory array PM, which are typically arranged in an array of rows and columns.

[0071] The state transistor TE (TEsel, TEnsel) comprises a floating gate FG and a control gate CG, the floating gate FG being electrically isolated from the well PW1 by a so-called “tunnel” dielectric layer and from the control gate CG by a so-called “gate” dielectric layer.

[0072] In this example, the access transistor TA is a buried vertically oriented gate transistor and is shared by two state transistors TE (TEsel, TEnsel) on either side of the vertical gate. The vertical gate fills a trench etched vertically in the well PW1, the sides and bottom of the trench being covered in a gate dielectric layer.

[0073] The vertical gate of the access transistor TA is also formed perpendicular to the Figure 1 A word line WL extends in the direction of the plane in FIG. 1 , and the word line WL is common to a row of memory cells, for example.

[0074] The buried semiconductor region NISO allows the well PW1 accommodating the memory cell to be electrically isolated from the semiconductor substrate PSUB on the one hand, and allows the source region of the access transistor TA to be formed on the other hand.

[0075] According to the so-called "triple well" isolated well structure, the well PW1 accommodating the memory cells is effectively isolated from the semiconductor substrate PSUB by the buried semiconductor region NISO and by an isolation well of N doping type laterally surrounding the well PW1. This specifically allows the well PW1 to be biased with a positive potential.

[0076] The drain D of the access transistor TA is located at the surface of the well PW1 and simultaneously forms the source region of the corresponding state transistor TEsel.The drain regions of the state transistors Tesel, TEnsel are coupled via contacts to a bit line BL in a first level of the interconnection part of the integrated circuit.

[0077] In order to record data in the memory, the write circuit device is configured to logically select the memory cells to be written, and the memory cells not to be written are referred to as unselected.

[0078] The erase circuitry is configured to collectively erase memory cells belonging to at least one selected page during an erase cycle.A page of memory is a group of memory cells, typically a whole row of memory cells, in a matrix organization of a memory array.

[0079] The programming circuit is configured to selectively program the memory cells during an erase cycle. For example, a programming cycle includes commonly biasing the control gate line CGLsel with a first programming voltage and selectively biasing the bit line BL with a second programming voltage according to the data to be stored.

[0080] Reference now Figure 2 .

[0081] Figure 2 shows the implementation of the above reference Figure 1 An example of an erase cycle of a memory NVM is described.

[0082] During an erase cycle, the erase circuitry is configured to bias the semiconductor well PW1 with a first erase voltage VYP and to bias a selected control gate line CGLsel with a second erase voltage -VNN.

[0083] The rest of the description below will consider the common convention in which the first erase voltage VYP is positive and the second erase voltage VNN is negative. The first erase voltage VYP can therefore be represented as a "positive erase voltage" and the second erase voltage VNN can therefore be represented as a "negative erase voltage".

[0084] That is, by considering the increase in the absolute value of the negative voltage, the embodiments and implementations described below may be applicable to voltages of opposite signs, and specifically in wells accommodating memory cells of opposite conductivity (N-type).

[0085] The positive erase voltage VYP and the negative erase voltage -VNN are configured with each other to generate charge "e" transferred from the floating gate of the state transistor TEsel of the selected memory cell to the well PW1 through the tunnel dielectric layer, typically by the Fowler-Nordheim effect.

[0086] Furthermore, during the erase cycle, the erase circuitry is configured to bias the unselected control gate lines CGLnsel with a neutralization voltage +VPP (positive in this example).

[0087] The neutralization voltage +VPP neutralizes a pseudo-erase phenomenon in the unselected state transistor TEnsel that may be caused by a positive erase voltage VYP applied to the well PW1 that also accommodates the unselected memory cells. For example, the neutralization voltage +VPP may be initially selected to be equal to the positive erase voltage VYP.

[0088] Furthermore, the bit line BL is maintained at a floating potential HZ; the vertical gate of the access transistor TA is biased with approximately 5V or 7V (volts) to limit the stress induced on the gate oxide of the access transistor TA by the positive erase voltage VYP in the well PW1; and the buried semiconductor isolation region NISO is biased with the positive erase voltage VYP.

[0089] Thus, the erase cycle specifically includes biasing the selected control gate line CGLsel with a negative erase voltage -VNN, and biasing the unselected control gate lines CGLnsel with a positive neutralization voltage +VPP.

[0090] Reference now Figure 3 .

[0091] Figure 3 An example of a control gate switch circuit GCSW for transmitting a negative erase voltage -VNN or a positive neutralization voltage +VPP in the control gate lines CGLi, CGLi+1, CGLi+2, ..., CLGi+k of memory cells is shown.

[0092] The control gate switch CGSW selectively transmits a negative erase voltage -VNN or a positive neutralization voltage +VPP, depending on whether the memory cells of the page are selected or unselected. In this regard, the control gate switch CGSW decodes the selection control signal through an inverter type circuit using complementary high voltage metal oxide semiconductor HVMOS technology well known to those skilled in the art.

[0093] Therefore, the PMOS transistor of the inverter INVP is formed in the common N-type semiconductor well CMNNW, and the NMOS transistor of the inverter INVN is formed in the common P-type semiconductor well CMNPW. In addition, the PMOS and NMOS transistors of the common source and common gate type CASP and CASCN can be set on the CGLi-CGLi+k output of the inverter and formed in the isolated wells SGLNW and SGLPW.

[0094] Therefore, in the control gate switch circuit CGSW, the potential difference (HVmax, Figure 4 and 5 ) is limited by the characteristics of the HVMOS transistor (INVP, INVN, CASCP, CASCN). Specifically, the bipolar junction between the conductive region (specifically, the drain region, because the well is usually biased by the potential of the source region) of the HVMOS transistor and the corresponding well is usually limited by its breakdown level (HVmax), for example, about 11V.

[0095] Therefore, in order to enhance the erase stimulus, the voltage condition of the erase cycle, the levels of the voltages VPP, VNN in absolute value form, cannot be increased via the control gate switch circuit CGSW.

[0096] However, as the memory cells age, erase cycles are less efficient at the same erase voltage than at the beginning of the life of the memory NVM.

[0097] This aging phenomenon is typically caused by degradation of the floating gate oxide that has been subjected to a large number of erase cycles (eg, approximately 500,000 cycles).

[0098] In this regard, the erase circuit arrangement is configured to increase the level of the positive erase voltage VYP according to aging of the memory cell.

[0099] For example, the write circuit device or the erase circuit device is configured to evaluate the wear value (AG) representing the aging of the memory cell by reading in the memory cell "in margin mode" after each application of the erase stimulus. Reading in margin mode is a reading that measures the threshold value of the floating gate transistor TEsel in a quantitative manner. In this case, the write circuit device can be configured to implement a repetition of the iterative erase cycle in a closed loop until the correct erase state is obtained.

[0100] Alternatively, the write or erase circuit arrangement may estimate a wear value (AG, VYP) representing the aging of the memory cell from a record of the last values ​​of the erase voltages VYP, VNN. Figure 4 and 5 ). More specifically, the write or erase circuit device can be automatic so as to measure the erase state regularly "in margin mode" and increase the value of the erase voltage VYP, VNN if necessary. The new erase voltage value VYP, VNN is recorded and can be used as a reference for evaluating the wear value AG during the next erase cycle.

[0101] Therefore, the level of the positive erase voltage VYP may increase according to the evolution of the wear value (AG).

[0102] Since the positive erase voltage VYP biases the well PW1 and is not transmitted via the control gate switch circuit CGSW, it is not directly limited by the breakdown level (HVmax) of the bipolar junction of the circuit CGSW.

[0103] Therefore, the level of the positive erase voltage VYP can be greater than the breakdown level (HVmax) of the control gate switch CGSW. When the aging of the memory cell causes the maximum levels of the positive voltage (VPP) and the negative voltage (VNN) of the control gate switch circuit CGSW to be reached and no longer sufficient to produce an erased state that can be strictly distinguished from a programmed state, the voltage conditions of the write cycle are allowed to be enhanced.

[0104] In this regard, reference Figure 4 and Figure 5 .

[0105] Figure 4 and Figure 5 As shown in the above reference Figures 1 to 3 Two examples of implementing a write method in a memory NVM are described.

[0106] Figure 4 and Figure 5 The evolution of the levels of positive voltages achieved during an erase cycle is shown, including the positive erase voltage VYP applied in the well PW1 and the neutralization voltage VPP applied in the control gate CG of the unselected state transistor TEnsel.

[0107] In both examples, the method includes increasing the level of the positive erase voltage VYP due to an increase in the wear value AG representing the aging of the memory cells. As a result, the amplitude of the erase stimulus is increased to limit the drift of the threshold of the aged memory cells, allowing the overall endurance of the memory to increase.

[0108] For example, the increase in the level of the positive erase voltage VYP is due to the increase in the wear value AG because they are proportional. The increase in the level of the positive erase voltage VYP can also be broken down into several steps whose levels increase proportionally with the increase in the wear value AG.

[0109] It should be remembered that the wear value AG can be obtained directly or by reading erased memory cells in margin mode.

[0110] The neutralization voltage VPP is configured with respect to the positive erasing voltage VYP in order to neutralize a pseudo erasure phenomenon of the unselected memory cells TEnsel.

[0111] The neutralization voltage may be selected so that it is equal to or close to the positive erase voltage VYP.

[0112] Therefore, the method includes increasing the level of the neutralization voltage VPP generated due to the increase in the level of the positive erase voltage VYP.

[0113] Although the neutralization voltage VPP and the positive erase voltage VYP are initially different, the neutralization voltage VPP is increased to keep the initial difference constant.

[0114] The neutralization voltage VPP is limited by the breakdown level of the control gate switch CGSW since it is transmitted on the control gate lines of the unselected memory cells TEnsel.

[0115] Therefore, in Figure 4 In the example of , when the neutralization voltage VPP increases until reaching the maximum level HVmax of the control gate switch circuit CGSW, the neutralization voltage VPP is set to the maximum level HVmax and no longer increases according to the wear value AG of the memory cell.

[0116] It goes without saying that the term maximum level is understood to mean a safety margin taken for the breakdown level of the bipolar junction of the control gate switching circuit CGSW.

[0117] The threshold AGplf of the wear value AG is defined as a wear value when the positive erase voltage VYP and the neutralization voltage VPP reach a maximum level HVmax (which will be referred to as "wear threshold AGplf" hereinafter).

[0118] Exceeding the wear threshold AGplf, the level of the neutralization voltage VPP no longer increases, but the level of the positive erase voltage VYP still increases to a level exceeding the maximum level HVmax and to a level exceeding the breakdown level of the bipolar junction of the control gate switch circuit CGSW.

[0119] In the same way as below the wear threshold AGplf, increasing the positive erase voltage VYP in proportion to the increase in the wear value AG, optionally in steps, further results in an increase in the wear value AG.

[0120] Therefore, above the wear threshold AGplf, the deviation between the positive erase voltage VYP and the neutralization voltage VPP increases according to the increase in the wear AG of the memory cell. This generates a pseudo erase phenomenon that gradually increases from the wear threshold AGplf.

[0121] Methods exist for compensating for this type of artifacts, such as refresh algorithms.

[0122] When the level of the positive erase voltage VYP is greater than the tolerance margin with respect to the breakdown level HVmax of the control gate switch CGSW, the level does not increase any more.

[0123] For example, the tolerance margin is chosen to be specifically 2 V in order to limit pseudo-erasure phenomena and to be able to easily compensate for them using a “refresh” type method.

[0124] exist Figure 5 In the example shown, above the wear threshold AGplf, the method includes, on the one hand, offsetting the level of the neutralization voltage VPP by ΔD to obtain the offset neutralization voltage DVPP, and on the other hand, increasing the level of the offset neutralization voltage DVPP while keeping the offset ΔD (between the level of the offset neutralization voltage DVPP and the level of the positive erase voltage VYP) constant.

[0125] The level of the positive erase voltage VYP continues to increase as the wear value AG increases.

[0126] Therefore, as a result of the shift ΔD, the neutralization voltage VPP can also continue to follow the evolution of the positive erase voltage VYP without exceeding the maximum level HVmax.

[0127] Furthermore, when the neutralization voltage VPP reaches a level closest to the breakdown voltage HVmax of the control gate switch CGSW for a safety margin, the positive erasing voltage VYP no longer increases.

[0128] Keeping the offset ΔD constant when increasing the positive erase voltage VYP makes it easy to adjust the generated positive voltages VYP, VPP and also allows easy control of the compensation of the pseudo-erasure phenomenon generated by this constant difference.

[0129] For example, the offset ΔD is set to about 2 V in order to limit the pseudo-erasure phenomenon and to be able to easily compensate for the pseudo-erasure phenomenon using a “refresh” type method.

[0130] For example, if the positive voltages VYP, VPP are equal before the wear threshold AGplf is reached, the positive erase voltage VYP and the positive neutralization voltage VPP are generated on the same output of a charge pump circuit (not shown). After the wear threshold AGplf is reached, an additional charge pump stage can be coupled in parallel to provide a positive erase voltage VYP that is then greater than the positive neutralization voltage VPP through a separate output. Keeping the deviation ΔV between the positive erase voltage VYP and the positive neutralization voltage DVPP constant advantageously allows the regulation of the positive voltages VYP, DVPP to be aggregated at least on the charge pump stage common to their generation.

[0131] Therefore, in the above reference Figure 4 and 5 In both examples described, the method includes increasing the level of the positive erase voltage VYP above the breakdown voltage HVmax in order to continue increasing the amplitude of the erase stimulus to limit the drift of the thresholds of the aged memory cells, thereby allowing the overall endurance of the memory to increase well beyond the wear threshold AGplf.

[0132] Figure 6 The above reference is shown in a comprehensive and top view Figures 1 to 5 An advantageous exemplary embodiment of the memory NVM described herein. Figure 6 As shown, the control circuit arrangement comprises in particular a distribution circuit NISOVGEN.

[0133] Well PW1 accommodates memory cells in a memory array PM, which are generally arranged in an array of rows and columns. Specifically, control gate lines CGLi-CGLi+k other than word lines WL extend row by row in the memory array, while bit lines BL and control gate decoding lines sent to control gate switching circuits CGSW extend column by column in the memory array PM.

[0134] The well PW1 accommodates, in addition to the transistor T2 of the grounding device CLAMP of the bit line BL, the transistor T1 of the column decoder COLPASS.

[0135] The semiconductor well PW1 housing the memory cells is isolated from the rest of the circuit by a “triple well” type structure, in which a semiconductor isolation region NISO surrounds the well PW1 .

[0136] The semiconductor isolation region NISO has conductivity opposite to that of the well PW1 accommodating the memory array, and is biased with the same voltage as the well PW1 surrounded by it.

[0137] Isolation is produced by mutually opposite bipolar junctions between the well PW1 and the isolation region NISO and between the isolation region NISO and the semiconductor substrate.

[0138] The bias line of the isolation region NISOVL allows obtaining a bias in the isolation region NISO and in the well PW1 accommodating the memory cells.

[0139] The distribution circuit NISOVGEN is configured to transmit a bias voltage that can specifically have the level of the positive erase voltage VYP during the erase cycle. For example, the distribution circuit NISOVGEN includes a boost latch circuit. The boost latch circuit is configured to actuate a latch (e.g., a type with two head-to-tail inverters, the output of one inverter looping to the input of the other inverter) to provide a high output voltage level; and then increase the low reference voltage to positively shift the output to the level of the positive erase voltage VYP.

[0140] Outside of the erase cycle, the bias line of the isolation region NISOVL is brought to the ground reference GND, specifically through a reset transistor RSTGND as described below.

[0141] The conducting terminal of the transistor T2 of the grounding device CLAMP for the bit line BL is coupled on the one hand to the bit line BL of the memory array PM and on the other hand to the bias line of the isolation area NISOVL. The transistor T2 of the grounding device CLAMP is used to carry the unused bit line BL at the ground potential GND present on the bias line of the isolation area NISOVL or at the high impedance HZ in order to put the bit line BL at a floating potential.

[0142] A conducting terminal of the transistor T1 of the column decoder COLPASS is coupled on the one hand to the bit line BL of the memory array PM and on the other hand to devices of the peripheral circuit PRPH.

[0143] The peripheral circuit PRPH of the memory NVM specifically includes a programming and direct memory access circuit PRGDMA and a read circuit RDAMP.

[0144] The programming and direct memory access circuit PRGDMA is specifically used during the programming cycle to selectively bias the decoded bit line BL. The read circuit RDAMP is configured to detect a voltage or current change on the bit line BL representing the state of the memory cell, the state transistor of the memory cell is also controlled at the read voltage. The read circuit RDAMP is capable of reading the memory cell in a margin mode.

[0145] The peripheral circuits of PRPH devices are usually not capable of supporting more than the specific reference Figure 4 and Figure 5 The voltage described by the maximum level HVmax.

[0146] However, in the bit line BL maintaining the floating potential during the erase cycle, the potential may rise to the level of the positive erase voltage VYP closest to the bipolar junction threshold. As a result, the voltage present in the bit line BL during the erase cycle may rise to a level exceeding the breakdown level of the peripheral circuit PRPH.

[0147] Therefore, a buffer semiconductor well PW2 accommodating buffer transistors TBF1, TBF2, TBF3 of the same conductivity type as the well PW1 of the memory array PM is advantageously provided.

[0148] The buffer transistors TBF1 , TBF2 are configured to protect the peripheral circuit PRPH from possible high values ​​of the positive erase voltage VYP on the bit line BL.

[0149] More specifically, on the one hand, the bit line BL is coupled to the peripheral circuit PRPH through the conductive terminals of the buffer transistors TBF1, TBF2, TBF3. Specifically, the components PRGDMA, RDAMP of the peripheral circuit PRPH are coupled to the sources of the buffer transistors TBF1, TBF2, and the bit line BL is coupled to the drains of the buffer transistors TBF1, TBF2.

[0150] On the other hand, the buffer well PW2 and the gates of the buffer transistors TBF1 - TBF3 are biased with a buffer isolation voltage VGNDLFT generated, for example, by a buffer isolation control circuit.

[0151] The source of one of the buffer transistors, referred to as buffer control transistor TBF3, is coupled to the bias line LPW2 of the buffer well PW2. Thus, the bias of the buffer well PW2 is controlled by the gate voltage VGNFLFT of the buffer control transistor TBF3.

[0152] Furthermore, a reset transistor RSTGND is provided in the peripheral circuit PRPH to re-bias the bias lines of the buffer well PW2 and the isolation region NISOVL with the ground reference potential GND outside the write cycle. The reset transistor RSTGND is blocked during the write cycle.

[0153] The buffer isolation voltage VGNDLFT is, for example, at least equal to a difference between the level of the positive erase voltage VYP and the breakdown level HVmax of the control gate switch CGSW.

[0154] Thus, assuming that the gates of buffer transistors TBF1-TBF3 are biased with buffer isolation voltage VGNDLFT, peripheral circuit PRPH is protected from the positive erase voltage VYP (closest to the bipolar junction threshold voltage) present on bit line BL during the erase cycle.

[0155] More specifically, assuming that the buffer transistors TBF1 , TBF2 , TBF3 are controlled with the buffer isolation voltage VGNDLFT at their gates, their sources cannot be biased above this buffer isolation voltage VGNDLFT.

[0156] Furthermore, given that the buffer semiconductor well PW2 is also biased with the buffer isolation voltage VGNDLFT, the buffer transistor will not be damaged by the positive erase voltage VYP of the bit line BL due to the selection of the level of the buffer isolation voltage VGNDLFT specified above.

[0157] Furthermore, the buffered isolation voltage VGNDLFT may advantageously be derived from a distribution circuit NISOVGEN of the positive erase voltage VYP.

[0158] More specifically, to distribute the positive erase voltage VYP (which, recall, may be greater than the breakdown voltage of the bipolar junction of the circuit), the distribution circuit NISOVGEN is, for example, configured to actuate a latch circuit to provide a high output voltage level initially equal to VPP=HVmax.

[0159] The distribution circuit NISOVGEN then increases the low reference voltage GND of the latch by the voltage VGNDLFT in order to shift the output (initially equal to VPP) forward by VGNDLFT until the level VPP+VGNDLFT=VYP of the positive erase voltage VYP is reached without breaking down the junctions of the transistors of the latch.

[0160] In other words, according to an exemplary embodiment and implementation, when the wear threshold AGplf is exceeded, the increase in the level of the positive erase voltage VYP may include offsetting VGNDLFT from the low reference voltage GND in the boost latch NISOVGEN, whose output has been locked at the high reference voltage VPP, so as to offset the level of the output to a level of the positive erase voltage VYP greater than the breakdown level HVmax of the bipolar junction of the control gate switch circuit CGSW.

[0161] Furthermore, both the semiconductor well PW1 accommodating the memory cells and the buffer semiconductor well PW2 are isolated from the rest of the circuit by a “triple well” type structure, advantageously using the same semiconductor isolation region NISO to surround the two wells PW1 , PW2 .

[0162] Isolation is achieved by two reverse bipolar junctions represented by diodes D1 and D2 coupled in series with opposite polarities.

[0163] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer readable medium is provided, which includes a computer program suitable for performing one or more of the above methods or functions. The medium may be a physical storage medium, such as a read-only memory (ROM) chip, or a disk, such as a digital versatile disk (DVD-ROM), a compact disk (CD-ROM), a hard disk, a memory, a network, or a portable media product to be read by an appropriate drive or via an appropriate connection, including one or more bar codes or other related codes encoded as stored on one or more such computer readable media and read by an appropriate reader device.

[0164] In addition, in some embodiments, some or all of these methods and / or functionalities can be implemented or configured in other ways, such as at least partially in firmware and / or hardware, including but not limited to, one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices using RFID technology, and different combinations thereof.

[0165] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0166] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for writing to a non-volatile memory, comprising: erasing memory cells contained in a semiconductor well of the nonvolatile memory, each of the memory cells having a floating gate and a control gate, the erasing comprising biasing the semiconductor well with a first erase voltage, the first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switch circuit of the memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell with a wear threshold, wherein the absolute value of the first erase voltage is increased in response to the comparison indicating that the value of the wear indication is greater than the wear threshold, and wherein the erasing comprises: biasing the control gate of the selected memory cell with a second erase voltage using the control gate switch circuit; and writing one or more of the memory cells, wherein an erase cycle comprises: biasing the control gates of unselected memory cells with a neutralizing voltage via the control gate switching circuit, wherein in response to the value of the wear indication being greater than the wear threshold, the level of the first erase voltage is maintained at a level equal to a tolerance margin taken for the breakdown voltage level of the bipolar junction of the control gate switch circuit, and The memory includes a peripheral circuit and a buffer transistor contained in a buffer semiconductor well; the memory cell is coupled to the peripheral circuit through a conductive terminal of the buffer transistor; and the buffer semiconductor well and the gate of the buffer transistor are biased by a buffer isolation voltage to isolate the peripheral circuit from the first erase voltage.

2. The method of claim 1 , wherein in response to the value of the wear indication being less than the wear threshold, the buffer isolation voltage is set to be at least equal to the difference between the level of the first erase voltage and the breakdown voltage level of the bipolar junction of the control gate switch circuit.

3. The method according to claim 1, wherein a semiconductor isolation region is biased by the first erase voltage, the semiconductor isolation region surrounds the semiconductor well accommodating the memory cell and the buffer semiconductor well, and the memory has a triple well type structure.

4. The method of claim 1, wherein in response to the value of the wear indication being less than the wear threshold, the level of the neutralization voltage is increased in absolute value to maintain a constant initial deviation relative to the level of the first erase voltage.

5. The method of claim 1 , wherein in response to the value of the wear indication being greater than the wear threshold, the level of the neutralization voltage is shifted to an offset neutralization voltage level, and the level of the offset neutralization voltage is increased in absolute value form so as to maintain a constant offset relative to the level of the first erase voltage.

6. The method of claim 5, wherein in response to the value of the wear indication being greater than the wear threshold and the level of the neutralization voltage reaching the breakdown voltage level of the bipolar junction of the control gate switch circuit, the level of the first erase voltage is maintained.

7. A non-volatile memory integrated circuit comprising: memory cells housed in the semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; a control circuit arrangement coupled to the memory cell, wherein the control circuit arrangement in operation controls reading, writing and erasing of the memory cell, wherein the erasing comprises biasing the semiconductor well with a first erase voltage, the first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switch circuit of the nonvolatile memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell with a wear threshold, wherein the absolute value of the first erase voltage is increased in response to the comparison indicating that the value of the wear indication is greater than the wear threshold, and wherein the control circuit arrangement in operation biases the control gate of a selected memory cell with a second erase voltage using the control gate switch circuit; wherein the control circuit means biases the control gates of unselected memory cells with a neutralizing voltage via the control gate switching circuit during an erase cycle, and wherein when the value indicating wear is greater than the wear threshold, when the level of the first erase voltage is equal to a tolerance margin taken for the breakdown voltage level of the bipolar junction of the control gate switch circuit, the control circuit device maintains the level of the first erase voltage unchanged; as well as a peripheral circuit, and a buffer transistor housed in a buffer semiconductor well, wherein the memory cell is coupled to the peripheral circuit through a conductive terminal of the buffer transistor, and the control circuit means is operable to bias the buffer semiconductor well and a gate of the buffer transistor with a buffer isolation voltage to isolate the peripheral circuit from the first erase voltage.

8. An integrated circuit according to claim 7, wherein in operation, when the value of the wear indication is greater than the wear threshold, the control circuit device generates the buffered isolation voltage, which is at least equal to the difference between the level of the first erase voltage and the breakdown voltage level of the bipolar junction of the control gate switch circuit.

9. An integrated circuit according to claim 7, wherein the semiconductor well accommodating the memory cell is surrounded by a semiconductor isolation region in a triple-well structure, the buffer semiconductor well is surrounded by the semiconductor isolation region, and the control circuit device biases the semiconductor isolation region with the first erase voltage during operation.

10. The integrated circuit of claim 7, wherein during the erase cycle, when the value indicative of wear is less than the wear threshold, the control circuit device sets the level of the neutralization voltage in absolute value form to maintain a constant initial deviation relative to the level of the first erase voltage.

11. An integrated circuit according to claim 7, wherein during the erase cycle, when the value indicating wear is greater than the wear threshold, the control circuit device is operable to shift the level of the neutralization voltage to an offset neutralization voltage level and increase the level of the offset neutralization voltage in absolute value form so as to keep the offset constant relative to the level of the first erase voltage.

12. An integrated circuit according to claim 11, wherein when the value indicating wear is greater than the wear threshold, when the level of the neutralization voltage reaches the breakdown voltage level of the bipolar junction of the control gate switch circuit, the control circuit device maintains the level of the first erase voltage unchanged.

13. An electronic system comprising: one or more processing cores; as well as A non-volatile memory coupled to the one or more processing cores, the non-volatile memory comprising: memory cells housed in the semiconductor well, each memory cell including a state transistor having a floating gate and a control gate; and a control circuit arrangement that, in operation, controls reading, writing, and erasing of the memory cell, wherein the erasing includes biasing the semiconductor well with a first erase voltage, the first erase voltage having an absolute value greater than a breakdown voltage level of a bipolar junction of a control gate switch circuit of the nonvolatile memory, the absolute value of the first erase voltage being based on a comparison of a value of a wear indication of the memory cell with a wear threshold, wherein the absolute value of the first erase voltage is increased in response to the comparison indicating that the value of the wear indication is greater than the wear threshold, and wherein the control circuit arrangement, in operation, biases the control gate of a selected memory cell with a second erase voltage using the control gate switch circuit, wherein the control circuit means biases the control gates of unselected memory cells with a neutralizing voltage via the control gate switching circuit during an erase cycle, and wherein when the value indicating wear is greater than the wear threshold, the control circuit device maintains the level of the first erase voltage unchanged when the level of the first erase voltage is equal to a tolerance margin taken for the breakdown voltage level of the bipolar junction of the control gate switch circuit; and a peripheral circuit, and a buffer transistor housed in a buffer semiconductor well, wherein the memory cell is coupled to the peripheral circuit through a conductive terminal of the buffer transistor, and the control circuit means is operable to bias the buffer semiconductor well and a gate of the buffer transistor with a buffer isolation voltage to isolate the peripheral circuit from the first erase voltage.

14. The electronic system of claim 13, comprising an integrated circuit including the non-volatile memory.

15. The electronic system of claim 14, wherein the integrated circuit comprises the one or more processing cores.

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