Super junction semiconductor device and method for manufacturing super junction semiconductor device

Abstract

The present application provides a super junction semiconductor device and a manufacturing method thereof, which can easily form an SJ structure and reduce cost. The manufacturing method of a semiconductor device having an active region (30) for current flow and a termination structure (40) includes first to eighth processes. The first process forms a first semiconductor layer (2) of a first conductivity type on a front surface of a semiconductor substrate (1) of the first conductivity type. The second process forms a first trench. The third process forms a second semiconductor layer (27) of the first conductivity type having a lower impurity concentration than the first semiconductor layer (2) on a surface of the first semiconductor layer (2) and in the first trench. The fourth process forms a parallel pn structure (20). The fifth process forms a second trench (18B). The sixth process forms a second semiconductor region (5) of a second conductivity type. The seventh process forms a gate insulating film (7) and a gate electrode (8). The eighth process forms a first semiconductor region (6) of the first conductivity type.

Description

TECHNICAL FIELD

[0001] The present application relates to a super junction semiconductor device and a manufacturing method of a super junction semiconductor device. BACKGROUND

[0002] The electrification of automobiles typified by electric vehicles and hybrid vehicles is increasing, and in order to reduce power consumption, there is a stronger demand for low loss (low on-state resistance) of power semiconductors. In order to achieve low on-state resistance at a low withstand voltage level, trench gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) have an advantage. Furthermore, in terms of reducing the on-state resistance of trench gate MOSFETs, a super junction (SJ) structure is effective. The super junction structure includes a parallel pn region in which n-type column regions and p-type column regions are alternately and repeatedly arranged in a direction parallel to the main surface of a semiconductor substrate. As a method of forming the parallel pn region, a multi-stage epitaxial method and a trench filling method are known.

[0003] In the multi-stage epitaxial method, the parallel pn region is formed by the following procedures. First, an epitaxial layer is formed on the main surface of the semiconductor substrate. Next, impurities for forming n-type regions and p-type regions are ion implanted in the epitaxial layer. Thereafter, epitaxial layer formation and ion implantation are alternately and repeatedly performed so that a predetermined thickness of the parallel pn region corresponding to the withstand voltage of the super junction semiconductor device can be obtained. Thereafter, by performing heat treatment, the n-type regions and the p-type regions are respectively joined in the depth direction, and the parallel pn region is formed. (For example, refer to Patent Document 1 below).

[0004] In the trench filling method, the parallel pn region is formed by the following procedures. First, an n-type epitaxial layer is formed on the main surface of the semiconductor substrate. Next, a trench for forming a p-type column region is formed in the n-type epitaxial layer. The region where the trench is not formed becomes an n-type column region. The depth of the trench is set to a depth at which a predetermined thickness of the parallel pn region corresponding to the withstand voltage of the super junction semiconductor device can be obtained. Thereafter, by filling the inside of the trench with a p-type epitaxial layer, the parallel pn region is formed. (For example, refer to Patent Documents 1 and 2 below).

[0005] PRIOR ART DOCUMENTS

[0006] PATENT DOCUMENTS

[0007] Patent Document 1: Japanese Patent Application Publication No. 2016-21547

[0008] Patent Document 2: Japanese Patent Application Publication No. 2004-241768 SUMMARY

[0009] Technical problem

[0010] However, in the multi-stage epitaxial method, since the formation of a mask based on a photolithography technique and ion implantation are repeated in each epitaxial growth, the possibility of a change in characteristics due to size and / or composition non-uniformity increases. Furthermore, since mutual diffusion of the pn regions occurs in the thermal history of each epitaxial growth, it is possible that concentration compensation occurs in the adjacent n-type and p-type pillar regions, thereby increasing the on-state resistance. In addition, the process is complex, the preparation time is long, and the manufacturing cost is high.

[0011] In addition, in the trench fill method, after the p-type epitaxial layer formed on the surface of the n-type epitaxial layer that becomes the n-type pillar region is removed by a CMP (Chemical Mechanical Polisher) process when filling the trench with the p-type epitaxial layer, the n-type epitaxial layer is formed on the surface. The reason for removing the p-type epitaxial layer is because if the p-type layer is present in the edge termination region, the withstand voltage cannot be maintained. Therefore, with respect to the trench fill method, a CMP device is required, and it is possible that a change in characteristics occurs due to non-uniformity in the polishing amount in the CMP process. In addition, since the non-uniformity in impurity concentration is greater in the epitaxial growth of the p-type than in the epitaxial growth of the n-type, control of the impurity concentration is required. Furthermore, since the junction between the high-concentration p-type epitaxial layer and the n-type drift layer, the gradient of the impurity concentration is large, and it is possible that the depletion layer is difficult to expand, and the withstand voltage decreases.

[0012] To solve the problems of the conventional technology described above, the object of the present application is to provide a super junction semiconductor device in which an SJ structure can be easily formed, and a manufacturing method of a super junction semiconductor device in which the cost can be reduced.

[0013] Technical solution

[0014] To solve the above problems, and achieve the object of the present application, the manufacturing method of a super junction semiconductor device of the present application is a manufacturing method of a super junction semiconductor device having an active region through which a current flows and a termination structure portion disposed outside the active region and formed with a voltage resistance structure surrounding the periphery of the active region. First, a first semiconductor layer of a first conductivity type having a lower impurity concentration than that of a semiconductor substrate is formed on the front surface of the semiconductor substrate of the first conductivity type in a first step. Next, a second step of forming a first trench from the surface of the first semiconductor layer is performed. Next, a third step of forming a second semiconductor layer of the first conductivity type having a lower impurity concentration than that of the first semiconductor layer on the surface of the first semiconductor layer and in the first trench is performed. Next, a fourth step of injecting an impurity of a second conductivity type into the second semiconductor layer is performed, thereby forming a well region of the second conductivity type inside the second semiconductor layer and forming a parallel pn structure in which a first pillar of the first conductivity type and a second pillar of the second conductivity type are alternately arranged in a direction parallel to the front surface, the upper surface of the second pillar being in contact with the bottom surface of the well region. Next, a fifth step of forming a second trench that penetrates the second semiconductor layer and reaches the first pillar is performed. Next, a sixth step of forming a second semiconductor region of the second conductivity type on the surface of the parallel pn structure of the active region is performed. Next, a seventh step of forming a gate insulating film and a gate electrode inside the second trench is performed. Next, an eighth step of selectively forming a first semiconductor region of the first conductivity type on the surface layer of the second semiconductor region of the active region is performed.

[0015] Further, in the above-mentioned application, in the sixth step of the manufacturing method of a super junction semiconductor device of the present application, the bottom surface of the second semiconductor region is formed shallower than the bottom surface of the well region.

[0016] Further, in the above-mentioned application, in the sixth step of the manufacturing method of a super junction semiconductor device of the present application, the impurity concentration of the well region is formed lower than the impurity concentration of the second semiconductor region.

[0017] Further, in the above-mentioned application, in the fourth step of the manufacturing method of a super junction semiconductor device of the present application, the impurity of the second conductivity type is injected into the second semiconductor layer inside the first trench.

[0018] Further, in the above-mentioned application, in the fourth step of the manufacturing method of a super junction semiconductor device of the present application, the impurity of the second conductivity type is injected into the surface layer of the second semiconductor layer on the surface of the first semiconductor layer.

[0019] Further, the manufacturing method of the super junction semiconductor device of the present application, in the above-mentioned application, forms the second column in the terminal structure portion in the fourth process.

[0020] Further, the manufacturing method of the super junction semiconductor device of the present application, in the above-mentioned application, performs the sixth process before the fifth process.

[0021] Further, the manufacturing method of the super junction semiconductor device of the present application, in the above-mentioned application, implants the second semiconductor layer in the first trench as the second conductive type in the fourth process.

[0022] To solve the above-mentioned problems, to achieve the object of the present application, the super junction semiconductor device of the present application has the following features. The super junction semiconductor device has an active region through which a current flows and a terminal structure portion, the terminal structure portion is disposed outside the active region, and a withstand voltage structure surrounding the periphery of the active region is formed. On the front surface of a semiconductor substrate of a first conductive type, a first semiconductor region of the first conductive type having a lower impurity concentration than the semiconductor substrate is provided. Inside the first semiconductor layer, a parallel pn structure in which a first column of the first conductive type and a second column of a second conductive type are alternately arranged in a direction parallel to the front surface is provided. On the surface layer of the parallel pn structure of the active region, a second semiconductor region of the second conductive type is provided. On the surface layer of the second semiconductor region of the active region, a first semiconductor region of the first conductive type is selectively provided. A second trench that penetrates the first semiconductor region and the second semiconductor region and reaches the first column is provided. Inside the second trench, a gate electrode is provided through a gate insulating film. Inside the first semiconductor layer, a well region of the second conductive type is provided, the lower surface of the well region is in contact with the upper surface of the second column, the bottom surface of the well region is deeper than the bottom surface of the second semiconductor region, and the width of the upper surface of the well region is wider than the width of the second column.

[0023] Further, the super junction semiconductor device of the present application, in the above-mentioned application, the impurity concentration of the well region is lower than the impurity concentration of the second semiconductor region.

[0024] Further, the super junction semiconductor device of the present application, in the above-mentioned application, the parallel pn structure is also provided in the terminal structure portion.

[0025] Further, the super junction semiconductor device of the present application, in the above-mentioned application, the repeating pitch of the parallel pn structure of the terminal structure portion is narrower than the repeating pitch of the parallel pn structure of the active region.

[0026] In addition, in the super junction semiconductor device of the present application, in the above-mentioned application, a second semiconductor layer of a first conductivity type having a lower impurity concentration than the first semiconductor layer is provided in a surface layer on the side opposite to the semiconductor substrate side of the termination structure portion.

[0027] In addition, in the super junction semiconductor device of the present application, in the above-mentioned application, the well region and the second semiconductor region are in contact with the side wall of the second trench.

[0028] According to the above-mentioned application, in the edge termination region, an n - type epitaxial layer (second semiconductor layer of a first conductivity type) is provided in the n - type epitaxial layer, and a field oxide film is provided on the surface of the n - type epitaxial layer. By the n - type epitaxial layer, the depletion layer extending from the pn junction between the n -- type epitaxial layer and the p - type low surface field region is expanded to the n - type epitaxial layer, whereby the withstand voltage of the SJ-MOSFET can be increased. In addition, since the impurity concentration of the n

[0029] In addition, in the region to be a p-type pillar region, a p-type pillar trench is formed, and an n - type epitaxial layer having a lower impurity concentration than the n-type drift layer to be an n-type pillar region is deposited, and a p-type pillar region 4 and a p-type well region are formed by ion implantation and diffusion of p-type impurities from the surface of the n - type epitaxial layer. Thus, since the p-type pillar region can be formed without depositing a p-type epitaxial layer, it is not necessary to remove the p-type epitaxial layer in the edge termination region. In addition, the surface portion after filling the p-type pillar trench does not need to be planarized by a CMP device or the like. Thus, the SJ structure can be easily formed, and the manufacturing cost can be reduced.

[0030] Technical Effects

[0031] According to the super junction semiconductor device and the manufacturing method of the super junction semiconductor device of the present application, the following effects can be obtained: the SJ structure can be easily formed, and the cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a cross-sectional view showing the structure of the SJ-MOSFET of the embodiment.

[0033] Figure 2A is a cross-sectional view showing another structure of the SJ-MOSFET of the embodiment.

[0034] Figure 2B is a sectional view showing another structure of the SJ-MOSFET according to the embodiment.

[0035] Figure 2C is a sectional view showing another structure of the SJ-MOSFET according to the embodiment.

[0036] Figure 2D is a sectional view showing another structure of the SJ-MOSFET according to the embodiment.

[0037] Figure 3 is a plan view showing a structure of the SJ-MOSFET according to the embodiment.

[0038] Figure 4 is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (1).

[0039] Figure 5 is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (2).

[0040] Figure 6 is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (3).

[0041] Figure 7 is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (4).

[0042] Figure 8 is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (5).

[0043] Figure 9A is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (6).

[0044] Figure 9B is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (7).

[0045] Figure 9C is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (8).

[0046] Figure 10A is a sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET according to the embodiment (9).

[0047] Figure 10B is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 10).

[0048] Figure 10C is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 11).

[0049] Figure 11 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 12).

[0050] Figure 12 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 13).

[0051] Figure 13 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 14).

[0052] Figure 14 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 15).

[0053] Figure 15 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 16).

[0054] Figure 16 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 17).

[0055] Figure 17 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 18).

[0056] Figure 18 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 19).

[0057] Figure 19 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 20).

[0058] Figure 2A is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 21).

[0059] Figure 2C is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 22).

[0060] Figure 2A is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 23).

[0061] Figure 4-17 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 24).

[0062] Figure 18 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 25).

[0063] Figure 20 is a cross-sectional view showing a state in a manufacturing process of the first manufacturing method of the SJ-MOSFET based on the embodiment (its 26).

[0064] Figure 17 is a cross-sectional view showing a state in a manufacturing process of the second manufacturing method of the SJ-MOSFET based on the embodiment (its 1).

[0065] Figure 20 is a cross-sectional view showing a state in a manufacturing process of the second manufacturing method of the SJ-MOSFET based on the embodiment (its 2).

[0066] Figure 2C is a cross-sectional view showing a state in a manufacturing process of the second manufacturing method of the SJ-MOSFET based on the embodiment (its 3).

[0067] Figure 21 is a cross-sectional view showing a state in a manufacturing process of the second manufacturing method of the SJ-MOSFET based on the embodiment (its 4).

[0068] Figure 21 is a cross-sectional view showing a state in a manufacturing process of the second manufacturing method of the SJ-MOSFET based on the embodiment (its 5).

[0069] Figure 2C is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (its 1).

[0070] Figure 2C is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (its 2).

[0071] Figure 2A is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (3).

[0072] Figure 4-17 is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (4).

[0073] Figure 18 is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (5).

[0074] Figure 22-25 is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (6).

[0075] Figure 17 is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (7).

[0076] Figure 22 is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (8).

[0077] Figure 23 is a cross-sectional view showing a state in a manufacturing process of the third manufacturing method of the SJ-MOSFET based on the embodiment (9).

[0078] Symbol explanation

[0079] 1...n + semiconductor substrate, 2...n-type drift layer, 3, 3B...n-type pillar region, 4, 4A, 4B...p-type pillar region, 5, 5A...p-type base region, 6...n + type source region, 7...gate insulating film, 8...gate electrode, 9...interlayer insulating film, 10...source electrode, 11...back surface electrode, 12...p -- type surface electric field reduction region, 13...field oxide film, 14, 14A...p ++ type contact region, 18A, 18B...trench, 19...contact plug, 20, 20B...parallel pn region, 21, 65...ion implantation mask, 22...ion implantation, 23...oxide film, 24...resist mask, 25A, 25B...p-type pillar trench, 27...n -n-type epitaxial layer, 28…oxide film, 29…field plate, 30…active region, 40…edge termination region, 50…SJ-MOSFET, 61…metal gate runner, 62…channel stopper, 63, 63A, 63B…p-type well region, 64A, 64B, 64C, 64D, 64E, 64F…contact hole, 66A, 66B, 66C…insulating film, 67A, 67B, 67C, 67D, 67E, 67F…recess, 90, 91-1, 91-2, 92, 93…implantation region, 100…upper surface, W1, W2, W3…width, T1…thickness, D1, D2…interval DETAILED DESCRIPTION

[0080] A preferred embodiment of the super junction semiconductor device and the manufacturing method of the super junction semiconductor device of the present application will be described in detail below with reference to the accompanying drawings. In the present specification and the accompanying drawings, as for a layer or a region with n or p, it means that electrons or holes are majority carriers, respectively. In addition, + and - with n or p mean that the impurity concentration is higher and lower than that of a layer or a region without + and -, respectively. In the case where the same n or p with + or - is indicated, it means that the concentration is similar, and the concentration is not necessarily the same. It should be noted that, in the description of the embodiment and the accompanying drawings below, the same symbol is indicated for the same configuration, and the repeated description is omitted.

[0081] (Embodiment)

[0082] The super junction semiconductor device of the present application will be described taking the SJ-MOSFET as an example. Figure 2C is a cross-sectional view showing the structure of the SJ-MOSFET of the embodiment.

[0083] Figure 24 The SJ-MOSFET (super junction semiconductor device) 50 shown is a SJ-MOSFET 50 provided with a MOS (Metal Oxide Semiconductor) gate on the front surface (the surface on the side of the p-type base region 5 described later) side of a semiconductor substrate (silicon substrate: semiconductor chip) containing silicon (Si). The SJ-MOSFET 50 is provided with an active region 30 and an edge termination region 40 surrounding the periphery of the active region 30. The active region 30 is a region in which current flows in an on state. The edge termination region 40 contains a drift region and a withstand voltage maintaining region that mitigates the electric field on the front surface side of the semiconductor substrate and maintains the withstand voltage. It should be noted that the boundary between the active region 30 and the edge termination region 40 is provided with an n-type source region 6 described later on only one side of the center of the trench 18B of the p-type source region 6. + The p-type source region 6 is provided with a trench 18B in the center of the p-type source region 6. Figure 25In the active region 30, only one unit cell (functional unit of the element) is shown, and the drawings of other unit cells adjacent thereto are omitted. The unit cell indicates from the center of the trench 18B up to the center of the adjacent trench 18B.

[0084] n + The n-type semiconductor substrate (semiconductor substrate of the first conductivity type) 1 is a single-crystal silicon substrate doped with, for example, arsenic (As) or phosphorus (P). In the n + On the n-type semiconductor substrate 1, an n-type drift layer (first semiconductor layer of the first conductivity type) 2 is provided. The n-type drift layer 2 is a low-concentration n-type layer doped with, for example, phosphorus, and has a lower impurity concentration than the n + The n-type semiconductor substrate 1 is a single-crystal silicon substrate doped with, for example, arsenic (As) or phosphorus (P). In the n + The n-type semiconductor substrate 1 and the n-type drift layer 2 are collectively referred to as a semiconductor base. In the n + Between the n-type semiconductor substrate 1 and the n-type drift layer 2, an n-type buffer layer (not shown) can be provided at an impurity concentration lower than that of the n-type drift layer 2. The n-type buffer layer is a low-concentration n-type layer doped with, for example, phosphorus. A MOS gate structure (element structure) is formed on the front surface side of the semiconductor base. In addition, a back electrode 11 that becomes a drain electrode is provided on the back surface of the semiconductor base.

[0085] In the active region 30 of the SJ-MOSFET 50, a parallel pn region 20 in which n-type pillar regions 3 and p-type pillar regions 4 are alternately and repeatedly arranged is provided. In the edge termination region 40, a parallel pn region 20B described later can also be provided.

[0086] In the n Figure 25 In the n - The p-type well region 63 of the active region 30 is provided so as not to reach the surface of the n + The p-type well region 63 of the active region 30 is provided so as not to reach the surface of the n - The surface of the n - The surface of the n

[0087] Because the width of the upper surface of the p-type well region 63 is wider than the width of the p-type pillar region 4, the reverse withstand voltage (BVDSS: drain-source breakdown voltage) can be improved. As described later, the planar shapes of the n-type pillar region 3 and the p-type pillar region 4 of the active region 30 and the edge termination region 40 are, for example, striped shapes. When the planar shape of the p-type pillar region 4 is striped, the planar shape of the p-type well region 63 is also striped.

[0088] The impurity concentration in n-type column region 3 is lower than that in n-type column region 3. + The impurity concentration of the p-type semiconductor substrate 1. The impurity concentration of the p-type pillar region 4 can be equal to the impurity concentration of the p-type well region 63. In addition, the impurity concentration of the n-type pillar region 3 can also be equal to the impurity concentration of the p-type pillar region 4.

[0089] A p-type base region (a second semiconductor region of a second conductivity type) 5 is selectively disposed on the upper surface 100 side of the active region 30 (above the first main surface of the semiconductor substrate). The p-type base region 5 is configured to overlap with the p-type well region 63. The bottom surface of the p-type well region 63 is... Figure 2C It is located at a depth greater than the bottom surface of the p-type base region 5 in the y-direction (depth direction). The impurity concentration of the p-type base region 5 is higher than that of the p-type well region 63. In addition, the impurity concentration of the p-type base region 5 is higher than that of the p-type pillar region 4.

[0090] An n-type base region 5 is selectively disposed on the surface side of the p-type base region 5 in the active region 30. + Source region (first semiconductor region of the first conductivity type) 6. A region corresponding to the n-type base region 5 can be selectively disposed on the surface side of the p-type base region 5 of the active region 30. + p in phase 6 of the source region ++ Type contact area 14.

[0091] A trench structure is formed in the active region 30 and at the boundary between the active region 30 and the edge terminal region 40. Specifically, the trench 18B (the second trench) extends from the upper surface 100 through the p-type base region 5, the p-type base region 5A (described later), and the n-type base region 40. + The source region 6 reaches the n-type column region 3.

[0092] p-type base region 5 and n + The source region 6 is in contact with the sidewall of the trench 18B disposed in the active region 30. Additionally, at the sidewall of the trench 18B located at the boundary between the active region 30 and the edge terminal region 40, the p-type base region 5 and the n-type base region 6 are... + The source region 6 is connected to the active region 30 side of the sidewall of the trench 18B, and the p-type base region 5A, described later, is connected to the edge terminal region 40 side of the sidewall of the trench 18B. It should be noted that the trench 18B is not provided in the edge terminal region 40.

[0093] The trench 18B of the active region 30 is provided between the selectively provided p-type base regions 5, and the trench 18B of the boundary between the active region 30 and the edge termination region 40 is provided between the p-type base region 5 and the p-type base region 5A. The planar shape of the trench 18B is, for example, a stripe shape extending in the depth direction (z direction) of Figure 4-21 .

[0094] With regard to the trench 18B, a gate insulating film 7 is formed along the inner wall of the trench 18B. A gate electrode 8 is provided inside the gate insulating film 7 within the trench 18B. The gate electrode 8 is insulated from the n-type pillar region 3 (n-type drift layer 2) and the p-type base region 5 by the gate insulating film 7. A part of the gate electrode 8 can be provided as a gate wiring (not shown) that protrudes from above the trench 18B (the side on which the source electrode 10 described later is provided) toward the source electrode 10 side. The gate insulating film 7 is provided at the lower portion of the gate wiring. An interlayer insulating film 9 is provided at the upper portion of the gate wiring.

[0095] The interlayer insulating film 9 is provided on the upper surface 100 so as to cover the upper surface of the gate electrode 8 that is buried into the trench 18B. An insulating film (not shown) is provided between the gate electrode 8 and the interlayer insulating film 9 (the boundary of the interlayer insulating film 9 that covers the gate insulating film 7 formed along the inner wall of the trench 18B and the upper portion of the gate electrode 8, and the boundary of the insulating film provided between the gate electrode 8 and the interlayer insulating film 9 are not shown). In the interlayer insulating film 9 that covers the upper surface of the gate electrode 8 buried into the trench 18B of the active region 30, a contact hole 64A is provided between it and the adjacent trench 18B, and the n + -type source region 6 and the p ++ -type contact region 14 are exposed. Similarly, in the interlayer insulating film 9 that covers the upper surface of the gate electrode 8 buried into the above-described adjacent trench 18B of the active region 30 and the upper surface of the gate electrode 8 of the trench 18B provided at the boundary between the active region 30 and the edge termination region 40, a contact hole 64A is also provided, and the n + -type source region 6 and the p ++ -type contact region 14 are exposed. Hereafter, the description of the insulating film (not shown) provided between the gate electrode 8 and the interlayer insulating film 9 is omitted.

[0096] The source electrode 10 is provided on the upper surface of the interlayer insulating film 9, and is connected to the n + -type source region 6 and the p ++The contact hole 64A is formed in the interlayer insulating film 9 and an insulating film (not shown) provided on the lower surface of the interlayer insulating film 9. Subsequently, the description of the insulating film (not shown) provided on the lower surface of the interlayer insulating film 9 is omitted. The source electrode 10 is electrically insulated from the gate electrode 8 by the interlayer insulating film 9. Between the source electrode 10 and the interlayer insulating film 9, a barrier metal (not shown) that prevents diffusion of metal atoms from the source electrode 10 toward the gate electrode 8 side, for example, can be provided. On the source electrode 10, a protective film (not shown) such as a passivation film including polyimide, for example, is selectively provided. In an opening portion of the protective film provided on the source electrode 10, a region in which the source electrode 10 is exposed becomes a source pad region (not shown).

[0097] Further, in the edge terminal region 40 that maintains the withstand voltage, a p-type pillar region 4A having the same width as the p-type pillar region 4 of the active region 30 is provided on the side closest to the active region 30. The p-type pillar region 4 and the p-type pillar region 4A can be the same depth in the y direction (depth direction). A p-type well region 63A is provided on the p-type pillar region 4A. The upper surface of the p-type pillar region 4A is in contact with the bottom surface of the p-type well region 63A. Note that the impurity concentration of the p-type pillar region 4 can be the same as the impurity concentration of the p-type pillar region 4A, and the impurity concentration of the p-type well region 63 can be the same as the impurity concentration of the p-type well region 63A. Figure 26-30 The p-type base region 5A is provided so as to overlap the p-type well region 63A and is in contact with the side wall of the trench 18B provided at the boundary between the active region 30 and the edge terminal region 40. The bottom surface of the p-type well region 63A is provided at a position deeper than the bottom surface of the p-type base region 5A in the y direction (depth direction).

[0098] Figure 2D The p-type base region 5A can be formed at the same depth as the p-type base region 5 of the active region 30 in the y direction (depth direction). Further, the p-type well region 63A can be formed at the same depth as the p-type well region 63 of the active region 30 in the y direction (depth direction). Figure 26-30 Figure 4-8 The p-type well region 63A can be formed at the same depth as the p-type well region 63 of the active region 30 in the y direction (depth direction).

[0099] The impurity concentration of the p-type base region 5A is the same as the impurity concentration of the p-type base region 5. Further, the impurity concentration of the p-type base region 5A is higher than the impurity concentration of the p-type well region 63A. On the surface side of the p-type base region 5A, a p-type contact region 14A having an impurity concentration higher than the impurity concentration of the p-type base region 5A can be selectively provided. ++

[0100] ​​​A parallel pn region 20B is provided on the outer periphery of the SJ-MOSFET 50, relative to the p-type pillar region 4A of the edge termination region 40. The parallel pn region 20B consists of alternating n-type pillar regions 3B and p-type pillar regions 4B. The direction in which the n-type pillar regions 3B and p-type pillar regions 4B are alternately arranged is the same as the direction in which the n-type pillar regions 3 and p-type pillar regions 4 are alternately arranged in the active region 30.

[0101] Compared to the parallel pn region 20 of the active region 30, the sum of the widths of adjacent n-type pillars and p-type pillars in the parallel pn region 20B of the edge termination region 40 is smaller. Here, the sum of the widths of adjacent n-type pillars and p-type pillars is set as the repeating pitch. Therefore, the widths of the n-type pillar region 3B and p-type pillar region 4B of the edge termination region 40 are smaller than the widths of the n-type pillar region 3 and p-type pillar region 4 of the active region 30. As a result, the depletion layer in the edge termination region 40 becomes easier to expand, enabling the withstand voltage of the edge termination region 40 to be higher than that of the active region 30.

[0102] p is set in the edge terminal area 40 -- The surface electric field is reduced in region 12 p. -- The type-reduced surface electric field region 12 extends from the boundary between the active region 30 and the edge terminal region 40 to the field plate 29 (described later) and below the field oxide film 13. -- The planar shape of the region 12 that reduces the surface electric field is annular.

[0103] p -- Type 12 reduces surface electric field region 12 Figure 9A It is set deeper than the p-type base region 5A in the y-direction (depth direction). -- The impurity concentration in the surface electric field reduction region 12 is lower than that in the p-type well region 63A. Therefore, the impurity concentration in the p-type well region 63A, the p-type base region 5A, and the p-type base region 63A are all lower than that in the p-type well region 63A. ++ Type contact area 14A is set at p -- The surface electric field is reduced within region 12. -- The type of reduced surface electric field region 12 is connected to the trench 18B disposed at the boundary between the active region 30 and the edge terminal region 40.

[0104] via p -- The reduced surface electric field region 12 can alleviate the electric field concentration at the outer peripheral end of the SJ-MOSFET 50 in the p-type base region 5A, thereby improving the breakdown voltage of the edge termination region 40. In the parallel pn structure 20B of the edge termination region 40, a portion of the upper surface of the n-type pillar region 3B and the p-type pillar region 4B on the active region 30 side is connected to the p-type base region 4A. -- The bottom surface of the type-reduced surface electric field region 12 is connected.

[0105] The upper surface of the p-type pillar region 4B of the parallel pn region 20B located on the outermost periphery of the SJ-MOSFET 50 is in contact with the bottom surface of the p-type well region 63B located on the outermost periphery of the SJ-MOSFET 50. The p-type well region 63B located on the outermost periphery of the SJ-MOSFET 50 and the p-type pillar region 4B are in contact with the bottom surface of the p-type well region 63B located on the outermost periphery of the SJ-MOSFET 50. -- Between the regions 12 where the surface electric field is reduced, Figure 8 The x-direction is set with n (described later). - Type epitaxial layer 27.

[0106] Additionally, in the edge terminal region 40, an n-type drift layer 2 (semiconductor substrate) is disposed on the surface of the n-type drift layer 2. - Type epitaxial layer (second semiconductor layer of first conductivity type) 27. As described later, n - The n-type epitaxial layer 27 is formed over the entire surface of the n-type drift layer 2. - The surface layer of the epitaxial layer 27 is provided with p-type well regions 63, 63A, 63B, p-type base regions 5, 5A, and p-type base regions 63, 63A, 63B ... -- The upper portion of each of the type-reduced surface electric field region 12, and n + Type source region 6 and p ++ Type contact areas 14 and 14A.

[0107] Additionally, n - The impurity concentration of the p-type epitaxial layer 27 is lower than that of the n-type drift layer 2. Therefore, the impurities implanted by ion implantation, after heat treatment following ion implantation, result in a lower impurity concentration in the p-type drift layer compared to the n-type drift layer 2. - Diffusion becomes easier in the p-type epitaxial layer 27 and difficult in the n-type drift layer 2. Therefore, the diffusion of the p-type base region 5, which is achieved through heat treatment after ion implantation, can be easily controlled, and the non-uniformity of the gate threshold voltage VTh can be suppressed.

[0108] exist Figure 9A In the x-direction, from the outer periphery of the SJ-MOSFET 50 to n - p-type epitaxial layer 27, p-type well region 63B and p -- A field oxide film 13 is disposed on the surface of the reduced surface electric field region 12. The field oxide film 13 has a lower surface electric field compared to the upper surface 100. Figure 6 The field oxide film 13 can be set to a deeper position in the y-direction. The field oxide film 13 extends from the end of the active region 30 side of the field oxide film 13 to a portion of the lower surface and is p -- The surface electric field reduction region 12 is covered. A p-type oxide film is disposed on the lower surface of the field oxide film 13. -- Type 12, p-type well region 63B, and n-type surface electric field reduction region - The epitaxial layer 27 is provided with n-type epitaxial layer 27, which extends from the other end of the field oxide film 13 to a portion of the lower surface. -p-type epitaxial layer 27.

[0109] In the p -- The upper surface of the p-type reduction surface field region 12, the p-type well region 63A, and the p-type base region 5A is provided with an insulating film 66A connected to the end portion of the field oxide film 13 on the side of the active region 30, and the n - The upper surface of the p-type epitaxial layer 27 is provided with an insulating film 66B connected to the other end portion of the field oxide film 13. The insulating films 66A, 66B can be formed in the same process as the gate insulating film 7.

[0110] The field plate 29 is provided on the upper surface of the field oxide film 13 and the insulating film 66A connected to the end portion of the field oxide film 13 on the side of the active region 30. The field plate 29 is electrically connected to the gate electrode 8 and also has the function of a gate wiring.

[0111] The channel stopper 62 is provided on the upper surface of the field oxide film 13 and the insulating film 66B connected to the other end portion of the field oxide film 13. Note that the field plate 29 and the channel stopper 62 are separated on the field oxide film 13 and are provided at intervals. The interlayer insulating film 9 is provided so as to cover the field oxide film 13, the field plate 29, and the channel stopper 62. Note that an insulating film (not shown) is provided between the interlayer insulating film 9 and the field plate 29 and the channel stopper 62. Hereinafter, the description of the insulating film (not shown) provided between the interlayer insulating film 9 and the field plate 29 and the channel stopper 62 is omitted.

[0112] A contact hole 64B is provided between the interlayer insulating film 9 provided so as to cover the upper surface of the gate electrode 8 buried in the trench 18B provided at the boundary between the active region 30 and the edge termination region 40 and the interlayer insulating film 9 covering the field plate 29, and the p ++ The p-type contact region 14A is exposed.

[0113] A contact hole 64C is provided in the interlayer insulating film 9 covering the field oxide film 13, the field plate 29, and the channel stopper 62, and the field plate 29 is exposed.

[0114] The source electrode 10 provided on the upper surface of the interlayer insulating film 9 extends from the active region 30 to the upper surface of a portion of the edge termination region 40, and is electrically connected to the p ++ The p-type contact region 14A and the p-type base region 5A are electrically connected.

[0115] The metal gate runner 61 is electrically connected to the field plate 29 via the contact hole 64C formed in the interlayer insulating film 9. The p --The interlayer insulating film 9 of the p-type reduced surface field region 12, the field oxide film 13, the field plate 29, the channel stopper 62, and the edge termination region 40 can be provided in a ring shape at the outer periphery of the SJ-MOSFET 50. Note that the metal gate runner 61 is electrically insulated from the source electrode 10.

[0116] Figure 26 is a cross-sectional view of another structure of the SJ-MOSFET 50 according to the embodiment. Figure 27 With Figure 28 the difference is that the parallel pn region 20B is not provided at a position on the outer periphery side of the SJ-MOSFET 50 compared to the p-type pillar region 4A of the edge termination region 40. In the case where the parallel pn region 20B is not provided, the n - type epitaxial layer 27, the depletion layer extending from the pn junction of the p - type epitaxial layer 27 and the p -- type reduced surface field region 12 extends to the outer periphery side of the SJ-MOSFET 50 of the n-type epitaxial layer 27, whereby the withstand voltage of the SJ-MOSFET 50 can be increased.

[0117] Figure 29 is a cross-sectional view of another structure of the SJ-MOSFET 50 according to the embodiment. Figure 30 With Figure 2D the difference is that the p-type well region 63 that is in contact with the upper surface of the p-type pillar region 4 of the active region 30 and the p-type well region 63A that is in contact with the upper surface of the p-type pillar region 4A of the edge termination region 40 are not provided. In the case where the p-type well region 63 and the p-type well region 63A are not provided, the n Figure 26-30 In the case of the SJ-MOSFET 50 of the present embodiment, the p-type base region 5 is provided on the upper surface of the p-type pillar region 4 of the active region 30. The upper surface of the p-type pillar region 4 of the active region 30 is in contact with the bottom surface of the p-type base region 5. In addition, the p-type base region 5A is provided on the upper surface of the p-type pillar region 4A of the edge termination region 40. The upper surface of the p-type pillar region 4A of the edge termination region 40 is in contact with the bottom surface of the p-type base region 5A. Figure 31-39 The cross-sectional shape of the SJ-MOSFET 50 of the present embodiment is different from that of the SJ-MOSFET 50 of the first embodiment because the positions of the implantation regions for forming the p-type pillar regions 4 are different. Figure 2B The cross-sectional shape of the SJ-MOSFET 50 of the present embodiment is different from that of the SJ-MOSFET 50 of the first embodiment because the positions of the implantation regions for forming the p-type pillar regions 4 are different. Figure 4-8 The SJ-MOSFET 50 shown in the drawing, as described later, has an implantation region 92 formed in the region D2. In the case where the implantation region 92 is not provided, the p Figure 9C The SJ-MOSFET 50 shown in the drawing, as described later, has an implantation region 92 formed in the region D2. In the case where the implantation region 92 is not provided, the p Figure 10CIn this configuration, because p-type well regions 63 and 63A are not provided, there is no region where the current path formed in the n-type drift layer 2 (n-type pillar region 3) is locally narrowed. Due to the conduction voltage generated by the current flowing through the current path, the depletion layer extends from the pn junction of the n-type pillar region 3 and the pn junction of ... Figure 31 In comparison, the on-state resistance (resistance during operation) can be reduced.

[0118] Figure 32 This is a cross-sectional view showing another structure of the SJ-MOSFET 50 in an embodiment. Figure 33 and Figure 34 The difference is that the contact holes 64D, 64E, and 64F formed in the interlayer insulating film 9 have recesses 67A, 67B, and 67C (grooves), and contact plugs 19 are embedded inside the recesses 67A, 67B, and 67C.

[0119] An interlayer insulating film 9 covering the upper surface of the gate electrode 8, which is buried in the trench 18B of the active region 30, has a recess 67A between it and the adjacent trench 18B. The recess 67A is deeper in the y direction than the upper surface 100. + Type source region 6 and p ++ The contact area is in contact with the sidewall of the recess 67A (exposed on the sidewall of the recess 67A). ++ The contact area 14 is in contact with the bottom of the recess 67A (exposed at the bottom of the recess 67A). This recess 67A is a contact hole 64D. It should be noted that an insulating film (not shown) is provided between the gate electrode 8 and the interlayer insulating film 9. Hereinafter, the description of the insulating film (not shown) provided between the gate electrode 8 and the interlayer insulating film 9 will be omitted.

[0120] Similarly, the interlayer insulating film 9 covering the upper surface of the gate electrode 8 that is buried in the adjacent trench 18B of the active region 30 and the upper surface of the gate electrode 8 that is buried in the trench 18B that is located at the boundary between the active region 30 and the edge terminal region 40 is also provided with a recess 67A that is deeper in the y direction than the upper surface 100. + Type source region 6 and p ++ The contact area 14 is in contact with the sidewall of the recess 67A (exposed on the sidewall of the recess 67A). ++ The contact area 14 is in contact with the bottom of the recess 67A (exposed at the bottom of the recess 67A). The recess 67A is a contact hole 64D.

[0121] A recess 67B deeper than the upper surface 100 in the y direction is provided between the interlayer insulating film 9 provided so as to cover the upper surface of the gate electrode 8 of the trench 18B provided at the boundary between the active region 30 and the edge termination region 40 and the interlayer insulating film 9 covering the field plate 29.p ++ The p-type contact region 14A is in contact with (exposed to) the side wall and the bottom of the recess 67B. The recess 67B is the contact hole 64E.

[0122] A recess 67C is provided in the interlayer insulating film 9 covering the field oxide film 13, the field plate 29, and the channel stopper 62. The recess 67C exposes the surface of the field oxide film 13 through the field plate 29. The field plate 29 is in contact with (exposed to) the side wall of the recess 67C. In addition, the recess 67C is also provided with a recess (trench) in the surface of the field oxide film 13, and the field oxide film 13 can be in contact with (exposed to) the side wall of the recess 67C. The field oxide film is in contact with (exposed to) the bottom of the recess 67C. The recess 67C is the contact hole 64F. Note that an insulating film (not shown) is provided between the interlayer insulating film 9 and the field plate 29 and the channel stopper 62. Hereinafter, the insulating film (not shown) provided between the interlayer insulating film 9 and the field plate 29 and the channel stopper 62 will be omitted from the description.

[0123] The contact plug 19 is, for example, a metal film using tungsten (W) having a high burying property as a material. In addition, the contact plug 19 can be provided in the contact holes 64D, 64E, 64F via a barrier metal. The source electrode 10 is electrically connected to the n + The p-type source region 6 and the p ++ The p-type contact region 14 is electrically connected. In addition, the source electrode 10 extends to a part of the edge termination region 40, and is electrically connected to the p ++ The p-type contact region 14A is electrically connected.

[0124] The metal gate runner 61 is electrically connected to the field plate 29 via the contact plug 19 in the contact hole 64F. Note that the source electrode 10 is electrically insulated from the metal gate runner 61.

[0125] In the case of the SJ-MOSFET 50 of the Figure 35 In the case of the SJ-MOSFET 50 of the Figure 36 Similarly, a case where the parallel pn region 20B is not provided at a position on the outer peripheral side of the SJ-MOSFET 50 than the p-type pillar region 4A of the edge termination region 40 is indicated. Figure 37 The parallel pn region 20B can be provided at a position on the outer peripheral side of the SJ-MOSFET 50 than the p-type pillar region 4A of the edge termination region 40 as in the case of the Figure 38 The parallel pn region 20B can be provided at a position on the outer peripheral side of the SJ-MOSFET 50 than the p-type pillar region 4A of the edge termination region 40 as in the case of the

[0126] Figure 39 is a cross-sectional view showing other structures of the SJ-MOSFET 50 of the embodiment. Figure 21 with Figure 2B the difference is that the p-type well regions 63, 63A which are in contact with the upper surfaces of the p-type pillar regions 4, 4A are in contact with the side walls of the trenches 18B. In ​ , the p-type well regions 63 of the active region 30 extend in the x direction and are in contact with the side walls of the trenches 18B, and the p-type well regions 63A of the edge termination region 40 extend in the x direction and are in contact with the trenches 18B which are provided at the boundary between the active region 30 and the edge termination region 40. ​ ​

[0127] Thus, the p-type well regions 63, 63A and the p-type base regions 5, 5A are in contact with the side walls of the trenches 18B. Therefore, it is easy to prevent a bad state caused by a channel defect such as a defect and / or a short channel of the p-type pillar regions 4, 4A. Further, the electric field near the junction of the channel is moderated by the secondary concentration gradient formed by the p-type well regions 63, 63A and the p-type base regions 5, 5A, and it is easy to ensure a sufficient channel length.

[0128] ​ is a plan view showing the structure of the SJ-MOSFET of the embodiment, and is a plan view of the A-A' section of ​ . As shown in ​ , the repeating pitch P2 of the parallel pn regions 20B of the edge termination region 40 is narrower than the repeating pitch PI of the parallel pn regions 20 of the active region 30.

[0129] The repeating pitch PI of the parallel pn regions 20 represents the sum of the width of the adjacent n-type pillar region 3 and the width of the p-type pillar region 4 in the x direction of ​ . In addition, the repeating pitch P2 of the parallel pn regions 20B represents the sum of the width of the adjacent n-type pillar region 3B and the width of the p-type pillar region 4B in the x direction of ​ . In the SJ-MOSFET 50 (super junction semiconductor device), in order to ensure the avalanche withstand voltage, it is necessary to make the withstand voltage of the edge termination region 40 higher than the withstand voltage of the active region 30. Therefore, the width of the n-type pillar region 3B and the width of the p-type pillar region 4B of the edge termination region 40 can be narrower than the width of the n-type pillar region 3 and the width of the p-type pillar region 4 of the active region 30. Thus, in the edge termination region 40, the depletion layer easily expands, and it is possible to make the withstand voltage of the edge termination region 40 higher than the withstand voltage of the active region 30.

[0130] As shown in ​ ​​As shown, the planar shape of the n-type pillar region 3 and the p-type pillar region 4 of the active region 30 can be, for example, a stripe structure in which the long side direction is parallel to the z direction. In addition, the n-type pillar region 3B and the p-type pillar region 4B in the edge termination region 40 can also be a stripe structure in which the long side direction is parallel to the z direction. Furthermore, although not shown, the planar shape of the trench 18B can also be a stripe shape in which the long side direction is parallel to the z direction.

[0131] (Method for manufacturing super junction semiconductor device)

[0132] Next, a method for manufacturing a super junction semiconductor device according to the embodiment will be described. ​ is a cross-sectional view showing a state in a manufacturing process based on the first manufacturing method of the SJ-MOSFET according to the embodiment. First, an n + -type semiconductor substrate 1 containing silicon and becoming an n + -type drain layer is prepared.

[0133] Next, an n-type drift layer 2 having a lower impurity concentration than that of the n + -type semiconductor substrate 1 is epitaxially grown on the front surface of the n + -type semiconductor substrate 1. At this time, the n-type drift layer 2 is epitaxially grown so as to be doped with n-type impurities, so that the impurity concentration of the n-type drift layer 2 becomes 1.0 x 10 16 / cm 3 or more and 3.0 x 10 17 / cm 3 or less. For example, in the case where a super junction semiconductor device having a withstand voltage of 40 V is formed, the impurity concentration of the n-type drift layer 2 can be set to 1.0 x 10 17 / cm 3 or more. In addition, for example, in the case where a super junction semiconductor device having a withstand voltage of 100 V is formed, the impurity concentration of the n-type drift layer 2 can be set to 5.0 x 10 16 / cm 3 The impurity concentration of the n-type drift layer 2 is constant in the depth direction. Here, the depth direction is a direction from the surface of the n-type drift layer 2 toward the n + -type semiconductor substrate 1. The state up to this point is described in ​ .

[0134] Next, an oxide film 23 is formed on the surface of the n-type drift layer 2. Next, a resist mask 24 having an opening portion at a position where the p-type pillar region 4 is to be formed is formed on the surface of the oxide film 23 by a photolithography technique. The state up to this point is described in ​ .

[0135] Next, an opening portion of the n-type drift layer 2 is formed in the oxide film 23 by dry etching with the resist mask 24 as a mask. Next, the resist mask 24 is removed, and the oxide film 23 having the opening portion is used as a mask, and, for example, anisotropic dry etching is performed to form a p-type pillar trench (first trench) 25A in the n-type drift layer 2. The state up to this point is illustrated in Fig. 6A. ​ .

[0136] Next, in a state where the oxide film 23 is attached, isotropic etching and sacrificial oxidation are performed. By this process, damage of the p-type pillar trench 25A is removed, and the bottom of the p-type pillar trench 25A is rounded. As for the order of performing the isotropic etching and the sacrificial oxidation, either one can be performed first. In addition, either one of the isotropic etching and the sacrificial oxidation can be performed alone.

[0137] After that, the oxide film 23 is removed. The oxide film 23 can be removed at the same time as a sacrificial oxide film (not shown). The width of the p-type pillar trench 25B formed after the oxide film 23 is removed is set to Wl. The state up to this point is illustrated in Fig. 6B. ​ .

[0138] Next, an n - -type epitaxial layer 27 having a lower impurity concentration than that of the n-type drift layer 2 is epitaxially grown so as to cover the surface of the n-type drift layer 2 and fill the inside of the p-type pillar trench 25B. At this time, the n - -type epitaxial layer 27 can be epitaxially grown so as to be doped with an n-type impurity, so that the impurity concentration of the n - -type epitaxial layer 27 becomes 1.0 x 10 15 / cm 3 or more and 5.0 x 10 16 / cm 3 or less. For example, in the case of forming a super junction semiconductor device having a withstand voltage of 40 V, the impurity concentration of the n - -type epitaxial layer 27 can be set to 2.0 x 10 16 / cm 3 . In addition, in the case of forming a super junction semiconductor device having a withstand voltage of 100 V, the impurity concentration of the n - -type epitaxial layer 27 can be set to 1.0 x 10 16 / cm 3 .

[0139] In the case where the impurity concentration of the n-type drift layer 2 is set to a ( / cm 3 ) and the impurity concentration of the n - -type epitaxial layer 27 is set to b ( / cm 3 ), the impurity concentration of the n-type drift layer 2 and the impurity concentration of the n -The relationship between the impurity concentrations of the n-type epitaxial layer 27 is a>b. Regarding the impurity concentration a ( / cm³) of the n-type drift layer 2... 3 ) and n - Impurity concentration b ( / cm²) of epitaxial layer 27 3 For example, the relationship 2≤a / b≤10 holds true.

[0140] n - The thickness of the flat portion of the epitaxial layer 27 is defined as thickness T1. - The flat portion of the n-type epitaxial layer 27 is formed on the surface of the n-type drift layer 2 where the p-type pillar trench 25B is not formed. - Part of the epitaxial layer 27. This n - The surface of the flat portion of the epitaxial layer 27 is designated as the upper surface 100.

[0141] In forming n - When the epitaxial layer 27 is used, the thickness T1 is set to be half the thickness of the width W1 of the p-type pillar trench 25B (T1>W1 / 2). By making the thickness T1 greater than half the width W1 of the p-type pillar trench 25B, n - The upper surface 100 (surface) of the epitaxial layer 27 can be planarized without the need for a CMP apparatus or similar process. The state up to this point is described in... ​ .

[0142] ​ This is a cross-sectional view showing the state of the implanted region formed under different conditions using ion implantation mask 21 for ion implantation 22. First, in n - On the surface (upper surface 100) of the epitaxial layer 27, an ion implantation mask 21 with predetermined openings is formed using photolithography, for example, with a photoresist. The openings of the ion implantation mask 21 are formed on the upper part of the p-type pillar trench 25B. Ion implantation 22 of p-type impurities is performed using the ion implantation mask 21 as a mask. The p-type impurities are, for example, boron (B) or aluminum (Al). Ion implantation 22 can be performed once or multiple times at different implantation depths. When multiple ion implantations 22 are performed at different depths, the order of ion implantation 22 can be varied. Here, depth refers to the sequence from n... - The upper surface 100 (surface) of the epitaxial layer 27 faces n + The front side of the semiconductor substrate 1. The implantation depth is the depth of the implantation from n... - The depth of impurities on the upper surface 100 (surface) of the epitaxial layer 27 (the peak position of the impurity concentration distribution).

[0143] Further, the injection regions 90, 91-1, 91-2, 92 to be described later, which are formed by the ion implantation 22, indicate regions in which impurities from the upper surface 100 are injected (peak positions of impurity concentration distribution). Thus, the injection depth indicates a depth from the upper surface 100 (surface) of the p-type epitaxial layer 27 up to the injection region 90, 91-1, 91-2, 92 formed in the p-type epitaxial layer 27. - Further, the injection regions 90, 91-1, 91-2, 92 to be described later, which are formed by the ion implantation 22, indicate regions in which impurities from the upper surface 100 are injected (peak positions of impurity concentration distribution). Thus, the injection depth indicates a depth from the upper surface 100 (surface) of the p-type epitaxial layer 27 up to the injection region 90, 91-1, 91-2, 92 formed in the p-type epitaxial layer 27. - Further, the injection regions 90, 91-1, 91-2, 92 to be described later, which are formed by the ion implantation 22, indicate regions in which impurities from the upper surface 100 are injected (peak positions of impurity concentration distribution). Thus, the injection depth indicates a depth from the upper surface 100 (surface) of the p-type epitaxial layer 27 up to the injection region 90, 91-1, 91-2, 92 formed in the p-type epitaxial layer 27.

[0144] ​ Further, the injection regions 90, 91-1, 91-2, 92 to be described later, which are formed by the ion implantation 22, indicate regions in which impurities from the upper surface 100 are injected (peak positions of impurity concentration distribution). Thus, the injection depth indicates a depth from the upper surface 100 (surface) of the p-type epitaxial layer 27 up to the injection region 90, 91-1, 91-2, 92 formed in the p-type epitaxial layer 27. - Further, the injection regions 90, 91-1, 91-2, 92 to be described later, which are formed by the ion implantation 22, indicate regions in which impurities from the upper surface 100 are injected (peak positions of impurity concentration distribution). Thus, the injection depth indicates a depth from the upper surface 100 (surface) of the p-type epitaxial layer 27 up to the injection region 90, 91-1, 91-2, 92 formed in the p-type epitaxial layer 27. - Further, the injection regions 90, 91-1, 91-2, 92 to be described later, which are formed by the ion implantation 22, indicate regions in which impurities from the upper surface 100 are injected (peak positions of impurity concentration distribution). Thus, the injection depth indicates a depth from the upper surface 100 (surface) of the p-type epitaxial layer 27 up to the injection region 90, 91-1, 91-2, 92 formed in the p-type epitaxial layer 27.

[0145] ​ The injection region 90 is formed by the one-time ion implantation 22. The injection region 90 is formed in the interval Dl. For example, in a case where the interval Dl is 0.8 μm and the interval D2 is 1.0 μm, the injection depth of the injection region 90 is 0.4 μm. The interval Dl can be 0.5 μm or more and 1.0 μm or less. The injection depth of the injection region 90 can be 0.2 μm or more and 1.0 μm or less. The interval D2 can be 0.5 μm or more and 2.0 μm or less. Note that the injection region 90 can also be formed at the boundary between the interval Dl and the interval D2.

[0146] ​ The injection regions 91-1, 91-2 are formed by the two-time ion implantation 22. The injection region 91-1 is formed in the interval Dl, and the injection region 91-2 is formed in the interval D2. For example, in a case where the interval Dl is 0.8 μm and the interval D2 is 1.0 μm, the injection depth of the injection region 91-1 is set to 0.4 μm, and the injection depth of the injection region 91-2 is set to 1.6 μm. The interval Dl can be 0.5 μm or more and 1.5 μm or less. The injection depths of the injection region 91-1 and the injection region 91-2 can be 0.2 μm or more and 2.0 μm or less. The interval D2 can be 1.0 μm or more and 4.0 μm or less. Note that either one of the injection region 91-1 or the injection region 91-2 can also be formed at the boundary between the interval Dl and the interval D2. As for the order in which the injection region 91-1 and the injection region 91-2 are formed, either one can be formed first.

[0147] ​An ion implantation 22 is performed to form an implantation region 92. The implantation region 92 is formed within interval D2. For example, if interval D1 is 0.8 μm and interval D2 is 1.0 μm, the implantation depth of the implantation region 92 is set to 1.2 μm. Interval D1 only needs to be between 0.5 μm and 1.5 μm. The implantation depth of the implantation region 92 only needs to be between 0.4 μm and 2.0 μm. The implantation region 92 can also be formed at the boundary between interval D1 and interval D2.

[0148] exist ​ , ​ as well as ​ The image shows a representative example of the implantation depth and number of implantations of p-type impurities in ion implantation 22, but the implantation depth and number of implantations in the implantation region can be varied.

[0149] ​ Is ​ A cross-sectional view showing the removal of ion implantation mask 21 after ion implantation 22, followed by heat treatment to diffuse p-type impurities. Since n - The impurity concentration of the p-type epitaxial layer 27 is lower than that of the n-type drift layer 2. Therefore, through ion implantation 22 of p-type impurities and subsequent heat treatment, p-type impurities can easily extend from the implantation region 90 to the n-type drift layer 2. - n-type epitaxial layer 27. Therefore, n-type drift layer 2 is formed. - The width W3 of the upper surface 100 of the epitaxial layer 27 is wider than the width W2 of the p-type pillar region 4, forming a p-type well region 63.

[0150] Adjacent p-type column regions 4 form n-type column regions 3, and parallel pn regions 20 are formed in the n-type drift layer 2. In addition, the p-type column region 4A and the p-type trap region 63A of the edge terminal region 40 are also formed in the same manner.

[0151] about ​ Regarding the concentration of p-type impurities, in ​ The impurity concentration is highest in the injection region 90 shown, and decreases in the depth direction as one moves away from the injection region 90. Here, the depth direction is from n... - The surface of the epitaxial layer 27 is oriented towards n. + The orientation of the semiconductor substrate 1.

[0152] ​ Is ​ A cross-sectional view showing the removal of ion implantation mask 21 after ion implantation 22, followed by heat treatment to diffuse p-type impurities. Since n -The impurity concentration of the p-type epitaxial layer 27 is lower than that of the n-type drift layer 2, so the p-type impurities are easily diffused from the implanted regions 91-1 and 91-2 to the n-type epitaxial layer 27 by the ion implantation 22 of the p-type impurities and the subsequent heat treatment. Thus, the p-type column regions 4 are formed in the n-type epitaxial layer 27. - The impurity concentration of the p-type epitaxial layer 27 is lower than that of the n-type drift layer 2, so the p-type impurities are easily diffused from the implanted regions 91-1 and 91-2 to the n-type epitaxial layer 27 by the ion implantation 22 of the p-type impurities and the subsequent heat treatment. Thus, the p-type column regions 4 are formed in the n-type epitaxial layer 27. - The width W3 of the upper surface 100 of the p-type epitaxial layer 27 is wider than the width W2 of the p-type column regions 4. Thus, the p-type well regions 63 are formed in the n-type epitaxial layer 27.

[0153] The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process.

[0154] The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process. ​ The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process. ​ The impurity concentration of the p-type epitaxial layer 27 is lower than that of the n-type drift layer 2, so the p-type impurities are easily diffused from the implanted regions 91-1 and 91-2 to the n-type epitaxial layer 27 by the ion implantation 22 of the p-type impurities and the subsequent heat treatment. Thus, the p-type column regions 4 are formed in the n-type epitaxial layer 27. - The surface of the p-type epitaxial layer 27 faces the n-type epitaxial layer 27. + The surface of the p-type epitaxial layer 27 faces the n-type epitaxial layer 27.

[0155] ​ The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process. ​ The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process. - The impurity concentration of the p-type epitaxial layer 27 is lower than that of the n-type drift layer 2, so the p-type impurities are easily diffused from the implanted regions 91-1 and 91-2 to the n-type epitaxial layer 27 by the ion implantation 22 of the p-type impurities and the subsequent heat treatment. Thus, the p-type column regions 4 are formed in the n-type epitaxial layer 27. - The impurity concentration of the p-type epitaxial layer 27 is lower than that of the n-type drift layer 2, so the p-type impurities are easily diffused from the implanted regions 91-1 and 91-2 to the n-type epitaxial layer 27 by the ion implantation 22 of the p-type impurities and the subsequent heat treatment. Thus, the p-type column regions 4 are formed in the n-type epitaxial layer 27.

[0156] ​ The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process. - The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process. - The p-type column regions 4 are formed in the n-type drift layer 2. The p-type well regions 63 are formed in the n-type epitaxial layer 27. The p-type column regions 4 and the p-type well regions 63 are formed in the same process. - The width W3 of the upper surface 100 of the p-type epitaxial layer 27 can also be formed in the same width.

[0157] Adjacent p-type column regions 4 form n-type column regions 3, and parallel pn regions 20 are formed in the n-type drift layer 2. Additionally, the p-type column regions 4A and p-type trap regions 63A of the edge terminal region 40 are also formed using the same process. Regarding... ​ Regarding the concentration of p-type impurities, in ​ The impurity concentration is highest in injection region 92, and decreases as one moves away from injection region 92. Here, the depth direction is from n... - The surface of the epitaxial layer 27 is oriented towards n. + The orientation of the semiconductor substrate 1.

[0158] ​ as well as ​ The cross-sectional shape of the p-type well region is the same, but ​ and ​ as well as ​ The cross-sectional shapes are different. This is because the implantation regions formed by ion implantation 22 are located at different positions. Subsequent manufacturing processes... ​ This explanation is based on the state. Here, the depth direction is set from n. - The surface (upper surface 100) of the epitaxial layer 27 faces n + The orientation of the semiconductor substrate 1. Additionally, "shallow" and "deep" refer to depth in the depth direction.

[0159] Furthermore, while the use of photoresist as the ion implantation mask 21 has been described, an oxide film, for example, can also be used. When using an oxide film, openings are formed in the oxide film using photolithography and etching techniques. When an oxide film is used for the ion implantation mask 21, heat treatment for diffusing implanted impurities can be performed while the oxide film is attached.

[0160] Next, in n - On the surface (upper surface 100) of the epitaxial layer 27, a structure for forming p is formed by photolithography. -- An ion implantation mask 65 is used for the opening of the region 12 that reduces the surface electric field. The ion implantation mask 65 uses, for example, a photoresist. The ion implantation mask 65 is used as a mask for ion implantation of p-type impurities. The p-type impurities are, for example, boron (B) or aluminum (Al). ​ This indicates the state up to this point.

[0161] Next, after removing the ion implantation mask 65, a heat treatment is performed to diffuse the implanted p-type impurities, in the n... - The surface layer of the epitaxial layer 27 forms p -- Type 12 reduces surface electric field region. Due to p --The impurity concentration of the p-type lower surface electric field reduction region 12 is lower than the impurity concentration of the p-type well region 63A, so a p-type -- The p-type lower surface electric field reduction region 12 is formed. -- The bottom surface of the p-type lower surface electric field reduction region 12 is formed shallower than the boundary (dotted line) between the p-type pillar region 4A and the p-type well region 63A. The state up to this point is described in - The boundary between the p-type epitaxial layer 27 and the n-type drift layer 2 is deep. In addition, the p-type lower surface electric field reduction region 12 is formed. -- The bottom surface of the p-type lower surface electric field reduction region 12 can also be formed shallower than the boundary (dotted line) between the p-type pillar region 4A and the p-type well region 63A. The state up to this point is described in ​ .

[0162] Next, an oxide film 28 is formed on the upper surface 100. The oxide film 28 can be, for example, a LOCOS film. The thickness of the oxide film 28 of the active region 30 is formed thinner than the thick portion of the oxide film 28 formed on the outer peripheral side of the edge termination region 40. The oxide film 28 is formed on the n-type epitaxial layer 27, and the thick portion of the oxide film 28 is formed on the p-type lower surface electric field reduction region 12. - The upper surface of the p-type epitaxial layer 27 is formed with a thick portion, and the bottom surface of the thick portion of the oxide film 28 is formed to a position deeper than the upper surface 100. The end portion of the thick portion of the oxide film 28 on the active region 30 side is formed so as to be continuous to a portion of the lower surface from the end portion, and is covered by the p-type lower surface electric field reduction region 12. -- The other end portion of the thick portion of the oxide film 28 is formed so as to be continuous to a portion of the lower surface from the other end portion, and is covered by the n-type epitaxial layer 27. The state up to this point is described in - The p-type epitaxial layer 27 is covered. The state up to this point is described in ​ .

[0163] Next, a resist mask (not shown) having a predetermined opening portion is formed on the surface of the oxide film 28 by a lithography technique. Next, the resist mask is used as a mask, and an opening portion is formed in the oxide film 28 by dry etching. Next, the resist mask is removed, and the oxide film 28 is used as a mask, and a trench 18A is formed which penetrates the p-type epitaxial layer 27 from the upper surface 100 of the n-type epitaxial layer 27 to the n-type drift layer 2 by anisotropic dry etching. The state up to this point is described in - The p-type epitaxial layer 27 and reaches the n-type drift layer 2. The state up to this point is described in ​ .

[0164] Next, isotropic etching and sacrificial oxidation are performed while the oxide film 28 is attached. This process removes damage to trench 18A and rounds the bottom of trench 18A. The order of isotropic etching and sacrificial oxidation can be either performed first or secondarily. Afterward, the thin portion of the oxide film 28 used as the mask for forming trench 18A is removed. At this time, both the thin portion of the oxide film 28 and the sacrificial oxide film can be removed simultaneously. The trench after removing the oxide film 28 becomes trench 18B. Since the oxide film 28 has a thin portion and a thick portion at the edge terminal region 40, full-area etching is performed to remove the thin portion of the oxide film 28, while retaining the thick portion of the oxide film at the edge terminal region 40. The sacrificial oxide film (not shown) can also be removed together with the thin portion of the oxide film 28. Furthermore, by removing the oxide film 28 using photolithography and etching techniques, the oxide film 28 can be retained at the edge terminal region 40. The oxide film retained in the edge terminal region 40 (the thicker portion of oxide film 28) becomes the field oxide film 13. ​ This indicates the state up to this point.

[0165] Next, along n - Type epitaxial layer 27, p -- A gate insulating film 7 is formed on the surface (upper surface 100) of the p-type well regions 63 and 63A, and on the inner wall of the trench 18B. This gate insulating film 7 can be formed by thermal oxidation at a temperature of approximately 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 7 can be formed by deposition using a chemical reaction such as high-temperature oxidation (HTO).

[0166] Next, a polysilicon layer doped with, for example, phosphorus atoms is formed on the gate insulating film 7. This polysilicon layer is formed to fill the trench 18B. The polysilicon layer is patterned using photolithography and etching techniques, and a gate electrode 8 is formed inside the trench 18B, separated by the gate insulating film 7.

[0167] Alternatively, the polysilicon layer formed in the edge terminal region 40 can be selectively retained and used as the field plate 29 and the channel cut-off portion 62.

[0168] Field plate 29 is continuously formed in p -- The field plate 29 is located on the upper surface of the gate insulating film 7 (insulating film 66A) formed on the p-type low surface electric field region 12, the p-type well region 63A, and the p-type base region 5A (upper surface 100), and on the upper surface of the active region 30 side of the field oxide film 13. The field plate 29 is electrically connected to the gate electrode 8 and also has the function of gate wiring.

[0169] The channel cut-off portion 62 is continuously formed on the upper surface of the outer peripheral side of the field oxide film 13 and on the n - The upper surface of the gate insulating film 7 (insulating film 66B) on the epitaxial layer 27 (upper surface 100). It should be noted that the field plate 29 and the channel cut-off portion 62 are separated on the field oxide film 13.

[0170] Next, from n - The upper surface 100 of the epitaxial layer 27 (p-type well regions 63, 63A and n-type well regions) - Ion implantation 22 is performed on the surface of the epitaxial layer 27 to form p-type base regions 5 and 5A for p-type impurities. Examples of p-type impurities include boron (B) or aluminum (Al). At this time, in the n... - In the edge termination region 40 above the epitaxial layer 27, the field plate 29, the channel cutoff portion 62, and the field oxide film 13 function as a mask. Therefore, in n - The epitaxial layer 27 is not implanted with p-type impurities. Additionally, the gate electrode 8 also functions as a mask. The state up to this point is described in... ​ Next, the gate insulating film 7 formed on the upper surface 100 is removed. It should be noted that the removal of the gate insulating film 7 is permissible as long as the thickness of the gate insulating film 7 does not impede its use in forming the n described later. + The thickness of ion implantation in source region 6, for example Therefore, the removal of the gate insulating film 7 may not be necessary.

[0171] Next, p-type impurities are diffused through heat treatment, thereby increasing the concentration of n-type impurities. - p-type epitaxial layer 27, p-type well regions 63, 63A and p -- The surface layer of the reduced surface electric field region 12 forms p-type base regions 5 and 5A. Through this heat treatment, an insulating film 66C is formed to cover the upper surface of the gate electrode 8, the field plate 29, and the channel cut-off portion 62. The gate electrode 8 includes a polysilicon layer formed by filling trench 18B.

[0172] The p-type base region 5 overlaps with the p-type well region 63, and the bottom surface of the p-type base region 5 is shallower than the bottom surface of the p-type well region 63. The p-type base region 5A overlaps with the p-type well region 63A, and the bottom surface of the p-type base region 5A is shallower than the bottom surface of the p-type well region 63A.

[0173] The impurity concentrations of p-type base region 5 and p-type base region 5A can be equal. The impurity concentrations of p-type well region 63 and p-type well region 63A can be equal. The impurity concentration of p-type base region 5 is higher than that of p-type well region 63. In addition, the impurity concentration of p-type base region 5A is higher than that of p-type well region 63A. The p-type base regions 5 and 5A are formed to be in contact with the sidewall of trench 18B.

[0174] In the edge terminal region 40, since the oxide film 28, the field plate 29, and the channel cut-off portion 62 function as masks, the n area covered by the oxide film 28, the field plate 29, and the channel cut-off portion 62... - Type epitaxial layer 27 and p -- Boron (B) is not implanted in region 12, which reduces the surface electric field. Therefore, even if heat treatment is performed to diffuse the p-type impurities forming the p-type base regions 5 and 5A, the p-type impurities forming the p-type base regions 5 and 5A will not diffuse into the n-type base regions. - Type epitaxial layer 27 and p -- The diffusion in region 12 of the surface electric field is reduced. Therefore, in the edge terminal region 40, n - Type epitaxial layer 27 and p -- Region 12, which reduces the surface electric field, is retained.

[0175] Thus, through the first manufacturing method, a p-type base region 5 is formed after the trench 18B is formed, and the p-type base region 5 forms a channel. The state up to this point is described in... ​ .

[0176] Next, on the surface of the p-type base region 5, a photoresist is used, and a mask (not shown) with the desired opening is formed using photolithography. Using this photoresist mask as a template, n-type impurities are ion implanted. Through this ion implantation, n-type impurities are formed on the surface layer of the p-type base region 5. + An n-type impurity was injected at position 6 of the source region. The injected n-type impurities were arsenic (As), phosphorus (P), etc.

[0177] Next, remove the parts that are needed to form n + The ion implantation mask used for the source region 6. Furthermore, on the surface of the p-type base region 5, for example, a photoresist can be used, and a mask with the desired opening can be formed using photolithography. P-type impurities are then implanted into the surface layer of the p-type base region 5, and these p-type impurities form with the n-type base region 6. + p in phase 6 of the source region ++ Type contact region 14. Additionally, p-type base region 5A can also be implanted to form a p-type base layer. ++ p-type impurities in contact region 14A. It should be noted that n-type impurities do not form on the surface layer of the p-type base region 5A in the edge terminal region 40. + Source area 6.

[0178] Next, in order to form n + Type source region 6 and p ++In contact regions 14 and 14A, a heat treatment is performed to activate the implanted impurities. Here, the difference between the activation heat treatment and the post-ion implantation heat treatment (heat treatment that diffuses the ion-implanted impurities) will be explained. The ion-implanted semiconductor substrate, such as the n-type drift layer 2, is damaged by ion implantation, resulting in defects. The ion-implanted impurities become non-functional as a charge due to these defects. The activation heat treatment refers to the heat treatment that restores the defects caused by ion implantation to a charge (resistance) corresponding to the amount of implanted impurities. The post-ion implantation heat treatment (heat treatment that diffuses the ion-implanted impurities) refers to the heat treatment that restores the defects caused by ion implantation to a charge (resistance) corresponding to the amount of implanted impurities, thereby allowing the impurities to diffuse to any location in the semiconductor substrate, such as the n-type drift layer 2. Therefore, the activation heat treatment has a shorter thermal history compared to the post-ion implantation heat treatment (heat treatment that diffuses the ion-implanted impurities). A shorter thermal history means, for example, a lower heat treatment temperature or a shorter heat treatment time; a lower heat treatment temperature and a shorter heat treatment time are both desirable. Regarding the formation of n + Type source region 6 and p ++ Regarding the order of ion implantation in contact regions 14 and 14A, either order is acceptable. The state up to this point is recorded in... ​ .

[0179] Next, in n - An interlayer insulating film 9 is formed over the entire upper surface (upper surface 100) of the epitaxial layer 27. The interlayer insulating film 9 is formed to cover, for example, a gate insulating film 7, a gate electrode 8, and an inductor 66C, with the insulating film 66C as a buffer. + Source region 6, p ++ Type contact region 14, p-type base region 5A, p ++ The contact area 14A, field oxide film 13, field plate 29, and upper part of channel cutoff portion 62 are included. The interlayer insulating film 9 is formed from, for example, BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), etc. Alternatively, the interlayer insulating film 9 can also be formed as a laminate by forming, for example, HTO (High Temperature Oxide), NSG (None-doped Silicate Glass), and TEOS (Tetraethyl Orthosilicate) films under the BPSG (between the BPSG and the gate electrode 8). The thickness of the interlayer insulating film 9 can be approximately 1 μm.

[0180] Next, the interlayer insulating film 9 and the insulating film 66C are patterned using photolithography and etching techniques. In the active region 30, a pattern is formed that enables n... +Type source region 6 and p ++ The contact hole 64A exposed on the surface of the contact area 14 (the boundary of the interlayer insulating film 9 covering the gate insulating film 7 formed along the inner wall of the trench 18B and the upper part of the gate electrode 8 is not shown). Additionally, a contact hole 64A is formed in the edge terminal region 40 to make p ++ Contact holes 64B are exposed on the surface of contact area 14A. Furthermore, contact holes 64C are formed in the edge terminal area 40 to expose the surface of the field plate 29. Afterwards, heat treatment (reflow) is performed to planarize the interlayer insulating film 9. The state up to this point is described in... ​ .

[0181] Next, a metal film of aluminum or an aluminum-based alloy (Al-Si, Al-Cu, Al-Si-Cu, etc.) is formed by sputtering to continuously cover the upper surface of the interlayer insulating film 9, filling the contact holes 64A, 64B, and 64C. It should be noted that before forming the metal film, a barrier metal (not shown) comprising a titanium film (Ti), a titanium nitride film (TiN), or a stack of titanium and titanium nitride films (e.g., Ti / TiN) can be formed by sputtering along the inner walls of the contact holes 64A, 64B, and 64C to the upper surface of the interlayer insulating film 9. Then, the metal film and the barrier metal (not shown) are patterned using photolithography and etching techniques, thereby forming the source electrode 10, the metal gate runner 61, and the gate electrode pads (not shown). It should be noted that the barrier metal may also be formed only within the contact holes 64A, 64B, and 64C.

[0182] In the active region 30, the source electrode 10 and the n exposed on the surface of the contact hole 64A + Type source region 6 and p ++ The contact area 14 is electrically connected. Additionally, in the edge terminal area 40, the source electrode 10 is connected to the p-type contact area exposed on the surface of the contact hole 64B. ++ Contact area 14A is electrically connected. Additionally, the metal gate runner 61 is electrically connected to the field plate 29 exposed on the surface of contact hole 64C and the gate electrode 8. The gate electrode pad (not shown) is electrically connected to the metal gate runner 61 and the gate electrode 8. It should be noted that tungsten plugs or similar materials may be embedded in contact holes 64A, 64B, and 64C through a barrier metal.

[0183] Next, by sputtering on n +A back electrode 11 is formed on the back side of the semiconductor substrate 1 (the back side of the semiconductor substrate). The back electrode 11 can be formed from a metal film such as nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy with aluminum as the main component (Al-Si, Al-Cu, Al-Si-Cu). Alternatively, a multilayer film of metal films such as nickel, titanium, gold, silver, aluminum, or an alloy with aluminum as the main component (Al-Si, Al-Cu, Al-Si-Cu) can be formed (e.g., Ti / Ni / Au, Al / Ti / Ni / Au, etc.). After the back electrode 11 is formed, heat treatment is performed to form an n + The ohmic bonding between the semiconductor substrate 1 and the back electrode 11 is achieved. This completes the... ​ The SJ-MOSFET 50 is shown.

[0184] In this way, a p-type column trench 25B is formed in the region that becomes the p-type column region 4, 4A, and the impurity concentration is lower than that of the n-type drift layer 2 that becomes the n-type column region 3. - The outer extension layer 27 is filled into the trench 25 of the p-type column.

[0185] Furthermore, proceed with self-n - Ion implantation of p-type impurities into the surface (upper surface 100) of the p-type epitaxial layer 27 and heat treatment for diffusion of the implanted impurities form p-type pillar regions 4, 4A and p-type well regions 63, 63A. Therefore, since the p-type pillar region 4 can be formed without p-type epitaxial layer deposition, the process of removing the p-type epitaxial layer in the edge termination region 40 is unnecessary. Furthermore, the n-type well regions 63, 63A are filled into the p-type pillar trench 25B. - The surface of the epitaxial layer 27 does not require planarization using CMP equipment or similar processes. Therefore, manufacturing costs can be reduced by decreasing the number of manufacturing steps.

[0186] Furthermore, compared to multi-level epitaxy, the widths of the n-type pillar region 3 and the p-type pillar region 4 can be miniaturized, reducing the on-state resistance in, for example, SJ-MOSFETs (superjunction semiconductor devices) 50 with a breakdown voltage of 100V or less. Additionally, since the p-type pillar region 4 is formed through diffusion based on ion implantation and thermal processing, cross-diffusion occurs at the boundary between the p-type pillar region 4 and the n-type pillar region 3. Therefore, compared to the conventional method of forming p-type and n-type pillar regions using trench filling, the conductivity at the boundary between the p-type pillar region 4 and the n-type pillar region 3 changes more smoothly. As a result, the depletion layer expands more easily, mitigating the electric field and increasing the breakdown voltage.

[0187] ​ The SJ-MOSFET 50 shown is manufactured as follows. First, with... ​ Similarly, the SJ-MOSFET50 shown is used in conjunction with...​ The same process is repeated up to p-type base region 5. (Replacement) ​ , 19 The process and ​ , 21 The process forms the contact plug 19.

[0188] exist ​ Following the described process, an insulating film 66C is placed over the p-type base region 5, and a photoresist mask (not shown) with the desired opening is formed using photolithography. Ion implantation is performed using this photoresist mask to implant n-type impurities. n-type impurities are then implanted into the surface layer of the p-type base region 5 in the active region 30. + n-type impurities in source region 6. Examples of n-type impurities include, for example, arsenic (As) or phosphorus (P). Afterwards, the resist mask is removed.

[0189] Next, a photoresist mask (not shown) with desired openings is formed on the upper part of the p-type base regions 5 and 5A via an insulating film 66C using photolithography. Ion implantation is performed using this photoresist mask to implant p-type impurities. p-type impurities are then implanted into the surface layer of the p-type base regions 5 and 5A. ++ p-type impurities in contact regions 14 and 14A. Forming p-type impurities. ++ p-type impurities in contact regions 14 and 14A are implanted into the n-type contact regions. + The n-type impurities in source region 6 are located deeper.

[0190] p-type base region 5A can be implanted in the surface layer of the p-type base region 5A in the edge terminal region 40 to form p ++ p-type impurities in contact region 14A are not injected to form n-type impurities. + n-type impurities in source region 6.

[0191] Next, the process is performed to make n + Type source region 6 and p ++ The heat treatment that activates the impurities injected into the contact region 14. Compared to the heat treatment used to diffuse the injected impurities, the heat treatment that activates the injected impurities has a shorter thermal history. ++ The bottom surface of the contact area 14 is formed more than n + The bottom surface of source region 6 is deep. Additionally, n is formed. + Type source region 6 and p ++ The sequence of ion implantation in contact region 14 can be varied. The state up to this point is recorded in... ​ .

[0192] Next, in n - An interlayer insulating film 9 is formed over the entire upper surface (upper surface 100) of the epitaxial layer 27. The interlayer insulating film 9 is formed to cover, for example, a gate insulating film 7, a gate electrode 8, and an inductor 66C, with the insulating film 66C as a buffer.+ Source region 6, p ++ Type contact region 14, p-type base region 5A, p ++ The contact area 14A, field oxide film 13, field plate 29, and the upper part of the channel cutoff portion 62 are included. The interlayer insulating film 9 is formed from, for example, BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), etc. Alternatively, the interlayer insulating film 9 can also be formed as a laminate by forming, for example, HTO (High Temperature Oxide), NSG (None-doped Silicate Glass), and TEOS (Tetraethyl Orthosilicate) films under, for example, BPSG (between BPSG and gate electrode 8). The thickness of the interlayer insulating film 9 can be about 1 μm.

[0193] Next, a resist mask (not shown) with openings is formed on the surface of the interlayer insulating film 9, for example, using photolithography. Then, using the resist mask, anisotropic dry etching is used to form openings in the interlayer insulating film 9 and the insulating film 66C (the boundary of the insulating film 66C covering the gate insulating film 7 formed along the inner wall of the trench 18B and the upper part of the gate electrode 8 is not shown). Next, recesses 67D, 67E, and 67F are formed by anisotropic dry etching. When the SJ-MOSFET 50 is completed, recesses 67D, 67E, and 67F become... ​ The recesses are 67A, 67B, and 67C.

[0194] The interlayer insulating film 9 and the insulating film 66C covering the upper surface of the gate electrode 8, which is buried in the trench 18B of the active region 30, form a recess 67D that is deeper than the upper surface 100 between them and the adjacent trench 18B. + Type source region 6 and p ++ The contact area 14 is in contact with the sidewall of the recess 67D (exposed on the sidewall of the recess 67D). ++ The contact area 14 is in contact with the bottom of the recess 67D (exposed at the bottom of the recess 67D). The recess 67D is a contact hole 64D.

[0195] Similarly, between the interlayer insulating film 9 and insulating film 66C covering the upper surface of the gate electrode 8 of the adjacent trench 18B buried in the active region 30 and the interlayer insulating film 9 and insulating film 66C covering the upper surface of the gate electrode 8 of the trench 18B located at the boundary between the active region 30 and the edge terminal region 40, a recess 67D deeper than the upper surface 100 is also formed. + Type source region 6 and p ++The contact area 14 is in contact with the sidewall of the recess 67D (exposed on the sidewall of the recess 67D). ++ The contact area 14 is in contact with the bottom of the recess 67D (exposed at the bottom of the recess 67D). The recess 67D is a contact hole 64D.

[0196] A recess 67E, deeper than the upper surface 100, is formed between the interlayer insulating film 9, which is disposed in such a way as to cover the upper surface of the gate electrode 8, which is buried in the trench 18B between the active region 30 and the edge terminal region 40, and between the insulating film 66C and the interlayer insulating film 9 covering the field plate 29. ++ The contact area 14A is in contact with the sidewall and bottom of the recess 67E (exposed on the sidewall and bottom of the recess 67E). The recess 67E is a contact hole 64E.

[0197] A recess 67F is formed in the interlayer insulating film 9 and insulating film 66C covering the field plate 29 and the channel cut-off portion 62. At the bottom of the recess 67F, the surface of the field oxide film 13 is exposed through the field plate 29. The field plate 29 and the field oxide film 13 are in contact with the sidewalls of the recess 67F (exposed on the sidewalls of the recess 67F). The field oxide film 13 is in contact with the bottom of the recess 67F (exposed on the bottom of the recess 67F). This recess 67F is a contact hole 64F. It should be noted that the field oxide film 13 may also not be in contact with the sidewalls of the recess 67F.

[0198] After dry etching to form contact holes 64D, 64E, and 64F, the resist mask is removed and heat treatment (reflow) is performed to planarize the interlayer insulating film 9.

[0199] Next, a barrier metal (not shown) comprising a titanium film (Ti), a titanium nitride film (TiN), or a stack of titanium film and titanium nitride film (e.g., Ti / TiN) is formed by sputtering from the surface of the interlayer insulating film 9 along the inner walls of the contact holes 64D, 64E, and 64F. Then, a tungsten film (W), for example, is formed to be embedded within the contact holes 64D, 64E, and 64F through the barrier metal.

[0200] Next, tungsten film etching is performed to form contact plugs 19 within contact holes 64D, 64E, and 64F. The contact plug 19 formed within contact hole 64D is separated from the contact hole by a barrier metal (not shown) and n + Type source region 6 and p ++ The contact area 14 is electrically connected. Additionally, the contact plug 19 formed within the contact hole 64E is separated from the contact by a barrier metal (not shown) and p. ++ Contact area 14A is electrically connected. Additionally, contact plug 19 formed within contact hole 64F is electrically connected to field plate 29 via barrier metal (not shown). The state up to this point is described in... ​ .

[0201] Next, by sputtering on ​ The SJ-MOSFET (superjunction semiconductor device) shown has a metal film of aluminum or an aluminum-based alloy (Al-Si, Al-Cu, Al-Si-Cu) deposited on its upper surface. Then, the metal film is patterned using photolithography and etching techniques to form the source electrode 10, the metal gate runner 61, and the gate electrode pad (not shown).

[0202] The source electrode 10 is electrically connected to the contact plug 19, and the contact plug 19 is connected to p ++ The contact area 14 is electrically connected. Additionally, the metal gate runner 61 is electrically connected to the field plate 29. Furthermore, the metal gate runner 61 is electrically connected to the gate electrode 8, and the gate electrode pad (not shown) is electrically connected to both the metal gate runner 61 and the gate electrode 8.

[0203] Next, by sputtering on n + A back electrode 11 is formed on the back side of the semiconductor substrate 1 (the back side of the semiconductor substrate). The back electrode 11 can be formed from a metal film such as nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy with aluminum as the main component (Al-Si, Al-Cu, Al-Si-Cu). Alternatively, a multilayer film of metal films such as nickel, titanium, gold, silver, aluminum, or an alloy with aluminum as the main component (e.g., Ti / Ni / Au, Al / Ti / Ni / Au, etc.) can be formed. After the back electrode 11 is formed, heat treatment is performed to form an n + The ohmic bonding between the semiconductor substrate 1 and the back electrode 11 is achieved. This completes the... ​ The SJ-MOSFET 50 is shown.

[0204] ​ The SJ-MOSFET 50 shown can be manufactured as follows. First, with... ​ Similarly, the SJ-MOSFET 50 shown is performed in conjunction with... ​ The same process is repeated up to p-type base region 5. (Replacement) ​ , 19 The process and ​ The process forms the contact plug 19.

[0205] Until ​ Following the first manufacturing method of the SJ-MOSFET described above, a mask (not shown) with a desired opening is formed on the surface of the p-type base region 5 using, for example, a photoresist and photolithography. This photoresist mask is used as a mask for ion implantation of n-type impurities. Through this ion implantation, n-type impurities are formed on the surface layer of the p-type base region 5. +An n-type impurity is implanted at the source region 6. The implanted n-type impurity is arsenic (As), phosphorus (P), etc. It should be noted that n-type impurities may not be implanted into the surface layer of the p-type base region 5A at the edge terminal region 40 to form an n-type base. + n-type impurities in source region 6. Next, impurities for forming n-type impurities are removed. + The ion implantation mask used for source region 6. Next, in order to form n... + In source region 6, a heat treatment is performed to activate the injected impurities. The state up to this point is recorded in... ​ .

[0206] Next, in n - An interlayer insulating film 9 is formed over the entire upper surface (upper surface 100) of the epitaxial layer 27. The interlayer insulating film 9 is formed to cover, for example, a gate insulating film 7, a gate electrode 8, and an inductor 66C, with the insulating film 66C as a buffer. + Source region 6, p ++ Type contact region 14, p-type base region 5A, p ++ The contact area 14A, field oxide film 13, field plate 29, and the upper part of the channel cutoff portion 62 are described. The interlayer insulating film 9 is formed from, for example, BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), etc. Alternatively, the interlayer insulating film 9 can also be formed as a laminate by forming, for example, HTO (High Temperature Oxide), NSG (None-doped Silicate Glass), and TEOS (Tetraethyl Orthosilicate) films under the BPSG (between the BPSG and the gate electrode 8). The thickness of the interlayer insulating film 9 can be about 1 μm. The state up to this point is described in ​ .

[0207] Next, a resist mask (not shown) with openings is formed on the surface of the interlayer insulating film 9 using, for example, photolithography. Then, using the resist mask, anisotropic dry etching is used to form openings in the interlayer insulating film 9 and the insulating film 66C (the boundary of the insulating film 66C covering the gate insulating film 7 formed along the inner wall of the trench 18B and the upper part of the gate electrode 8 is not shown). Next, recesses 67D, 67E, and 67F are formed by anisotropic dry etching. When the SJ-MOSFET 50 is completed, recesses 67D, 67E, and 67F become... ​ The recesses are 67A, 67B, and 67C.

[0208] The interlayer insulating film 9 and the insulating film 66C covering the upper surface of the gate electrode 8, which is buried in the trench 18B of the active region 30, form a recess 67D that is deeper than the upper surface 100 between them and the adjacent trench 18B. + The source region 6 and the p-type base region 5 are in contact with the sidewall of the recess 67D (exposed on the sidewall of the recess 67D). The p-type base region 5 is in contact with the bottom of the recess 67D (exposed on the bottom of the recess 67D). The recess 67D is a contact hole 64D.

[0209] Similarly, between the interlayer insulating film 9 and insulating film 66C covering the upper surface of the gate electrode 8 of the adjacent trench 18B buried in the active region 30 and the interlayer insulating film 9 and insulating film 66C covering the upper surface of the gate electrode 8 of the trench 18B located at the boundary between the active region 30 and the edge terminal region 40, a recess 67D deeper than the upper surface 100 is also formed. + The source region 6 and the p-type base region 5 are in contact with the sidewall of the recess 67D (exposed on the sidewall of the recess 67D). The p-type base region 5 is in contact with the bottom of the recess 67D (exposed on the bottom of the recess 67D). The recess 67D is a contact hole 64D.

[0210] A recess 67E, deeper than the upper surface 100, is formed between the interlayer insulating film 9, which is disposed in such a way as to cover the upper surface of the gate electrode 8, which is buried in the trench 18B between the active region 30 and the edge terminal region 40, and between the insulating film 66C and the interlayer insulating film 9 covering the field plate 29. The p-type base region 5A is in contact with the sidewalls and bottom of the recess 67E (exposed on the sidewalls and bottom of the recess 67E). This recess 67E is a contact hole 64E.

[0211] A recess 67F is formed in the interlayer insulating film 9 and insulating film 66C covering the field plate 29 and the channel cut-off portion 62. At the bottom of the recess 67F, the surface of the field oxide film 13 is exposed through the field plate 29. The field plate 29 and the field oxide film 13 are in contact with the sidewalls of the recess 67F (exposed on the sidewalls of the recess 67F). The field oxide film 13 is in contact with the bottom of the recess 67F (exposed on the bottom of the recess 67F). This recess 67F is a contact hole 64F. It should be noted that the field oxide film 13 may not be in contact with the sidewalls of the recess 67F.

[0212] Next, ion implantation 22 is performed using the interlayer insulating film 9 as a mask to implant p-type impurities. P-type impurities are implanted into the surface layer of the p-type base regions 5 and 5A at the bottom of recess 67D, the sides of recess 67E, and the bottom of recess 67E to form p-type base regions 5 and 5A. ++ p-type impurities in contact regions 14 and 14A. p-type impurities can be formed by implantation into the surface layer of the p-type base region 5A in the edge terminal region 40. ++ p-type impurities in contact region 14A are not injected to form n-type impurities. +n-type impurities in source region 6. The state up to this point is recorded in... ​ .

[0213] Next, heat treatment (reflow) is performed to planarize the interlayer insulating film 9. Alternatively, the implanted p-forming material can be planarized simultaneously with the interlayer insulating film 9. ++ Activation of p-type impurities in contact regions 14 and 14A.

[0214] Next, a barrier metal (not shown) comprising a titanium film (Ti), a titanium nitride film (TiN), or a stack of titanium film and titanium nitride film (e.g., Ti / TiN) is formed by sputtering from the surface of the interlayer insulating film 9 along the inner walls of the contact holes 64D, 64E, and 64F. Then, a tungsten film (W), for example, is formed to be embedded within the contact holes 64D, 64E, and 64F through the barrier metal.

[0215] Next, tungsten film etching is performed to form contact plugs 19 within contact holes 64D, 64E, and 64F. The contact plug 19 formed within contact hole 64D is separated from the contact hole by a barrier metal (not shown) and n + Type source region 6 and p ++ The contact area 14 is electrically connected. Additionally, the contact plug 19 formed within the contact hole 64E is separated from the contact by a barrier metal (not shown) and p. ++ Contact area 14A is electrically connected. Additionally, contact plug 19 formed within contact hole 64F is electrically connected to field plate 29 via barrier metal (not shown). The state up to this point is described in... ​ .

[0216] Next, by sputtering on ​ The SJ-MOSFET (superjunction semiconductor device) shown has a metal film of aluminum or an aluminum-based alloy (Al-Si, Al-Cu, Al-Si-Cu) deposited on its upper surface. Then, the metal film is patterned using photolithography and etching techniques to form the source electrode 10, the metal gate runner 61, and the gate electrode pads (not shown).

[0217] The source electrode 10 is electrically connected to the contact plug 19, and the contact plug 19 is connected to p ++ The contact area 14 is electrically connected. Additionally, the metal gate runner 61 is electrically connected to the field plate 29. Furthermore, the metal gate runner 61 is electrically connected to the gate electrode 8, and the gate electrode pad (not shown) is electrically connected to both the metal gate runner 61 and the gate electrode 8.

[0218] Next, by sputtering on n +A back electrode 11 is formed on the back side of the semiconductor substrate 1 (the back side of the semiconductor substrate). The back electrode 11 can be formed from a metal film such as nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy with aluminum as the main component (Al-Si, Al-Cu, Al-Si-Cu). Alternatively, a laminated film of metal films such as nickel, titanium, gold, silver, aluminum, or an alloy with aluminum as the main component (e.g., Ti / Ni / Au, Al / Ti / Ni / Au, etc.) can be formed. After the back electrode 11 is formed, heat treatment is performed to form an n + The ohmic bonding between the semiconductor substrate 1 and the back electrode 11 is achieved. This completes the... ​ The SJ-MOSFET 50 is shown.

[0219] Next, regarding... ​ A second manufacturing method, different from the first manufacturing method shown, will be described. ​ This is a cross-sectional view showing the state of the manufacturing process in the second manufacturing method of the SJ-MOSFET based on the embodiment. The second manufacturing method is... ​ The manufacturing method of the SJ-MOSFET is shown. Since the manufacturing method of the edge termination region 40 is the same as the first manufacturing method, therefore... ​ The image shows a cross-sectional view of the active region 30. The second manufacturing method... ​ The process shown is the same as the first manufacturing method, which involves performing the same steps up to the point shown to form n. - Type epitaxial layer 27.

[0220] The difference between the second manufacturing method and the first manufacturing method lies in n. - The epitaxial layer 27 is implanted into an implantation region 93 by ion implantation 22. Specifically, the second manufacturing method differs from the first manufacturing method in that, within region D1, ion implantation 22 is performed on the entire surface of a predetermined region, excluding a portion of the edge terminal region 40, to form the implantation region 93. The predetermined region is... ​ The opening of the ion implantation mask 21 that forms the p-type column region 4A is shown compared to the region on the side of the active region 30.

[0221] Here, depth refers to the distance from n. - The upper surface 100 (surface) of the epitaxial layer 27 faces n + The front side of the semiconductor substrate 1. The implantation depth is the depth of the implantation from n... - The depth of impurities on the upper surface 100 (surface) of the epitaxial layer 27 (the peak position of the impurity concentration distribution).

[0222] Additionally, the implantation region 93 formed by ion implantation 22 represents the region where impurities from the upper surface 100 are implanted (the peak position of the impurity concentration distribution). The implantation depth represents the depth from n...- The upper surface 100 (surface) of the epitaxial layer 27 serves to form on n - The depth up to the injection region 93 within the epitaxial layer 27.

[0223] Therefore, let n - The surface (upper surface 100) of the n-type epitaxial layer 27 and the surface of the n-type drift layer 2 (n - The thickness T1 of the flat portion of the n-type epitaxial layer 27 is defined as interval D1, and the interval from the surface of the n-type drift layer 2 to the bottom of the p-type column trench 25B (the depth of the p-type column trench 25B) is defined as interval D2.

[0224] In formation ​ Following the process of the n-type epitaxial layer 27 shown, ion implantation 22 of p-type impurities is performed from the surface of the n-type epitaxial layer 27 into a predetermined region. Examples of p-type impurities include, for example, boron (B) or aluminum (Al). In the second manufacturing method, ion implantation 22 can be performed in a predetermined region of the n-type epitaxial layer 27, and... ​ Compared to the outer peripheral region, the opening of the ion implantation mask 21 for the p-type column region 4A, which forms the edge terminal region 40 where ion implantation is not performed, does not form a new ion implantation mask. In the outer peripheral region where ion implantation is not performed, the mask can be retained... ​ The oxide film 23 shown serves as a mask, and no p-type impurities are implanted. In addition, in the peripheral region, ion implantation 22 can be performed by forming an ion implantation mask 21 on the surface (upper surface 100) of the n-type epitaxial layer 27 using a photoresist or the like.

[0225] The implantation region 93, formed by ion implantation 22, is formed in interval D1. With interval D1 being 0.8 μm and interval D2 being 1.0 μm, the implantation region 93 will be formed from n... - The depth from the surface of the epitaxial layer 27 to the implantation region 93 is set to 0.4 μm. The interval D1 (thickness T1) only needs to be between 0.5 μm and 1.0 μm. From n - The implantation depth from the surface (upper surface 100) of the epitaxial layer 27 to the implantation region 93 only needs to be 0.2 μm or more and 1.0 μm or less. Additionally, the depth of interval D2 only needs to be 0.5 μm or more and 2.0 μm or less. The implantation region 93 can also be formed at the boundary between intervals D1 and D2. The state up to this point is described in... ​ .

[0226] Next, the mask (not shown) used in ion implantation 22, such as oxide film 23, ion implantation mask 21 formed by photoresist, etc., are removed, and then heat treatment is performed to diffuse p-type impurities. As a result, p-type pillar region 4 and p-type well region 63 are formed.

[0227] Here, n - The p-type epitaxial layer 27 is formed with a lower impurity concentration than the n-type drift layer 2. Through ion implantation 22 of p-type impurities and subsequent heat treatment, p-type impurities can easily extend from the implantation region 93 to the n-type layer 94. - Type epitaxial layer 27.

[0228] Adjacent p-type column regions 4 form n-type column regions 3, creating parallel pn regions 20. A p-type trap region 63 is formed on the entire surface of a predetermined region that has undergone ion implantation 22.

[0229] Regarding the impurity concentration in the p-type well region 63 and the p-type column region 4, the impurity concentration is highest in the implantation region 93, and decreases in the depth direction as the impurity concentration moves away from the implantation region 93. Here, the depth direction is from n... - The surface of the epitaxial layer 27 is oriented towards n. + The orientation of the semiconductor substrate 1.

[0230] Following ion implantation 22 and a heat treatment to diffuse p-type impurities, an oxide film 28 is formed on the surface (upper surface 100) of the p-type well region 63. It should be noted that the oxide film 28 can also be formed during the heat treatment following ion implantation 22 to diffuse p-type impurities.

[0231] During heat treatment, the shape of the boundary between the p-type pillar region 4 and the p-type well region 63 (the corner between the p-type pillar trench 25B and the surface of the n-type drift layer 2) can be formed into a rounded shape through impurity diffusion. The state up to this point is described in... ​ .

[0232] Thus, in the second manufacturing method, before forming the trench 18A (described later), ion implantation 22 is performed on the entire surface of a predetermined region, excluding a portion of the edge terminal region 40, to form the implantation region 93. After ion implantation 22, heat treatment is performed to form the p-type pillar region 4 and the p-type well region 63.

[0233] n - The impurity concentration of the n-type epitaxial layer 27 is formed by an impurity concentration lower than that of the n-type drift layer 2. Because the n-type drift layer 2... - The concentration difference of impurities between the p-type epitaxial layer 27 and the n-type drift layer 2 is large, so the p-type impurities implanted by ion implantation 22 are difficult to diffuse into the n-type drift layer 2, but are more likely to diffuse into the n-type drift layer 2. - Diffusion occurs in the epitaxial layer 27.

[0234] Since the p-type well region 63 is formed on the entire surface of the predetermined region where ion implantation 22 has been performed, and it is in contact with the sidewall of the trench 18B, it has the same function as the p-type base region 5 formed by subsequent processes. Because the p-type impurities implanted by ion implantation 22 are difficult to diffuse into the n-type drift layer 2, the expansion of the channel length due to heat treatment can be suppressed.

[0235] Next, a photoresist mask (not shown) with predetermined openings is formed on the surface of the oxide film 28 using photolithography. Then, using the photoresist mask, openings are formed in the oxide film 28 by, for example, anisotropic dry etching. Next, the photoresist mask (not shown) is removed, and using the oxide film 28 as a mask, a trench 18A is formed through the p-type well region 63 and reaches the n-type drift layer 2 (n-type pillar region 3) by anisotropic dry etching. In the second manufacturing method, the p-type well region 63 is in contact with the sidewalls of the trench 18A. The state up to this point is described in... ​ .

[0236] Next, with the oxide film 28 attached, isotropic etching and sacrificial oxidation are performed. This process removes damage to trench 18A and rounds the bottom of trench 18A. The order of isotropic etching and sacrificial oxidation can be either performed first. Alternatively, only one of them can be performed. Afterward, the oxide film 28 is removed. The sacrificial oxide film (not shown) can be removed simultaneously with the oxide film 28.

[0237] Next, along the surface (n) of the p-type well region 63 - A gate insulating film 7 is formed on the upper surface 100 of the epitaxial layer 27 and the inner wall of the trench 18B. This gate insulating film 7 can be formed by thermal oxidation at a temperature of about 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 7 can also be formed by deposition using a chemical reaction such as high-temperature oxidation (HTO).

[0238] Next, a polysilicon layer doped with, for example, phosphorus atoms is formed on the gate insulating film 7. This polysilicon layer is formed to fill the trench 18B. The polysilicon layer is patterned using photolithography and etching techniques, and a gate electrode 8 is formed inside the trench 18B, separated by the gate insulating film 7. The p-type well region 63 is in contact with the sidewall of the trench 18B.

[0239] Next, from the surface (n) of the p-type well region 63 - Ion implantation 22 is performed on the upper surface 100 of the epitaxial layer 27 to form the p-type base region 5 using p-type impurities such as boron (B). In the active region 30, the gate electrode 8 functions as a mask. The state up to this point is described in... ​ .

[0240] Next, a heat treatment is performed to diffuse the p-type impurities implanted by ion implantation 22 to form the p-type base region 5. The p-type base region 5 is formed on the surface layer of the p-type well region 63, and the impurity concentration of the p-type base region 5 is higher than that of the p-type well region 63. In the depth direction, the bottom surface of the p-type base region 5 is formed to be shallower than the bottom surface of the p-type well region 63. The p-type base region 5 and the p-type well region 63 are formed to be in contact with the sidewalls of the trench 18B.

[0241] Similarly, on the active region 30 side, the p-type base region 5 and the p-type well region 63 are in contact with the sidewall of the trench 18B (not shown) formed at the boundary between the active region 30 and the edge terminal region 40, and in the edge terminal region 40, the p-type base region 5A and the p-type well region 63A are in contact with the sidewall of the trench 18B (not shown) formed at the boundary between the active region 30 and the edge terminal region 40.

[0242] When trench 18B is formed after the formation of p-type well region 63, the non-uniformity of the gate threshold voltage may increase due to p-type impurity diffusion in p-type well region 63 caused by processes such as heating the SJ-MOSFET (superjunction semiconductor device) 50, forming oxide film 28, sacrificial oxide film, and gate insulating film 7. Therefore, by forming p-type base region 5 after forming trench 18B (after forming gate electrode 8), the gate threshold voltage can be stabilized. The state up to this point is described in ​ .

[0243] It should be noted that by not performing ion implantation 22 to form p-type impurities in the p-type base region 5, the number of ion implantations can be reduced, thereby lowering manufacturing costs. Subsequently, the process is carried out in the same manner as the first manufacturing method, by forming n... + The process following the process in source area 6 is completed. ​ The SJ-MOSFET 50 is shown. In the second manufacturing method, the p-type well region 63 is different from the p-type well region 63 in the first manufacturing method, and the p-type well region 63 is connected to the sidewall of the trench 18B.

[0244] Next, regarding... ​ A third manufacturing method, different from the second manufacturing method shown, will be explained. ​ This is a cross-sectional view showing the state of the manufacturing process in the third manufacturing method of the SJ-MOSFET based on the implementation method. The third manufacturing method is... ​ The manufacturing method of the SJ-MOSFET is shown. First, the third manufacturing method to... ​ , ​ , ​ The process shown is the same as the first manufacturing method, except that p-type impurities are diffused by heat treatment.

[0245] The third manufacturing method differs from the first manufacturing method in that it only fills the n-type column groove 25B with n. - Ion implantation of a second type of conductivity impurity is performed in the region of the epitaxial layer 27 to form p-type column regions 4 and 4A.

[0246] Next, in n - On the surface (upper surface 100) of the epitaxial layer 27, a structure for forming p is formed by photolithography. -- An ion implantation mask 65 is used for the opening of the region 12 that reduces the surface electric field. The ion implantation mask 65 uses, for example, a photoresist. Ion implantation of p-type impurities is performed using the ion implantation mask 65 as a mask. The p-type impurities are, for example, boron (B) or aluminum (Al). ​ This indicates the state up to this point.

[0247] Next, after removing the ion implantation mask 65, a heat treatment is performed to diffuse the implanted p-type impurities. - The surface layer of the epitaxial layer 27 forms p -- Type 12 reduces surface electric field region. Due to p -- The impurity concentration in the reduced surface electric field region 12 is lower than that in the p-type well region 63A, therefore no p-type well is formed in the p-type well region 63A. -- The surface electric field is reduced in region 12 p. -- The bottom surface of the type-reduced surface electric field region 12 is formed more than n - The boundary depth between the n-type epitaxial layer 27 and the n-type drift layer 2. Additionally, p... -- The bottom surface of the p-type reduced surface electric field region 12 can be formed deeper than the boundary (dashed line) between the p-type pillar region 4A and the p-type well region 63A. -- The bottom surface of the reduced surface electric field region 12 can also be formed shallower than the boundary (dashed line) between the p-type pillar region 4A and the p-type well region 63A. The state up to this point is described in... ​ .

[0248] Next, an oxide film 28 is formed on the upper surface 100. The oxide film 28 can be, for example, a LOCOS film. The thickness of the oxide film 28 in the active region 30 is thinner than the thicker portion of the oxide film 28 formed on the outer periphery of the edge terminal region 40. Regarding the oxide film 28, the thicker portion is formed on the n... - On the upper surface of the epitaxial layer 27, the bottom surface of the thick portion of the oxide film 28 is formed to a depth 100 mm deeper than the upper surface. The end of the thick portion of the oxide film 28 on the active region 30 side is formed as a portion that continues from the end to the lower surface and is p- -- The surface electric field reduction region 12 is covered. Additionally, the other end of the thick portion of the oxide film 28 is formed as a continuous portion extending from the other end to the lower surface and is covered by n.- The epitaxial layer 27 covers the structure. The state up to this point is described in... ​ .

[0249] Next, a photoresist mask (not shown) with predetermined openings is formed on the surface of the oxide film 28 using photolithography. Then, using the photoresist mask as a mask, the openings are formed on the oxide film 28 by dry etching. Next, the photoresist mask is removed, and using the oxide film 28 as a mask, anisotropic dry etching is performed to form openings from n... - The upper surface of the epitaxial layer 27 extends from 100 through n - The epitaxial layer 27 reaches the trench 18A of the n-type drift layer 2. The state up to this point is recorded in... ​ .

[0250] Next, isotropic etching and sacrificial oxidation are performed while the oxide film 28 is attached. This process removes damage to trench 18A and rounds the bottom of trench 18A. The order of isotropic etching and sacrificial oxidation can be either performed first or secondarily. Afterward, the thin portion of the oxide film 28 used as the mask for forming trench 18A is removed. At this time, both the thin portion of the oxide film 28 and the sacrificial oxide film can be removed simultaneously. The trench after removing the oxide film 28 becomes trench 18B. Since the oxide film 28 has a thin portion and a thick portion at the edge terminal region 40, full-area etching is performed to remove the thin portion of the oxide film 28, retaining the thick portion of the oxide film at the edge terminal region 40. The sacrificial oxide film (not shown) can be removed together with the thin portion of the oxide film 28. Alternatively, the oxide film 28 can be removed using photolithography and etching techniques, thereby retaining the oxide film 28 at the edge terminal region 40. The oxide film retained in the edge terminal region 40 (the thicker portion of oxide film 28) becomes the field oxide film 13. ​ This indicates the state up to this point.

[0251] Next, along n - Type epitaxial layer 27, p -- A gate insulating film 7 is formed on the surface (upper surface 100) of the p-type well regions 63 and 63A, and on the inner wall of the trench 18B. This gate insulating film 7 can be formed by thermal oxidation at a temperature of approximately 1000°C in an oxygen atmosphere. Alternatively, the gate insulating film 7 can also be formed by deposition using a chemical reaction such as high-temperature oxidation (HTO).

[0252] Next, a polysilicon layer doped with, for example, phosphorus atoms is formed on the gate insulating film 7. This polysilicon layer is formed to fill the trench 18B. The polysilicon layer is patterned using photolithography and etching techniques, and a gate electrode 8 is formed inside the trench 18B, separated by the gate insulating film 7.

[0253] Alternatively, the polysilicon layer formed in the edge terminal region 40 can be selectively retained and used as the field plate 29 and the channel cut-off portion 62.

[0254] Field plate 29 is continuously formed in p -- The field plate 29 is located on the upper surface of the gate insulating film 7 (insulating film 66A) formed on the p-type low surface electric field region 12, the p-type well region 63A, and the p-type base region 5A (upper surface 100), and on the upper surface of the active region 30 side of the field oxide film 13. The field plate 29 is electrically connected to the gate electrode 8 and also has the function of gate wiring.

[0255] The channel cut-off portion 62 is continuously formed on the upper surface of the outer peripheral side of the field oxide film 13 and on the n - The upper surface of the gate insulating film 7 (insulating film 66B) on the epitaxial layer 27 (upper surface 100). It should be noted that the channel cut-off portion 62 is separated from the field plate 29 on the field oxide film 13.

[0256] Next, from n - The upper surface 100 of the epitaxial layer 27 (p-type well regions 63, 63A and n-type well regions) - Ion implantation 22 is performed on the surface of the epitaxial layer 27 to form p-type base regions 5 and 5A for p-type impurities. Examples of p-type impurities include boron (B) or aluminum (Al). At this time, in the n... - In the edge termination region 40 above the epitaxial layer 27, the field plate 29, the channel cutoff portion 62, and the field oxide film 13 function as a mask. Therefore, in n - The epitaxial layer 27 is not implanted with p-type impurities. Additionally, the gate electrode 8 also functions as a mask. The state up to this point is described in... ​ .

[0257] Next, the gate insulating film 7 formed on the upper surface 100 is removed. It should be noted that the removal of the gate insulating film 7 is permissible as long as the thickness of the gate insulating film 7 does not impede its use in forming the n described later. + The thickness of ion implantation in source region 6, for example Therefore, the removal of the gate insulating film 7 may not be necessary.

[0258] Next, p-type impurities are diffused through heat treatment, thereby increasing the concentration of n-type impurities. - p-type epitaxial layer 27, p-type well regions 63, 63A and p --The surface layer of the reduced surface electric field region 12 forms p-type base regions 5 and 5A. Through this heat treatment, an insulating film 66C is formed to cover the upper surface of the gate electrode 8, the field plate 29, and the channel cut-off portion 62, the gate electrode 8 including a polycrystalline silicon layer formed by filling trench 18B.

[0259] The p-type base region 5 overlaps with the p-type well region 63, and the bottom surface of the p-type base region 5 is shallower than the bottom surface of the p-type well region 63. The p-type base region 5A overlaps with the p-type well region 63A, and the bottom surface of the p-type base region 5A is shallower than the bottom surface of the p-type well region 63A.

[0260] The impurity concentrations of p-type base region 5 and p-type base region 5A can be equal. The impurity concentrations of p-type well region 63 and p-type well region 63A can be equal. The impurity concentration of p-type base region 5 is higher than that of p-type well region 63. In addition, the impurity concentration of p-type base region 5A is higher than that of p-type well region 63A. The p-type base regions 5 and 5A are formed to be in contact with the sidewall of trench 18B.

[0261] In the edge terminal region 40, since the oxide film 28, the field plate 29, and the channel cut-off portion 62 function as masks, the n area covered by the oxide film 28, the field plate 29, and the channel cut-off portion 62... - Type epitaxial layer 27 and p -- Boron (B) is not implanted in region 12, which reduces the surface electric field. Therefore, even if heat treatment is performed to diffuse the p-type impurities forming the p-type base regions 5 and 5A, the p-type impurities forming the p-type base regions 5 and 5A will not diffuse into the n-type base regions. - Type epitaxial layer 27 and p -- The diffusion in region 12 of the surface electric field is reduced. Therefore, in the edge terminal region 40, n - Type epitaxial layer 27 and p -- Region 12, which reduces the surface electric field, is retained.

[0262] Thus, in the third manufacturing method, after forming the trench 18B, a p-type base region 5 is formed, and the p-type base region 5 forms a channel. The state up to this point is described in... ​ .

[0263] Next, on the surface of the p-type base region 5, a mask (not shown) with the desired opening is formed using photolithography, for example, with a photoresist. Using this photoresist mask as a template, n-type impurities are ion implanted. Through this ion implantation, n-type impurities are formed on the surface layer of the p-type base region 5. + An n-type impurity was injected at position 6 of the source region. The injected n-type impurities were arsenic (As), phosphorus (P), etc.

[0264] Next, remove the parts that are needed to form n +The ion implantation mask used for the source region 6. Furthermore, on the surface of the p-type base region 5, for example, a photoresist can be used to form a mask with the desired opening using photolithography. P-type impurities are then implanted into the surface layer of the p-type base region 5, and these p-type impurities form with the n-type base region 6. + p in phase 6 of the source region ++ Type contact region 14. Additionally, p-type base region 5A can also be implanted to form a p-type base layer. ++ p-type impurities in contact region 14A. It should be noted that n-type impurities do not form on the surface layer of the p-type base region 5A in the edge terminal region 40. + Source area 6.

[0265] Next, the process of injecting into n is performed. + Type source region 6 and p ++ Heat treatment for impurity activation in contact regions 14 and 14A. The heat treatment for activating the implanted impurities has a shorter thermal history compared to the heat treatment for diffusion of the implanted impurities. Regarding the formation of n... + Type source region 6 and p ++ Regarding the order of ion implantation in contact regions 14 and 14A, either order is acceptable. The state up to this point is recorded in... ​ .

[0266] Next, in n - An interlayer insulating film 9 is formed over the entire upper surface (upper surface 100) of the epitaxial layer 27. The interlayer insulating film 9 is formed to cover, for example, a gate insulating film 7, a gate electrode 8, and an inductor 66C, with the insulating film 66C as a buffer. + Source region 6, p ++ Type contact region 14, p-type base region 5A, p ++ The device includes a contact area 14A, a field oxide film 13, a field plate 29, and a channel cutoff portion 62. The interlayer insulating film 9 is formed from, for example, BPSG, PSG, etc. Alternatively, the interlayer insulating film 9 can also be formed as a laminate by forming, for example, any one of HTO, NSG, and TEOS films under the BPSG (between the BPSG and the gate electrode 8). The thickness of the interlayer insulating film 9 can be approximately 1 μm.

[0267] Next, the interlayer insulating film 9 and the insulating film 66C are patterned using photolithography and etching techniques. In the active region 30, n is formed... + Type source region 6 and p ++ The contact hole 64A exposed on the surface of the contact area 14 (the boundary of the interlayer insulating film 9 covering the gate insulating film 7 formed along the inner wall of the trench 18B and the upper part of the gate electrode 8 is not shown). Additionally, a contact hole 64A is formed in the edge terminal region 40 to make p ++Contact holes 64B are exposed on the surface of contact area 14A. Furthermore, contact holes 64C are formed in the edge terminal area 40 to expose the surface of the field plate 29. Afterwards, heat treatment (reflow) is performed to planarize the interlayer insulating film 9. The state up to this point is described in... ​ .

[0268] Next, a metal film of aluminum or an aluminum-based alloy (Al-Si, Al-Cu, Al-Si-Cu) is sputtered to continuously cover the upper surface of the interlayer insulating film 9 by filling the contact holes 64A, 64B, and 64C. It should be noted that before forming the metal film, a barrier metal (not shown) comprising a titanium film (Ti), a titanium nitride film (TiN), or a stack of titanium and titanium nitride films (e.g., Ti / TiN) can be sputtered along the inner walls of the contact holes 64A, 64B, and 64C to the upper surface of the interlayer insulating film 9. Then, the metal film and the barrier metal (not shown) are patterned using photolithography and etching techniques to form the source electrode 10, the metal gate runner 61, and the gate electrode pads (not shown). It should be noted that the barrier metal may also be formed only within the contact holes 64A, 64B, and 64C.

[0269] In the active region 30, the source electrode 10 and the n exposed on the surface of the contact hole 64A + Type source region 6 and p ++ The contact area 14 is electrically connected. Additionally, in the edge terminal area 40, the source electrode 10 is connected to the p-type contact area exposed on the surface of the contact hole 64B. ++ Contact area 14A is electrically connected. Additionally, the metal gate runner 61 is electrically connected to the field plate 29 exposed on the surface of contact hole 64C and the gate electrode 8. The gate electrode pad (not shown) is electrically connected to the metal gate runner 61 and the gate electrode 8. It should be noted that tungsten plugs or the like can be embedded in contact holes 64A, 64B, and 64C through a barrier metal. Contact holes 64A, 64B, and 64C can be formed to... ​ The first manufacturing method shown also has a contact hole with a recess.

[0270] Next, by sputtering on n +A back electrode 11 is formed on the back side of the semiconductor substrate 1 (the back side of the semiconductor substrate). The back electrode 11 can be formed from a metal film such as nickel (Ni), titanium (Ti), gold (Au), silver (Ag), aluminum (Al), or an alloy with aluminum as the main component (Al-Si, Al-Cu, Al-Si-Cu). Alternatively, a multilayer film of metal films such as nickel, titanium, gold, silver, aluminum, or an alloy with aluminum as the main component (Al-Si, Al-Cu, Al-Si-Cu) can be formed (e.g., Ti / Ni / Au, Al / Ti / Ni / Au, etc.). After the back electrode 11 is formed, heat treatment is performed to form an n + The ohmic bonding between the semiconductor substrate 1 and the back electrode 11 is achieved. This completes the... ​ The SJ-MOSFET 50 is shown.

[0271] Thus, since n is only filled in the groove 25B of the p-type column - Ion implantation of a second type of conductivity impurity is performed in the region of the epitaxial layer 27, so p-type well regions 63 and 63A are not formed.

[0272] As explained above, according to the embodiment, n are provided in the edge terminal area 40. - Type epitaxial layer, and in n - A field oxide film 13 is formed on the surface of the epitaxial layer 27. Through n - Type epitaxial layer 27 will be from n - Type epitaxial layer 27 and p -- The depletion layer of the pn junction extends to n, reducing the surface electric field region 12. - The epitaxial layer 27 enables the SJ-MOSFET 50 to improve its breakdown voltage.

[0273] In other embodiments, by having a parallel pn structure 20B in the edge terminal region 40 with the width of the n-type pillar region 3B and the width of the p-type pillar region 4B being narrower than the width of the n-type pillar region 3 and the width of the p-type pillar region 4 in the active region 30, the depletion layer in the edge terminal region 40 can be easily extended, thereby enabling the withstand voltage of the edge terminal region 40 to be higher than that of the active region 30.

[0274] Furthermore, due to n - The low impurity concentration of the p-type epitaxial layer 27 makes it easy to control the diffusion of the p-type well regions 63 and 63A and the p-type base regions 5 and 5A, thereby suppressing the non-uniformity of the gate threshold voltage VTh.

[0275] Furthermore, since the p-type column region 4 is formed by simply depositing the p-type epitaxial layer instead of using the conventional trench filling method, it is not necessary to remove the surface p-type epitaxial layer using a CMP device or similar equipment, and it is also not necessary to form an n-type epitaxial layer on the surface after removing the p-type epitaxial layer. Consequently, the surface portion after filling the p-type column with the trench 25B does not require a planarization process using a CMP device or similar equipment. Therefore, the SJ structure can be easily formed, reducing manufacturing costs.

[0276] The above description uses the case where a MOS gate structure is formed on the first main surface of a silicon substrate as an example, but it is not limited to this. Various changes can be made to the type of semiconductor (e.g., silicon carbide (SiC)) and the orientation of the main surface of the substrate. Furthermore, in the embodiments of the present invention, a trench MOSFET is used as an example, but it is not limited to this. It can be applied to various semiconductor devices with different configurations, such as superjunction semiconductor devices like planar MOSFETs and superjunction semiconductor devices like IGBTs (Insulated Gate Bipolar Transistors). Although the first conductivity type is set to n-type and the second conductivity type to p-type in each embodiment of the present invention, the present invention also holds true even if the first conductivity type is p-type and the second conductivity type is n-type.

[0277] Industrial availability

[0278] As described above, the superjunction semiconductor device and the manufacturing method of the superjunction semiconductor device of the present invention are useful for high-voltage semiconductor devices used in power conversion devices and / or power supply devices for various industrial machinery.

Claims

1. A method for manufacturing a superjunction semiconductor device, characterized in that, The superjunction semiconductor device has an active region for current flow and a terminal structure disposed outside the active region and having a voltage-resistant structure forming therearound the active region. The manufacturing method includes: In the first step, a first semiconductor layer of a first conductivity type is formed on the front side of a semiconductor substrate of a first conductivity type, wherein the impurity concentration of the first semiconductor layer is lower than the impurity concentration of the semiconductor substrate. The second step involves forming a first trench from the surface of the first semiconductor layer; In the third step, a second semiconductor layer of a first conductivity type is formed on the surface of the first semiconductor layer and in the first trench, wherein the impurity concentration of the second semiconductor layer is lower than that of the first semiconductor layer. In the fourth step, impurities of the second conductivity type are implanted into the second semiconductor layer, thereby forming a well region of the second conductivity type inside the second semiconductor layer and forming a parallel pn structure. The parallel pn structure is a structure in which the first pillar of the first conductivity type and the second pillar of the second conductivity type are repeatedly and alternately arranged in a direction parallel to the front side, and the upper surface of the second pillar is in contact with the bottom surface of the well region. The fifth step involves forming a second trench that penetrates the second semiconductor layer and reaches the first pillar; The sixth step involves forming a second semiconductor region of a second conductivity type on the surface of the parallel pn structure in the active region; The seventh step involves forming a gate insulating film and a gate electrode inside the second trench; and In the eighth step, a first semiconductor region of a first conductivity type is selectively formed on the surface layer of the second semiconductor region in the active region.

2. The method for manufacturing a superjunction semiconductor device according to claim 1, characterized in that, In the sixth step, the bottom surface of the second semiconductor region is formed to be shallower than the bottom surface of the well region.

3. The method for manufacturing a superjunction semiconductor device according to claim 1, characterized in that, In the sixth step, the impurity concentration in the well region is set to be lower than that in the second semiconductor region.

4. The method for manufacturing a superjunction semiconductor device according to claim 1, characterized in that, In the fourth step, impurities of the second conductivity type are implanted into the second semiconductor layer within the first trench.

5. The method for manufacturing a superjunction semiconductor device according to claim 1, characterized in that, In the fourth step, impurities of the second conductivity type are implanted into the surface layer of the second semiconductor layer on the surface of the first semiconductor layer.

6. The method for manufacturing a superjunction semiconductor device according to claim 1, characterized in that, In the fourth process, the second column is also formed in the terminal structure section.

7. The method for manufacturing a superjunction semiconductor device according to claim 1, characterized in that, The sixth step is performed before the fifth step.

8. The method for manufacturing a superjunction semiconductor device according to claim 1, characterized in that, In the fourth step, impurities of the second conductivity type are implanted only in the second semiconductor layer within the first trench.

9. A superjunction semiconductor device, characterized in that, It has an active region for current flow and a terminal structure portion disposed outside the active region and having a withstand voltage structure, the withstand voltage structure surrounding the active region. The superjunction semiconductor device includes: A first semiconductor layer of a first conductivity type is disposed on the front side of a semiconductor substrate of the first conductivity type, and the impurity concentration is lower than that of the semiconductor substrate. A parallel pn structure is disposed inside the first semiconductor layer and is formed by repeatedly alternating first pillars of a first conductivity type and second pillars of a second conductivity type in a direction parallel to the front side. A second semiconductor region of a second conductivity type is disposed on the surface layer of the parallel pn structure of the active region; A first semiconductor region of a first conductivity type is selectively disposed on the surface layer of the second semiconductor region of the active region; The second trench penetrates the first semiconductor region and the second semiconductor region and reaches the first pillar; as well as The gate electrode is disposed inside the second trench, separated by a gate insulating film. A well region of a second conductivity type is disposed inside the first semiconductor layer. The lower surface of the well region is in contact with the upper surface of the second pillar, and the bottom surface of the well region is deeper than the bottom surface of the second semiconductor region. The width of the upper surface of the well region is wider than the width of the second pillar. The surface of the first semiconductor layer in the terminal structure has a second semiconductor layer of a first conductivity type with an impurity concentration lower than that of the first semiconductor layer. The surface of the first semiconductor layer in the terminal structure has a second conductivity type region that reduces the surface electric field, where the impurity concentration is lower than that of the well region. The bottom surface of the region for reducing the surface electric field is set deeper than the boundary between the first semiconductor layer and the second semiconductor layer.

10. The superjunction semiconductor device according to claim 9, characterized in that, The impurity concentration in the well region is lower than that in the second semiconductor region.

11. The superjunction semiconductor device according to claim 9, characterized in that, The parallel pn structure is also provided in the terminal structure section.

12. The superjunction semiconductor device according to claim 9, characterized in that, The repeating pitch of the parallel pn structure in the terminal structure is narrower than the repeating pitch of the parallel pn structure in the active region.

13. The superjunction semiconductor device according to claim 9, characterized in that, The well region and the second semiconductor region are in contact with the sidewall of the second trench.

14. The superjunction semiconductor device according to claim 9, characterized in that, The second semiconductor layer is also disposed between the well region located on the outermost side of the terminal structure and the reduced surface electric field region.

15. The superjunction semiconductor device according to claim 9, characterized in that, The impurity concentration in the well region is higher than that in the second column.

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