Integrated circuit including vertical channel structure and layout method of the integrated circuit

Abstract

Provided are an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells and a layout method for the integrated circuit, wherein a distance between a pair of second vertical channel structures in a first cell and an adjacent pair of first vertical channel structures in a second cell is the same as a distance between the pair of first vertical channel structures in the first cell and a pair of second vertical channel structures arranged adjacent to the pair of first vertical channel structures, and the pair of second vertical channel structures in the first cell and the adjacent pair of first vertical channel structures in the second cell both face a cell boundary between the first cell and the second cell.

Description

Technical Field

[0001] The inventive concept relates to integrated circuits, and more particularly, to an integrated circuit implemented in a semiconductor cell including a transistor having a vertical channel structure. Background Art

[0002] An integrated circuit can be designed based on one or more cells. Specifically, the layout of the integrated circuit can be generated by placing one or more cells based on information that defines the integrated circuit and wiring the cells. Such cells can be pre-designed and stored in a cell library and can be referred to as standard cells.

[0003] In recent semiconductor manufacturing processes, there is a need to reduce the size of a pattern included in a cell and the size of the cell. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor unit including a plurality of transistors having a vertical channel structure.

[0005] Embodiments also provide methods of forming semiconductor units.

[0006] Note that the present invention is not limited to the embodiments described herein, and the present invention will become more apparent to those skilled in the art by referring to the detailed description of the embodiments presented below.

[0007] According to one embodiment, an integrated circuit is provided, comprising a first unit and a second unit adjacent to each other in a first direction, wherein the first unit may comprise: a first lower source / drain region and a second lower source / drain region, extending on a substrate in the first direction and arranged to be spaced apart from each other in the second direction; a pair of first vertical channel structures, positioned to intersect the first lower source / drain region and the second lower source / drain region in the second direction; a pair of second vertical channel structures, positioned to intersect the first lower source / drain region and the second lower source / drain region in the second direction, and arranged to be spaced apart from the pair of first vertical channel structures in the first direction; a pair of first upper source / drain regions and a pair of second upper source / drain regions, respectively positioned on the pair of first vertical channel structures and the pair of second vertical channel structures; a first to the fourth gate electrode, respectively surrounding the side surfaces of the pair of first vertical channel structures and the pair of second vertical channel structures; a connecting metal layer, connected to the first to fourth gate electrodes; an input wiring, connected to at least one gate electrode of the first to fourth gate electrodes through a gate path to receive an input signal; and an output wiring, connected to the pair of second upper source / drain regions through an upper source / drain path, wherein, in a first direction, a distance between the pair of second vertical channel structures of the first unit and an adjacent pair of first vertical channel structures in the second unit is the same as a distance between the pair of first vertical channel structures and the pair of second vertical channels, and the pair of second vertical channel structures of the first unit and the adjacent pair of first vertical channel structures in the second unit both face a cell boundary between the first unit and the second unit.

[0008] According to one embodiment, an integrated circuit is provided, which includes a first unit and a second unit adjacent to each other in a first direction. Each of the first unit and the second unit may include: a first fin region and a second fin region, which are positioned to be spaced apart from each other in the first direction and extend in the second direction; a first vertical channel structure and a second vertical channel structure, which are arranged to be spaced apart from each other in the second direction on the first fin region; a third vertical channel structure and a fourth vertical channel structure, which are arranged to be spaced apart from each other in the second direction on the second fin region; first to fourth upper source / drain regions, which are respectively positioned on the first to fourth vertical channel structures; a first lower source / drain region, which extends in the first direction and is positioned below the first vertical channel structure and the third vertical channel structure; a second lower source / drain region, which extends in the first direction and is positioned below the second vertical channel structure and the fourth vertical channel structure; and first to fourth gate electrodes, which are between the first to fourth upper source / drain regions and the first and second lower source / drain regions. respectively surround the side surfaces of the first to fourth vertical channel structures; a spacer layer formed between the first to fourth vertical channel structures and the first and second lower source / drain regions; and a connecting metal layer placed between the first to fourth vertical channel structures and connected to at least one of the first to fourth gate electrodes, wherein the distance separating the connecting metal layer and the first and second lower source / drain regions in the first cell from the cell boundary between the first cell and the second cell is equal to the distance separating the connecting metal layer and the first and second lower source / drain regions in the second cell from the cell boundary, and wherein, in a first direction, the distance between the second fin region in the first cell and the first fin region in the second cell is equal to the distance between the first fin region and the second fin region in the first cell or the second cell, and the second fin region in the first cell and the first fin region in the second cell both face the cell boundary.

[0009] According to one embodiment, a layout method for an integrated circuit is provided, the integrated circuit including a first unit and a second unit adjacent to the first unit in a first direction. The method may include: forming a first lower source / drain region and a second lower source / drain region on a substrate, the first lower source / drain region and the second lower source / drain region extending in the first direction and spaced apart from each other in the second direction; patterning a first fin region and a second fin region, the first fin region and the second fin region extending in the second direction and intersecting the first lower source / drain region and the second lower source / drain region; forming a first vertical channel structure and a second vertical channel structure on the first fin region to correspond to the first lower source / drain region and the second lower source / drain region, respectively, and forming a third vertical channel structure and a fourth vertical channel structure on the second fin region to correspond to the first lower source / drain region and the second lower source / drain region, respectively; forming first to fourth gate electrodes, the first to fourth gate electrodes respectively surrounding side surfaces of the first to fourth vertical channel structures; forming a connecting metal layer, the connecting metal layer connecting the first to fourth gate electrodes; forming first to fourth upper source / drain structures on the first to fourth vertical channel structures, respectively. region; forming at least one first upper source / drain contact and at least one second upper source / drain contact on at least two upper source / drain regions among the first to fourth upper source / drain regions; forming at least one gate contact on the connecting metal layer; forming a first source / drain path and a second source / drain path on the first upper source / drain contact and the second upper source / drain contact, respectively, and forming a gate path on the gate contact; forming an input wiring, the input wiring extending in the second direction and connected to the gate path; and forming an output wiring, the output wiring extending in the second direction and connected to at least one source / drain path of the first source / drain path and the second source / drain path, wherein, in the first direction, a distance between the second fin region in the first cell and an adjacent fin region in the second cell is the same as a distance between the first fin region and the second fin region, and the second fin region in the first cell and the adjacent fin region in the second cell both face a cell boundary between the first cell and the second cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other embodiments and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is a plan view of a layout of a standard cell for an integrated circuit according to one embodiment, the standard cell being an inverter.

[0012] Figure 2 According to one embodiment, Figure 1 The cross-sectional view is taken along the line AA' shown.

[0013] Figure 3According to one embodiment, Figure 1 A cross-sectional view taken along line BB' is shown.

[0014] Figure 4 According to one embodiment, Figure 1 A cross-sectional view taken along line CC' is shown.

[0015] 5A to 5I A process of forming a standard cell for an inverter in a plan view according to an embodiment is shown.

[0016] Figure 6 is a layout of a plurality of standard cells for an integrated circuit in a plan view according to an embodiment.

[0017] Figure 7A This is a schematic diagram of a NAND circuit. Figures 7B to 7D A layout of a standard cell for a NAND circuit in a plan view according to an embodiment is shown.

[0018] Figure 8A This is a schematic diagram of a NOR circuit. Figures 8B to 8D A layout of a standard cell for a NOR circuit in plan view is shown according to an embodiment.

[0019] Figure 9A is a schematic diagram of an AND-OR-inverter (AOI) circuit in plan view, Figures 9B to 9D A layout of a standard cell for an AOI circuit in a plan view according to an embodiment is shown.

[0020] Figure 10A is a schematic diagram of the buffer circuit, FIG. 10B to FIG. 10D A layout of a standard cell for a buffer circuit in a plan view according to an embodiment is shown. DETAILED DESCRIPTION

[0021] Hereinafter, various embodiments according to the present inventive concept will be described with reference to the accompanying drawings. The embodiments described herein are all example embodiments, and thus, the present inventive concept is not limited thereto and can be implemented in various other forms.

[0022] It will be understood that when an element or layer is referred to as being “on,” “over,” “on,” “below,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly above, directly on, directly below, directly below, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly below,” “directly below,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. Like numbers refer to like elements throughout.

[0023] In the following description, various embodiments of integrated circuits formed on a substrate, such as a semiconductor substrate, are provided. The integrated circuit has a layout that includes one or more cells. These cells can be pre-designed for reuse in separate integrated circuit designs. An effective integrated circuit design layout can include various types of pre-designed cells and pre-defined rules regarding the arrangement of cells to enhance the performance of the integrated circuit and reduce the area of ​​the integrated circuit. These cells can be referred to as standard cells.

[0024] An integrated circuit according to some embodiments may include one or more standard cells that are placed in the integrated circuit layout according to predefined rules. Such standard cells are reused in the integrated circuit design. Therefore, standard cells are designed in advance based on manufacturing technology and stored in a standard cell library. An integrated circuit designer can search for such standard cells, include them in the integrated circuit design, and place them in the integrated circuit layout according to predefined placement rules.

[0025] Standard cells may include various basic circuits commonly used in digital circuit design for electronic devices, such as central processing units (CPUs), graphics processing units (GPUs), and systems on chips (SoCs), but are not limited thereto. Basic circuits included in standard cells may include, but are not limited to, circuits for inverters, AND, NAND, OR, XOR, and NOR. Standard cells may also include other commonly used circuit blocks, such as flip-flops and latches.

[0026] Figures 1 to 4A cell for an inverter circuit formed of a plurality of vertical field effect transistors (VFETs) having a vertical channel structure is shown. Figures 1 to 4 In the current embodiment of FIG, each vertical channel is shown to include two vertical channel structures, but the inventive concept is not limited thereto. That is, the vertical channel of the VFET according to the embodiment may include three or more vertical channel structures.

[0027] Figure 1 FIG is a plan view of a layout of a cell for an integrated circuit according to one embodiment, the cell being an inverter. Figure 1 In FIG, the unit is shown from the front-end of the line (FEOL) to the back-end of the line (BEOL). Figure 2 It is along Figure 1 The cross-sectional view is taken along the line AA' shown. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB' is shown. Figure 4 It is along Figure 1 The cross-sectional view taken along the line CC' is shown. Figures 1 to 4 , the integrated circuit may be formed of at least one cell, and the at least one cell may include at least one VFET.

[0028] The cell for the inverter may include an n-type metal oxide semiconductor field effect transistor (hereinafter referred to as "NMOS") and a p-type metal oxide semiconductor field effect transistor (hereinafter referred to as "PMOS"). The gates of the PMOS and the NMOS are commonly connected to the input node Vin, and one of the source / drain regions of the PMOS is connected to the power supply voltage Vdd. The other of the source / drain regions of the PMOS and one of the source / drain regions of the NMOS are commonly connected to the output node Vout. The other of the source / drain regions of the NMOS is grounded. As described below, the above-mentioned NMOS and PMOS of the inverter in the cell according to the current embodiment can be implemented as VFETs.

[0029] The integrated circuit may include multiple fin regions F1 and F2 on a substrate 100. Substrate 100 may be a semiconductor substrate including silicon, germanium, silicon germanium, or the like, or may be a compound semiconductor substrate. Fin regions F1 and F2 may have a pillar shape protruding vertically from substrate 100. Fin regions F1 and F2 may also have a strip shape extending in the Y direction. Vertical channel structures FF11, FF12, FF21, and FF22 are formed from fin regions F1 and F2 to form vertical channels for respective VFETs. A lower active region 111 may be formed below the vertical channel structures FF11 and FF21, and a lower active region 112 may be formed below the vertical channel structures FF12 and FF22. In addition, an upper active region 115 may be formed above the vertical channel structures FF11 and FF21, and an upper active region 116 may be formed above the vertical channel structures FF12 and FF22. Fin regions F1 and F2 are spaced equidistantly from each other in the X direction and may be parallel to each other in a strip shape extending in the Y direction.

[0030] According to the current embodiment, the lower active regions 111 and 112 may be partial regions of the substrate 100. Specifically, according to the current embodiment, the lower active region 111 may be a source / drain region below the vertical channel structures FF11 and FF21, the source / drain region being a region on the substrate 100 doped with P-type impurities (e.g., boron). The lower active region 112 may be a source / drain region below the vertical channel structures FF12 and FF22, the source / drain region being a region on the substrate 100 formed by being doped with N-type impurities (e.g., arsenic or phosphorus). Alternatively, according to one embodiment, the lower active regions 111 and 112 may be doped with N-type impurities and P-type impurities, respectively.

[0031] The lower active regions 111 and 112 may be spaced apart from each other in the Y direction while extending in the X direction. An active region separation film may be provided between the lower active regions 111 and 112. The lower active regions 111 and 112 may be isolated by, for example, shallow trench isolation (STI) of the substrate 100.

[0032] The lower active regions 111 and 112 can be divided into an upper portion UP and a lower portion LP. The lower active regions 111 and 112 have the same area as the lower portion LP in plan view, but may have an upper portion UP region that partially protrudes in the Z direction. The upper portion UP of the lower active regions 111 and 112 has a shorter width in the X and Y directions than the lower portion LP of the lower active regions 111 and 112. The upper portion UP of the lower active regions 111 and 112 has a strip shape extending in the Y direction corresponding to the fin regions F1 and F2.

[0033] The vertical channel structures FF11, FF12, FF21, and FF22 may be placed on the lower active regions 111 and 112. The vertical channel structures FF11, FF12, FF21, and FF22 may have a planar shape substantially the same as the upper portion of the lower active regions 111 and 112. The vertical channel structures FF11, FF12, FF21, and FF22 may be semiconductor pillars grown using the upper portion UP of the lower active regions 111 and 112 as a seed layer. The semiconductor material of the vertical channel structures FF11, FF12, FF21, and FF22 may be the same as the semiconductor material of the substrate 100, such as undoped silicon, or may be different therefrom.

[0034] The spacer layer SL may be formed on the lower active regions 111 and 112. The spacer layer SL may be provided on the sidewalls of the upper portions UP of the lower active regions 111 and 112. The level of the upper surface of each spacer layer SL may be the same as or higher than the level of the upper surface of the upper portions UP of the lower active regions 111 and 112. The level of the upper surface of each spacer layer SL may be the same as or higher than the level of the bottom surfaces of the vertical channel structures FF11, FF12, FF21, and FF22. The spacer layer SL may be an insulator and may include, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0035] Gate electrodes 210, 211, 220, and 221 may be provided on the spacer layer SL. The gate electrodes 210, 211, 220, and 221 may surround the channel regions formed by the vertical channel structures FF11, FF12, FF21, and FF22, respectively. The gate electrodes 210, 211, 220, and 221 may be separated from the lower active regions 111 and 112 by the spacer layer SL.

[0036] The upper active regions 115 and 116 may protrude vertically upward from the level of the upper surfaces of the gate electrodes 210, 211, 220, and 221. The level of the upper surfaces of the gate electrodes 210, 211, 220, and 221 may be the same as or lower than the level of the bottom surfaces of the upper active regions 115 and 116. As an example, the gate electrodes 210, 211, 220, and 221 may include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0037] The gate insulating film 219 may be disposed between the gate electrodes 210, 211, 220, and 221 and the vertical channel structures FF11, FF12, FF21, and FF22. The gate insulating film 219 may include a gate dielectric pattern (not shown) extending from the sidewalls of the vertical channel structures FF11, FF12, FF21, and FF22 to the upper surface of the spacer layer SL. Therefore, the gate insulating film 219 may also be disposed on the bottom surfaces of the gate electrodes 210, 211, 220, and 221 and the inner sidewalls of the gate electrodes 210, 211, 220, and 221. At least one surface of the gate insulating film 219 may contact the bottom surface and at least one side surface of the gate electrodes 210, 211, 220, and 221. The gate insulating film 219 may include a silicon oxide film, a silicon oxynitride film, and / or a high dielectric constant material. As an example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0038] The gate contact 161 may be formed on a gate connection structure (not shown) between the vertical channel structures FF11 and FF12 in the Y direction. The gate contact 161 is connected to the gate electrodes 210 and 211 through the gate connection structure and may be formed as shown in FIG. Figure 1 It is shown formed to be spaced apart from the vertical channel structures FF11 , FF12 , FF21 , and FF22 .

[0039] The fin region of the integrated circuit can form a vertical transistor, or VFET, in which carriers move in the vertical direction (Z direction). When a voltage is applied to the gate electrodes 210, 211, 220, and 221 to turn on the vertical transistor, carriers can move from the lower active regions 111 and 112 to the upper active regions 115 and 116 through the vertical channel structures FF11, FF12, FF21, and FF22. In other words, the vertical channel structures FF11, FF12, FF21, and FF22 can serve as channels for both NMOS and PMOS transistors.

[0040] The gate contact 161 may be connected to the input wiring IM through the gate via 165. The input wiring IM extends in the Y direction but is formed to be spaced apart from the power wirings PM1 and PM2 in the Y direction. According to the present embodiment, the power wiring PM1 may provide a power supply voltage Vdd, and the power wiring PM2 may be grounded.

[0041] A vertical transistor such as a VFET including a vertical channel structure has a form in which a gate electrode surrounds all sidewalls of the vertical channel structure and may also be referred to as a gate-all-around transistor or a vertical fin field effect transistor (VTFET).

[0042] Upper active regions 115 and 116, also referred to herein as upper source / drain regions 115 and 116, may be formed on each of the vertical channel structures FF11, FF12, FF21, and FF22. The upper source / drain region 115 may be doped with the same material as the lower source / drain region 111. The upper source / drain region 116 may be doped with the same material as the lower source / drain region 112.

[0043] The upper source / drain contacts 120 and 130 may be formed to be spaced apart from each other in the Y direction. The distance between the upper source / drain contacts 120 and 130 in the Y direction may be equal to or greater than the distance between the vertical channel structures FF11 (or FF21) and FF12 (or FF22) in the Y direction. The upper source / drain contacts 120 may be formed to completely cover the upper source / drain regions 115 on the vertical channel structures FF11 and FF21 and may be connected to each upper source / drain region 115. The upper source / drain contacts 130 may be formed to completely cover the upper source / drain regions 116 on the vertical channel structures FF12 and FF22 and may be connected to each upper source / drain region 116. A contact insulating film 121 may also be provided on the bottom surfaces of the upper source / drain contacts 120 and 130 and on the inner sidewalls of the upper source / drain contacts 120 and 130. At least one surface of the contact insulating film 121 may contact the bottom surface and at least one side surface of the upper source / drain contacts 120 and 130. The contact insulating film 121 may include a silicon oxide film, a silicon oxynitride film, and / or a high-k dielectric material. As an example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead-scandium-tantalum oxide, and lead-zinc niobate.

[0044] An interlayer insulating layer 101 may be formed between the upper source / drain contacts 120 and 130 and between the upper source / drain region 115 and the upper source / drain region 116. The interlayer insulating layer 101 may include a low-k dielectric material.

[0045] The output wiring OM may be electrically connected to the upper source / drain contacts 120 and 130 through vias 167-1 and 167-2 formed on the upper source / drain contacts 120 and 130. Each of the vias 167-1 and 167-2 and the output wiring OM may be disposed on a plane together with the interlayer insulating layers 102 and 103.

[0046] 5A to 5I A process of forming a cell for an inverter in a plan view according to an embodiment is shown. 5A to 5I The units from FEOL to BEOL are shown.

[0047] 5A to 5I The formation of Figure 1 According to the current embodiment, the inverter may include a pair of PMOS and a pair of NMOS.

[0048] exist Figure 5A , lower active regions 111 and 112 are defined on a substrate 100 to form lower source / drain regions by doping impurities therein using an ion implantation process or a diffusion process. The substrate 100 may be formed of bulk silicon. For example, although the substrate 100 may include a silicon substrate or Ge, SiGe, SiC, GeP, GeN, InGaAs, GaAs, InSb, InAs, GaSb, and InP, the substrate 100 may include materials other than silicon that are not limited thereto. The substrate 100 may be part of a bulk silicon wafer. The substrate 100 may be formed of silicon on insulator (SOI). The substrate 100 may be a silicon portion of an SOI wafer. The substrate 100 according to the current embodiment may also refer to a semiconductor layer formed on a base substrate by epitaxial growth.

[0049] The lower active regions 111 and 112 may be formed to be spaced apart from each other in the Y direction. An active region separation film 113 - 1 may be disposed between the lower active region 111 and the lower active region 112 .

[0050] According to the current embodiment, the lower active regions 111 and 112 can be formed by etching the substrate 100 to a desired depth using a hard mask pattern (not shown) as an etching mask on the substrate. Subsequently, a semiconductor material layer is formed by epitaxial growth in the recessed region defined by the semiconductor etching, and the lower active region 111 is doped with P-type impurities for PMOS, and the lower active region 112 can be doped with N-type impurities for NMOS. Alternatively, according to some embodiments, the lower active regions 111 and 112 can be doped with N-type impurities and P-type impurities, respectively.

[0051] The P-type impurity is formed of a material such as boron, aluminum, and / or gallium, and the N-type impurity is formed of a material such as phosphorus, arsenic, and / or antimony.

[0052] The lower active regions 111 and 112 may be spaced apart from the boundary of the cell by a distance W1 in the X direction. According to an embodiment, because the lower active regions 111 of two adjacent cells are each spaced apart by W1 from the boundary between the two cells, the distance between the lower active regions 111 of the two cells may be 2W1. According to an embodiment, each of the lower active regions 111 and 112 of a cell may be formed to have a width W2 in the X direction. The lower active regions 111 and 112 may be spaced apart from each other by a distance W3 in the Y direction.

[0053] The active region separation film 113-1 may extend in the X direction and may fill the trench that divides the lower active regions 111 and 112. The trench may be filled with an insulating material for forming shallow trench isolation (STI). That is, the active region separation film 113-1 will be interpreted as an insulating material film provided inside the cell.

[0054] Furthermore, at the boundary between two adjacent cells, a boundary separation film 113-2 may be included between the lower active regions 111 and 112 of the first cell and the lower active regions 111 and 112 of the second cell. The boundary separation film 113-2 may extend in the Y direction and may fill a trench. The trench may be filled with an insulating material. In other words, the boundary separation film will be interpreted as an insulating material film provided on the periphery of the cell.

[0055] exist Figure 5B In the embodiment, fin regions F1 and F2 may be patterned on substrate 100 and lower active regions 111 and 112. Fin regions F1 and F2 may be arranged to intersect active regions 111 and 112 and active region separation film 113-1 while extending in the Y direction. Fin region F1 may be spaced apart from fin region F2 by 1 contact polysilicon pitch (1CPP). "CPP" is also referred to as "contact polysilicon pitch" or "critical polysilicon pitch." The distance between fin regions F1 and F2 may refer to the distance between imaginary Y-direction center lines of fin regions F1 and F2.

[0056] The distance between fin regions in a plurality of cells may be the same. That is, in a first cell and a second cell adjacent to each other, the distance between the fin regions (or the outermost fin regions) closest to the boundary between the two cells may be the same as the distance between two adjacent fin regions included in the first cell. That is, each of the adjacent cells can be independently provided without a cell separation film or diffusion prevention region formed as a dummy at the cell boundary.

[0057] The lower source / drain regions 111 and 112 may be formed in the lower active regions 111 and 112 through an ion implantation process. Therefore, the lower active regions 111 and 112 may be referred to herein as lower source / drain regions 111 and 112, respectively.

[0058] Reference Figure 5C , in a plan view, vertical channel structures FF11, FF12, FF21, and FF22 may be formed in the fin regions F1 and F2 inside the lower source / drain regions 111 and 112. The fin regions F1 and F2 outside the vertical channel structures FF11, FF12, FF21, and FF22 may be wet-etched away using a mask, thereby leaving only the vertical channel structures FF11, FF12, FF21, and FF22 in the fin regions F1 and F2. However, in Figure 5B and Figure 5CIn the figure, for the convenience of description, the fin regions F1 and F2 are still shown as including the wet-etched portions. Figure 2-Figure 4 The spacer layer SL is shown.

[0059] According to an embodiment, if there is a cell boundary between two adjacent fin regions, the STI film may be positioned between the two adjacent fin regions. According to an embodiment, if there is no cell boundary between the two adjacent fin regions, the STI film may not exist between the two adjacent fin regions.

[0060] A pair of vertical channel structures FF11 and FF12 may be spaced apart from each other by a distance W5 in the Y direction (refer to FIG. Figure 5H A pair of vertical channel structures FF21 and FF22 may be spaced apart from each other by the same distance W5 in the Y direction (refer to Figure 5H ).

[0061] Each of the lower source / drain regions 111 and 112 may include a recess RS formed in an upper portion thereof. The recess RS may define an upper portion UP and a lower portion LP of the lower source / drain regions 111 and 112. A spacer layer SL filling the recess RS may be provided on the upper portion of the lower source / drain regions 111 and 112. The spacer layer SL may be formed on the upper surface of the STI film.

[0062] Each of the lower source / drain regions 111 and 112 is provided to extend in the Y direction and may be connected to a bottom contact to be described later.

[0063] Reference Figure 5D , gate electrodes 210, 211, 220, and 221 may be formed to surround the vertical channel structures FF11, FF12, FF21, and FF22, respectively. Each of the gate electrodes 210, 211, 220, and 221 may have a bar shape or a line shape extending in the Y direction.

[0064] Reference Figure 5E , a connection metal layer 200 may be formed to connect the gate electrode 210 and the gate electrode 211 and to connect the gate electrode 220 and the gate electrode 221. The connection metal layer 200 may be formed to partially overlap each of the vertical channel structures FF11, FF12, FF21, and FF22.

[0065] According to some embodiments, gate electrode 210 and gate electrode 211 may be connected to each other, and gate electrode 220 and gate electrode 221 may be connected to each other. According to some embodiments, gate electrode 210 and gate electrode 211 are not connected and may be separated, and gate electrode 220 and gate electrode 221 are not connected and may be separated and serve as separate electrodes.

[0066] Reference Figure 5FAccording to the current embodiment, when the connection metal layer 200 is cut at the boundary of the cell to be separated from the adjacent cell, the separated active areas 111 and 112 and the connection metal layer 201 can be electrically independent of the adjacent cell. In the figure, the connection metal layer 200 can be cut to be spaced W1 away from the boundary of the cell on both side surfaces. The connection metal layer 201 after cutting according to the current embodiment can have a width of W2 in the X direction, and its two side surfaces can be spaced W1 away from the cell boundary. For clarity of the illustration, the two side surfaces of the connection metal layer 201 are not completely aligned with the corresponding side surfaces of the active areas 111 and 112.

[0067] exist Figure 5G In the embodiment, a gate contact 161 may be formed on the connection metal layer 201 intersecting the fin region F1. In addition, upper source / drain contacts 120 and 130 may be formed on the upper source / drain regions 115 and 116, respectively. In addition, lower source / drain contacts 151 and 152 may be formed on the lower source / drain regions 111 and 112 extending along the Y direction.

[0068] The upper source / drain contact 120 extends in the X direction to intersect both the vertical channel structure FF11 and the vertical channel structure FF21, and may be formed to have a width that is the same as or narrower than the width W2 of the lower active region 111 in the X direction. The upper source / drain contact 130 extends in the X direction to intersect both the vertical channel structure FF12 and the vertical channel structure FF22, and may be formed to have a width that is the same as or narrower than the width W2 of the lower active region 112 in the X direction.

[0069] The upper source / drain contact 120 may be formed to overlap at least a portion of the upper source / drain region 115 in the Y direction. That is, the distance W4 between the upper source / drain contact 120 and the upper source / drain contact 130 in the Y direction may be the same as or greater than the distance W5 between the vertical channel structure FF11 and the vertical channel structure FF12.

[0070] Lower source / drain contacts 151 and 152 may be formed to be electrically connected to the lower source / drain regions 111 and 112, respectively. The lower source / drain contacts 151 and 152 may include a conductive material such as a metal.

[0071] According to the current embodiment, the upper source / drain contacts 120 and 130 and the lower source / drain contacts 151 and 152 may include the same material. According to some embodiments, the upper source / drain contacts 120 and 130 and the lower source / drain contacts 151 and 152 may be formed simultaneously in the same process. The upper source / drain contacts 120 and 130 and the lower source / drain contacts 151 and 152 may be formed substantially in the same manner as shown in FIG. Figure 2 and Figure 3 The same height as shown is formed on the upper surface of the substrate 100.

[0072] exist Figure 5H In the embodiment, a plurality of vias 165 , 163 , 167 - 1 , and 167 - 2 may be formed on upper surfaces of the gate contact 161 , the lower source / drain contacts 151 and 152 , and the upper source / drain contacts 120 and 130 , respectively.

[0073] exist Figure 5I In the embodiment, a plurality of metal wirings may be formed to correspond to the vias 165, 163, 167-1, and 167-2.

[0074] Input wiring IM may be formed on gate via 165 to extend in the Y direction to connect to gate contact 161 through gate via 165. Output wiring OM may be formed on upper source / drain via 167-1 and upper source / drain via 167-2 to extend in the Y direction to connect to upper source / drain contacts 120 and 130 simultaneously.

[0075] The power wiring PM1 is provided on the lower source / drain contact 151 to be connected to the lower source / drain region 111 and may be connected through at least one lower source / drain via 163. The power wiring PM2 is provided on the lower source / drain contact 152 to be connected to the lower source / drain region 112 and may be connected through at least one additional lower source / drain via 163.

[0076] Figure 6 is a layout of multiple cells for an integrated circuit in plan view according to one embodiment.

[0077] The cell according to the present embodiment may include at least one PMOS and at least one NMOS formed on at least two fin regions. That is, the cell may include a multi-gate NMOS and a multi-gate PMOS. Here, the PMOS and NMOS may be VFETs.

[0078] Figure 6 An integrated circuit is shown, which is formed of seven cells CELL1 to CELL7 including fin regions F1 to F12. For ease of explanation, it is assumed that each of CELL1 to CELL7 is implemented as a single-height cell including lower active regions 111 and 112 and at least two vertical channel structures between two power wirings PM1 and PM2 or PM2 and PM3.

[0079] According to various embodiments, the cell may be implemented as a multi-height cell including at least three or more power wirings and at least two active regions.

[0080] Reference Figure 6, the lower active regions 111 and 112 of the cell, which serve as the lower source / drain regions, are formed to have a predetermined distance from the adjacent cell. Based on the boundary between CELL1 and CELL2 according to the current embodiment, the lower active regions 111 and 112 of CELL1 can be formed to be spaced apart from the corresponding lower active regions 111 and 112 of CELL2 in the X direction by a preset minimum distance 2W1.

[0081] The connection metal layer 200 is cut by the metal cutting pattern 300 to have a predetermined distance based on the boundary between CELL1 and CELL2. The width (length in the X direction) of the metal cutting pattern 300 may be less than or equal to 2W1. According to the current embodiment, the connection metal layer 201 of CELL1 after cutting may be formed to be spaced apart from the connection metal layer 201 of CELL2 after cutting by a predetermined distance greater than 2W1.

[0082] According to the embodiments described herein, the distance between two facing outermost fin regions of two adjacent cells is 1 CPP, which may be equal to or greater than the distance between two adjacent fin regions in each cell. Figure 6 In the embodiment, the distance between fin region F2 of cell 1 and fin region F3 of cell 2 according to the current embodiment is 1CPP, which may be the same as the distance between other fin regions (e.g., F1 and F2, and F3 and F4) of cells 1 and 2. That is, the cells may be positioned so that no dummy fin region or additional diffusion-preventing region is formed at the boundary between standard cells. Similarly, the distance between outermost fin regions F6 and F7 formed at the boundary between cells 2 and 3, the distance between outermost fin regions F9 and F10 formed at the boundary between cells 3 and 4, the distance between outermost fin regions F6 and F7 formed at the boundary between cells 5 and 6, and the distance between outermost fin regions F8 and F9 formed at the boundary between cells 6 and 7 may be the same as the distance between two adjacent fin regions in each of cells CELL1 to CELL7, which is 1CPP.

[0083] According to the embodiments described herein, fin regions are regularly arranged without dummy fin regions or diffusion-stopping regions, and by distinguishing cell boundaries, layout errors occurring at cell boundaries can be reduced, thereby enabling the design of integrated circuits to be more error-free. Furthermore, even when an engineering change order cell (ECO), a filler cell, a tap cell, etc. are additionally provided between cells, the distance between the fin regions at the cell boundaries can be regularly spaced.

[0084] Furthermore, in a VFET, a fin protruding vertically from the substrate can serve as a channel, and a structure surrounding the sidewall of the fin can serve as a gate. Therefore, compared to conventional planar or horizontal field-effect transistors, the upper source / drain contacts connected to the upper source / drain regions of the VFET and the lower source / drain contacts connected to the lower source / drain regions of the VFET can be less affected by the area occupied by the gate.

[0085] A multi-gate VFET according to an embodiment has two or more vertical channel structures, each of which serves as a channel of the VFET, and a fully surrounding gate structure surrounding the vertical channel structure serves as a gate that can be connected to each other using a gate connection. Therefore, compared to a single-gate VFET or a conventional planar or horizontal field-effect transistor, the multi-gate VFET can provide a wider area for each of the gate contact structure, the upper source / drain contact, and / or the lower source / drain contact.

[0086] Figure 7A This is a schematic diagram of a NAND circuit. Figures 7B to 7D FIG. 1 shows a layout of a cell for a NAND circuit in a plan view according to an embodiment. Specifically, Figure 7B It shows the layout of the unit up to FEOL, Figure 7C This shows the layout of the unit up to the middle of the line (MOL). Figure 7D FIG. 1 shows the layout of the cell up to BEOL.

[0087] exist Figure 7A In the NAND circuit, two PMOS transistors (PMOS transistors) MP1 and MP2 are connected in parallel between a power supply voltage terminal (VDD) and an output node, and two NMOS transistors (NMOS transistors) MN1 and MN2 are connected in series between the output node and a ground voltage terminal (GND). Each of the PMOS transistors and the NMOS transistors is implemented as a VFET. In the NAND circuit, the PMOS transistors MP1 and MN1 receive input signal A at their gates, while the PMOS transistors MP2 and MN2 receive input signal B at their gates. Output signal C is output through the output node.

[0088] exist Figure 7B In the embodiment of the present invention, the NAND cell may include three fin regions F1, F2, and F3. The distance between the fin regions F1, F2, and F3 may be 1CPP, and the distance between the fin region F1 or F3 and the outermost fin region (not shown) of the adjacent cell may also be 1CPP. The NAND cell may include a pair of vertical channel structures F11 and F12 in the fin region F1, a pair of vertical channel structures F21 and F22 in the fin region F2, and a pair of vertical channel structures F31 and F32 in the fin region F3. As described above, each of the vertical channel structures F11 to F32 forms a vertical channel of a corresponding VFET.

[0089] According to the current embodiment, the lower active region 111 may be formed below the vertical channel structures F11, F21, and F31 and be doped with P-type impurities. According to the current embodiment, the lower active region 112 may be formed below the vertical channel structures F12, F22, and F32 and be doped with N-type impurities. Therefore, the lower active regions 111 and 112 may function as corresponding lower source / drain regions.

[0090] A spacer layer SL (not shown) may be formed on the lower active regions 111 and 112 around the vertical channel structures F11, F12, F21, F22, F31, and F32, respectively. The spacer layer SL may also be formed on the sidewalls of the upper portions of the lower active regions 111 and 112. Gate electrodes 210, 211, 220, 221, 230, and 231 may be formed on the spacer layer SL. The gate electrodes 210, 211, 220, 221, 230, and 231 may surround the sidewalls of the vertical channel structures F11, F12, F21, F22, F31, and F32, respectively. The gate electrodes 210, 211, 220, 221, 230, and 231 may be spaced apart from the lower active regions 111 and 112 by the spacer layer SL.

[0091] The connection metal layer 201 may connect the gate electrodes 210 and 211. The connection metal layer 202 may connect the gate electrodes 220, 221, 230, and 231. The connection metal layers 201 and 202 may be cut along a metal cutting pattern (not shown) to be spaced apart from each other and from the connection metal layers (if any) of adjacent cells. The connection metal layers 201 and 202 may be spaced apart from each other in the X direction and receive a plurality of electrodes for the connection metal layers. Figure 7A The input signals A and B of the NAND circuit.

[0092] Reference Figure 7C , lower source / drain contacts 151 and 152 may be formed on lower active regions 111 and 112 , respectively, as lower source / drain regions, and the lower active regions 111 and 112 extend in the Y direction of the NAND standard cell.

[0093] exist Figure 7C In the embodiment, the upper source / drain contacts 172 may extend in the X direction to be formed on the upper source / drain regions (not shown) above the vertical channel structures F11, F21, and F31 for Figure 7A The PMOSs MP1 and MP2 are shown connected in parallel. Upper source / drain contacts 171 may be formed on upper source / drain regions (not shown) above the vertical channel structure F12.

[0094] The upper source / drain contact 173 may extend in the X direction to be placed above the vertical channel structures F22 and F32. The upper source / drain contact 171 may be placed to extend in the Y direction up to the upper surface of the lower source / drain contact 152. The upper source / drain contact 173 may be placed so as not to overlap with the lower source / drain contact 152 in the Z direction. That is, the length of the upper source / drain contact 171 is greater than the length of the upper source / drain contact 173 in the Y direction. That is, the upper source / drain contacts 171 and 173 may be formed separately for Figure 7A The NMOS MN1 and MN2 are shown connected in series.

[0095] The lower active regions 111 and 112 may be positioned to be spaced apart from each other by a distance W3 in the Y direction, and connection metal layers 201 and 202 may be formed between the active region 111 and the active region 112 .

[0096] A connection metal layer 201 may be positioned between vertical channel structures F11 and F12 , and a connection metal layer 202 may be positioned between vertical channel structures F21 , F22 , F31 , and F32 The connection metal layer 202 may extend in the X direction to be positioned over the fin regions F2 and F3 .

[0097] exist Figure 7D , power wirings PM1 and PM2 may extend in the X direction and be connected to lower source / drain contacts 151 and 152, respectively, via lower source / drain vias 163. Depending on the embodiment, power wirings PM1 and PM2 may be formed at a level in the Z direction that is the same as or different from the level of input wirings IM1 and IM2 and output wiring OM. If lower active region 111 is P-type doped, power supply voltage Vdd may be applied to power wiring PM1, and if lower active region 112 is N-type doped, ground voltage may be applied to power wiring PM2.

[0098] The input wiring IM1 may extend in the Y direction and be connected to the connection metal layer 201 through the gate via 165-1. The input wiring IM1 may be positioned parallel to the fin region F1 in the Y direction and overlap a portion of the fin region F1. Figure 7A The input signal A of the NAND circuit can be input to the input wiring IM1. The input wiring IM2 can extend in the Y direction and be connected to the connection metal layer 202 through the gate via 165-2. The input wiring IM2 can be formed to be parallel to the fin region F2 in the Y direction and overlap with a portion of the fin region F2 in a plan view. Figure 7A The input signal B of the NAND circuit can be input to the input wiring IM2.

[0099] The output wiring OM may be formed parallel to the fin region F3 in the Y direction and overlap a portion of the fin region F3 in plan view. The output wiring OM may be connected to upper source / drain contacts 172 and 173 through upper source / drain vias 167-1 and 167-2, respectively. Figure 7A The output signal C of the NAND circuit can be output to an upper wiring (not shown) through an output path (not shown) formed on the output wiring OM.

[0100] Figure 8A This is a schematic diagram of a NOR circuit. Figures 8B to 8D FIG. 1 shows a layout of a cell for a NOR circuit in a plan view according to an embodiment. Specifically, Figure 8B It shows the layout of the unit up to FEOL, Figure 8C It shows the layout of the unit up to MOL. Figure 8D FIG. 1 shows the layout of the cell up to BEOL.

[0101] exist Figure 8A In the NOR circuit, two PMOS transistors (PMOS transistors) MP1 and MP2 are connected in series between a power supply voltage terminal (VDD) and an output node, and two NMOS transistors (NMOS transistors) MN1 and MN2 are connected in parallel between the output node and a ground voltage terminal (GND). Each of the PMOS transistors and the NMOS transistors is implemented as a VFET. In the NOR circuit, the PMOS transistors MP1 and NMOS transistors MN2 receive input signal A at their gates, while the PMOS transistors MP2 and NMOS transistors MN1 receive input signal B at their gates. Output signal C is output through the output node.

[0102] exist Figure 8B In the embodiment of the present invention, the NOR cell may include four fin regions F1, F2, F3, and F4. The distance between the fin regions F1, F2, F3, and F4 may be 1CPP, and the distance between the fin region F1 or F4 and the outermost fin region (not shown) of the adjacent cell may also be 1CPP. The NOR cell may include a pair of vertical channel structures F11 and F12 in the fin region F1, a pair of vertical channel structures F21 and F22 in the fin region F2, a pair of vertical channel structures F31 and F32 in the fin region F3, and a pair of vertical channel structures F41 and F42 in the fin region F4. As described above, each of the vertical channel structures F11 to F42 forms a vertical channel of a corresponding VFET.

[0103] According to the current embodiment, the lower active region 111 may be formed below the vertical channel structures F11, F21, F31, and F41 and doped with P-type impurities. According to the current embodiment, the lower active region 112 may be placed below the vertical channel structures F12, F22, F32, and F42 and doped with N-type impurities. Therefore, the lower active regions 111 and 112 may function as corresponding lower source / drain regions.

[0104] A spacer layer SL (not shown) may be formed on the lower active regions 111 and 112 around the vertical channel structures F11, F12, F21, F22, F31, F32, F41, and F42, respectively. The spacer layer SL may also be formed on the sidewalls of the upper portions of the lower active regions 111 and 112. Gate electrodes 210, 211, 220, 221, 230, 231, 240, and 241 may be formed on the spacer layer SL. The gate electrodes 210, 211, 220, 221, 230, 231, 240, and 241 may surround the sidewalls of the vertical channel structures F11, F12, F21, F22, F31, F32, F41, and F42, respectively. The gate electrodes 210 , 211 , 220 , 221 , 230 , 231 , 240 , and 241 may be spaced apart from the lower active regions 111 and 112 by the spacer layer SL.

[0105] The connection metal layer 201 may connect the gate electrodes 210, 211, 220, and 221. The connection metal layer 202 may connect the gate electrodes 230, 231, 240, and 241. The connection metal layers 201 and 202 may be cut along a metal cutting pattern (not shown) to be spaced apart from each other and from an adjacent connection metal layer of another cell (if any). The connection metal layers 201 and 202 may be spaced apart from each other in the X direction and receive a plurality of electrodes for the connection metal layers. Figure 8A The input signals A and B of the NOR circuit.

[0106] Reference Figure 8C , lower source / drain contacts 151 and 152 may be formed on lower active regions 111 and 112 , respectively, as lower source / drain regions, which extend in the Y direction of the NOR cell.

[0107] exist Figure 8C The upper source / drain contacts 170 and 171 may be formed to be spaced apart from each other in the X direction for Figure 8A The PMOSs MP1 and MP2 are shown connected in series. Upper source / drain contacts 170 may be formed on upper source / drain regions (not shown) above the vertical channel structures F11 and F21, and upper source / drain contacts 171 may be formed on upper source / drain regions (not shown) above the vertical channel structures F31 and F41.

[0108] The upper source / drain contact 170 may be positioned to extend in the Y direction up to the upper surface of the lower source / drain contact 151. That is, the upper source / drain contact 170 may be positioned to overlap with the lower source / drain contact 151 in the Z direction. The upper source / drain contact 171 may be positioned not to overlap with the lower source / drain contact 151 in the Z direction. That is, the length of the upper source / drain contact 170 is greater than the length of the upper source / drain contact 171 in the Y direction.

[0109] The upper source / drain contacts 172 may be formed to extend in the X direction for Figure 8A The NMOSs MN1 and MN2 are shown connected in parallel and disposed on upper source / drain regions (not shown) above the vertical channel structures F12 , F22 , F32 , and F42 .

[0110] Reference Figure 8A and Figure 8C , the upper source / drain contact 170 may correspond to the source terminal of the PMOS MP1, the upper source / drain contact 171 may correspond to the drain terminal of the PMOS MP2, and the upper source / drain contact 172 may correspond to the drain terminals of the NMOS MN1 and MN2.

[0111] The lower active regions 111 and 112 may be positioned to be spaced apart from each other by a distance W3 in the Y direction, and each of the connection metal layers 201 and 202 may be positioned between the lower active regions 111 and 112 .

[0112] The connection metal layer 201 may be positioned between the vertical channel structures F11, F21, F12, and F22. That is, the connection metal layer 201 may extend in the X direction to be positioned above the fin regions F1 and F2. The connection metal layer 202 may be positioned between the vertical channel structures F31, F41, F32, and F42. That is, the connection metal layer 202 may extend in the X direction to be positioned above the fin regions F3 and F4.

[0113] The gate via 161-1 may be positioned on an upper surface of the connection metal layer 201 corresponding to the fin region F1. The gate via 161-2 may be positioned on an upper surface of the connection metal layer 202 corresponding to the fin region F3.

[0114] exist Figure 8D, power wirings PM1 and PM2 may extend in the X direction and be connected to lower source / drain contacts 151 and 152, respectively, through lower source / drain vias 163. According to some embodiments, power wirings PM1 and PM2 may be formed at a level in the Z direction that is the same as or different from the level of input wirings IM1 and IM2 and output wiring OM. If lower active region 111 is P-type doped, power supply voltage Vdd may be applied to power wiring PM1, and if lower active region 112 is N-type doped, ground voltage may be applied to power wiring PM2.

[0115] The input wiring IM1 may extend in the Y direction and be connected to the connection metal layer 201 through the gate via 161-1. The input wiring IM1 may be positioned parallel to the fin region F1 in the Y direction and overlap a portion of the fin region F1 in the Z direction. Figure 8A The input signal A of the NOR circuit can be input to the input wiring IM1. The input wiring IM2 can extend in the Y direction and be connected to the connection metal layer 202 through the gate via 161-2. The input wiring IM2 can be placed parallel to the fin region F3 in the Y direction and overlap with a portion of the fin region F3 in a plan view. Figure 8A The input signal B of the NOR circuit can be input to the input wiring IM2.

[0116] The output wiring OM may be formed parallel to the fin region F4 in the Y direction and overlap a portion of the fin region F4 in plan view. The output wiring OM may be connected to upper source / drain contacts 171 and 172 through upper source / drain vias 167-1 and 167-2, respectively. Figure 8A The output signal C of the NOR circuit can be output to an upper wiring (not shown) through an output path (not shown) placed on the output wiring OM.

[0117] Figure 9A is a schematic diagram of an AND-OR-inverter (AOI) circuit in plan view, Figures 9B to 9D FIG. 1 shows a layout of a unit for an AOI circuit in a plan view according to an embodiment. Specifically, Figure 9B It shows the layout of the unit up to FEOL, Figure 9C It shows the layout of the unit up to MOL. Figure 9D FIG. 1 shows the layout of the cell up to BEOL.

[0118] exist Figure 9AIn the AOI circuit, an AND circuit, an OR circuit, and an inverter circuit are included. The AOI circuit includes a PMOS transistor MP1 between a power supply voltage terminal (VDD) and an intermediate node, PMOS transistors MP2 and MP3 connected in parallel between the intermediate node and an output node, and an NMOS transistor MN3 connected in parallel with two NMOS transistors MN1 and MN2 connected in series between the output node and a ground voltage terminal (GND). Each of the PMOS transistors and the NMOS transistors is implemented as a VFET. In the AOI circuit, the PMOS transistors MP1 and NMOS transistors MN3 receive input signal A at their gates, the PMOS transistors MP2 and NMOS transistors MN1 receive input signal B at their gates, and the PMOS transistors MP3 and NMOS transistors MN2 receive input signal C at their gates. Output signal D is output through the output node.

[0119] exist Figure 9B In the embodiment of the present invention, the AOI cell may include six fin regions F1 to F6. The distance between the fin regions F1, F2, F3, F4, F5, and F6 may be 1CPP, and the distance between the fin region F1 or F6 and the outermost fin region (not shown) of the adjacent cell may also be 1CPP. The AOI cell may include a pair of vertical channel structures F11 and F12 in the fin region F1, a pair of vertical channel structures F21 and F22 in the fin region F2, a pair of vertical channel structures F31 and F32 in the fin region F3, a pair of vertical channel structures F41 and F42 in the fin region F4, a pair of vertical channel structures F51 and F52 in the fin region F5, and a pair of vertical channel structures F61 and F62 in the fin region F6. As described above, each of the vertical channel structures F11 to F62 forms a vertical channel of a corresponding VFET.

[0120] According to the current embodiment, the lower active region 111 may be positioned below the vertical channel structures F11, F21, F31, F41, F51, and F61 and be doped with P-type impurities. According to the current embodiment, the lower active region 112-1 may be formed below the vertical channel structures F12, F22, F32, and F42 and be doped with N-type impurities. According to the current embodiment, the lower active region 112-2 may be formed below the vertical channel structures F52 and F62 and be doped with N-type impurities. Therefore, the lower active regions 111, 112-1, and 112-2 may function as corresponding lower source / drain regions.

[0121] The lower active regions 112 - 1 and 112 - 2 may be positioned to be spaced apart from each other in the X direction. The lower active region 112 - 2 may be formed to extend longer than the lower active region 112 - 1 in the Y direction.

[0122] A spacer layer SL (not shown) may be formed on the lower active regions 111, 112-1, and 112-2 around the vertical channel structures F11 to F62, respectively. The spacer layer SL may also be formed on the sidewalls of the upper portions of the lower active regions 111, 112-1, and 112-2. Gate electrodes 210, 211, 220, 221, 230, 231, 240, 241, 250, 251, 260, and 261 may be formed on the spacer layer SL. The gate electrodes 210, 211, 220, 221, 230, 231, 240, 241, 250, 251, 260, and 261 may surround the sidewalls of the vertical channel structures F11 to F62, respectively. The gate electrodes 210 , 211 , 220 , 221 , 230 , 231 , 240 , 241 , 250 , 251 , 260 , and 261 may be spaced apart from the lower active regions 111 , 112 - 1 , and 112 - 2 by the spacer layers SL.

[0123] The connection metal layers 201, 202, and 203 may be cut along a metal cutting pattern (not shown) to be spaced apart from each other and from an adjacent connection metal layer (if any) of another cell. The connection metal layer 201 may connect the gate electrodes 210, 211, 220, and 221. The connection metal layer 202 may connect the gate electrodes 230, 231, 240, and 241. The connection metal layer 203 may connect the gate electrodes 250, 251, 260, and 261. The connection metal layers 201, 202, and 203 may be spaced apart from each other in the X direction and may receive a plurality of electrodes for the connection metal layers 201, 202, and 203. Figure 9A The input signals A, B and C of the AOI circuit.

[0124] Reference Figure 9C , lower source / drain contacts 151 and 152 extending in the X direction may be formed on both ends of the AOI unit in the Y direction and on the lower source / drain region 112 - 2 .

[0125] exist Figure 9C In the embodiment, the upper source / drain contacts 170, 171 and 172 may be placed to be spaced apart from each other in the X direction for Figure 9A The series connection between the PMOSs MP1 and MP2 / MP3 and the parallel connection between the PMOSs MP2 and MP3 are shown. The upper source / drain contact 170 may be placed on the upper source / drain region (not shown) above the vertical channel structures F11 and F21, the upper source / drain contact 171 may be placed on the upper source / drain region (not shown) above the vertical channel structures F31 and F41, and the upper source / drain contact 172 may be placed on the upper source / drain region (not shown) above the vertical channel structures F51 and F61.

[0126] The upper source / drain contacts 170 and 171 may be positioned to extend in the Y direction up to the upper surface of the lower source / drain contact 151. That is, the upper source / drain contacts 170 and 171 may be positioned to overlap with portions of the lower source / drain contact 151 in the Z direction, respectively. The upper source / drain contact 172 may be positioned so as not to overlap with the lower source / drain contact 151 in the Z direction. That is, the lengths of the upper source / drain contacts 170 and 171 are greater than the length of the upper source / drain contact 172 in the Y direction.

[0127] The upper source / drain contacts 173 and 174 may be placed spaced apart from each other in the X direction for Figure 9A The parallel connection of NMOS MN1 / MN2 and MN3 and the series connection of MN1 and MN2 are shown. Upper source / drain contacts 173 may be positioned to extend in the X direction and disposed on the upper source / drain regions above vertical channel structures F12 and F22. Upper source / drain contacts 174 may be positioned to extend in the X direction and disposed on the upper source / drain regions above vertical channel structures F32, F42, F52, and F62.

[0128] The upper source / drain contact 173 may be positioned to extend in the Y direction up to the upper surface of the lower source / drain contact 152. That is, the upper source / drain contact 173 may be positioned to overlap a portion of the lower source / drain contact 152 in the Z direction. The upper source / drain contact 174 may be positioned so as not to overlap with the lower source / drain contact 152 in the Z direction. That is, the length of the upper source / drain contact 173 in the Y direction is greater than the length of the upper source / drain contact 174 in the Y direction.

[0129] Reference Figure 9A and Figure 9C Upper source / drain contact 170 may correspond to the source terminal of PMOS MP1, upper source / drain contact 171 may correspond to the source terminal of PMOS MP2, and upper source / drain contact 172 may correspond to the source terminal of PMOS MP3. Upper source / drain contact 173 may correspond to the drain terminal of NMOS MN3, and upper source / drain contact 174 may correspond to the source and drain terminals of NMOS MN1 and MN2.

[0130] The lower active regions 111 and 112-1 may be spaced apart from each other by a distance W3 in the Y direction, and the lower active regions 111 and 112-2 may also be spaced apart from each other by a distance W3 in the Y direction. Connection metal layers 201, 202, and 203 may be positioned between the lower active regions 111, 112-1, and 112-2.

[0131] The connection metal layer 201 may also be placed between the vertical channel structures F11, F21, F12, and F22. That is, the connection metal layer 201 may extend in the X direction to be placed above the fin regions F1 and F2. The connection metal layer 202 may be placed between the vertical channel structures F31, F41, F32, and F42. That is, the connection metal layer 202 may extend in the X direction to be placed above the fin regions F3 and F4. The connection metal layer 203 may be placed between the vertical channel structures F51, F61, F52, and F62. That is, the connection metal layer 203 may extend in the X direction to be placed above the fin regions F5 and F6.

[0132] The gate via 161-1 may be disposed on the upper surface of the connection metal layer 201 corresponding to the fin region F2. The gate via 161-2 may be disposed on the upper surface of the connection metal layer 202 corresponding to the fin region F4. The gate via 161-3 may be disposed on the upper surface of the connection metal layer 203 corresponding to the fin region F5.

[0133] exist Figure 9D , power wirings PM1 and PM2 may extend in the X direction and be connected to lower source / drain contacts 151 and 152, respectively, through lower source / drain vias 163. According to some embodiments, power wirings PM1 and PM2 may be placed at a level in the Z direction that is the same as or different from the level of input wirings IM1 and IM2 and output wiring OM. If lower active region 111 is P-type doped, power supply voltage Vdd may be applied to power wiring PM1, and if lower active regions 112-1 and 112-2 are N-type doped, ground voltage may be applied to power wiring PM2.

[0134] The input wiring IM1 may extend in the Y direction and be connected to the connection metal layer 201 through the gate via 161-1. The input wiring IM1 may be positioned parallel to the fin region F2 in the Y direction and overlap a portion of the fin region F2 in the Z direction. Figure 9A The input signal A of the AOI circuit can be input to the input wiring IM1. The input wiring IM2 can extend in the Y direction and be connected to the connection metal layer 202 through the gate via 161-2. The input wiring IM2 can be placed parallel to the fin region F4 in the Y direction and overlap a portion of the fin region F4 in the Z direction. Figure 9A The input signal B of the AOI circuit can be input to the second input wiring IM2. The input wiring IM3 can extend in the Y direction and be connected to the connection metal layer 203 through the gate via 161-3. The input wiring IM3 can be placed parallel to the fin region F5 in the Y direction and overlap a portion of the fin region F5 in the Z direction. Figure 9AThe input signal C of the AOI circuit can be input to the input wiring IM3.

[0135] The output wiring OM may be positioned parallel to the fin region F6 in the Y direction and overlap a portion of the fin region F6 in the Z direction. The output wiring OM may be connected to the upper source / drain contacts 171 and 172 through upper source / drain vias 167-1 and 167-2, respectively. The output signal D may be output to an upper wiring (not shown) through an output via (not shown) positioned on the output wiring OM.

[0136] Figure 10A is a schematic diagram of the buffer circuit, FIG. 10B to FIG. 10D FIG. 1 shows a layout of a unit for a buffer circuit in a plan view according to an embodiment. Specifically, Figure 10B It shows the layout of the unit up to FEOL, Figure 10C It shows the layout of the unit up to MOL. Figure 10D FIG. 1 shows the layout of the cell up to BEOL.

[0137] exist Figure 10A In the embodiment of the present invention, the buffer circuit includes multiple inverter circuits. For ease of description, the description will be provided under the premise of a buffer circuit including two inverter circuits. The first inverter circuit may include a PMOS MP1 connected between a power supply voltage terminal (VDD) and a first output node, and an NMOS MN1 connected between the first output node and a ground voltage terminal (GND). The second inverter circuit may include a PMOS MP2 connected between a power supply voltage terminal (VDD) and a second output node, and an NMOS MN2 connected between the second output node and a ground voltage terminal (GND). Here, each of the PMOS and NMOS is implemented by a VFET. The first output node of the first inverter circuit serves as the input node of the second inverter circuit. When the input signal A of the buffer circuit is input to the gates of the PMOS MP1 and the NMOS MN1 at the input node of the first inverter, an inverted signal ā is output from the first output node of the first inverter. The second inverter receives the inverted signal ā at the gates of the PMOS MP2 and the NMOS MN2, and outputs the output signal A through the second output node.

[0138] exist Figure 10BIn the embodiment of the present invention, the buffer unit may include four fin regions F1 to F4. The distance between the fin regions F1, F2, F3 and F4 may be 1CPP, and the distance between the fin region F1 or F4 and the outermost fin region (not shown) of the adjacent cell may also be 1CPP. The buffer unit includes a pair of vertical channel structures F11 and F12 in the fin region F1, a pair of vertical channel structures F21 and F22 in the fin region F2, a pair of vertical channel structures F31 and F32 in the fin region F3, and a pair of vertical channel structures F41 and F42 in the fin region F4. As described above, each of the vertical channel structures F11 to F42 forms a vertical channel of the corresponding VFET.

[0139] The lower active region 111-1 may be positioned below the vertical channel structures F11 and F21, and the lower active region 111-2 may be positioned below the vertical channel structures F31 and F41. According to the current embodiment, the lower active regions 111-1 and 111-2 may be doped with P-type impurities. The lower active region 112-1 may be positioned below the vertical channel structures F12 and F22, and the lower active region 112-2 may be positioned below the vertical channel structures F32 and F42. According to the current embodiment, the lower active regions 112-1 and 112-2 may be doped with N-type impurities. Therefore, the lower active regions 111-1, 111-2, 112-1, and 112-2 may function as corresponding lower source / drain regions.

[0140] The lower active regions 111-1 and 111-2 may be positioned to be spaced apart from each other in the X direction, and the lower active regions 112-1 and 112-2 may also be positioned to be spaced apart from each other in the X direction. The lower active regions 111-1 and 111-2 may be formed to have the same length in the Y direction. The lower active regions 112-1 and 112-2 may also be formed to have the same length in the Y direction.

[0141] A spacer layer SL (not shown) may be formed on the lower active regions 111-1, 111-2, 112-1, and 112-2 around the vertical channel structures F11 to F42, respectively. The spacer layer SL may also be formed on the sidewalls of the upper portions of the lower active regions 111-1, 111-2, 112-1, and 112-2. Gate electrodes 210, 211, 220, 221, 230, 231, 240, and 241 may be formed on the spacer layer SL. The gate electrodes 210, 211, 220, 221, 230, 231, 240, and 241 may surround the sidewalls of the vertical channel structures F11 to F42, respectively. The gate electrodes 210 , 211 , 220 , 221 , 230 , 231 , 240 , and 241 may be spaced apart from the lower active regions 111 - 1 , 111 - 2 , 112 - 1 , and 112 - 2 by the spacer layers SL.

[0142] The connection metal layers 201 and 202 may be cut along a metal cutting pattern (not shown) to be spaced apart from each other and from an adjacent connection metal layer (if any) of another cell. The connection metal layer 201 may connect the gate electrodes 210, 211, 220, and 221. The connection metal layer 202 may connect the gate electrodes 230, 231, 240, and 241. The connection metal layers 201 and 202 may be spaced apart from each other in the X direction and receive Figure 10A The buffer circuit takes the input signal A and the inverted signal ā.

[0143] Reference Figure 10C Lower source / drain contacts 151 and 152 extending in the X direction may be formed on both ends of the buffer unit in the Y direction and on the lower active regions 111-1, 111-2, 112-1, and 112-2 as corresponding lower source / drain regions.

[0144] exist Figure 10C , upper source / drain contacts 170 and 171 may be positioned to be spaced apart from each other in the X direction, and upper source / drain contacts 173 and 174 may be positioned to be spaced apart from each other in the X direction. Upper source / drain contact 170 may be positioned on an upper source / drain region (not shown) above vertical channel structures F11 and F21, and upper source / drain contact 171 may be positioned on an upper source / drain region (not shown) above vertical channel structures F31 and F41.

[0145] Upper source / drain contacts 170, 171, 173, and 174 may be positioned so as not to overlap lower source / drain contacts 151 and 152 in the Z direction. Upper source / drain contacts 170, 171, 173, and 174 may have the same length in the Y direction and the same length in the X direction.

[0146] Reference Figure 10A and Figure 10C Upper source / drain contact 170 may correspond to the drain terminal of PMOS MP1, upper source / drain contact 171 may correspond to the drain terminal of PMOS MP2, upper source / drain contact 173 may correspond to the drain terminal of NMOS MN1, and upper source / drain contact 174 may correspond to the drain terminal of NMOS MN2.

[0147] The lower active regions 111-1 and 111-2 and the lower active regions 112-1 and 112-2 may be positioned to be spaced apart from each other by a distance W3 in the Y direction. A connection metal layer 201 may be positioned between the lower active regions 111-1 and 111-2, and a connection metal layer 202 may be positioned between the lower active regions 112-1 and 112-2.

[0148] The connection metal layer 201 may also be positioned between the vertical channel structures F11, F21, F12, and F22. That is, the connection metal layer 201 may extend in the X direction to be positioned above the fin regions F1 and F2. The connection metal layer 202 may be positioned between the vertical channel structures F31, F41, F32, and F42. That is, the connection metal layer 202 may extend in the X direction to be positioned above the fin regions F3 and F4.

[0149] The gate via 161-1 may be positioned on an upper surface of the connection metal layer 201 corresponding to the fin region F1. The gate via 161-2 may be positioned on an upper surface of the connection metal layer 202 corresponding to the fin region F3.

[0150] exist Figure 10D , power wirings PM1 and PM2 may extend in the X direction and be connected to lower source / drain contacts 151 and 152, respectively, through lower source / drain vias 163. Depending on the embodiment, power wirings PM1 and PM2 may be placed at a level in the Z direction that is the same as or different from the level of input wirings IM1 and IM2 and output wirings OM1 and OM2. If lower active regions 111-1 and 111-2 are P-type doped, power supply voltage Vdd may be applied to power wiring PM1, and if lower active regions 112-1 and 112-2 are N-type doped, ground voltage may be applied to power wiring PM2.

[0151] The input wiring IM1 may extend in the Y direction and be connected to the connection metal layer 201 through the gate via 161-1. The input wiring IM1 may be positioned parallel to the fin region F1 in the Y direction and overlap a portion of the fin region F1 in the Z direction. Figure 10A The input signal A of the buffer circuit can be input to the input wiring IM1.

[0152] Output wiring OM1 can output an inverted signal ā. Output wiring OM1 can be positioned parallel to fin region F2 in the Y direction and overlap a portion of fin region F2 in the Z direction. Output wiring OM1 can be connected to upper source / drain contacts 170 and 173 via upper source / drain vias 167-1 and 167-2, respectively. The inverted signal ā can be output to the intermediate connection wiring CM via a connection via V11 positioned above output wiring OM1.

[0153] The input wiring IM2 may extend in the Y direction and be connected to the connection metal layer 202 through the gate via 161-2. The input wiring IM2 may be positioned parallel to the fin region F3 in the Y direction and overlap a portion of the fin region F3 in the Z direction.

[0154] When the connection path V11 is placed on the output wiring OM1, the connection path V12 is placed on the input wiring IM2 and connected to the intermediate connection wiring CM. The intermediate connection wiring CM is placed on the input wiring IM2 and the upper metal wiring (not shown) of the output wiring OM1. The intermediate connection wiring CM extends in the X direction and connects to the connection paths V11 and V12. The intermediate connection wiring CM is placed so as to intersect the output wiring OM1 and the input wiring IM2 extending in the Y direction in the X direction. The input wiring IM2 can receive the intermediate connection wiring CM. Figure 10A The buffer circuit is the inverting signal ā.

[0155] The output wiring OM2 can output the output signal A. The output wiring OM2 can be placed parallel to the fin region F4 in the Y direction and overlap a portion of the fin region F4 in the Z direction. The output wiring OM2 can be connected to the upper source / drain contacts 171 and 174 through the upper source / drain vias 167-3 and 167-4. The output signal A can be output to an upper wiring (not shown) through a connection via (not shown) placed on the output wiring OM2.

[0156] exist Figures 10A-10D In the embodiment, the buffer circuit is implemented in a single unit. However, according to one embodiment, the buffer circuit can be implemented by combining and modifying two inverter units (such as Figure 1 The unit shown is implemented.

[0157] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the above embodiments without departing substantially from the principles of the present invention. Therefore, the above embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. An integrated circuit comprising a first unit and a second unit adjacent to each other in a first direction, wherein: The first unit includes: a first lower source / drain region and a second lower source / drain region extending on the substrate in the first direction and arranged to be spaced apart from each other in a second direction; a pair of first vertical channel structures positioned to cross the first lower source / drain region and the second lower source / drain region in the second direction; a pair of second vertical channel structures positioned to intersect the first lower source / drain region and the second lower source / drain region in the second direction and arranged to be spaced apart from the pair of first vertical channel structures in the first direction; a pair of first upper source / drain regions and a pair of second upper source / drain regions, disposed on the pair of first vertical channel structures and the pair of second vertical channel structures, respectively; a first gate electrode and a second gate electrode, respectively surrounding side surfaces of the pair of first vertical channel structures, and a third gate electrode and a fourth gate electrode, respectively surrounding side surfaces of the pair of second vertical channel structures; a connecting metal layer connected to the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode; an input wiring connected to at least one of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode through a gate path to receive an input signal; and an output wiring connected to the pair of second upper source / drain regions through an upper source / drain path, Wherein, in the first direction, the distance between the pair of second vertical channel structures of the first unit and the adjacent pair of first vertical channel structures in the second unit is the same as the distance between the pair of first vertical channel structures and the pair of second vertical channels, and the pair of second vertical channel structures of the first unit and the adjacent pair of first vertical channel structures in the second unit face the cell boundary between the first unit and the second unit.

2. The integrated circuit according to claim 1, wherein: The second unit also includes the first lower source / drain region and the second lower source / drain region, the pair of first vertical channel structures, the pair of second vertical channel structures, the pair of first upper source / drain regions, the pair of second upper source / drain regions, the first gate electrode, the second gate electrode, the third gate electrode, the fourth gate electrode, the connecting metal layer, the input wiring and the output wiring.

3. The integrated circuit according to claim 1, wherein: In the first direction, the connection metal layer in the first cell and the adjacent connection metal layer in the second cell are spaced apart from the cell boundary by the same distance, and the connection metal layer in the first cell and the adjacent connection metal layer in the second cell face the cell boundary.

4. The integrated circuit according to claim 1, wherein: The first unit further comprises: a first lower source / drain contact and a second lower source / drain contact extending in the first direction and connected to the first lower source / drain region and the second lower source / drain region, respectively; and A first upper source / drain contact and a second upper source / drain contact are placed on the pair of first upper source / drain regions and the pair of second upper source / drain regions to be connected thereto.

5. The integrated circuit according to claim 1, wherein: In the first direction, the first lower source / drain region in the first cell and the adjacent first lower source / drain region in the second cell are spaced apart from the cell boundary by the same distance, and the first lower source / drain region in the first cell and the adjacent first lower source / drain region in the second cell face the cell boundary.

6. The integrated circuit according to claim 5, wherein: In the first direction, the distance between the connecting metal layer in the first unit and the adjacent connecting metal layer in the second unit is the same as or smaller than the distance between the first lower source / drain region in the first unit and the adjacent first lower source / drain region in the second unit, the connecting metal layer in the first unit and the adjacent connecting metal layer in the second unit face the unit boundary, and the first lower source / drain region in the first unit and the adjacent first lower source / drain region in the second unit face the unit boundary.

7. The integrated circuit according to claim 1, wherein: The first cell and the second cell do not include a diffusion stopping region or a dummy fin area therebetween.

8. An integrated circuit comprising a first unit and a second unit adjacent to each other in a first direction, wherein: Each of the first unit and the second unit includes: a first fin region and a second fin region disposed to be spaced apart from each other in the first direction and extending in the second direction; a first vertical channel structure and a second vertical channel structure arranged to be spaced apart from each other in the second direction on the first fin region; a third vertical channel structure and a fourth vertical channel structure arranged to be spaced apart from each other in the second direction on the second fin region; a first upper source / drain region, a second upper source / drain region, a third upper source / drain region, and a fourth upper source / drain region, respectively disposed on the first vertical channel structure, the second vertical channel structure, the third vertical channel structure, and the fourth vertical channel structure; a first lower source / drain region extending in the first direction and disposed below the first vertical channel structure and the third vertical channel structure; a second lower source / drain region extending in the first direction and disposed below the second vertical channel structure and the fourth vertical channel structure; a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode, respectively surrounding side surfaces of the first vertical channel structure, the second vertical channel structure, the third vertical channel structure, and the fourth vertical channel structure between the first upper source / drain region, the second upper source / drain region, the third upper source / drain region, and the fourth upper source / drain region and the first lower source / drain region and the second lower source / drain region; a spacer layer formed between the first vertical channel structure, the second vertical channel structure, the third vertical channel structure, and the fourth vertical channel structure and the first lower source / drain region and the second lower source / drain region; and a connecting metal layer disposed between the first vertical channel structure, the second vertical channel structure, the third vertical channel structure, and the fourth vertical channel structure and connected to at least one gate electrode of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode, wherein the distance between the connection metal layer and the first lower source / drain region and the second lower source / drain region in the first cell and the cell boundary between the first cell and the second cell is equal to the distance between the connection metal layer and the first lower source / drain region and the second lower source / drain region in the second cell and the cell boundary; and Wherein, in the first direction, the distance between the second fin region in the first cell and the first fin region in the second cell is equal to the distance between the first fin region and the second fin region in the first cell or the second cell, and the second fin region in the first cell and the first fin region in the second cell face the cell boundary.

9. The integrated circuit according to claim 8, wherein: In the first direction, the distance between the connecting metal layer in the first cell and the connecting metal layer facing the cell boundary in the second cell is the same as or smaller than the distance between the first lower source / drain region in the first cell and the first lower source / drain region in the second cell, the connecting metal layer in the first cell and the connecting metal layer facing the cell boundary in the second cell face the cell boundary, and the first lower source / drain region in the first cell and the first lower source / drain region in the second cell face the cell boundary.

10. The integrated circuit according to claim 8, wherein: Each of the first unit and the second unit further comprises: a gate contact disposed on the connection metal layer and connected to the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode; an input wiring placed on the gate contact to be connected thereto through a gate via and extending in the second direction; at least two upper source / drain contacts disposed on the first upper source / drain region, the second upper source / drain region, the third upper source / drain region, and the fourth upper source / drain region to overlap at least two of the first to fourth upper source / drain regions; and An output wiring is placed on the at least two upper source / drain contacts to be connected thereto through the at least two upper source / drain vias.

11. The integrated circuit of claim 10 , further comprising: a first connection path placed on the output wiring in the first unit; a second connection path placed on the input wiring in the second cell; as well as An intermediate connection wiring is placed on the first connection via and the second connection via to be connected thereto and extends in the first direction.

12. The integrated circuit according to claim 8, wherein: Each of the first unit and the second unit further comprises: a first lower source / drain contact and a second lower source / drain contact extending in the first direction and connected to an extension portion of the first lower source / drain region and an extension portion of the second lower source / drain region; a first power wiring extending in the first direction and connected to the first lower source / drain contact through a first lower source / drain via; and a second power supply wiring extending in the first direction and connected to the second lower source / drain contact through a second lower source / drain path, The first power wiring and the second power wiring provide power voltages of different polarities.

13. The integrated circuit according to claim 8, wherein: A distance between the second fin region in the first cell and the first fin region in the second cell is 1 contact polysilicon pitch, and the second fin region in the first cell and the first fin region in the second cell face the cell boundary.

14. A layout method for an integrated circuit, the integrated circuit comprising a first unit and a second unit adjacent to the first unit in a first direction, the method comprising: forming a first lower source / drain region and a second lower source / drain region on a substrate, wherein the first lower source / drain region and the second lower source / drain region extend in a first direction and are spaced apart from each other in a second direction; patterning a first fin region and a second fin region, the first fin region and the second fin region extending in the second direction and crossing the first lower source / drain region and the second lower source / drain region; forming a first vertical channel structure and a second vertical channel structure on the first fin region to correspond to the first lower source / drain region and the second lower source / drain region, respectively, and forming a third vertical channel structure and a fourth vertical channel structure on the second fin region to correspond to the first lower source / drain region and the second lower source / drain region, respectively; forming a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode, wherein the first to fourth gate electrodes respectively surround side surfaces of the first to fourth vertical channel structures; forming a connection metal layer, wherein the connection metal layer connects the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode; forming a first upper source / drain region, a second upper source / drain region, a third upper source / drain region, and a fourth upper source / drain region on the first vertical channel structure, the second vertical channel structure, the third vertical channel structure, and the fourth vertical channel structure, respectively; forming at least one first upper source / drain contact and at least one second upper source / drain contact on at least two of the first upper source / drain region, the second upper source / drain region, the third upper source / drain region, and the fourth upper source / drain region; forming at least one gate contact on the connection metal layer; forming a first source / drain path and a second source / drain path on the first upper source / drain contact and the second upper source / drain contact, respectively, and forming a gate path on the gate contact; forming an input wiring extending in the second direction and connected to the gate path; as well as forming an output wiring extending in the second direction and connected to at least one of the first source / drain path and the second source / drain path, Wherein, in the first direction, the distance between the second fin region in the first unit and the adjacent fin region in the second unit is the same as the distance between the first fin region and the second fin region, and the second fin region in the first unit and the adjacent fin region in the second unit face the unit boundary between the first unit and the second unit.

15. The integrated circuit layout method according to claim 14, wherein: In the first direction, the connection metal layer is formed so that the connection metal layer in the first cell and the adjacent connection metal layer in the second cell are spaced apart from the cell boundary by the same distance, and the connection metal layer in the first cell and the adjacent connection metal layer in the second cell face the cell boundary.

16. The integrated circuit layout method according to claim 14, wherein: In the first direction, the first lower source / drain region and the second lower source / drain region are formed so that the first lower source / drain region and the second lower source / drain region in the first cell and the adjacent first lower source / drain region and the second lower source / drain region in the second cell are spaced apart from the cell boundary by the same distance, and the first lower source / drain region and the second lower source / drain region in the first cell and the adjacent first lower source / drain region and the second lower source / drain region in the second cell face the cell boundary.

17. The method for layout of an integrated circuit according to claim 16, further comprising forming a boundary separation film extending in the second direction between the first lower source / drain region and the second lower source / drain region in the first cell and the adjacent first lower source / drain region and the second lower source / drain region in the second cell. 18 . The method for layout of an integrated circuit according to claim 14 , further comprising an active region separation film between the first source / drain region and the second source / drain region.

19. The integrated circuit layout method according to claim 14, wherein: A distance between the second fin region in the first cell and an adjacent fin region in the second cell is 1 contact polysilicon pitch, and the second fin region in the first cell and the adjacent fin region in the second cell face the cell boundary.

20. The integrated circuit layout method according to claim 14, further comprising: forming a first lower source / drain contact and a second lower source / drain contact, the first lower source / drain contact and the second lower source / drain contact extending in the first direction and connected to the extension portions of the first and second lower source / drain regions; forming a first power supply wiring extending in the first direction; as well as forming a second power supply wiring extending in the first direction, The first power wiring is connected to the first upper source / drain contact or the first lower source / drain contact, and the second power wiring is connected to the second upper source / drain contact or the second lower source / drain contact.

21. The integrated circuit layout method according to claim 20, wherein: The first lower source / drain contact or the second lower source / drain contact extends in the first direction to overlap at least three or more fin regions including the first fin region and the second fin region.

22. The integrated circuit layout method according to claim 14, wherein: The first upper source / drain contact or the second upper source / drain contact is formed to extend in the first direction to overlap at least three or more fin regions including the first fin region and the second fin region.

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