Image sensor with embedded well for accommodating light emitter

Abstract

An image sensor having embedded wells for containing light emitters and a method of manufacturing the same, and an apparatus for luminescence-based interrogation of a plurality of samples and a method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including an array of doped sensing regions corresponding to an array of light-sensitive pixels of the image sensor, respectively. The semiconductor substrate forms an array of wells. Each well is aligned with a respective doped sensing region to facilitate detection of light emitted by a light emitter disposed in the well to a light-sensitive pixel including the respective doped sensing region by the light-sensitive pixel. The image sensor further includes a light-blocking barrier between adjacent doped sensing regions to reduce propagation of light from a well that is not aligned with a doped sensing region of each light-sensitive pixel to the doped sensing region of the each light-sensitive pixel.

Description

Technical Field

[0001] The present invention relates to an image sensor having an embedded trap for accommodating a light emitter and a method for manufacturing the same, as well as a device for emissivity-based interrogation of multiple samples and a method for manufacturing the same. Background Technology

[0002] Deoxyribonucleic acid (DNA) is a molecule composed of two intertwined strands forming a double helix that carries the genetic instructions for the development, function, growth, and reproduction of all known organisms and many viruses. The two DNA strands are composed of nucleotides. Each nucleotide includes one of four nitrogenous nucleobases: cytosine (C), guanine (G), adenine (A), or thymine (T). Following the base-pairing rules of pairing A with T and C with G, the two DNA strands are linked together by hydrogen bonds between the nucleobases.

[0003] DNA sequencing is the process of determining the sequence (i.e., physical order) of nucleobases in DNA. DNA sequencing can be used to determine the sequence of individual genes, larger genetic regions (i.e., clusters of genes or operons), complete chromosomes, or the entire genome of any organism. While DNA sequencing has historically been a very time-consuming process, the recent emergence of “fast” and less expensive DNA sequencing technologies has made it a key technology in many other fields of science, including biology and medicine, forensic science, and anthropology.

[0004] Many rapid DNA sequencing technologies are based on the parallel sequencing of small fragments of the complete DNA to be sequenced. In DNA nanosphere sequencing, the DNA to be sequenced is cut into small fragments, and each fragment is then replicated to produce many copies of the fragment in tandem strands, coiled into nanospheres (approximately 300 nanometers in diameter). Many nanospheres can be attached to different corresponding sites in a flow cell, and then the nanospheres can be sequenced in parallel by simultaneously detecting the binding of the nuclei to each nanosphere as a series of bases are passed through the flow cell.

[0005] Shotgun sequencing is a method applicable to various rapid DNA sequencing technologies based on parallel sequencing of small fragments. In Shotgun sequencing, fragmentation is randomized. After sequencing the individual random fragments, the sequenced patterns are stitched together based on the analysis of overlap between patterns. Summary of the Invention

[0006] The present invention provides an image sensor having an embedded trap for accommodating a light emitter and a method for manufacturing the same, as well as a device for emissivity-based interrogation of multiple samples and a method for manufacturing the same.

[0007] In a first aspect, an image sensor is provided having an embedded well for housing a light emitter. The image sensor includes a semiconductor substrate comprising an array of doped sensing regions, each corresponding to an array of photosensitive pixels of the image sensor. The semiconductor substrate forms an array of wells. Each well is aligned with a corresponding doped sensing region to facilitate the detection by a photosensitive pixel including the corresponding doped sensing region of light emitted by a light emitter disposed in the well to the photosensitive pixel. The image sensor also includes a light-blocking barrier between adjacent doped sensing regions to reduce light propagation from wells not aligned with the doped sensing regions of each photosensitive pixel to the doped sensing region of each photosensitive pixel.

[0008] In this embodiment, the light-blocking barrier is at least partially reflective.

[0009] In one embodiment, the well is located in the light-receiving surface of the semiconductor substrate, and the light-blocking barrier spans at least from the top of the light-receiving surface of the semiconductor substrate to the bottom of the well in a dimension orthogonal to the plane of the array of doped sensing regions.

[0010] In one embodiment, each doped sensing region spans at least from above to below the bottom of the well in a dimension orthogonal to the plane of the array of photosensitive pixels.

[0011] In one embodiment, the well is located in the light-receiving surface of the semiconductor substrate, and the image sensor further includes one or more top layers disposed on the light-receiving surface and lining the well to form an array of lined wells, the one or more top layers including at least one passivation layer.

[0012] In one embodiment, the light-blocking barrier has a first span in a first dimension orthogonal to the plane of the array of photosensitive pixels, the first span extending at least from the top of the light-receiving surface to below the bottom of the lined trap.

[0013] In one embodiment, each doped sensing region has a second span in the first dimension, the second span overlapping the first span.

[0014] In one embodiment, the second span extends at least from above the bottom of the lined trap to below the bottom of the trap.

[0015] In one embodiment, the second span is located only below the bottom of the trap.

[0016] In an embodiment, the one or more top layers include: a first passivation layer disposed on the light-receiving surface; a high-k dielectric layer disposed on the first passivation layer; and a second passivation layer disposed on the high-k dielectric layer.

[0017] In one embodiment, the semiconductor substrate also forms trenches between adjacent photosensitive pixels, the first passivation layer and the high-k dielectric layer are lining the trenches, and the light-blocking barrier is a light-blocking deep trench isolation disposed on the high-k dielectric layer in the trenches.

[0018] In one embodiment, the bottom of each well is located between 50 and 300 nanometers below the top of the semiconductor substrate, each well has a width in the range of 50 to 1000 nanometers, and the array of photosensitive pixels is characterized by a pitch in the range of 0.5 to 3.0 micrometers.

[0019] In this embodiment, each well has a flat bottom surface.

[0020] In a second aspect, an apparatus for luminescence-based interrogation of multiple samples is provided. The apparatus includes: an image sensor according to an embodiment of the first aspect, wherein each light emitter is a sample; and a cover disposed on one side of the image sensor having the traps, the cover forming (a) a fluid chamber above at least some of the traps in the traps, (b) an inlet port for receiving fluid into the fluid chamber to interact with the plurality of samples when each of the samples is placed in a corresponding trap accessible from the fluid chamber in the traps, and (c) an outlet port cooperating with the inlet port to allow the fluid to flow through the sample chamber.

[0021] In a third aspect, a method is provided for manufacturing an image sensor having embedded wells for housing light emitters. The method includes: (a) etching an array of wells in a first surface of a semiconductor substrate; (b) etching trenches in the first surface such that, after the step of etching the array of wells, the trenches are between adjacent wells; and (c) depositing deep trench isolation comprising a light-blocking material in the trenches, wherein, when the semiconductor substrate includes an array of doped sensing regions respectively aligned with the array of wells, the deep trench isolation reduces the propagation of light from each well to doped sensing regions not aligned with that well.

[0022] In an embodiment, the method further includes:

[0023] After the step of etching the array of wells and the trenches and before the step of depositing the deep trench isolation, a high-k dielectric liner is deposited on the first surface to prevent recombination of photogenerated charges at the first surface;

[0024] In the step of depositing the deep trench isolation, the deep trench isolation is deposited on the liner of the high-k dielectric material.

[0025] In one embodiment, the deep trench isolation is an oxide, and the method further includes:

[0026] Prior to the step of depositing the high-k dielectric material, a first passivation layer is deposited on the first surface; and

[0027] In the step of depositing the deep trench isolation:

[0028] The trenches are filled with the oxide to form a light-blocking barrier, and

[0029] The oxide is used to cover the liner of the high-k dielectric material to form a second passivation layer;

[0030] In the step of depositing the high-k dielectric material, the liner of the high-k dielectric material is deposited on the first passivation layer.

[0031] In an embodiment, the method further includes doping the semiconductor substrate to form an array of doped sensing regions, such that after the steps of etching the array of wells and etching the trenches, each doped sensing region extends from a maximum depth below the first surface to a minimum depth less than each of (a) the depth of the trenches below the first surface and (b) the depth of the wells below the first surface.

[0032] In an embodiment, the method further includes doping the semiconductor substrate to form an array of doped sensing regions, such that (a) after the steps of etching the array of wells and etching the trenches, each doped sensing region has a first span in a first dimension orthogonal to the array of doped sensing regions, the first span being only below the array of wells, and (b) the light-blocking material has a second span in the first dimension, the second span extending to the top of the first surface and overlapping the first span.

[0033] In a fourth aspect, a method is provided for manufacturing a light-emitting-based interrogation device for multiple light emitters. The method includes: performing the method according to an embodiment of the third aspect; and forming fluid chambers on at least some of the traps in the traps. Attached Figure Description

[0034] Figure 1 and Figure 2 An image sensor with an embedded trap according to an embodiment is illustrated, the embedded sensor being used to house a light emitter to be evaluated by the image sensor. Figure 1 This is a cross-sectional view of the image sensor in the example use case. Figure 2 This is a top view of the image sensor.

[0035] Figure 3An example device is shown, which has a trap on top of the light-receiving surface of the semiconductor substrate of an image sensor.

[0036] Figure 4 Showing more details Figure 1 and Figure 2 The pixel configuration of the image sensor.

[0037] Figure 5 An image sensor with a trap embedded in a doped sensing region is illustrated according to an embodiment.

[0038] Figure 6 An image sensor with an embedded well and a high-k passivation liner according to an embodiment is illustrated.

[0039] Figure 7 yes Figure 6 A more detailed view of a portion of the image sensor.

[0040] Figure 8 The illustration depicts a method for manufacturing an image sensor having an embedded trap for housing a light emitter, according to an embodiment.

[0041] Figure 9A –D is Figure 8 A schematic diagram illustrating some steps of the method.

[0042] Figure 10 The illustration depicts a method for manufacturing an apparatus for luminescence-based interrogation of multiple light emitters, according to an embodiment.

[0043] Figure 11 A light emission-based interrogation apparatus for multiple light emitters according to an embodiment is schematically illustrated.

[0044] Figure 12 Another device for luminescence-based interrogation of multiple light emitters according to an embodiment is schematically illustrated. Detailed Implementation

[0045] Figure 1 and Figure 2 An image sensor 100 with an embedded well is illustrated, which is used to house a light emitter to be evaluated by the image sensor. Figure 1 This is a cross-sectional view of the image sensor 100 in the example use case. Figure 2 This is a top view of the image sensor 100. Figure 1 and Figure 2 It also shows the right-handed Cartesian coordinate system 190. Figure 1 The cross-section lies in the xz plane of coordinate system 190, and Figure 2 The view is in the xy plane of coordinate system 190. It is best to view both in the following description. Figure 1 and Figure 2 The image sensor 100 includes an array of photosensitive pixels 120, each photosensitive pixel 120 being configured to detect light emitted by a corresponding light emitter 160 disposed in a well 124 embedded in the photosensitive pixel 120. Therefore, the image sensor 100 is well-suited for parallel processing of a large number of light emitters 160 via near-field imaging.

[0046] Each light emitter 160 is, for example, (a) a biological or chemical sample capable of emitting light (such as fluorescence in response to, for example, ultraviolet light excitation or luminescence caused by a reaction), (b) one or more quantum dots emitting fluorescence in response to, for example, ultraviolet light excitation, or (c) a light emitting device such as a light-emitting diode. Each light emitter 160 may emit light in the ultraviolet, visible, and / or infrared wavelength range. In one use case, each light emitter 160 is a DNA sample or DNA fragment.

[0047] It should be understood that the image sensor 100 may include more than Figure 1 and Figure 2 The image sensor 100 may include, for example, thousands or tens of thousands of pixels 120, as depicted in the image.

[0048] Compared to devices that place a sample or other form of light emitter on top of or above the image sensor for near-field imaging, image sensor 100 benefits from improved light detection efficiency. Image sensor 100 is also configured to reduce or eliminate crosstalk between pixels. The combination of improved light collection efficiency and crosstalk suppression results in image sensor 100 having improved sensitivity for detecting light emitted by light emitter 160 disposed in trap 124.

[0049] Image sensor 100 includes a semiconductor substrate 110 comprising an array of doped sensing regions 122. Image sensor 100 may be a complementary metal-oxide-semiconductor (CMOS) image sensor, and semiconductor substrate 110 may be a silicon substrate. Each doped sensing region 122 belongs to a corresponding photosensitive pixel 120 of a pixel array of image sensor 100. In one embodiment, semiconductor substrate 110 is generally p-doped, except that the semiconductor substrate 110 contains n-doped sensing regions 122. In other embodiments, the polarity may be reversed, for example, by utilizing p-doped sensing regions formed in an n-doped semiconductor substrate. Each pixel 120 detects light incident upon it by measuring one or more photoinduced charges generated in the corresponding doped sensing region 122. Semiconductor substrate 110 forms an array of wells 124 in its light-receiving surface 112. Each well 124 is embedded in a corresponding pixel 120 and aligned with the doped sensing region 122 of that pixel 120; that is, a pair of co-aligned wells 124 and doped sensing regions 122 are at the same x and y positions. Each well 124 is configured to accommodate a light emitter 160, such that the pixel 120 in which the well 124 is embedded can detect light emitted by the light emitter 160. Although in Figure 1 The image shows the sensor region 122 located only below the light-receiving surface 112, but each doped sensing region 122 may extend closer to the light-receiving surface 112 and surround at least a portion of the corresponding light-receiving surface 124.

[0050] To reduce or eliminate crosstalk between different pixels 120, the image sensor 100 also includes a grid of light-blocking barriers 132. Each barrier 132 is embedded in the semiconductor substrate 110 along the boundary 130 between adjacent pixels 120 and optionally also around the periphery of the array of pixels 120, as shown. Figure 2 As shown in the diagram. Barrier 132 can be used as a deep trench isolation between adjacent pixels 120. In a typical scenario, when light emitter 160 emits light, this light is emitted from light emitter 160 in all directions. Therefore, for light emitter 160 disposed in a trap 124, some of the emitted light propagates from light emitter 160 along the path remaining within the corresponding pixel 120, and the resulting photoinduced charge is collected by the doped sensing region 122 (e.g., see...). Figure 1 The light 170 propagates from the trap 124 of pixel 120(2) along the negative z direction. However, other light can propagate from the light emitter 160 in the direction toward the adjacent pixel 120 (e.g., see [link]). Figure 1The light 170 propagates from the well 124 of pixel 120 (2) in the direction toward adjacent pixels 120 (1) and 120 (3). The barrier 132 around each pixel 120 helps prevent at least some of this light from reaching adjacent pixels 120, which would otherwise cause photoinduced charges to be generated in the doped sensing area 122 of the adjacent pixel 120.

[0051] In some embodiments, barrier 132 is at least partially reflective. In such embodiments, barrier 132 redirects light incident upon it back to the pixel 120 from which the light originates. Depending on the angle of incidence of the light on barrier 132 and the exact location of the doped sensing region 122 (e.g., relative to the corresponding well 124), this reflected light can be redirected to the doped sensing region 122 of the pixel 120 from which the light originates. Thus, in these embodiments, barrier 132 not only suppresses crosstalk but also increases the light collection efficiency of pixel 120. Barrier 132 may comprise a metal, such as tungsten. Alternatively, barrier 132 may comprise a dielectric material. In one example, barrier 132 comprises a dielectric material having a lower refractive index than semiconductor substrate 110 to facilitate total internal reflection of light incident on barrier 132 at a relatively shallow angle.

[0052] Figure 1 An image sensor 100 is illustrated in an example use case where it is implemented in device 102 for emissivity-based interrogation of multiple samples, each representing an example of a light emitter 160. In addition to the image sensor 100, device 102 also includes a cover 150 forming a fluid chamber 158 on a light-receiving surface 112 of the image sensor 100. The cover 150 also forms at least two ports 156. The cover 150 may include (a) a baffle 152 forming an aperture over at least some of the array of pixels 120, and (b) a cap 154 ​​covering this aperture, such that the baffle 152 and the cap 154 ​​cooperate to form the fluid chamber 158. In an embodiment, a space or gap 158H exists between the light-receiving surface 112 and the cap 154. The baffle 152 and the cap 154 ​​may be two separate components or a single integrally formed (e.g., molded) part. Figure 2 The area 252 covered by the baffle 152 of the light receiving surface 112 is shown.

[0053] In the depicted example, the cover 150 is configured such that the fluid chamber 158 is located over the entire array of pixels 120. Without departing from the scope of the invention, the cover 150 may alternatively be configured to form the fluid chamber 158 only over a subset of the array of pixels 120, or the cover 150 may be configured to form several fluid chambers 158 over corresponding subsets of the array of pixels 120. Moreover, although in Figure 1The central port 156 is depicted as being formed in the cover 154, but one or more ports 156 may alternatively be formed in the baffle 152 without departing from the scope of the invention.

[0054] In the operation of device 102, each sample (light emitter 160) is placed in a different trap 124, and then image sensor 100 monitors the sample's response to fluid added to fluid chamber 158 via at least one port 156. More specifically, if the sample's exposure to the fluid in fluid chamber 158 causes luminescence, such as chemiluminescence, then this luminescence can be detected by the pixel 120 where the sample is located.

[0055] Figure 3 With similar Figure 1 A cross-sectional view of the image sensor 302 shows a device 302 having a sample well on top of the light-receiving surface 312 of the semiconductor substrate 310 of the image sensor 300. In addition to the image sensor 300, the device 302 also includes a structure 340 disposed on the light-receiving surface 312 of the semiconductor substrate 310. The structure 340 forms a well 344 configured to accommodate a corresponding sample 360. The image sensor 300 includes (a) an array of photosensitive pixels 320 and (b) light-blocking deep trench isolation 332 in the semiconductor substrate 310 along a boundary 330 between adjacent pixels 320. Each pixel 320 includes a doped sensing region 322 of the semiconductor substrate 310. Each well 344 is aligned with the corresponding doped sensing region 322, i.e., each well 344 is located at the same x and y positions as the corresponding doped sensing region 322. For each well 344, the pixel 320 aligned therewith is configured to detect light emitted from a sample 360 ​​disposed in the well 344 located above the pixel 320.

[0056] Because the well 344 is located on or above the light-receiving surface 312, the light collection efficiency of the pixel 320 for light emitted from the sample 360 ​​in the corresponding well 344 is limited. Even in the optimal scenario (where the bottom of each well 344 coincides with the light-receiving surface 312), the solid angle of the light emitted by the sample 360 ​​in the well 344 reaches at most half of the corresponding pixel 320. In practice, the pixel 320 can detect less than half of the solid angle of this emitted light. Furthermore, the light blocking provided by the deep trench isolation 332 is only below the well 344 (in the negative z direction). Therefore, some light emitted by the sample 360 ​​disposed in one well 344 can pass over the deep trench isolation 332 and reach adjacent pixels 320, thus generating crosstalk. This crosstalk is particularly prominent for instances of image sensors 300 characterized by a small pitch 328 of the array of pixels 320. Therefore, instances of devices 302 that implement high-resolution image sensors 300 are particularly affected by crosstalk.

[0057] Alternatively, device 302 can be provided without structure 340, instead relying on the binding site where sample 360 ​​is attached to light-receiving surface 312. However, this alternative version of device 302 suffers from the same problems, namely, low light collection efficiency and high crosstalk, as discussed above for device 302 with structure 340.

[0058] Compared to image sensor 300, the embedded well 124 of image sensor 100 enables the detection of a larger solid angle of light emitted by light emitter 160 (e.g., a sample) disposed in well 124. Furthermore, compared to device 302 where sample 360 ​​must be located above deep trench isolation 332 in the z-direction, barrier 132 of image sensor 100 cooperates with embedded well 124 to improve crosstalk suppression.

[0059] Refer again Figure 1 and Figure 2 The image sensor 100 is particularly advantageous in scenarios where the light emitter 160 emits only relatively little light due to its improved sensitivity. The image sensor 100 can detect light emission below the detection threshold of the device 302.

[0060] Device 102 can be used to perform deoxyribonucleic acid (DNA) sequencing. In one such example, DNA fragment samples are added to fluid chamber 158 via port 156. Each DNA fragment sample can be a DNA nanosphere having many copies of the same DNA fragment. At least some of the DNA fragment samples are attached to traps 124 of image sensor 100 in such a way that, ideally, each trap 124 contains at most one DNA fragment sample (which may include many copies of the same DNA fragment). Next, a series of solutions (each containing a corresponding nucleobase) are added to fluid chamber 158 via port 156. In this example scenario, the binding of nucleobases to the DNA fragment samples produces chemiluminescence. For each solution, image sensor 100 captures an image. In these images, a light level above a threshold detected by a given pixel 120 indicates that nucleobases have bound to the DNA fragment sample set in trap 124 of that pixel 120. Thus, the series of images captured in this scheme provides the nucleobase sequence of each DNA fragment sample. Since the chemiluminescence generated during the binding process may be weak, the accuracy of DNA sequencing can greatly benefit from the increased sensitivity of the image sensor 100.

[0061] Figure 4Three adjacent pixels 120(1), 120(2), and 120(3) of the image sensor 100 are depicted in cross-sectional view to illustrate the pixel configuration of the image sensor 100 in more detail. Each well 124 has a span 454 in the z-axis from the top of the light-receiving surface 112 to the bottom 426 of the well 124. The bottom 426 may be flat. The bottom 426 of the well 124 has a width 464, and the top of each well 124 has a width 465. In one embodiment, each well 124 has a square cross-section (e.g., Figure 2 (As depicted in the illustration), and widths 464 and 465 are the side lengths of the square cross-section. In an alternative embodiment, each well 124 has a circular cross-section, and widths 464 and 465 are the diameters of the circular cross-section. In another alternative embodiment, each well 124 has an oblong rectangular (or elongated oval) cross-section, and widths 464 and 465 are the diameters of the oblong rectangular cross-section. Widths 464 and 465 can be exactly the same, or width 465 can be greater than width 464, such that well 124 is tapered. In one example, width 464 is in the range of 50 to 300 nanometers, width 465 is in the range of 100 to 1000 nanometers, and span 454 is in the range of 50 to 500 nanometers. In one scenario, light emitter 160 is disposed directly on or within 100 nanometers of bottom 426. Without departing from the scope of the invention, light receiving surface 112 (including well 124 and trenches housing barrier 132) may be covered with one or more passivation layers / liners. In such an embodiment, the dimensions listed here for width 464, width 465 and span 454 can be applied to a trap covered by such a passivation layer / liner.

[0062] Each pixel 120 has a width equal to the pitch 128. Each barrier 132 has a width of 468. The width 468 can be in the range between 100 and 500 nanometers. The pitch 128 is at least as large as the sum of widths 465 and 468. The pitch 128 can be in the range between 0.5 and 3.0 micrometers. Each doped sensing region 122 has a width of 462. The width 462 is smaller than the pitch 128. The width 462 can exceed the width 464, and the width 462 can also exceed the width 465.

[0063] Each doped sensing region 122 has a span of 452 in the z-axis. For example... Figure 4As shown, span 452 may not overlap with span 454 of well 124. Alternatively, in pixel 120, the doped sensing region 122 extends above bottom 426 such that span 452 overlaps with span 454. In one example, the doped sensing region 122 extends into the space between well 124 and adjacent barrier 132. Barrier 132 has a span 456 in the z-dimensional, which extends from the top of light-receiving surface 112 in the negative z-direction. Span 456 may be the same as span 454. However, when span 456 exceeds span 454, more effective crosstalk suppression (such as...) can be achieved. Figure 4 (as shown in the image).

[0064] Figure 5 The illustration shows an image sensor 500 with a trap embedded in a doped sensing region. Figure 5 To be used for Figure 4 A similar view to the image sensor 100 depicts image sensor 500. Image sensor 500 is an embodiment of image sensor 300. Image sensor 500 includes an array of pixels 520, which are embodiments of pixels 120. Each pixel 520 includes a doped sensing region 522 formed, for example, in a semiconductor substrate 110 by ion implantation. The doped sensing region 522 is an embodiment of doped sensing region 122. Each doped sensing region 522 is formed to extend sufficiently close to the light-receiving surface 112 to surround a portion of a corresponding well 124. In other words, the span 552 of each doped sensing region 522 overlaps with the span 454 of the well 124 in the z-axis.

[0065] The configuration of the doped sensing region 522 helps to further improve the efficiency of detecting light 170 emitted by the light emitter 160 disposed in the trap 124. In particular, the light 170 emitted by the light emitter 160 in a slightly upward direction (i.e., a direction with components in both the xy and positive z directions) can cause photoinduced charges to be generated in a portion of the doped sensing region 522 above the bottom 426 of the trap 124. Therefore, the pixel 520 is able to detect more than half of the solid angle of the light 170 emitted from the light emitter 160.

[0066] Figure 6 An image sensor 600 with an embedded well and a high-k passivation liner is illustrated. Image sensor 600 is an embodiment of image sensor 100. Figure 6 To be similar to the use of Figure 4A cross-sectional view of image sensor 600 is shown in the image sensor 100. In image sensor 600, a light-receiving surface 112 of semiconductor substrate 110 is lined with a high-k passivation liner 642. The high-k passivation liner 642 is disposed on top of the light-receiving surface 112, including the surface of well 624 and the surface of the trench in semiconductor substrate 110 that accommodates barrier 132. A passivation layer 640 may be disposed between semiconductor substrate 110 and high-k passivation liner 642. In this example, each of the passivation layer 640 and the high-k passivation liner 642 is conformally deposited onto the inner surface of well 624.

[0067] The high-k passivation liner 642 is a dielectric material with a dielectric constant κ, for example, greater than the dielectric constant of the passivation layer 640. The passivation layer 640 is used to passivate the surface of the semiconductor substrate 110. The high-k passivation liner 642 has a negative charge, which pushes photoinduced electrons located near the surface of the semiconductor substrate 110 into the doped sensing region 122, preventing such electrons from recombining at the surface of the semiconductor substrate 110 (such as at the interface between the well 624 and the semiconductor substrate 110 material). In one embodiment, the passivation layer 640 is silicon dioxide, and the dielectric constant κ of the high-k passivation liner 642 is greater than 3.9 (the dielectric constant of silicon dioxide). In another embodiment, the passivation layer 640 comprises silicon nitride. The high-k passivation liner 642 is or includes, for example, aluminum oxide (Al2O3), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), or combinations thereof. In one embodiment, after depositing the high-k passivation liner 642, the trench is filled with a filler material to form the barrier 132. The filler material is, for example, a dielectric material such as silicon dioxide or a reflective material such as a metal.

[0068] Image sensor 100 may also include a passivation layer 644 covering a high-k passivation liner 642. Passivation layer 644 may be formed by deposition and conformally fitted to the high-k passivation liner 642. Passivation layer 644 may be used to provide a surface 612 for image sensor 600 (facing fluid chamber 158 when image sensor 600 is implemented in device 102), which is adapted to place light emitter 160 thereon. Passivation layer 644 may include silicon dioxide and / or silicon nitride.

[0069] Image sensor 600 forms lined wells 624. Each lined well 624 is a well 124 lined with a high-k passivation liner 642 and optionally one or both of passivation layers 640 and 644. The dimensions of well 624 can be similar to Figure 4 Those indicated by trap 124.

[0070] Figure 7This is a more detailed view of portion 690 of the image sensor 600 near the well 624. A high-k passivation liner 642 has a thickness 772 on top of the light-receiving surface 112 and a thickness 782 at the bottom 626 of the well 624. Thicknesses 772 and 782 can range between 3 and 100 nanometers. A passivation layer 640 has a thickness 770 on top of the light-receiving surface 112 and a thickness 780 at the bottom 626 of the well 624. Thicknesses 770 and 780 can range between 5 and 100 nanometers. A passivation layer 644 has a thickness 774 on top of the light-receiving surface 112 and a thickness 784 at the bottom 626 of the well 624. Thickness 784 can range between 1 and 200 nanometers. Thickness 774 can be similar to or greater than thickness 784.

[0071] Without deviating from its range, the image sensor 600 can realize a doped sensing area 522.

[0072] Figure 8 A method 800 for manufacturing an image sensor having embedded wells for housing light emitters is illustrated. Method 800 can be used to manufacture an image sensor 100. Method 800 includes steps 810 and 840. Step 810 includes steps 812 and 814. Step 812 etches an array of wells in a first surface of a semiconductor substrate. Step 814 etches trenches in the first surface such that, after step 812, these trenches are between adjacent wells. Step 840 deposits deep trench isolation comprising a light-blocking material in the trenches formed in step 814. When the semiconductor substrate includes an array of doped sensing regions aligned with the array of wells, the light-blocking material reduces the propagation of light from each well to doped sensing regions not aligned with that well.

[0073] Method 800 may include one or both of steps 820 and 830 performed between steps 810 and 840. Step 820 deposits a passivation layer on the first surface. Step 830 deposits a high-k dielectric liner on the first surface to prevent recombination of photogenerated charges at the first surface from causing dark currents and white pixels. In embodiments of method 800 that include both steps 820 and 830, step 830 deposits a high-k dielectric liner on the passivation layer deposited in step 820. Each of steps 820 and 830 may utilize chemical vapor deposition, plasma vapor deposition, or atomic layer deposition.

[0074] Figure 9AAn example of step 810 is shown. In this example, step 812 etches wells 124 in the light-receiving surface 112 of the semiconductor substrate 110, and step 814 etches trenches 934 in the light-receiving surface 112 of the semiconductor substrate 110 between adjacent wells 124. Steps 812 and / or 814 can be performed before or after forming the doped semiconductor substrate 110 to form a doped sensing region 122 in the pixel 120. The trenches 934 and wells 124 can have the same depth relative to the light-receiving surface 112, or be deeper than each well 124. In some embodiments, the depth of the trench 934 is less than the depth of the well 124.

[0075] Figure 9B An example of steps 820 and 830 is shown, wherein a passivation layer 640 and / or a high-k passivation liner 642 are deposited on the light-receiving surface 112, including in a trench 934 and in a well 124 (to form a lined well 924).

[0076] Figure 9C An example of step 840 is shown. In this example, trench 934 is filled with light-blocking deep trench isolation 932. Deep trench isolation 932 may be similar to or the same as barrier 132. In embodiments where deep trench isolation is filled with a metallic material (e.g., tungsten or aluminum), well 124 may be covered with a photoresist material or a sacrificial oxide material before metal deposition. After metal deposition, the photoresist material or sacrificial oxide material is removed, for example by an etching process, to form an opening in each well 124. Subsequently, oxide may be deposited into the well 124 to form an oxide liner layer lining the sidewalls of the well 124.

[0077] Refer again Figure 8 One embodiment of method 800 includes step 802, which involves doping a semiconductor substrate to form a doped sensing region. For example... Figure 8 As shown, step 802 may be performed before step 810, or step 802 may be performed at a later stage of method 800. In one example of step 802, the semiconductor substrate 110 is doped to form a doped sensing region 122 (optionally in the form of a doped sensing region 522).

[0078] In one embodiment, the deep trench isolation deposited in step 840 is an oxide, method 800 includes step 830, and step 840 includes steps 842 and 844. In this embodiment, the oxide may be a dielectric material having a lower refractive index than the semiconductor substrate, such as silicon oxide, to promote total internal reflection of light incident on the barrier in the trench at a relatively shallow angle. In this embodiment, a deposition process (a) fills the trench with oxide to form a light-blocking barrier (in step 842), and (b) covers a high-k dielectric liner with oxide to form a second passivation layer on top of the high-k dielectric liner. This embodiment of step 840 may utilize chemical vapor deposition, plasma vapor deposition, or atomic layer deposition. In this embodiment, the trench is narrower than the well, such that when the deposition process fills the trench with oxide, the oxide liner has accumulated over the entire surface of the high-k dielectric liner. In one embodiment, the second passivation layer formed by oxide deposition may also extend over the entire surface. Figure 9D An example of step 844 is shown. In this example, step 844 covers the high-k dielectric passivation liner 642 with an oxide material and etches the oxide to (a) reopen the well 924 to form the well 624, while (b) the remaining oxide material forms the passivation layer 644. Step 844 may also include thinning the portion of the passivation layer 644 located above the top of the light-receiving surface 912 and covering it with a deep trench isolation 932. Figure 9D As depicted, the deep trench isolation 932 can extend deeper into the semiconductor substrate 110 than the bottom 626 of the lined well 624.

[0079] In another embodiment, the deep trench isolation deposited in step 840 comprises a metal (such as tungsten and / or aluminum), and method 800 includes steps 820 and 830. The metal can block light by reflecting and / or absorbing it. In this embodiment, step 840 may include the following steps in the listed order: (1) depositing a mask material (e.g., a sacrificial oxide) on the surface of a semiconductor substrate (e.g., on a high-k dielectric material deposited in step 830) to fill the trenches and wells and cover the entire light-receiving surface of the semiconductor substrate such that no metal will be deposited in the wells; (2) chemically and mechanically polishing the mask material (e.g., the sacrificial oxide) for subsequent processes (e.g., photolithography and etching processes); (3) reopening the deposited trenches of the deep trench isolation; (4) depositing metal in the trenches; (5) reopening the wells; and (6) depositing an oxide across the entire surface and lining the inner surface of the wells to form a second passivation layer.

[0080] Without departing from the scope of the invention, method 800 may further include forming a control and readout circuitry system on a side of the semiconductor substrate opposite to the side of the semiconductor substrate forming the well. In one example, the control and readout circuitry system is formed on the side of the semiconductor substrate opposite to the light-receiving surface 112.

[0081] Figure 10 A method 1000 for manufacturing a light-emitting based interrogation device for multiple light emitters is illustrated. Method 1000 can be used to manufacture device 102. Method 1000 includes steps 1010 and 1020. Step 1010 performs method 800 to form an image sensor, such as image sensor 100, having embedded wells. Step 1020 forms fluid chambers over at least some of the wells. In one example of step 1020, method 1000 places a cover 150 on the light-receiving surface 112 of the image sensor 100, such that the cover 150 forms fluid chambers 158 over at least a portion of the array of wells 124.

[0082] Figure 11 A device 1100 for light emission-based interrogation of multiple light emitters is schematically illustrated. Device 1100 is an embodiment of device 102 and includes an image sensor 100, a baffle 1110, and a cover 1120. The baffle 1110 is disposed on a light-receiving surface 112 and surrounds at least a portion of an array of wells 124. The baffle 1110 forms an aperture over a portion of the light-receiving surface 112. The cover 1120 covers the aperture formed by the baffle 1110 to form a fluid chamber similar to a fluid chamber 158. In one embodiment, the baffle 1110 is located outside the array of wells 124. In this embodiment, the baffle 1110 may have a shape similar to... Figure 2 The coverage area 252 shown is the coverage area. In another embodiment, baffle 1110 covers some of the array of traps 124, and the covered traps 124 cannot be accessed from the fluid chamber formed by baffle 1110 and cover 1120. Cover 1120 forms at least two ports 1122. In one scenario, ports 1122 are connected to an external device that supplies samples (e.g., DNA polymer chains) and known polymer-based chains to flow into and out of the fluid chamber (e.g., fluid chamber 158). Without departing from the scope of the invention, baffle 1110 and cover 1120 may be integrally formed.

[0083] In an extension of device 1100, baffle 1110 is modified to form two or more separate holes above light-receiving surface 112. In this extension, baffle 1110 and cover 1120 cooperate to form two or more separate fluid chambers on light-receiving surface 112, and cover 1120 may include two ports 1122 for each of these fluid chambers.

[0084] Figure 12 Another device 1200 for light emission-based interrogation of multiple samples is schematically illustrated. Device 1200 is an embodiment of device 102 and includes an image sensor 100, two baffles 1210, and a cover 1220. The baffles 1210 are disposed on two different portions of a light-receiving surface 112, spaced apart from each other, such that a portion of an array of traps 124 is not covered by the baffles 1210. The cover 1220 covers the space between the baffles 1210 to form a fluid chamber similar to a fluid chamber 158. This fluid chamber has two ports 1222, with the periphery of the cover 1220 spanning the gap between the two baffles 1210. In one embodiment, the baffles 1210 are located outside the array of traps 124. In another embodiment, at least one of the baffles 1210 covers some of the array of traps 124, and the covered traps 124 cannot be accessed from the fluid chamber formed by the baffles 1210 and the cover 1220. Without departing from the scope of the invention, the baffle 1210 and the cover 1220 may be integrally formed.

[0085] In the extension, device 1200 includes three or more baffles 1210 that cooperate with cover 1220 to form two or more separate fluid chambers on light receiving surface 112.

[0086] Combination of features

[0087] The features described above and the features claimed below can be combined in various ways without departing from the scope of the invention. For example, it will be understood that aspects of an image sensor or associated method described herein can be combined with or exchanged with features of another image sensor or associated method described herein. The following examples illustrate some possible non-limiting combinations of the above embodiments. It should be clear that many other changes and modifications can be made to the methods, products, and systems described herein without departing from the spirit and scope of the invention:

[0088] (A1) An image sensor having embedded wells for housing a light emitter includes a semiconductor substrate comprising an array of doped sensing regions corresponding respectively to an array of photosensitive pixels of the image sensor. The semiconductor substrate forms an array of wells. Each well is aligned with a corresponding doped sensing region to facilitate the detection by a photosensitive pixel including the corresponding doped sensing region of light emitted by a light emitter disposed in the well to the photosensitive pixel. The image sensor also includes light-blocking barriers between adjacent doped sensing regions to reduce light propagation from wells not aligned with the doped sensing regions of each photosensitive pixel to the doped sensing regions of each photosensitive pixel.

[0089] (A2) In an image sensor denoted as (A1), the light-blocking barrier may be at least partially reflective.

[0090] (A3) In either of the image sensors represented as (A1) and (A2), the trap may be located in the light-receiving surface of the semiconductor substrate, and the light-blocking barrier may span at least from the top of the light-receiving surface of the semiconductor substrate to the bottom of the trap in a dimension orthogonal to the plane of the array of doped sensing regions.

[0091] (A4) In any image sensor denoted as (A1) to (A3), each doped sensing region can span at least from above to below the bottom of the well in a dimension orthogonal to the plane of the array of photosensitive pixels.

[0092] (A5) In any image sensor denoted as (A1) to (A4), the trap may be located in the light-receiving surface of a semiconductor substrate, and the image sensor may further include one or more top layers disposed on the light-receiving surface and lining the traps to form an array of lined traps. The one or more top layers include at least one passivation layer.

[0093] (A6) In the image sensor denoted as (A5), the light-blocking barrier may have a first span in a first dimension orthogonal to the plane of the array of photosensitive pixels, and the first span may extend at least from the top of the light-receiving surface to below the bottom of the lined trap.

[0094] (A7) In an image sensor denoted as (A6), each doped sensing region may have a second span in a first dimension, the second span overlapping the first span.

[0095] (A8) In an image sensor denoted as (A7), the second span may extend at least from above the bottom of the lined trap to below the bottom of the trap.

[0096] (A9) In an image sensor denoted as (A7), the second span may be located only below the bottom of the trap.

[0097] (A10) In any image sensor denoted as (A5) to (A9), one or more top layers may include (a) a first passivation layer disposed on a light-receiving surface, (b) a high-k dielectric layer disposed on the first passivation layer, and (c) a second passivation layer disposed on the high-k dielectric layer.

[0098] (A11) In the image sensor denoted as (A10), a semiconductor substrate may form trenches between adjacent photosensitive pixels, a first passivation layer and a high-k dielectric layer are lined to the trenches, and a light-blocking barrier is a light-blocking deep trench isolation disposed on a high-k dielectric layer in the trenches.

[0099] (A12) In any image sensor denoted as (A5) to (A11), the bottom of each lined well may be between 50 and 300 nanometers below the top of the semiconductor substrate, each lined well may have a width in the range of 50 and 1000 nanometers, and the array of photosensitive pixels may be characterized by a pitch in the range of 0.5 and 3.0 micrometers.

[0100] (A13) In any image sensor denoted as (A5) to (A12), each lined trap may have a flat bottom surface.

[0101] (A14) In any image sensor denoted as (A1) to (A4), the bottom of each well may be between 50 and 300 nanometers below the top of the semiconductor substrate, each well may have a width in the range of 50 and 1000 nanometers, and the array of photosensitive pixels may be characterized by a pitch in the range of 0.5 and 3.0 micrometers.

[0102] (A15) In any image sensor denoted as (A14) and (A1) through (A4), each well may have a flat bottom surface.

[0103] (A16) A light emission-based interrogation device for multiple samples, comprising any one of an image sensor (represented as (A1) to (A16) wherein each light emitter is a sample), and a cover disposed on one side of the image sensor having a trap. The cover forms (a) a fluid chamber above at least some of the traps, (b) an inlet port for receiving fluid into the fluid chamber so as to interact with the plurality of samples when each of the plurality of samples is disposed in a corresponding trap accessible from the fluid chamber, and (c) an outlet port for cooperating with the inlet port to allow fluid flow through the sample chamber.

[0104] (B1) A method for manufacturing an image sensor having embedded wells for housing light emitters, comprising (a) etching an array of wells in a first surface of a semiconductor substrate, (b) etching trenches in the first surface such that, after the step of etching the array of wells, the trenches are between adjacent wells, and (c) depositing deep trench isolation comprising a light-blocking material in the trenches, wherein the light-blocking material reduces the propagation of light from each well to a doped sensing region not aligned with the well when the semiconductor substrate includes an array of doped sensing regions respectively aligned with the array of wells.

[0105] (B2) The method denoted as (B1) may further include: depositing a high-k dielectric material liner on the first surface after the step of etching the array of traps and trenches and before the step of depositing deep trench isolation to prevent recombination of photogenerated charges at the first surface, such that the deep trench isolation is deposited on the high-k dielectric material liner in the step of depositing deep trench isolation.

[0106] (B3) The method represented as (B2) may further include (i) depositing a first passivation layer on a first surface prior to the step of depositing the high-k dielectric material, and (ii) in the step of depositing deep trench isolation, (1) filling the trench with oxide to form a light-blocking barrier, and (2) covering the liner of the high-k dielectric material with oxide to form a second passivation layer, such that in the step of depositing the high-k dielectric material, the liner of the high-k dielectric material is deposited on the first passivation layer.

[0107] (B4) Any method represented as (B1) to (B3) may further include doping the semiconductor substrate to form an array of doped sensing regions, such that after the steps of etching the array of wells and etching the trenches, each doped sensing region extends from a maximum depth below the first surface to a minimum depth, wherein the minimum depth is less than each of the trench depth below the first surface and the well depth below the first surface.

[0108] (B5) Any method represented as (B1) to (B3) may further include doping a semiconductor substrate to form an array of doped sensing regions, such that (I) after the steps of etching the array of traps and etching trenches, each doped sensing region has a first span in a first dimension orthogonal to the array of doped sensing regions, the first span being only below the array of traps, and (II) the light-blocking material has a second span in the first dimension, the second span extending to the top of the first surface and overlapping the first span.

[0109] (B6) A method for manufacturing a light-emitting based interrogation device for a plurality of light emitters, comprising performing any of the methods represented by (B1) to (B5) and forming a fluid chamber above at least some of the traps in the traps.

[0110] Modifications to the above system and method may be made without departing from the scope of the invention. Therefore, it should be noted that the content contained in the above description and shown in the accompanying drawings should be interpreted as illustrative rather than restrictive. The following claims are intended to cover all statements regarding the general and specific features described herein, as well as the scope of the system and method, and for the purposes of language, may be considered to be somewhere in between.

Claims

1. An image sensor having multiple embedded wells for accommodating light emitters, comprising: A semiconductor substrate includes an array of doped sensing regions corresponding to an array of photosensitive pixels of the image sensor. The light-receiving surface of the semiconductor substrate forms an array of wells, each well extending from the light-receiving surface of the semiconductor substrate to a certain depth in the semiconductor substrate. Each well is aligned with a corresponding doped sensing region to facilitate the detection by a photosensitive pixel including the corresponding doped sensing region of light emitted by a light emitter disposed in the well. as well as A grid of light-blocking barriers is embedded in the semiconductor substrate along the boundaries between adjacent pixels in the array of photosensitive pixels and around the periphery of the array of photosensitive pixels to reduce the propagation of light from traps that are never aligned with the doped sensing regions of each photosensitive pixel to the doped sensing regions of each photosensitive pixel. The light-blocking barrier spans at least from the top of the light-receiving surface of the semiconductor substrate to the bottom of the well in a dimension orthogonal to the plane of the array of doped sensing regions, and the array of doped sensing regions at least partially overlaps the light-blocking barrier in that dimension.

2. The image sensor according to claim 1, wherein the light-blocking barrier is at least partially reflective.

3. The image sensor according to claim 1 or 2, wherein each doped sensing region spans at least from above to below the bottom of the well in a dimension orthogonal to the plane of the array of photosensitive pixels.

4. The image sensor according to claim 1 or 2, wherein the well is located in the light-receiving surface of the semiconductor substrate, and the image sensor further comprises one or more top layers disposed on the light-receiving surface and lining the array of wells to form an array of lined wells, the one or more top layers comprising at least one passivation layer.

5. The image sensor of claim 4, wherein the light-blocking barrier has a first span in a first dimension orthogonal to the plane of the array of photosensitive pixels, the first span extending at least from the top of the light-receiving surface to below the bottom of the lined trap.

6. The image sensor of claim 5, wherein each doped sensing region has a second span in the first dimension, the second span overlapping the first span.

7. The image sensor of claim 6, wherein the second span extends at least from above the bottom of the lined trap to below the bottom of the trap.

8. The image sensor of claim 6, wherein the second span is located only below the bottom of the trap.

9. The image sensor of claim 4, wherein the one or more top layers comprise: A first passivation layer is disposed on the light-receiving surface; A high-k dielectric layer disposed on the first passivation layer; as well as A second passivation layer is disposed on the high-k dielectric layer.

10. The image sensor according to claim 9, wherein the semiconductor substrate further forms a trench between adjacent photosensitive pixels, the first passivation layer and the high-k dielectric layer lining the trench, and the light-blocking barrier is a light-blocking deep trench isolation disposed on the high-k dielectric layer in the trench.

11. The image sensor of claim 1 or 2, wherein the bottom of each well is between 50 and 300 nanometers below the top of the semiconductor substrate, each well has a width in the range of 50 and 1000 nanometers, and the array of photosensitive pixels is characterized by a pitch in the range of 0.5 and 3.0 micrometers.

12. The image sensor according to claim 1 or 2, wherein each well has a flat bottom surface.

13. A device for luminescence-based interrogation of multiple samples, comprising: The image sensor according to any one of claims 1 to 12, wherein each light emitter is a sample; as well as A cover disposed on one side of the image sensor having the traps, the cover forming: (a) a fluid chamber above at least some of the traps in the traps; (b) for receiving fluid into the fluid chamber at an inlet port so that the fluid interacts with the plurality of samples when each of the samples is placed in a corresponding trap accessible from the fluid chamber in the trap; and (c) for cooperating with the inlet port to allow the fluid to flow through an outlet port of the sample chamber.

14. A method for manufacturing an image sensor having an embedded well for housing a light emitter, the method comprising: An array of traps is etched into the first surface of a semiconductor substrate; Trenches are etched in the first surface such that, after the step of etching the array of wells, the trenches are between adjacent wells; and Deep trench isolation comprising a light-blocking material is deposited in the trench. When the semiconductor substrate includes an array of doped sensing regions respectively aligned with the array of wells, the light-blocking material reduces the propagation of light from each well to the doped sensing regions not aligned with the wells, wherein the array of doped sensing regions corresponds to the array of photosensitive pixels of the image sensor. The deep trench isolation of the light-blocking material serves as a light-blocking barrier, which is embedded in the semiconductor substrate along the boundary between adjacent pixels in the array of photosensitive pixels and around the periphery of the array of photosensitive pixels. The light-blocking barrier spans at least from the top of the light-receiving surface of the semiconductor substrate to below the bottom of the well in a dimension orthogonal to the plane of the array of doped sensing regions, and the array of doped sensing regions at least partially overlaps with the light-blocking barrier in that dimension.

15. The method of claim 14, further comprising: After etching the array of wells and the trenches and before depositing the deep trench isolation, a high-k dielectric liner is deposited on the first surface to prevent recombination of photogenerated charges at the first surface. In the step of depositing the deep trench isolation, the deep trench isolation is deposited on the liner of the high-k dielectric material.

16. The method of claim 15, wherein the deep trench isolation is an oxide, and the method further comprises: Prior to the step of depositing the high-k dielectric material, a first passivation layer is deposited on the first surface; and In the step of depositing the deep trench isolation: The trenches are filled with the oxide to form a light-blocking barrier, and The oxide is used to cover the liner of the high-k dielectric material to form a second passivation layer; In the step of depositing the high-k dielectric material, the liner of the high-k dielectric material is deposited on the first passivation layer.

17. The method of any one of claims 14 to 16, further comprising doping the semiconductor substrate to form an array of doped sensing regions, such that after the steps of etching the array of wells and etching the trenches, each doped sensing region extends from a maximum depth below the first surface to a minimum depth, the minimum depth being less than each of (a) the depth of the trenches below the first surface and (b) the depth of the wells below the first surface.

18. The method of any one of claims 14 to 16, further comprising doping the semiconductor substrate to form an array of doped sensing regions, such that (a) after the steps of etching the array of wells and etching the trenches, each doped sensing region has a first span in a first dimension orthogonal to the array of doped sensing regions, the first span being only below the array of wells, and (b) the light-blocking material has a second span in the first dimension, the second span extending to the top of the first surface and overlapping the first span.

19. A method for manufacturing an apparatus for emitting light based interrogation of a plurality of light emitters, comprising: Perform the method according to any one of claims 14 to 18; and Fluid chambers are formed on at least some of the wells in the well.

Images