Light emitting display device and method of manufacturing light emitting display device

Abstract

The present disclosure relates to a light emitting display device and a method of manufacturing a light emitting display device, the light emitting display device including a substrate including a display area and a non-display area adjacent to the display area, a lower pad electrode on the substrate in the non-display area, a planarization layer overlapping the lower pad electrode, and an upper pad electrode on the lower pad electrode and overlapping at least a portion of the lower planarization layer. The planarization layer includes an opening exposing an upper surface of the lower pad electrode, the lower pad electrode and the upper pad electrode are electrically connected to each other through the opening, the lower planarization layer includes an exposed portion exposing an upper surface of the lower planarization layer and an overlapping portion overlapping at least a portion of the upper pad electrode, and a height of the upper surface of the exposed portion is lower than a height of an upper surface of the overlapping portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0047919, filed on April 21, 2020, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0079129, filed on June 29, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a light-emitting display device and a method for manufacturing the light-emitting display device. Background Technology

[0004] The light-emitting display device can be a self-emissive display device that uses light-emitting diodes (LEDs) to display images.

[0005] Unlike liquid crystal displays (LCDs), light-emitting displays do not require a separate light source, and therefore can be made relatively thinner and / or lighter. Furthermore, light-emitting displays can possess relatively better quality characteristics such as low power consumption, high brightness, and high response speed. Therefore, there is a growing demand for the development of light-emitting displays as the next generation of display devices for portable electronic devices.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background of the technology, and therefore, the information may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] Examples have been made in an effort to reduce damage to pad electrodes in non-display areas that may occur in subsequent processes such as color filter forming.

[0008] An embodiment provides a light-emitting display device, which may include: a substrate including a display area and a non-display area adjacent to the display area; a lower pad electrode disposed on the substrate in the non-display area; a planarization layer overlapping a portion of the lower pad electrode; and an upper pad electrode disposed on the lower pad electrode and overlapping at least a portion of the planarization layer, wherein the planarization layer may include an opening exposing the upper surface of the lower pad electrode, through which the lower pad electrode and the upper pad electrode may be electrically connected to each other, the planarization layer may include an exposed portion exposing the upper surface of the planarization layer and an overlapping portion overlapping at least a portion of the upper pad electrode, and the height of the upper surface of the exposed portion of the planarization layer may be lower than the height of the upper surface of the overlapping portion of the planarization layer.

[0009] The upper pad electrode may include an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti), and the lower pad electrode may include an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti).

[0010] The planarization layer may include at least one of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0011] The display area may include: a semiconductor layer disposed on the substrate; a gate insulating layer overlapping the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer overlapping the gate electrode; and a source electrode and a drain electrode disposed on the interlayer insulating layer and electrically connected to the semiconductor layer, wherein the lower pad electrode, the source electrode, and the drain electrode may be disposed on the same layer.

[0012] The light-emitting display device may further include: a pixel electrode disposed on the planarization layer; an emission layer disposed on the pixel electrode; and a common electrode disposed on the emission layer, wherein the planarization layer may overlap with the source electrode and the drain electrode, and may include vias, and the drain electrode and the pixel electrode may be electrically connected through the vias.

[0013] The display area may include: an encapsulation layer that overlaps with the common electrode; a sensing insulating layer disposed on the encapsulation layer; a sensing electrode disposed on the sensing insulating layer; and an inorganic passivation layer that overlaps with the sensing electrode, wherein the sensing electrode and the upper pad electrode may be disposed on the same layer.

[0014] The light-emitting display device may further include: a buffer layer disposed between the encapsulation layer and the sensing insulating layer, and disposed between the lower pad electrode and the upper pad electrode, wherein the lower pad electrode and the upper pad electrode are electrically connected to each other.

[0015] An embodiment provides a light-emitting display device, which may include: a substrate including a display area and a non-display area adjacent to the display area; a first lower pad electrode and a second lower pad electrode, the first lower pad electrode and the second lower pad electrode being spaced apart from each other and disposed in the non-display area; a first lower planarization layer, the first lower planarization layer at least partially overlapping the first lower pad electrode; a second lower planarization layer, the second lower planarization layer at least partially overlapping the second lower pad electrode; a first upper pad electrode, the first upper pad electrode overlapping the first lower pad electrode and the first lower planarization layer; a second upper pad electrode, the second upper pad electrode overlapping the second lower pad electrode and the second lower planarization layer; and a light-shielding member, the light-shielding member at least partially overlapping the first upper pad electrode and the second upper pad electrode, wherein the first upper pad electrode and the second upper pad electrode may be disposed on the same layer.

[0016] The upper surface of the light-shielding member may be higher than the upper surface of the first upper pad electrode and the upper surface of the second upper pad electrode.

[0017] Each of the first upper pad electrode and the second upper pad electrode may include an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti), and each of the first lower pad electrode and the second lower pad electrode may include an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti).

[0018] The distance from one end of the first lower pad electrode to one end of the second lower pad electrode can be in the range of about 10 μm to about 20 μm.

[0019] The distance from one end of the first upper pad electrode to one end of the second upper pad electrode can be approximately 10 μm or less.

[0020] The display area may include: a semiconductor layer disposed on the substrate; a gate insulating layer overlapping the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer overlapping the gate electrode; and a source electrode and a drain electrode disposed on the interlayer insulating layer and electrically connected to the semiconductor layer, wherein the first lower pad electrode, the second lower pad electrode, the source electrode, and the drain electrode may be disposed on the same layer.

[0021] The light-emitting display device may further include: a pixel electrode disposed on the first lower planarization layer; an emission layer disposed on the pixel electrode; a common electrode disposed on the emission layer; an encapsulation layer disposed on the common electrode; and a sensing electrode disposed on a sensing insulating layer, wherein the sensing insulating layer may be disposed on the encapsulation layer in the display area, the first lower planarization layer may overlap with the source electrode and the drain electrode, and the sensing electrode and the upper pad electrode may be disposed on the same layer.

[0022] The light-emitting display device may further include: a buffer layer disposed between the encapsulation layer and the sensing insulating layer, disposed between the first lower pad electrode and the first upper pad electrode, and disposed between the second lower pad electrode and the second upper pad electrode, wherein the first lower pad electrode can be electrically connected to the first upper pad electrode, and the second lower pad electrode can be electrically connected to the second upper pad electrode.

[0023] An embodiment provides a method for manufacturing a light-emitting display device, the light-emitting display device comprising: forming a gate insulating layer and an interlayer insulating layer on a substrate; forming a source electrode and a drain electrode on the interlayer insulating layer in a display region of the substrate; forming a lower pad electrode on the interlayer insulating layer in a non-display region of the substrate; forming a lower planarization layer on the source electrode, the drain electrode, and the lower pad electrode; forming a sensing electrode on a sensing insulating layer located on the lower planarization layer in the display region of the substrate; forming an upper pad electrode on the lower planarization layer in the non-display region of the substrate; forming an inorganic passivation layer to overlap with the sensing electrode and the upper pad electrode; forming a light-shielding member and a color filter on the inorganic passivation layer in the display region of the substrate; forming an upper planarization layer on the color filter; and etching the inorganic passivation layer in the non-display region of the substrate to partially expose the upper surface of the lower planarization layer.

[0024] The formation of the inorganic passivation layer may include etching the inorganic passivation layer by a dry etching process.

[0025] The exposed upper surface of the lower planarization layer may have a lower height than the upper surface of the lower planarization layer that overlaps with the upper pad electrode.

[0026] An embodiment provides a method for manufacturing a light-emitting display device, the method comprising: forming a gate insulating layer and an interlayer insulating layer on a substrate; forming a source electrode and a drain electrode on the interlayer insulating layer in a display region of the substrate; forming a first lower pad electrode and a second lower pad electrode on the interlayer insulating layer in a non-display region of the substrate; forming a lower planarization layer on the source electrode, the drain electrode, the first lower pad electrode, and the second lower pad electrode; forming a sensing electrode on a sensing insulating layer located on the lower planarization layer in the display region of the substrate; forming a first upper pad electrode and a second upper pad electrode on the lower planarization layer in the non-display region of the substrate; forming a light-shielding member and a color filter on the sensing electrode in the display region of the substrate; and forming the light-shielding member in the non-display region of the substrate to partially overlap with the first upper pad electrode and the second upper pad electrode.

[0027] The formation of the light-shielding member may include forming the light-shielding member between the first upper pad electrode and the second upper pad electrode in the non-display area of ​​the substrate.

[0028] An embodiment provides a light-emitting display device, which may include: a substrate, the substrate including a display area and a non-display area adjacent to the display area; a lower pad electrode disposed on the substrate in the non-display area; an upper pad electrode disposed on a pad inorganic insulating layer; an inorganic passivation layer disposed on the upper pad electrode or the pad inorganic insulating layer; and a planarization layer disposed on the inorganic passivation layer, wherein one end of the planarization layer may be aligned with one end of the inorganic passivation layer.

[0029] One end of the lower surface of the planarization layer can be aligned with one end of the upper surface of the inorganic passivation layer.

[0030] The inorganic passivation layer may be configured to partially overlap with the upper pad electrode, and the upper surface of the pad electrode may partially expose the light-emitting display device.

[0031] The inorganic passivation layer can be disposed on the inorganic insulating layer of the pad, and one end of the inorganic passivation layer can be spaced apart from the opposite end of the pad electrode.

[0032] The planarization layer may include organic insulating materials.

[0033] An embodiment provides a light-emitting display device, which may include: a substrate including a display area and a non-display area adjacent to the display area; an interlayer insulating layer disposed on the substrate; a lower pad electrode disposed on the interlayer insulating layer in the non-display area; a buffer layer overlapping a portion of the lower pad electrode; and an upper pad electrode disposed on the lower pad electrode to overlap at least a portion of the buffer layer, wherein the thickness of the portion of the buffer layer not overlapping the upper pad electrode may be thinner than the thickness of the portion of the buffer layer overlapping the upper pad electrode.

[0034] The upper pad electrode may include an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti), and the lower pad electrode may include an upper layer containing titanium (Ti), an intermediate layer containing aluminum (Al), and a lower layer containing titanium (Ti).

[0035] The display area may include: a semiconductor layer disposed on the substrate; a gate insulating layer overlapping the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer overlapping the gate electrode; a source electrode and a drain electrode disposed on the interlayer insulating layer and electrically connected to the semiconductor layer; and a lower planarization layer overlapping the source electrode and the drain electrode, wherein the lower pad electrode, the source electrode, and the drain electrode may be disposed on the same layer.

[0036] The light-emitting display device may further include: a pixel electrode disposed on the lower planarization layer; an emission layer disposed on the pixel electrode; and a common electrode disposed on the emission layer, wherein the lower planarization layer may overlap with the source electrode and the drain electrode and may include vias, and the drain electrode and the pixel electrode may be electrically connected through the vias.

[0037] The display area may include: an encapsulation layer overlapping the common electrode; a sensing insulating layer disposed on the encapsulation layer; a sensing electrode disposed on the sensing insulating layer; and an inorganic passivation layer overlapping the sensing electrode, wherein the sensing electrode and the upper pad electrode may be disposed on the same layer, the buffer layer may be disposed between the encapsulation layer and the sensing insulating layer, and the lower pad electrode may be electrically connected to the upper pad electrode.

[0038] According to an embodiment, when the pad electrode is formed in the non-display area, subsequent processes can be performed after an inorganic protective film is deposited on the pad electrode, thereby reducing potential damage to the pad electrode in subsequent processes such as color filter formation.

[0039] In addition, since the metal layer of the pad electrode can be protected, the performance of the pad electrode can also be maintained.

[0040] According to an embodiment, the end of the upper pad electrode can be protected by a light-shielding member, and thus the upper pad electrode can be formed, and damage to the upper pad electrode that may occur during the color filter forming process can be reduced. Attached Figure Description

[0041] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments and, together with the description, serve to illustrate the disclosure in conjunction with the drawings, in which:

[0042] Figure 1 A schematic top plan view of a light-emitting display device according to an embodiment is shown;

[0043] Figure 2 A top plan view of a portion of a light-emitting display device according to an embodiment, including a sensor, is shown;

[0044] Figure 3 A schematic cross-sectional view showing a portion of the display area in a light-emitting display device according to an embodiment is shown;

[0045] Figure 4 It shows Figure 3 A magnified scanning electron microscope image of region A in the image;

[0046] Figure 5 A portion of the pad portion in the light-emitting display device according to an embodiment is shown;

[0047] Figure 6 It shows along Figure 5 A schematic cross-sectional view of line VI-VI';

[0048] Figure 7 It shows Figure 6 Detailed view of region B in the image;

[0049] Figures 8 to 11 The method for manufacturing pads in a method for manufacturing a light-emitting display device according to an embodiment is illustrated schematically;

[0050] Figure 12 A schematic cross-sectional view of a portion of the display area in a light-emitting display device according to an embodiment is shown;

[0051] Figure 13 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown;

[0052] Figure 14A and Figure 14B A scanning electron microscope image showing a portion of a pad removed from a light-emitting display device according to an example;

[0053] Figure 15A and Figure 15B A scanning electron microscope image showing a portion of a pad removed from a light-emitting display device according to a comparative example;

[0054] Figure 16 and Figure 17 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown;

[0055] Figure 18 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown;

[0056] Figure 19 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown;

[0057] Figures 20 to 23 The method for manufacturing pads in a method for manufacturing a light-emitting display device according to an embodiment is illustrated schematically;

[0058] Figure 24 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown;

[0059] Figure 25 and Figure 26 A schematic cross-sectional view of a portion of the display area in a light-emitting display device according to an embodiment is shown;

[0060] Figure 27 A portion of a substrate including pads is shown in a light-emitting display device according to an embodiment;

[0061] Figure 28 It shows along Figure 27 A schematic cross-sectional view taken from line XXI-XXI'; and

[0062] Figure 29 and Figure 30 It shows Figure 28 Examples of implementations. Detailed Implementation

[0063] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. As those skilled in the art will recognize, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0064] For clarity of description, parts irrelevant to the description may be omitted, and throughout the specification, the same reference numerals denote the same or similar constituent elements.

[0065] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0066] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof.

[0067] The terms “and” and “or” can be used in the sense of combination or separation and can be understood as equivalent to “and / or”. In this specification and claims, for the purposes of its meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0068] While terms such as "first," "second," etc., can be used to describe various components, these components are not limited to those terms. The terms are used only to distinguish one component from another. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims.

[0069] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on said other element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in this specification, the terms "on" or "above" indicate positioning on or below a target portion, and do not necessarily indicate positioning above the target portion based on the direction of gravity.

[0070] Furthermore, when a layer, film, region, substrate, or location or element is referred to as being "below" another layer, film, region, substrate, or location or element, the layer, film, region, substrate, or location or element may be directly below the other layer, film, region, substrate, or location or element, or intermediate layers, intermediate films, intermediate regions, intermediate substrates, or intermediate locations or elements may exist between the layer, film, region, substrate, or location or element and the other layer, film, region, substrate, or location or element. Conversely, when a layer, film, region, substrate, or location or element is referred to as being "directly below" another layer, film, region, substrate, or location or element, intermediate layers, intermediate films, intermediate regions, intermediate substrates, or intermediate locations or elements may not exist between the layer, film, region, substrate, or location or element and the other layer, film, region, substrate, or location or element. Additionally, "above" or "on" can include being positioned on or below a target, and does not necessarily imply a direction based on gravity.

[0071] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” or “above” may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned “below” or “under” another device may be placed “above” another device. Therefore, the example term “below” can encompass both below and above orientations. The device may also be oriented in other directions, and thus, spatial relative terms may be interpreted differently depending on the orientation.

[0072] Additionally, the terms "overlapping" or "overlapping" indicate that the first target may be above or below the second target, or located to one side of the second target, and vice versa. Furthermore, the term "overlapping" may include layering, stacking, facing or oriented towards, extending above, covering or partially covering, or any other suitable term as will be understood and appreciated by those skilled in the art. The terms "facing" and "oriented towards" indicate that the first element may be directly or indirectly opposite the second element. Where a third element intervenes between the first and second elements, the first and second elements may be understood as being indirectly opposite each other, although still facing each other. When an element is described as "not overlapping" or "not intersecting" with another element, this may include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as will be understood and appreciated by those skilled in the art.

[0073] Additionally, when an element is referred to as being "in contact" or "in contact" with another element, the element may be "in electrical contact" or "in physical contact" with the other element; or "indirect contact" or "in direct contact" with the other element.

[0074] As used herein, taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" includes the value and indicates an acceptable deviation from the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the value.

[0075] In addition, unless explicitly stated otherwise, the word “including” and variations such as “containing,” “comprising,” “having,” or “comprising” will be understood to implicitly include the said element, but not exclude any other element.

[0076] Additionally, in this specification, the phrase "in a plan view" refers to the view of the target portion from above, and the phrase "in a schematic cross-sectional view" refers to the view of the target portion as a schematic cross-section taken by vertically cutting it from the side.

[0077] Furthermore, in this specification, "connection" means that two or more components are not only directly connected, but also indirectly connected, physically connected, and electrically connected through other components, or may be referred to by different names depending on their location or function, but may include connecting each substantially integral part to each other.

[0078] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Furthermore, it will be further understood that, unless expressly defined herein, terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and not as having an idealized or overly formal meaning.

[0079] The light-emitting display device and its manufacturing method will be described in detail below with reference to the accompanying drawings.

[0080] Figure 1 A schematic top plan view of a light-emitting display device according to an embodiment is shown, and Figure 2 A top plan view of a portion of a light-emitting display device according to an embodiment, including a sensor, is shown.

[0081] Reference Figure 1The light-emitting display device according to the embodiment may include a substrate 100 and a pad portion 30.

[0082] The substrate 100 may include a display area DA and a non-display area NA. The display area DA may be an area in which pixels including light-emitting diodes and transistors can be formed or set to display an image, and the non-display area NA may be an area in which no image is displayed, and the non-display area NA may surround the display area DA or may be adjacent to the display area DA, and the non-display area NA may include a pad portion 30 on which pads PAD for applying drive signals to pixels can be formed.

[0083] Pixels (not shown) including transistors and light-emitting diodes can be formed or set in the display area DA.

[0084] In the non-display area NA, the drive voltage line (not shown), the drive low voltage line (not shown), and the pad portion 30 can be configured to transmit drive signals such as voltage and signals to the pixels formed or disposed in the display area DA.

[0085] The display area DA can be formed or set to include Figure 2 The sensing areas TA of the sensing electrodes 520 and 540 are used to recognize touch, and sensing wiring for applying signals to the sensing electrodes can be additionally formed or provided in the non-display area NA. Figure 2 (Refer to 512 and 522). Figure 2 The description includes sensing wires 512 and 522 and sensing electrodes 520 and 540 that can be electrically connected to sensing wires 512 and 522.

[0086] The pad portion 30 can be positioned or disposed within a portion of the non-display area NA, and may include a pad PAD. The pad PAD can apply signals to voltage lines (not shown) and sensing wiring electrically connected to the display area DA. Figure 2 (Referring to 512 and 522 in the diagram). A flexible printed circuit board (not shown) can be attached to the non-display area NA. The flexible printed circuit board (FPCB) can be electrically connected to the pad portion 30 to transmit drive signals for driving pixels, etc., from the outside to the pad portion 30. The flexible printed circuit board (FPCB) and the pad portion 30 can be electrically connected by an anisotropic conductive film. As an example, a driver integrated circuit (not shown) may be additionally included, and the drive signals output from the driver integrated circuit can be supplied to each pixel through the pads PAD of the pad portion 30.

[0087] Reference Figure 2The substrate 100 may include a sensing region TA and a peripheral region PA surrounding or adjacent to the sensing region TA. Sensing electrodes 520 and 540 may be formed or disposed above the display region DA in the sensing region TA. According to an embodiment, the sensing region TA may include... Figure 1 The display area DA may include a portion of the non-display area NA, and the surrounding area PA may be from... Figure 1 The non-display area NA excludes the sensing area TA from the non-display area NA.

[0088] The sensing region TA may include sensing electrodes 520 and 540. Sensing electrodes 520 and 540 may include a first sensing electrode 520 and a second sensing electrode 540.

[0089] The first sensing electrode 520 and the second sensing electrode 540 can be electrically isolated from each other. According to an embodiment, the first sensing electrode 520 can be a sensing input (Tx) electrode, and the second sensing electrode 540 can be a sensing output (Rx) electrode.

[0090] The first sensing electrode 520 and the second sensing electrode 540 can be alternately distributed so that they do not overlap in the sensing area TA, and the first sensing electrode 520 and the second sensing electrode 540 can be arranged in a grid pattern. The first sensing electrode 520 can be arranged in the column direction and the second sensing electrode 540 can also be arranged in the column direction and the second sensing electrode 540 can also be arranged in the row direction.

[0091] The first sensing electrode 520 and the second sensing electrode 540 may be disposed on the same layer, but this is merely exemplary, and in embodiments, the first sensing electrode 520 and the second sensing electrode 540 may be disposed on different layers. The first sensing electrode 520 and the second sensing electrode 540 may have a generally rhomboid shape, but are not limited thereto, and may have a generally polygonal shape such as a quadrilateral or hexagon, or a generally circular or generally elliptical shape, and may be implemented in various shapes such as having protrusions to improve the sensitivity of the sensor. The first sensing electrode 520 and the second sensing electrode 540 may be formed of a transparent conductor or an opaque conductor, and each of the first sensing electrode 520 and the second sensing electrode 540 may have an opening. The openings formed in the sensing electrodes 520 and 540 can be used to allow light emitted from the light-emitting diode to be emitted onto the front side without interference.

[0092] The first sensing electrode 520 can be electrically connected to each other by a first sensing electrode connector 521 (also referred to as a bridge), and the second sensing electrode 540 can be electrically connected to each other by a second sensing electrode connector 541. When the first sensing electrodes 520 can be electrically connected to each other in a first direction, the second sensing electrodes 540 can be electrically connected to each other in a second direction intersecting the first direction. When the first sensing electrodes 520 and the second sensing electrodes 540 can be disposed on the same layer, one of the first sensing electrode connector 521 and the second sensing electrode connector 541 can be disposed on the same layer as the first sensing electrodes 520 and the second sensing electrodes 540, and the other can be disposed on a different layer than the first sensing electrodes 520 and the second sensing electrodes 540. Therefore, the first sensing electrodes 520 and the second sensing electrodes 540 can be electrically isolated. Sensing electrode connectors disposed on different layers can be disposed on the upper or lower layer of the first sensing electrodes 520 and the second sensing electrodes 540, and in the following embodiments, embodiments in which the sensing electrode connectors can be disposed on the lower layer (e.g., a layer closer to the substrate) will be described with attention to those embodiments.

[0093] Sensing wires 512 and 522 can be electrically connected to the first sensing electrode 520 and the second sensing electrode 540, respectively, in the peripheral region PA. The first sensing wire 512 can be electrically connected to the second sensing electrode 540 disposed in the row direction, and the second sensing wire 522 can be electrically connected to the first sensing electrode 520 disposed in the column direction. According to an embodiment, the first sensing wire 512 and the second sensing wire 522 can be electrically connected to [the portion of the peripheral region PA] included in the [the peripheral region PA]. Figure 1 A certain number or a predetermined number of pads in the pad section 30.

[0094] exist Figure 2 The diagram illustrates a mutual capacitive sensor that can use two sensing electrodes 520 and 540 to sense touch. However, according to an embodiment, it can be configured as a self-capacitive sensor that can sense touch using only one sensing electrode.

[0095] In the following text, reference will be made to Figure 3 and Figure 4 The structure of a light-emitting display device, including a sensing area TA, is described by a schematic cross-sectional view of the structure of the light-emitting display device in the display area DA.

[0096] Figure 3 A schematic cross-sectional view of a portion of the display area in a light-emitting display device according to an embodiment is shown, and Figure 4 It shows Figure 3 A magnified scanning electron microscope image of region A in the image.

[0097] Reference Figure 3In a light-emitting display device according to an embodiment, the display area DA may include: a substrate 100; a transistor (TFT) including a semiconductor layer 131, a gate electrode 124, a source electrode 173, and a drain electrode 175; a gate insulating layer 120; an interlayer insulating layer 160; a lower planarization layer 180; a pixel electrode 191; an emitter layer 350; a separator 370; a common electrode 270; and an encapsulation layer 400. In this document, the pixel electrode 191, the emitter layer 350, and the common electrode 270 may constitute a light-emitting diode (LED). The light-emitting display device may include a sensing area TA positioned or disposed above the display area DA, and the sensing area TA may include a sensing insulating layer 510, sensing electrodes 520 and 540, a sensing electrode connector 541, and an inorganic passivation layer 505. A light-shielding member 220, color filter layers 230R, 230G, and 230B, and an upper planarization layer 550 may be included above the sensing area TA.

[0098] The substrate 100 may include materials such as glass that can have rigid properties so as not to bend, or may include flexible materials such as plastics or polyimide that can be bent. Although in Figure 3 Although not shown in the figure, a buffer layer (not shown) or a barrier layer (not shown) may be provided on the substrate 100 to flatten the surface of the substrate 100 and block the penetration of impurities.

[0099] A semiconductor layer 131 may be disposed on the substrate 100. The semiconductor layer 131 may be formed of oxide semiconductor, amorphous silicon, polycrystalline silicon or other suitable materials, and may include a channel region, a source region and a drain region divided according to whether they can be doped with impurities, and the source region and drain region may have conductivity characteristics corresponding to conductors.

[0100] The gate insulating layer 120 may be disposed on the substrate 100 to cover or overlap the semiconductor layer 131 and the substrate 100. Within the spirit and scope of this disclosure, the gate insulating layer 120 may include an inorganic insulating layer comprising silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON) x ).

[0101] Gate electrode 124 may be disposed on gate insulating layer 120. Gate electrode 124 may comprise a metal or metal alloy thereof, such as copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), or tantalum (Ta), and gate electrode 124 may be formed as a single layer or multiple layers. The region of semiconductor layer 131 that may overlap with planar gate electrode 124 may be a channel region.

[0102] Interlayer insulating layer 160 may be disposed on substrate 100 to cover or overlap gate electrode 124 and gate insulating layer 120. Within the spirit and scope of this disclosure, interlayer insulating layer 160 may include an inorganic insulating layer comprising silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON) x ).

[0103] Source electrode 173 and drain electrode 175 can be disposed on interlayer insulating layer 160. Source electrode 173 and drain electrode 175 can be electrically connected to the source region and drain region of semiconductor layer 131, respectively, through openings formed in interlayer insulating layer 160 and gate insulating layer 120. Therefore, the semiconductor layer 131, gate electrode 124, source electrode 173, and drain electrode 175 described above can constitute a thin-film transistor (TFT). According to an embodiment, the transistor TFT may include only the source region and drain region of semiconductor layer 131 to replace source electrode 173 and drain electrode 175.

[0104] The source electrode 173 and drain electrode 175 may comprise metals or metal alloys thereof, such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta), and the source electrode 173 and drain electrode 175 may be formed of a single layer or multiple layers. According to an embodiment, the source electrode 173 and drain electrode 175 may comprise three layers: an upper layer, an intermediate layer, and a lower layer. The upper and lower layers may comprise titanium (Ti), and the intermediate layer may comprise aluminum (Al).

[0105] The lower planarization layer 180 may be disposed on the source electrode 173 and the drain electrode 175. The lower planarization layer 180 may be disposed on the substrate 100 to cover the source electrode 173, the drain electrode 175, and the interlayer insulating layer 160, or overlap with the source electrode 173, the drain electrode 175, and the interlayer insulating layer 160. In order to planarize the surface of the substrate 100 on which the transistor (TFT) is provided, the lower planarization layer 180 may be an organic insulating layer and may include at least one material selected from polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0106] Pixel electrode 191 can be disposed on the lower planarization layer 180. Pixel electrode 191 can also be referred to as an anode, and can be formed as a single layer comprising a transparent conductive oxide film and a metal material, or as multiple layers comprising a transparent conductive oxide film and a metal material. The transparent conductive oxide film may include indium tin oxide (ITO), polyITO, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), and the metal material may include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al).

[0107] The lower planarization layer 180 may include a via 81 (also referred to as an opening) exposing the drain electrode 175, and the drain electrode 175 and the pixel electrode 191 may be physically and electrically connected through the via 81 of the lower planarization layer 180. Therefore, the pixel electrode 191 may receive the output current that will be transmitted from the drain electrode 175 to the emitter layer 350.

[0108] A partition wall 370 may be disposed on the lower planarization layer 180. The partition wall 370 may also be referred to as a pixel defining layer (PDL) and may include a pixel opening 351 therein that can expose a portion of the upper surface of the pixel electrode 191. The pixel opening 351 of the partition wall 370 may separate the formation location of the emission layer 350 to provide the emission layer 350 on the portion exposed from the upper surface of the pixel electrode 191. The partition wall 370 may be formed as an organic insulator comprising at least one material selected from polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin. As an example, according to an embodiment, the partition wall 370 may be formed of a black pixel defining layer (PDL) having a black color.

[0109] An emitting layer 350 can be disposed within pixel openings 351 separated by partition walls 370. The emitting layer 350 may include organic materials that emit red, green, and blue light. The emitting layer 350 emitting red, green, and blue light may include low-molecular-weight or high-molecular-weight organic materials. Figure 3 In this paper, the emitter layer 350 is shown as a single layer, but in reality, auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer can be included above and below the emitter layer 350. The hole injection layer and the hole transport layer can be disposed below the emitter layer 350, and the electron transport layer and the electron injection layer can be disposed above the emitter layer 350.

[0110] A common electrode 270 can be disposed on the separator wall 370 and the emitting layer 350. The common electrode 270 can be referred to as a cathode and can be formed of a transparent conductive layer including, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). The common electrode 270 can have semi-transparent properties, and in this case, it can form a microcavity together with the pixel electrode 191. According to such a microcavity structure, light of a specific wavelength can be emitted to the upper part via the characteristics and spacing between the two electrodes, and therefore, red, green, or blue can be displayed.

[0111] An encapsulation layer 400 may be disposed on the common electrode 270. The encapsulation layer 400 may include at least one inorganic layer and at least one organic layer, and in embodiments, the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430. The first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430 may be positioned or disposed within a portion of the display area DA and a portion of the non-display area NA, and according to embodiments, the organic encapsulation layer 420 may be formed or disposed around the display area DA, and the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may be formed or disposed up to the non-display area NA. The encapsulation layer 400, used to protect the light-emitting diode from moisture or oxygen that may be introduced from the outside, may be formed or disposed in direct contact with a first end of the first inorganic encapsulation layer 410 and a first end of the second inorganic encapsulation layer 430. According to embodiments, the encapsulation layer 400 may include a structure in which inorganic and organic layers may be sequentially stacked.

[0112] A sensing insulating layer 510, sensing electrodes 520 and 540, a sensing electrode connector 541, and an inorganic passivation layer 505 may be disposed on the encapsulation layer 400.

[0113] In this embodiment, the sensing insulating layer 510, the sensing electrode connector 541, and the sensing electrodes 520 and 540 can constitute a sensor, which can be classified as resistive, capacitive, electromagnetic, or optical. The sensor according to this embodiment uses a capacitive sensor. A buffer layer comprising inorganic material can be provided between the sensing electrode connector 541, the sensing insulating layer 510, and the encapsulation layer 400 (see...). Figure 12 (501).

[0114] A sensing electrode connector 541 may be disposed on the encapsulation layer 400, and a sensing insulating layer 510 may be disposed on the sensing electrode connector 541, covering or overlapping the sensing electrode connector 541. The sensing insulating layer 510 may be an inorganic insulating layer, and according to an embodiment, the sensing insulating layer 510 may include an inorganic material. The inorganic material included in the inorganic insulating layer may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. In an embodiment, the sensing insulating layer 510 may include an organic material, which may be at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, and perylene resin.

[0115] Sensing electrodes 520 and 540 may be disposed on the sensing insulating layer 510, and the first sensing electrode 520 and the second sensing electrode 540 may be electrically insulated. The sensing insulating layer 510 may include an opening exposing the upper surface of the sensing electrode connector 541, and the sensing electrode connector 541 may be electrically connected to the second sensing electrode 540 through the opening in the sensing insulating layer 510 to electrically connect two adjacent second sensing electrodes 540. Meanwhile, the first sensing electrode connector 521, which is electrically connected to the first sensing electrode 520, may be formed or disposed on the same layer as the first sensing electrode 520 and the second sensing electrode 540.

[0116] Sensing electrodes 520 and 540 may comprise a conductive material with good conductivity. Sensing electrodes 520 and 540 may comprise a metal or an alloy thereof, such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta), and may be formed of a single layer or multiple layers. In this case, sensing electrodes 520 and 540 may include openings that allow light emitted from the light-emitting diode to be emitted upwards without interference. According to an embodiment, sensing electrodes 520 and 540 may be a three-layer structure comprising an upper layer, a middle layer, and a lower layer, wherein the upper and lower layers may comprise titanium (Ti), and the middle layer may comprise aluminum (Al).

[0117] An inorganic passivation layer 505 may be disposed on the sensing electrodes 520 and 540, covering the sensing electrodes 520 and 540 and the sensing insulating layer 510, or overlapping the sensing electrodes 520 and 540 and the sensing insulating layer 510. The inorganic passivation layer 505 may also be disposed on the pad electrodes to prevent damage to the pad electrodes applied during the process of forming the pad electrodes in subsequent processes (e.g., color filter forming processes). The following will... Figure 5The inorganic passivation layer 505 and the pad electrodes are described in detail.

[0118] Reference Figure 4 The schematic cross-sectional structure of the first sensing electrode 520 in sensing electrodes 520 and 540 is shown in detail.

[0119] According to an embodiment, the first sensing electrode 520 disposed on the sensing insulating layer 510 may include an upper layer 520a, an intermediate layer 520b, and a lower layer 520c. According to an embodiment, the upper layer 520a and the lower layer 520c of the first sensing electrode 520 may be titanium (Ti), and the intermediate layer 520b may be aluminum (Al). The thickness d2 of the upper layer 520a may be approximately 48.19 nm, the thickness d3 of the intermediate layer 520b may be approximately 302.9 nm, and the thickness d4 of the lower layer 520c may be approximately 48.19 nm.

[0120] An inorganic passivation layer 505 may be disposed on the sensing insulating layer 510 and the first sensing electrode 520, and the thickness d1 of the inorganic passivation layer 505 may be approximately 82.62 nm. The inorganic passivation layer 505 may remain in the display area DA and / or the sensing area TA without being etched, but this is only exemplary, and in embodiments, the inorganic passivation layer 505 may be removed in the non-display area NA and / or the peripheral area PA by a dry etching process, which will be described later.

[0121] A light-shielding member 220 and color filter layers 230R, 230G and 230B can be provided on the inorganic passivation layer 505.

[0122] The light-shielding member 220 can be configured to overlap with the sensing electrodes 520 and 540 in a planar view, but can also be configured not to overlap with the emitting layer 350 in a planar view. This is to prevent the emitting layer 350, which is capable of displaying images, from being blocked by the light-shielding member 220 and the sensing electrodes 520 and 540.

[0123] Color filter layers 230R, 230G, and 230B can be positioned or disposed on the inorganic passivation layer 505 and the light-shielding member 220. Color filter layers 230R, 230G, and 230B include a red color filter layer 230R for transmitting red light, a green color filter layer 230G for transmitting green light, and a blue color filter layer 230B for transmitting blue light. Each of the color filter layers 230R, 230G, and 230B can be configured to overlap with the emitting layer 350 of the light-emitting diode in a planar view. The emitting layer 350 overlapping with the red color filter layer 230R can emit red light, the emitting layer 350 overlapping with the green color filter layer 230G can emit green light, and the emitting layer 350 overlapping with the blue color filter layer 230B can emit blue light. The light-shielding member 220 can be disposed between the respective color filter layers 230R, 230G, and 230B. According to an embodiment, color filter layers 230R, 230G, and 230B may be replaced with color conversion layers, or may include color conversion layers. The color conversion layers may include quantum dots.

[0124] An upper planarization layer 550 may be provided on or covering the color filter layers 230R, 230G, and 230B, or overlapping the color filter layers 230R, 230G, and 230B. The upper planarization layer 550, which can be used to planarize the upper surface of the light-emitting display device, may be an organic insulating layer comprising at least one material selected from polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0125] In the following text, reference will be made to Figures 5 to 7 The pad portion 30 of the light-emitting display device is described based on a schematic cross-sectional view of the pad portion 30 of the light-emitting display device in the non-display area NA.

[0126] Figure 5 A portion of the pad portion in the light-emitting display device according to an embodiment is shown. Figure 6 It shows along Figure 5 A schematic cross-sectional view taken from line VI-VI', and Figure 7 It shows Figure 6 Detailed view of region B in the image.

[0127] Figure 5 The pad portion 30 shown can correspond to Figure 1 The pad portion 30, and Figure 6 and Figure 7 The stacking order of the light-emitting display devices shown can correspond to Figure 3 The stacking order of the light-emitting display devices.

[0128] Reference Figures 5 to 7 The pads (PADs) may include lower pad electrodes 170 and 171 and upper pad electrodes 530 and 531.

[0129] The lower pad electrodes 170 and 171 can be disposed on the interlayer insulating layer 160. The lower pad electrodes 170 and 171 include a first lower pad electrode 170 and a second lower pad electrode 171 spaced apart from each other. The lower pad electrodes 170 and 171 can be disposed on the interlayer insulating layer 160. Figure 3 The source electrode 173 and drain electrode 175 are located in the same layer, and can be used by using the same Figure 3 The source electrode 173 and drain electrode 175 are formed of the same or similar materials and using the same process. The lower pad electrodes 170 and 171 may comprise metals or metal alloys thereof, such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta), and the lower pad electrodes 170 and 171 may be formed of a single layer or multiple layers.

[0130] In one embodiment, the lower pad electrodes 170 and 171 can be formed as three layers. In another embodiment, the first ends of the lower pad electrodes 170 and 171 can have an inclined shape (conical shape).

[0131] Figure 7 The diagram shows lower pad electrodes 170 and 171 formed as a three-layer structure comprising an upper layer 170a, a middle layer 170b, and a lower layer 170c. The upper layer 170a and the lower layer 170c of the lower pad electrodes 170 and 171 may comprise titanium (Ti), and the middle layer 170b may comprise aluminum (Al).

[0132] A lower planarization layer 180 may be disposed on the lower pad electrodes 170 and 171 to cover the lower pad electrodes 170 and 171 and the substrate 100, or to overlap with the lower pad electrodes 170 and 171 and the substrate 100. The lower planarization layer 180 may be disposed between the first lower pad electrodes 170 and the second lower pad electrodes 171, which are spaced apart from each other, to include an opening 51. Figure 6 This exposes at least a portion of the upper surface of the lower pad electrode 170 and at least a portion of the upper surface of the lower pad electrode 171. The lower planarization layer 180 may be an organic insulating layer and may include at least one material selected from polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin. According to an embodiment, another organic or inorganic insulating layer disposed above the source electrode 173 and drain electrode 175 may be used instead of the lower planarization layer 180. As an example, a sensing insulating layer 510 may be used.

[0133] Upper pad electrodes 530 and 531 can be disposed on the lower pad electrodes 170 and 171. The upper pad electrodes 530 and 531 can be formed or disposed in the opening 51 of the lower planarization layer 180. Figure 6 The upper pad electrodes 530 and 531 may include a first upper pad electrode 530 and a second upper pad electrode 531 spaced apart from each other.

[0134] The upper pad electrodes 530 and 531 can be set in relation to... Figure 3 The sensing electrodes 520 and 540 are located in the same layer, and can be used by using the same Figure 3 The sensing electrodes 520 and 540 are formed of the same or similar materials and using the same process. The upper pad electrodes 530 and 531 may comprise metals or metal alloys thereof, such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta), and may be formed in single or multiple layers.

[0135] The lower planarization layer 180 may include an opening 51 thereon that exposes the upper surfaces of the lower pad electrodes 170 and 171, and the upper pad electrodes 530 and 531 and the lower pad electrodes 170 and 171 may be physically and electrically connected to each other through the opening 51 of the lower planarization layer 180. Except for the portions where the upper pad electrodes 530 and 531 contact the lower pad electrodes 170 and 171, the upper surface of the lower planarization layer 180 may be exposed to the outside.

[0136] exist Figure 7 In one embodiment, upper pad electrodes 530 and 531 are shown formed as three layers including an upper layer 530a, an intermediate layer 530b, and a lower layer 530c. The upper layer 530a and the lower layer 530c of the upper pad electrodes 530 and 531 may include titanium (Ti), and the intermediate layer 530b may include aluminum (Al).

[0137] Figure 7 It shows Figure 6 Region B, and therefore, Figure 7 The lower planarization layer 180 shown corresponds to the portion of the lower planarization layer 180 disposed between the pad electrodes. The lower planarization layer 180 may include an exposed portion 185 that exposes the upper surface of the lower planarization layer 180 and an overlapping portion 186 that partially overlaps with the upper pad electrodes 530 and 531.

[0138] In description Figure 7In the case of part X, on the upper surface of the lower planarization layer 180, the upper surface of the overlapping portion 186, which is covered by or overlaps with the upper pad electrodes 530 and 531, and the upper surface of the exposed portion 185 may have different heights. For example, the height h1 of the upper surface of the exposed portion 185 of the lower planarization layer 180 may be lower than the height h2 of the upper surface of the overlapping portion 186. The exposed portion 185 of the lower planarization layer 180 may be electrically connected to the pads of a flexible printed circuit board (FPCB).

[0139] The structure of the lower planarization layer 180 can be formed by the deposition process of the inorganic passivation layer 505 and the subsequent etching process to reduce damage to the upper pad electrodes 530 and 531.

[0140] Therefore, the light-emitting display device according to the embodiment can reduce damage to the upper pad electrodes 530 and 531 that may occur in subsequent processes such as color filter forming processes by forming upper pad electrodes 530 and 531 and depositing an inorganic passivation layer 505 on the upper pad electrodes 530 and 531.

[0141] In the following text, reference will be made to Figures 8 to 11 Detailed description of the methods used to reduce Figure 7 The manufacturing method addresses the potential issues of varying heights in the lower planarization layer 180 and the possible damage to the upper pad electrodes 530 and 531.

[0142] Figures 8 to 11 The method for manufacturing pads in a method for manufacturing a light-emitting display device according to an embodiment is illustrated schematically.

[0143] Figures 8 to 11 It can correspond to the reference. Figure 7 The non-display area of ​​the described light-emitting display device.

[0144] Reference Figure 8 A light-emitting display device is provided, in which a gate insulating layer 120 and an interlayer insulating layer 160 can be sequentially stacked on a substrate 100 in a non-display area NA.

[0145] Return to reference Figure 3 The gate insulating layer 120 and the interlayer insulating layer 160 can be sequentially disposed on the substrate 100 in the display area DA.

[0146] The lower pad electrodes 170 and 171 of the non-display area NA can be formed on the same layer as the source electrode 173 and drain electrode 175 of the display area DA, using the same or similar materials and methods as the source electrode 173 and drain electrode 175 of the display area DA. For example, if the source electrode 173 and drain electrode 175 can be disposed on the interlayer insulating layer 160 in the display area DA, the lower pad electrodes 170 and 171 can be disposed on the interlayer insulating layer 160 in the non-display area NA. In this embodiment, the source electrode 173, drain electrode 175, and lower pad electrodes 170 and 171 can have the same three-layer structure.

[0147] In the following description, a lower planarization layer 180 may be formed on the source electrode 173, drain electrode 175, and lower pad electrodes 170 and 171, covering or overlapping the source electrode 173, drain electrode 175, and lower pad electrodes 170 and 171. An etching process may be performed on the formed lower planarization layer 180 to form openings. The openings formed in the lower planarization layer 180 may include openings 51 that expose at least a portion of the lower pad electrodes 170 and 171.

[0148] In the following description, the process of forming upper pad electrodes 530 and 531 can be performed on the pad portion 30 of the non-display area NA. The upper pad electrodes 530 and 531 of the non-display area NA can be formed at the same layer as the sensing electrodes 520 and 540 of the display area DA using the same or similar materials and processes as the sensing electrodes 520 and 540 of the display area DA. For example, if the sensing electrodes 520 and 540 can be formed or disposed in the display area DA, the upper pad electrodes 530 and 531 can be disposed on the lower planarization layer 180 in the pad portion 30 of the non-display area NA. A process of forming layers in the display area DA can be included between the process of forming the lower planarization layer 180 and the process of forming the sensing electrodes 520 and 540, and such a process may not be performed in the pad portion 30 of the non-display area NA, or the corresponding layers may be removed by etching after formation.

[0149] In the non-display area NA, the lower planarization layer 180 disposed between the upper pad electrodes 530 and 531 and the lower pad electrodes 170 and 171 can be formed using the same or similar material and the same process as the lower planarization layer 180 of the display area DA. The lower planarization layer 180 can be formed or disposed above the display area DA and the non-display area NA.

[0150] like Figure 8 As shown, the lower planarization layer 180 disposed between the lower pad electrodes 170 and 171 can have a constant height of its upper surface until the process of forming the upper pad electrodes 530 and 531. For example, the height h4 of the upper surface of the overlapping portion 186 of the lower planarization layer 180 that overlaps with the upper pad electrodes 530 and 531 and the height h3 of the upper surface of the exposed portion 185 of the lower planarization layer 180 can be the same. However, according to an embodiment, if the upper pad electrodes 530 and 531 can be etched, the exposed portion 185 of the lower planarization layer 180 can be partially etched to have a low height.

[0151] Reference Figure 9 An inorganic passivation layer 505 may be disposed on the upper pad electrodes 530 and 531 and the lower planarization layer 180 to cover or overlap with the upper pad electrodes 530 and 531 and the lower planarization layer 180. The inorganic passivation layer 505 may also cover or overlap with the sensing electrodes 520 and 540 of the display area DA, so as to be disposed above the display area DA and the non-display area NA.

[0152] Return to reference Figure 3 In the display area DA, after forming the inorganic passivation layer 505, a process can be performed to form a light-shielding member 220 and color filter layers 230R, 230G, and 230B on the inorganic passivation layer 505. Subsequently, a process can be performed to form an upper planarization layer 550 on the color filter layers 230R, 230G, and 230B. However, since the light-shielding member 220, color filter layers 230R, 230G, and 230B, and upper planarization layer 550 may not be formed or disposed in the pad portion 30 of the non-display area NA, the inorganic passivation layer 505 may remain in areas such as... Figure 9 At the top position shown. In the process of forming and removing the light-shielding member 220, color filter layers 230R, 230G and 230B and the upper planarization layer 550, the inorganic passivation layer 505 protects the upper pad electrodes 530 and 531.

[0153] The upper pad electrodes 530 and 531 may need to be electrically connected to the pads of the flexible printed circuit board (FPCB), and therefore the upper pad electrodes 530 and 531 should be exposed to the outside. Therefore, it may be necessary to further perform a process to remove the inorganic passivation layer 505.

[0154] Reference Figure 10An etching process is performed to expose the upper pad electrodes 530 and 531. In this paper, a dry etching process is used. The dry etching process can be performed in a vacuum chamber, and the inorganic passivation layer 505 can be removed using an etching gas such as argon (Ar), chlorine (Cl2), or oxygen (O2).

[0155] The inorganic passivation layer 505 in the non-display area NA can be removed by a dry etching process. On the other hand, in the display area DA, the layer located below the upper planarization layer 550 is not etched because the lower layer is protected by the upper planarization layer 550, which includes an organic insulating material. Therefore, as... Figure 3 and Figure 4 As shown, the inorganic passivation layer 505 can be retained on the sensing electrodes 520 and 540 in the display area DA.

[0156] Reference Figure 11 The inorganic passivation layer 505 is removed from the upper pad electrodes 530 and 531 using a dry etching process, exposing the upper surface of the lower planarization layer 180 disposed between the lower pad electrodes 170 and 171. Pads of the flexible printed circuit board (FPCB) can be attached to the exposed upper pad electrodes 530 and 531 to apply voltage from the outside.

[0157] The upper surface of the exposed portion 185 of the lower planarization layer 180 can be made to have a different height than the upper surface of the overlapping portion 186 that is covered or overlaps with the upper pad electrodes 530 and 531 by a dry etching process. For example, the height h1 of the exposed portion 185 of the lower planarization layer 180 can be lower than the height h2 of the overlapping portion 186. The structure of the lower planarization layer 180 can be formed in the process of removing the inorganic passivation layer 505, which can be added to reduce damage to the upper pad electrodes 530 and 531. According to an embodiment, when etching is performed to complete the upper pad electrodes 530 and 531, the exposed portion 185 of the lower planarization layer 180 is etched first and then etched a second time in the process of removing the inorganic passivation layer 505, resulting in a low height.

[0158] Therefore, the light-emitting display device according to the embodiment can reduce the damage to the upper pad electrodes 530 and 531 that may occur during the color filter forming process by forming upper pad electrodes 530 and 531 and depositing an inorganic passivation layer 505 on the upper pad electrodes 530 and 531.

[0159] Already described Figure 3In one embodiment, there is no buffer layer between the sensor and the encapsulation layer 400, that is, there is no buffer layer between the sensing electrode connector 541, the sensing insulation layer 510 and the encapsulation layer 400.

[0160] However, according to an embodiment, a buffer layer 501 may be included between the sensor and the encapsulation layer 400, and reference will be made to... Figure 12 The description includes an embodiment including buffer layer 501.

[0161] Figure 12 A schematic cross-sectional view of a portion of the display area in a light-emitting display device according to an embodiment is shown.

[0162] Figure 12 Can be with Figure 3 They are largely the same, but the difference is that the buffer layer 501 can be placed on the encapsulation layer 400.

[0163] The buffer layer 501 may be formed of an inorganic insulating layer, and the inorganic material included in the inorganic insulating layer may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride.

[0164] A sensing insulating layer 510, a sensing electrode connector 541, and sensing electrodes 520 and 540 can be disposed on the buffer layer 501.

[0165] Even in Figure 12 In the embodiments, the source electrode 173 and the drain electrode 175 may be three layers comprising an upper layer, an intermediate layer, and a lower layer. The upper and lower layers may comprise titanium (Ti), and the intermediate layer may comprise aluminum (Al). The sensing electrodes 520 and 540 may also be three layers comprising an upper layer, an intermediate layer, and a lower layer. The upper and lower layers may comprise titanium (Ti), and the intermediate layer may comprise aluminum (Al).

[0166] like Figure 12 As shown, the layer structure of the pad portion 30 can be changed due to the formation or provision of the buffer layer 501 in the display area DA, which will refer to Figure 13 Describe it.

[0167] Figure 13 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown.

[0168] Figure 13 Structure and Figure 7 The difference in structure may be that it may include a buffer layer 501. According to Figure 13The exposed portion of the buffer layer 501 may have a thickness h5 that is thinner than the portion covered by or overlapping with the upper pad electrodes 530 and 531.

[0169] The thickness difference of the buffer layer 501 may be caused by the partial etching of the exposed upper surface of the buffer layer 501 during the process of removing the inorganic passivation layer 505 that is formed to protect the upper pad electrodes 530 and 531.

[0170] although Figure 13 The diagram shows that a buffer layer 501 can be disposed between the lower pad electrode 170 and the upper pad electrode 530 to prevent them from being electrically connected, but an opening can be formed in the buffer layer 501 to allow for... Figure 13 The lower pad electrode 170 and the upper pad electrode 530 are electrically connected in the portion not shown. This is because it may be necessary for the lower pad electrode 170 and the upper pad electrode 530 to be electrically connected to each other to form pads.

[0171] According to an embodiment, the height of the upper surface of the lower planarization layer 180 can be constant. For example, the height h4 of the upper surface of the overlapping portion 186 of the lower planarization layer 180 that overlaps with the upper pad electrodes 530 and 531 and the height h3 of the upper surface of the potentially exposed portion 185 of the lower planarization layer 180 can be the same.

[0172] In the following text, reference will be made to Figures 14A to 15B Comparison and description based on Figure 13 Example and comparison examples of pad structures.

[0173] Figure 14A and Figure 14B A scanning electron microscope image of a removable portion of a pad in an example light-emitting display device is shown, and Figure 15A and Figure 15B A scanning electron microscope image of a portion of a pad in a light-emitting display device according to a comparative example, which can be removed, is shown.

[0174] exist Figures 14A to 15B In the image, a bright layer is shown on top of the upper pad electrode 530. This bright layer can be additionally coated to achieve the desired effect. Figures 14A to 15B The image shown is a coating, and in fact, the upper pad electrode 530 has a structure that can be exposed to be electrically connected to another pad.

[0175] for Figures 14A to 15B Partially showing according to Figure 13The example and comparative example of the light-emitting display device include an interlayer insulating layer 160, a lower pad electrode 170, a lower planarization layer 180, a buffer layer 501, and an upper pad electrode 530 disposed in the non-display area.

[0176] The lower planarization layer 180 is positioned between the adjacent lower pad electrode 170 and the adjacent upper pad electrode 530, and the lower pad electrode 170 and the upper pad electrode 530 can each be formed as three layers.

[0177] The upper pad electrode 530 and the lower pad electrode 170 can be three layers, which are formed as a titanium (Ti) layer, an aluminum (Al) layer and a titanium (Ti) layer, that is, an upper titanium (Ti) layer and a lower titanium (Ti) layer that can be thinly colored in a light color, and a thick aluminum (Al) layer that is marked in a dark color between the upper titanium (Ti) layer and the lower titanium (Ti) layer.

[0178] Interlayer insulating layer 160 may be disposed at the lower part of lower pad electrode 170, and buffer layer 501 may be disposed in a portion of the area between lower pad electrode 170 and upper pad electrode 530.

[0179] The interlayer insulating layer 160 can be completely formed or disposed in the display area DA and the non-display area NA.

[0180] The buffer layer 501 is shown disposed between the lower pad electrode 170 and the upper pad electrode 530, but this is merely exemplary, and the buffer layer 501 may also be disposed on a portion of the pad, and the lower pad electrode 170 and the upper pad electrode 530 may extend to... Figure 14A and Figure 14B The right side portion of them is in direct contact with each other. For example, it may be necessary for the lower pad electrode 170 and the upper pad electrode 530 to be electrically connected to each other, and therefore, although in Figures 14A to 15B Although not shown in the diagram, an opening is formed in the buffer layer 501 so that the lower pad electrode 170 and the upper pad electrode 530 can be electrically connected to each other.

[0181] Reference Figure 14A and Figure 14B As can be seen, the upper surface of the upper pad electrode 530 is kept as a smooth surface, and therefore it can be seen that there is no damage to the upper pad electrode 530 according to the embodiment. This is because the upper pad electrodes 530 and 531 can be protected by the inorganic passivation layer 505 disposed on the upper pad electrodes 530 and 531 in subsequent processes. Therefore, in the embodiment, the upper pad electrode 530 can be protected even when performing the processes of forming the light-shielding member 220 and the color filter layers 230R, 230G and 230B.

[0182] On the other hand, according to Figure 15A and Figure 15B The comparison example shown in the figure is compared with Figure 14A and Figure 14B The difference is that the inorganic passivation layer 505 disposed on the upper pad electrodes 530 and 531 may not be formed, and therefore the upper pad electrodes 530 and 531 may be exposed during the process of forming the light-shielding member 220 and the color filter layers 230R, 230G and 230B on the upper pad electrodes 530 and 531.

[0183] Therefore, in Figure 15A and Figure 15B In the comparative example shown, the upper pad electrode 530 was damaged during the process of forming the light-shielding member 220 and color filter layers 230R, 230G and 230B on the sensing electrodes 520 and 540 after forming the upper pad electrodes 530 and 531 in the non-display area and the sensing electrodes 520 and 540 in the display area.

[0184] Reference Figure 15A and Figure 15B As can be seen, the upper surface of the upper pad electrode 530 is damaged, resulting in an uneven surface. Damage such as lift or sharpening may occur in the upper layer of the upper pad electrode 530, the metal in the intermediate layer may be corroded, and the contact performance of the pad electrode may be degraded. For example, the upper and lower layers of the upper pad electrode 530 according to the comparative example may include titanium (Ti), the intermediate layer may include aluminum (Al), and the aluminum (Al) may be corroded due to the damage to titanium (Ti).

[0185] On the other hand, refer to Figure 14A and Figure 14B In the light-emitting display device according to the embodiment, the metal layer of the upper pad electrode 530 can be protected by the inorganic passivation layer 505 during the process, thus maintaining the performance of the pad electrode.

[0186] In the following text, the buffer layer 501 can be as follows: Figure 12 In the embodiment shown, which is disposed on the encapsulation layer 400, it will be further described that it can be used with Figure 13 Schematic cross-sectional structures of different pad portions 30.

[0187] Figure 16 and Figure 17 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown.

[0188] First, with Figure 13 Unlike in China, in Figure 16The diagram illustrates a structure in which the lower planarization layer 180 is exposed while etching can expose the buffer layer 501 between the upper pad electrodes 530 and 531. In this case, the upper surface of the lower planarization layer 180 can be etched separately. For example, in the description... Figure 16 In the case of part X, on the upper surface of the lower planarization layer 180, the upper surface of the overlapping portion 186 that is covered or overlaps with the upper pad electrodes 530 and 531 and the upper surface of the exposed portion 185 may have different heights. The height h1 of the upper surface of the exposed portion 185 of the lower planarization layer 180 may be lower than the height h2 of the upper surface of the overlapping portion 186.

[0189] exist Figure 16 In one embodiment, an inorganic passivation layer 505 may be formed or disposed on the upper pad electrodes 530 and 531 to reduce potential damage to the upper pad electrodes 530 and 531 in subsequent processes such as color filter formation.

[0190] Meanwhile, according to the embodiment, the lower planarization layer 180 may not be included between the pad electrodes in the pad portion 30. When the lower planarization layer 180 can be provided between the pad electrodes, it is advantageous to eliminate the problem of electrical short circuits between adjacent pad electrodes; however, there may be a problem that the gap between adjacent pad electrodes may not be reduced to a specific or predetermined level or lower. For example, as resolution increases, it is necessary to reduce the gap between the pad electrodes in the pad portion 30, so that a pad portion 30 excluding the lower planarization layer 180 can also be formed.

[0191] In the following text, reference will be made to Figure 17 Describes a schematic cross-sectional structure of the pad portion, excluding the lower planarization layer 180 between the pad electrodes.

[0192] according to Figure 17 The lower pad electrodes 170 and 171 and the upper pad electrodes 530 and 531, each forming three layers, can be formed or disposed on the interlayer insulating layer 160, and the buffer layer 501 can be formed or disposed between the lower pad electrodes 170 and 171 and the upper pad electrodes 530 and 531.

[0193] A buffer layer 501 may be formed or disposed on the upper surfaces of the lower pad electrodes 170 and 171 and on the tapered side surfaces of the lower pad electrodes 170 and 171, and may also be disposed on the exposed interlayer insulating layer 160. However, the portion located on the exposed interlayer insulating layer 160 may have a thickness h5, which may be thinner than the thickness of other portions. This is because the buffer layer 501 may be partially etched when etching is performed to remove the inorganic passivation layer 505 formed or configured to protect the upper pad electrodes 530 and 531 from damage.

[0194] Therefore, according to Figure 17 The light-emitting display device of the embodiment can reduce damage to the upper pad electrodes 530 and 531 that may occur in subsequent processes such as color filter forming processes by forming upper pad electrodes 530 and 531 and depositing an inorganic passivation layer 505 on the upper pad electrodes 530 and 531.

[0195] although Figure 17 The diagram shows that a buffer layer 501 can be disposed between the lower pad electrode 170 and the upper pad electrode 530 to prevent them from being electrically connected to each other. However, an opening can be formed in the buffer layer 501 to allow for... Figure 17 The lower pad electrode 170 and the upper pad electrode 530 are electrically connected in the portion not shown. This is because it may be necessary for the lower pad electrode 170 and the upper pad electrode 530 to be electrically connected to each other in order to form a pad.

[0196] Meanwhile, according to the embodiments, with Figure 17 Unlike other methods, the buffer layer 501 may not be disposed between the pad electrodes. For example, the buffer layer 501 exposed between the pad electrodes may also be etched during the etching process of the inorganic passivation layer 505. In this case, the exposed portion of the interlayer insulating layer 160 disposed at the lower part of the inorganic passivation layer 505 may be etched separately.

[0197] The following will describe according to Figure 18 A schematic cross-sectional structure of the pad portion in an embodiment.

[0198] Figure 18 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown.

[0199] exist Figure 18 In this embodiment, the lower planarization layer 180 is not included between the pad electrodes, and is related to... Figure 17 The buffer layer 501 may be omitted, depending on the context.

[0200] exist Figure 18 In this embodiment, since the lower planarization layer 180 is not included, the following can be reduced: Figure 17The gap between adjacent pad electrodes. The buffer layer 501 may not be formed or disposed between the lower pad electrodes 170 and 171 and the upper pad electrodes 530 and 531, and therefore, even without forming an opening in the buffer layer 501 by using a mask, the lower pad electrodes 170 and 171 and the upper pad electrodes 530 and 531 can be directly electrically connected.

[0201] exist Figure 18 In one embodiment, damage to the upper pad electrodes 530 and 531 can be reduced by depositing an inorganic passivation layer 505 on the upper pad electrodes 530 and 531 and performing subsequent processes such as a color filter forming process in a state that can protect the upper pad electrodes 530 and 531.

[0202] In the process of removing the inorganic passivation layer 505, the exposed portion of the interlayer insulating layer 160 can be etched separately.

[0203] At the same time, Figure 18 Additional insulating layers may be disposed on the exposed interlayer insulation layer 160, and as an example, such as Figure 19 As shown, a light-shielding component 220 can be provided.

[0204] and Figure 18 The schematic cross-sectional structure of the display area DA corresponding to the embodiment can be compared with... Figure 3 The schematic cross-sectional structure of the display area DA is the same.

[0205] In the following text, reference will be made to Figures 19 to 23 The structure of the pads and the method of manufacturing the pads in the light-emitting display device according to the embodiments are described.

[0206] Figure 19 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown, and Figures 20 to 23 The method for manufacturing pads in a method for manufacturing a light-emitting display device according to an embodiment is illustrated schematically.

[0207] Figures 19 to 23 It can be similar to Figures 7 to 11 Therefore, the following description will focus on the differences. Figures 19 to 23 The structure shown can correspond to the reference. Figure 6 The aforementioned region B.

[0208] Reference Figure 19 A first pad electrode and a second pad electrode that are spaced apart from each other can be disposed on the interlayer insulating layer 160. The first pad electrode may include a first lower pad electrode 170 and a first upper pad electrode 530, and the second pad electrode may include a second lower pad electrode 171 and a second upper pad electrode 531.

[0209] The distance W1 from the first end of the first lower pad electrode 170 to the first end of the second lower pad electrode 171 can be in the range of about 10 μm to about 20 μm. By way of example, the distance W1 from the first end of the first lower pad electrode 170 to the first end of the second lower pad electrode 171 can be about 15 μm.

[0210] The lower pad electrodes 170 and 171 can be formed as three layers. The upper layer 170a and the lower layer 170c of the lower pad electrodes 170 and 171 may include titanium (Ti), and the middle layer 170b may include aluminum (Al).

[0211] Lower planarization layers 180 and 181 may be disposed on lower pad electrodes 170 and 171. Lower planarization layers 180 and 181 may be positioned or configured to at least partially overlap with lower pad electrodes 170 and 171, which may be spaced apart from each other, and have a structure covering or overlapping a first end of the lower pad electrodes 170 and 171. Lower planarization layers 180 and 181 may include a first lower planarization layer 180 and a second lower planarization layer 181, which may be spaced apart from each other. For example, a first lower planarization layer 180 may be disposed between a first lower pad electrode 170 and a first upper pad electrode 530 to partially cover the first lower pad electrode 170 or partially overlap with the first lower pad electrode 170, and a second lower planarization layer 181 may be disposed between a second lower pad electrode 171 and a second upper pad electrode 531 to partially cover the lower pad electrode 171 or partially overlap with the lower pad electrode 171.

[0212] Upper pad electrodes 530 and 531 can be disposed on lower pad electrodes 170 and 171 and lower planarization layers 180 and 181. Upper pad electrodes 530 and 531 include a first upper pad electrode 530 and a second upper pad electrode 531 spaced apart from each other.

[0213] The upper pad electrodes 530 and 531 may be configured to at least partially overlap with the lower pad electrodes 170 and 171 and the lower planarization layers 180 and 181. The upper layer 530a and the lower layer 530c of the upper pad electrodes 530 and 531 may include titanium (Ti), and the intermediate layer 530b may include aluminum (Al).

[0214] Each of the upper pad electrodes 530 and 531 may include a flat portion 535 that can directly contact the lower pad electrodes 170 and 171, and a protrusion 536 that can directly contact the lower planarization layers 180 and 181.

[0215] The distance W2 from the first end of the first upper pad electrode 530 to the first end of the second upper pad electrode 531 can be about 10 μm or less. By way of example, the distance W2 from the first end of the first upper pad electrode 530 to the first end of the second upper pad electrode 531 can be about 5 μm. The larger the distance between adjacent upper pad electrodes 530 and 531, the lower the resolution of the light-emitting display device; conversely, the smaller the distance between adjacent upper pad electrodes 530 and 531, the higher the resolution of the light-emitting display device. The step difference between the pads can be reduced by mismatching the first ends of the upper pad electrodes 530 and 531 with the first ends of the lower pad electrodes 170 and 171.

[0216] The light-shielding member 220 can be disposed between the first upper pad electrode 530 and the second upper pad electrode 531. (Refer to again...) Figure 5 The light-shielding member 220 can be disposed between adjacent pad electrodes.

[0217] The light-shielding member 220 can be configured to cover a portion of the first upper pad electrode 530 and a portion of the second upper pad electrode 531, or overlap with a portion of the first upper pad electrode 530 and a portion of the second upper pad electrode 531, and the light-shielding member 220 can be configured to contact the first ends of the upper pad electrodes 530 and 531. The upper surface of the light-shielding member 220 can be configured to be approximately 0.7 μm higher than the upper surface of the flat portion 535 of the upper pad electrodes 530 and 531. Figure 19 (h6 in the middle).

[0218] Therefore, in the light-emitting display device according to the embodiment, the ends of the upper pad electrodes 530 and 531 can be protected by the light-shielding member 220, and thus the upper pad electrodes 530 and 531 can be formed, thereby reducing the potential damage to the upper pad electrodes 530 and 531 during the color filter formation process. Therefore, in Figure 19 In one embodiment, the inorganic passivation layer 505 may not be deposited on the upper pad electrodes 530 and 531. However, according to another embodiment, the inorganic passivation layer 505 may be deposited on the upper pad electrodes 530 and 531, and in this case, the inorganic passivation layer 505 may be formed or disposed on. Figure 19 At the lower part of the light-shielding component 220.

[0219] In the following text, it will be through Figures 20 to 23 Sequential description of manufacturing Figure 19 Methods for determining the pad structure.

[0220] Reference Figure 20 The gate insulating layer 120 and the interlayer insulating layer 160 can be sequentially stacked in the non-display area NA of the substrate 100.

[0221] The first lower pad electrode 170 and the second lower pad electrode 171 can be spaced apart on the interlayer insulating layer 160. When the source electrode 173 and the drain electrode 175 can be disposed on the interlayer insulating layer 160 in the display area DA, the lower pad electrodes 170 and 171 can be disposed on the interlayer insulating layer 160 in the non-display area NA.

[0222] Reference Figure 21 The first lower planarization layer 180 and the second lower planarization layer 181 can be formed or configured to overlap with the first ends of the first lower pad electrode 170 and the first ends of the second lower pad electrode 171, respectively. The first lower planarization layer 180 and the second lower planarization layer 181 can be formed or configured to partially cover the first ends of the first lower pad electrode 170 and the first ends of the second lower pad electrode 171 and the substrate 100, or partially overlap with the first ends of the first lower pad electrode 170 and the first ends of the second lower pad electrode 171 and the substrate 100. The distance W1 between the first lower pad electrode 170 and the second lower pad electrode 171, which can be adjacent to each other, can be approximately 15 μm. The distance between the first lower pad electrode 170 and the second lower pad electrode 171 can be varied according to the resolution of the light-emitting display device.

[0223] Reference Figure 22 Upper pad electrodes 530 and 531 can be disposed on lower pad electrodes 170 and 171 and lower planarization layers 180 and 181. For example, the first upper pad electrode 530 can be formed or configured to cover or overlap with the first lower pad electrode 170 and the first lower planarization layer 180, and the second upper pad electrode 531 can be formed or configured to cover or overlap with the second lower pad electrodes 170 and 171 and the second lower planarization layer 181. When sensing electrodes 520 and 540 can be disposed on the lower planarization layer 180 in the display area DA, the upper pad electrodes 530 and 531 can be disposed on the lower planarization layers 180 and 181 in the non-display area NA.

[0224] The distance W2 between the first upper pad electrode 530 and the second upper pad electrode 531, which can be adjacent to each other, can be approximately 5 μm. The distance between the first upper pad electrode 530 and the second upper pad electrode 531 can be varied according to the resolution of the light-emitting display device. The step difference between the pads can be reduced by making the first ends of the upper pad electrodes 530 and 531 mismatched with the first ends of the lower pad electrodes 170 and 171.

[0225] Reference Figure 23The light-shielding member 220 can be formed or disposed between the first upper pad electrode 530 and the second upper pad electrode 531. The light-shielding member 220 in the non-display area NA can be formed or disposed in the same steps as the process of forming the light-shielding member 220 on the sensing electrodes 520 and 540 in the display area DA. For example, the light-shielding member 220 in the non-display area NA can be formed or disposed using the same or similar material as the material of the light-shielding member 220 in the display area DA and the same method as the method used for the light-shielding member 220 in the display area DA.

[0226] The upper surface of the light-shielding member 220 may be formed or configured to be approximately 0.7 μm higher than the upper surface of the flat portion 535 of the upper pad electrodes 530 and 531 (see [reference]). Figure 23 (h6 in the example). Therefore, flexible printed circuit boards (FPCBs) and the like can be stably attached to the upper surface of the light-shielding member 220 and the upper pad electrodes 530 and 531, and voltage can be applied to the pad electrodes.

[0227] In the light-emitting display device according to the embodiment, the first ends of the upper pad electrodes 530 and 531 can be protected by the light-shielding member 220, and thus the upper pad electrodes 530 and 531 can be formed, thereby reducing the damage to the upper pad electrodes 530 and 531 that may occur during the color filter formation process. Therefore, according to the embodiment, the inorganic passivation layer 505 may not be deposited or disposed on the upper pad electrodes 530 and 531.

[0228] According to embodiments, even when a buffer layer 501 may be included, it may still have the ability to... Figure 24 The one shown in the middle is the same as Figure 19 The schematic cross-sectional structure of the pad portion 30 is similar to that of the pad portion 30.

[0229] Figure 24 A schematic cross-sectional view of a portion of a pad in a light-emitting display device according to an embodiment is shown.

[0230] according to Figure 24 ,and Figure 19 In different structures, buffer layer 501 can be disposed on the lower pad electrodes 170 and 171 and the lower planarization layers 180 and 181, and upper pad electrodes 530 and 531 can be disposed on buffer layer 501. Buffer layer 501 may not be disposed between adjacent upper pad electrodes 530 and 531. However, according to an embodiment, buffer layer 501 can be disposed between adjacent upper pad electrodes 530 and 531.

[0231] according to Figure 24The upper surface of the light-shielding member 220 may be formed or configured to be higher than the upper surface of the flat portion 535 of the upper pad electrodes 530 and 531 (see [reference]). Figure 24 (h7 in the text). Figure 23 In the embodiments, the upper surface of the light-shielding member 220 may be formed or configured to be about 0.7 μm higher than the flat portion 535 of the upper pad electrodes 530 and 531, or the upper surface of the light-shielding member 220 may be formed or configured to be higher than a lower level (in the range of about 0.4 μm to about 0.6 μm).

[0232] In the following text, reference will be made to Figure 25 and Figure 26 The description includes according to Figures 19 to 24 A schematic cross-sectional structure of the display area in a light-emitting display device with pads.

[0233] Figure 25 and Figure 26 A schematic cross-sectional view of a portion of the display area in a light-emitting display device according to an embodiment is shown.

[0234] first, Figure 25 It shows the relationship with Figure 19 The schematic cross-sectional structure of the display area DA corresponding to the pad structure, and Figure 26 It shows the relationship with Figure 24 The schematic cross-sectional structure of the display area DA corresponding to the pad structure.

[0235] Reference Figure 25 ,because Figure 25 It can be similar to the above. Figure 3 The light-emitting display device is therefore the main focus of the following description of the differences.

[0236] Reference Figure 25 ,and Figure 3 Unlike other methods, the inorganic passivation layer 505 may not be formed or disposed. For example, the light-emitting display device according to the embodiment may include a substrate 100, a transistor TFT, a gate insulating layer 120, an interlayer insulating layer 160, a lower planarization layer 180, a light-emitting diode (LED), and an encapsulation layer 400. The light-emitting display device may include a sensing insulating layer 510, sensing electrodes 520 and 540, a light-shielding member 220, color filter layers 230R, 230G, and 230B, and an upper planarization layer 550 located on the encapsulation layer 400, and the inorganic passivation layer 505 may not be formed or disposed.

[0237] Sensing electrodes 520 and 540 can be disposed on the encapsulation layer 400, and light-shielding member 220 can be disposed directly on sensing electrodes 520 and 540 without inorganic passivation layer 505. Light-shielding member 220 can be configured to overlap with sensing electrodes 520 and 540, but can be configured not to overlap with emission layer 350.

[0238] like Figure 19 As shown, the light-shielding member 220 can be disposed in the non-display area NA between the first upper pad electrode 530 and the second upper pad electrode 531. The light-shielding member 220 can be configured to cover a portion of the first upper pad electrode 530 and a portion of the second upper pad electrode 531, or overlap with a portion of the first upper pad electrode 530 and a portion of the second upper pad electrode 531, and the light-shielding member 220 can be configured to contact the first ends of the upper pad electrodes 530 and 531.

[0239] Therefore, in the light-emitting display device according to the embodiment, the ends of the upper pad electrodes 530 and 531 can be protected by the light-shielding member 220, and thus the upper pad electrodes 530 and 531 can be formed or provided to reduce damage to the upper pad electrodes 530 and 531 that may occur during the color filter forming process.

[0240] Therefore, the inorganic passivation layer 505 may not be formed or may not be provided in the display area DA.

[0241] At the same time, Figure 24 In the embodiments, with Figure 19 Different embodiments may include a buffer layer 501, and therefore, as Figure 26 As shown, in relation to Figure 24 The display area DA corresponding to the pad portion may include a buffer layer 501.

[0242] exist Figure 26 In, with Figure 25 Unlike other layers, buffer layer 501 can be included on encapsulation layer 400. Figure 26 In the embodiments, such as Figure 25 As shown, the light-shielding member 220 can be directly disposed on the sensing electrodes 520 and 540 without the inorganic passivation layer 505. This is because the ends of the upper pad electrodes 530 and 531 in the pad portion 30 can be protected by the light-shielding member 220, and therefore, damage to the upper pad electrodes 530 and 531 can be reduced without the inorganic passivation layer 505.

[0243] In the following text, reference will be made to Figures 27 to 30 The construction of the non-display area in the light-emitting display device according to an embodiment is described.

[0244] Figure 27A portion of a substrate including pads is shown in a light-emitting display device according to an embodiment. Figure 28 It shows along Figure 27 A schematic cross-sectional view taken from line XXI-XXI', and Figure 29 and Figure 30 It shows Figure 28 Examples of implementations.

[0245] Figure 27 The pad portion 30 shown can correspond to Figure 1 The pad portion 30, and Figures 28 to 30 The stacking order of the light-emitting display devices shown can be related to... Figure 12 The stacking order of the light-emitting display devices is the same.

[0246] Reference Figure 27 The pads (PADs) of the pad portion 30 can be electrically connected to the connection wiring 21. The connection wiring 21 can extend to the display area. Figure 1 The DA is electrically connected to the components and wiring of the display area DA.

[0247] Reference Figure 28 A buffer layer 501 may be disposed on the substrate 100. The buffer layer 501 may be referred to as a pad inorganic insulating layer. An inorganic insulating layer, an organic insulating layer, and a lower pad electrode may be disposed between the substrate 100 and the buffer layer 501. Although not shown in the figures, for example, a gate insulating layer may be disposed on the substrate 100. Figure 6 120 in the middle) and interlayer insulation layer ( Figure 6 160), and a lower pad electrode can be disposed on the interlayer insulating layer 160. Figure 6 (170 in the middle). The lower pad electrode 170 may have a three-layer structure, and a buffer layer 501 may be disposed on the lower pad electrode 170.

[0248] An upper pad electrode 532 may be disposed on the buffer layer 501. The upper pad electrode 532 overlaps with the buffer layer 501, and the upper surface of the buffer layer 501 is exposed in the portion where the buffer layer 501 does not overlap with the upper pad electrode 532. In an embodiment, the connection wiring 21 may be formed or disposed on the same layer as the upper pad electrode 532, or may be formed or disposed on the same layer as the lower pad electrode 170. The upper pad electrode 532 may be collectively referred to as a pad electrode, and may be a three-layer structure consisting of a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer.

[0249] An inorganic passivation layer 505 may be disposed on the buffer layer 501 and the upper pad electrode 532. The inorganic passivation layer 505 may be configured to be spaced apart from the first end of the upper pad electrode 532, and the inorganic passivation layer 505 may be configured to overlap only a portion of the upper pad electrode 532.

[0250] An upper planarization layer 550 can be disposed on the inorganic passivation layer 505. (Refer to...) Figure 3 In the display area DA, the upper planarization layer 550 can be disposed on the light-shielding member 220 and the color filter layers 230R, 230G, and 230B. However, in the non-display area NA, the upper planarization layer 550 can be directly positioned on the inorganic passivation layer 505. Each of the upper planarization layer 550 and the inorganic passivation layer 505 includes an opening that exposes a portion of the upper pad electrode 532.

[0251] The first end of the upper planarization layer 550 covering or overlapping the inorganic passivation layer 505 coincides with or is aligned with the first end of the inorganic passivation layer 505. For example, the first end of the lower surface of the upper planarization layer 550 covering or overlapping the inorganic passivation layer 505 coincides with or is aligned with the first end of the upper surface of the inorganic passivation layer 505. For part Y1, the first end of the upper surface of the inorganic passivation layer 505 disposed on the upper pad electrode 532 coincides with or is aligned with the first end of the lower surface of the upper planarization layer 550. For part Y2, the first end of the upper surface of the inorganic passivation layer 505 disposed on the buffer layer 501 coincides with or is aligned with the first end of the lower surface of the upper planarization layer 550. The first end of the planar inorganic passivation layer 505 and the first end of the upper planarization layer 550 can coincide or be aligned with each other, and the openings located in the upper planarization layer 550 and the inorganic passivation layer 505 and exposing the upper pad electrode 532 can also coincide or be aligned with each other. When the inorganic passivation layer 505 and the upper planarization layer 550 can be etched with the same mask, the first end of the upper surface of the inorganic passivation layer 505 and the first end of the lower surface of the upper planarization layer 550 can coincide or be aligned with each other. However, due to the difference in etching rate, the first end of the inorganic passivation layer 505 and the first end of the upper planarization layer 550 may not coincide or be aligned completely.

[0252] In portions Y1 and Y2, the side surfaces of the inorganic passivation layer 505 can be formed in a generally tapered structure that can be tilted substantially perpendicular to the substrate 100. The side surfaces of the inorganic passivation layer 505 can be etched by a dry etching process, and in an embodiment, after the upper pad electrode 532 is formed, damage to the upper pad electrode 532 that may occur during the color filter formation process can be reduced by forming the inorganic passivation layer 505 on the upper pad electrode 532.

[0253] Flexible printed circuit boards (FPCBs) can be attached to portions of them that expose the upper surface of the upper pad electrode 532 and the upper surface of the buffer layer 501.

[0254] Reference Figure 29 and Figure 30 , Figure 29 and Figure 30 With Figure 28 The stacking order is the same as the stacking order, and therefore the differences will be mainly described.

[0255] exist Figure 29 In this configuration, the upper pad electrode 532 completely overlaps with the buffer layer 501. The inorganic passivation layer 505 can be configured to partially overlap and separate the upper pad electrode 532 from its opposite end around the exposed portion of its upper surface. An upper planarization layer 550 can be disposed on the inorganic passivation layer 505. A flexible printed circuit board (FPCB) or similar device can be attached to the portion exposing the upper surface of the upper pad electrode 532. The upper pad electrode 532 can extend beyond the pad portion 30 to become part of the connection wiring 21.

[0256] For part Y1, the first end of the upper surface of the inorganic passivation layer 505 disposed on the upper pad electrode 532 coincides with or is aligned with the first end of the lower surface of the upper planarization layer 550, and the openings positioned on the upper planarization layer 550 and the inorganic passivation layer 505 and exposing the upper pad electrode 532 can also coincide with or be aligned with each other.

[0257] exist Figure 30 In the middle, the upper pad electrode 532 partially overlaps with the buffer layer 501. An inorganic passivation layer 505 can be disposed on the buffer layer 501 to be spaced apart from the opposite end of the upper pad electrode 532. The first end of the inorganic passivation layer 505 is spaced apart from the opposite end of the upper pad electrode 532. The connection wiring 21, which can be electrically connected to the pad portion 30, can be positioned or disposed on a different layer than the upper pad electrode 532, and the upper pad electrode 532 can be electrically connected to the connection wiring 21 through an opening in the insulating layer.

[0258] For part Y2, the first end of the upper surface of the inorganic passivation layer 505 disposed on the buffer layer 501 coincides with or is aligned with the first end of the lower surface of the upper planarization layer 550.

[0259] In portions Y1 and Y2, the side surfaces of the inorganic passivation layer 505 can be formed obliquely in a direction substantially perpendicular to the substrate 100 using a dry etching process. According to an embodiment, the inorganic passivation layer 505 can be formed on the upper pad electrode 532 of the light-emitting display device to reduce potential damage to the upper pad electrode 532 during the color filter formation process following the formation of the upper pad electrode 532.

[0260] While this disclosure has been described in conjunction with embodiments that are considered actual embodiments, it will be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A light-emitting display device, wherein, The light-emitting display device includes: A substrate, the substrate including a display area and a non-display area adjacent to the display area; The lower pad electrode is disposed on the substrate in the non-display area; A planarization layer, which overlaps with a portion of the lower pad electrode; and An upper pad electrode is disposed on the lower pad electrode and overlaps at least a portion of the planarization layer, wherein... The planarization layer includes an opening that exposes the upper surface of the lower pad electrode. The lower pad electrode and the upper pad electrode are electrically connected to each other through the opening. The planarization layer includes: The exposed portion exposes the first upper surface of the planarization layer and does not overlap with the upper pad electrode; and The overlapping portion overlaps with at least a portion of the upper pad electrode and has a second upper surface that overlaps with at least a portion of the upper pad electrode. The height of the first upper surface of the exposed portion of the planarization layer is lower than the height of the second upper surface of the overlapping portion of the planarization layer. The bottom surface of the upper pad electrode is in direct contact with the second upper surface of the overlapping portion of the planarization layer. The planarization layer has an inclined surface extending from the first upper surface of the exposed portion of the planarization layer to the second upper surface of the overlapping portion of the planarization layer, and the upper edge of the inclined surface is in direct contact with the edge of the portion of the upper pad electrode that overlaps with the overlapping portion of the planarization layer. The first upper surface and the inclined surface of the planarization layer are formed by depositing an inorganic passivation layer on the upper pad electrode and the planarization layer and by etching the inorganic passivation layer.

2. The light-emitting display device according to claim 1, wherein, The upper pad electrode includes an upper layer containing titanium, an intermediate layer containing aluminum, and a lower layer containing titanium. The lower pad electrode includes an upper layer containing titanium, an intermediate layer containing aluminum, and a lower layer containing titanium.

3. The light-emitting display device according to claim 1, wherein, The planarization layer comprises at least one of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

4. The light-emitting display device according to claim 1, wherein, The display area includes: A semiconductor layer disposed on the substrate; A gate insulating layer, wherein the gate insulating layer overlaps the semiconductor layer; A gate electrode, wherein the gate electrode is disposed on the gate insulating layer; An interlayer insulating layer, the interlayer insulating layer overlapping the gate electrode; and A source electrode and a drain electrode are disposed on the interlayer insulating layer and electrically connected to the semiconductor layer. The lower pad electrode, the source electrode, and the drain electrode are disposed on the same layer.

5. The light-emitting display device according to claim 4, wherein, The light-emitting display device further includes: A pixel electrode, wherein the pixel electrode is disposed on the planarization layer; An emission layer, the emission layer being disposed on the pixel electrode; and A common electrode, wherein the common electrode is disposed on the emitter layer, wherein, The planarization layer overlaps with the source electrode and the drain electrode, and includes vias. The drain electrode and the pixel electrode are electrically connected through the via.

6. The light-emitting display device according to claim 5, wherein, The display area includes: An encapsulation layer that overlaps with the common electrode; A sensing insulating layer is disposed on the encapsulation layer; Sensing electrodes, the sensing electrodes being disposed on the sensing insulating layer; and An inorganic passivation layer, which overlaps with the sensing electrode, and The sensing electrode and the upper pad electrode are disposed on the same layer.

7. The light-emitting display device according to claim 6, wherein, The light-emitting display device further includes: A buffer layer is disposed between the encapsulation layer and the sensing insulating layer, and between the lower pad electrode and the upper pad electrode. The lower pad electrode and the upper pad electrode are electrically connected to each other.

8. The light-emitting display device according to claim 7, wherein, The inorganic passivation layer is formed by a deposition process, and / or The inorganic passivation layer is etched using a dry etching process.

9. A method for manufacturing a light-emitting display device, wherein, The manufacturing method includes: A gate insulating layer and an interlayer insulating layer are formed on the substrate; In the display area of ​​the substrate, a source electrode and a drain electrode are formed on the interlayer insulating layer; A lower pad electrode is formed on the interlayer insulating layer in a non-display area of ​​the substrate; A lower planarization layer is formed on the source electrode, the drain electrode, and the lower pad electrode; A sensing electrode is formed on a sensing insulating layer located on the lower planarization layer in the display area of ​​the substrate; An upper pad electrode is formed on the lower planarization layer in the non-display area of ​​the substrate; An inorganic passivation layer is formed to overlap with the sensing electrode and the upper pad electrode; A light-shielding member and a color filter are formed on the inorganic passivation layer in the display area of ​​the substrate; An upper planarization layer is formed on the color filter; and The inorganic passivation layer is etched to partially expose the upper surface of the lower planarization layer in the non-display area of ​​the substrate.

10. The manufacturing method according to claim 9, wherein, The inorganic passivation layer is formed by a deposition process, and / or The etching of the inorganic passivation layer includes etching the inorganic passivation layer by a dry etching process.

11. The manufacturing method according to claim 9, wherein, The exposed upper surface of the lower planarization layer has a lower height than the upper surface of the lower planarization layer that overlaps with the upper pad electrode.

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