Semiconductor devices

Abstract

This invention provides a semiconductor device. The semiconductor device includes: a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer, wherein a channel region is located in the channel layer and adjacent to the interface between the channel layer and the barrier layer; a doped compound semiconductor layer on a portion of the barrier layer; an undoped first capping layer on the doped compound semiconductor layer; a gate structure on the undoped first capping layer; and source / drain structures on opposite sides of the gate structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and particularly to a high electron mobility transistor and a method for forming the same. Background Technology

[0002] High electron mobility transistors (HEMTs), also known as heterostructure FETs (HFETs) or modulation-doped FETs (MODFETs), are a type of field-effect transistor (FET) composed of semiconductor materials with different energy gaps. A two-dimensional electron gas (2DEG) layer is generated at the interface formed by adjacent different semiconductor materials. Due to the high electron mobility of the 2DEG, HEMTs offer advantages such as high breakdown voltage, high electron mobility, low on-resistance, and low input capacitance, making them suitable for high-power devices.

[0003] Enhancement-mode (E-mode) high electron mobility transistors are in the off state when no external gate voltage is applied. Traditionally, a P-type group III-V semiconductor is electrically connected to the gate as a bandgap layer. With the increasing demands of ultra-high voltage applications, high electron mobility transistors are required to provide higher threshold voltages (Vt). However, high electron mobility transistors must possess high stability and reliability before system testing.

[0004] While existing high electron mobility transistors (HEMs) largely meet the requirements, they are not entirely satisfactory in every aspect, especially in terms of device uniformity and hysteresis effect. Summary of the Invention

[0005] This invention provides a semiconductor device comprising: a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer; a channel layer on the buffer layer, wherein a channel region is located in the channel layer and adjacent to an interface between the channel layer and the barrier layer; a doped compound semiconductor layer on a portion of the barrier layer; an undoped first capping layer on the doped compound semiconductor layer; a gate structure on the undoped first capping layer; and source / drain structures on opposite sides of the gate structure.

[0006] The present invention also provides a method for forming a conductor device, comprising: forming a buffer layer on a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer, wherein the channel region is located in the channel layer and adjacent to an interface between the channel layer and the barrier layer; forming a film stack on a portion of the barrier layer, comprising, from bottom to top, a doped compound semiconductor layer, an undoped first capping layer and a gate structure; and forming source / drain structures on both sides of the gate structure respectively. Attached Figure Description

[0007] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0008] Figures 1 to 9 and Figure 10A According to some embodiments of the present invention, cross-sectional views are drawn of various stages in the process of forming a semiconductor device.

[0009] Figure 10B A cross-sectional view of a semiconductor device is shown in another embodiment of the present invention.

[0010] [Symbol Explanation]

[0011] 100:Substrate

[0012] 102: Channel Layer

[0013] 103: Buffer layer

[0014] 104: Barrier Layer

[0015] 106: Passage Area

[0016] 108: Doped compound semiconductor layer

[0017] 110: Undoped first capping layer

[0018] 111: Second cap layer

[0019] 112: Gate auxiliary layer

[0020] 114: Passivation layer

[0021] 115a, 115b: Opening

[0022] 116: Gate

[0023] 118: Gate Structure

[0024] 120: Source / Drain Structure Detailed Implementation

[0025] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0026] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0027] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0028] While the steps in some embodiments are performed in a specific order, these steps can also be performed in other logical orders. In different embodiments, some of the described steps may be replaced or omitted, and other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. Other features may be added to the high electron mobility transistors in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0030] The semiconductor device provided in this embodiment of the invention protects the underlying doped compound semiconductor layer from damage caused by the high temperature and high energy of subsequent processes by providing an undoped capping layer between the gate structure and the doped compound semiconductor layer. Using a capping layer to protect the doped compound semiconductor layer improves the process uniformity and hysteresis of the semiconductor device, and enables the semiconductor device to provide higher saturation current (isat) and higher breakdown voltage.

[0031] Figures 1 to 9 and Figure 10A These are cross-sectional views illustrating various stages in the formation of a semiconductor device according to some embodiments of the present invention. (Refer to...) Figure 1A substrate 100 is provided. In some embodiments, the substrate 100 may be a bulk semiconductor substrate or a similar substrate, which may be doped (e.g., using p-type or n-type dopants) or undoped. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate may be an elemental semiconductor including silicon (Si) or germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination of the foregoing. In other embodiments, the substrate 100 may also be a glass substrate, a silicon substrate with an insulating layer overlaid, or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire substrate. In one embodiment, the ceramic substrate may be covered with an insulating layer.

[0032] In one embodiment, a seed layer (not shown) and a buffer layer (not shown) are formed on the substrate 100 as needed. The seed layer is located on the substrate 100. The buffer layer is located on the seed layer. The seed layer can mitigate lattice differences between the substrate 100 and the film layer grown above it, thereby improving crystal quality. The seed layer is optional. In other embodiments, the semiconductor device does not have a seed layer. In some embodiments, the material of the seed layer may be or include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or combinations thereof.

[0033] Reference Figure 2, forming a buffer layer 103 on the substrate 100 can mitigate the strain of the subsequent channel layer 102 formed above the buffer layer 103, preventing defects from forming in the upper channel layer 102. In some embodiments, as previously mentioned, a seed layer may not be provided in the semiconductor device, and the buffer layer 103 can be directly formed above the substrate 100 to simplify the manufacturing process steps. In some embodiments, the material of the buffer layer 103 may include III-V compound semiconductor materials, such as group III nitrides. For example, the material of the buffer layer 103 may be or include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), other suitable materials, or a combination of the foregoing.

[0034] Next, referring to Figure 2 , a channel layer 102 is formed on the buffer layer 103. In some embodiments, the channel layer 102 may include III-V semiconductors, such as gallium nitride (GaN). In other embodiments, the channel layer 102 may also include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V semiconductor materials, or a combination of the foregoing. The thickness of the channel layer 102 may be between about 1000 nm and about 10000 nm. The channel layer 102 can be formed by molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or a combination of the foregoing.

[0035] Next, referring to Figure 3 , a blocking layer 104 is formed on the channel layer 102. The material of the blocking layer 104 is different from that of the channel layer 102. In some embodiments, the blocking layer 104 may include III-V semiconductors, such as Al x Ga 1-x N, where 0 < x < 1. In other embodiments, the blocking layer 104 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination of the foregoing. The thickness of the blocking layer 104 may be between about 5 nm and about 50 nm. The blocking layer 104 can be formed by molecular beam epitaxy, metalorganic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination of the foregoing.

[0036] The channel layer 102 and the barrier layer 104 are made of different materials and have different band gaps, thus forming a heterojunction at the interface between them. Because the energy bands at the heterojunction bend, a quantum well can be formed deep within the bend of the conduction band, confining the electrons generated by the piezoelectric effect within the quantum well. Therefore, a two-dimensional electron gas (2DEG) is formed at the interface between the channel layer 102 and the barrier layer 104, thereby generating a conductive current. Figure 3 As shown, a channel region 106 is formed at the interface between the channel layer 102 and the barrier layer 104. The channel region 106 is where the two-dimensional electron gas forms a conducting current.

[0037] Next, refer to Figures 4 to 10A A film stack is formed on the barrier layer 104, the film stack including a doped compound semiconductor layer 108 to be formed subsequently, an undoped first capping layer 110, and a gate structure 118. First, as... Figure 4 As illustrated, a doped compound semiconductor layer 108 is formed on the barrier layer 104. In some embodiments, the doped compound semiconductor layer 108 may include a p-type doped group III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs. In some other embodiments, the doped compound semiconductor layer 108 may include a p-type doped group II-VI semiconductor, such as CdS, CdTe, or ZnS. In some embodiments, elements such as magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be), strontium (Sr), barium (Ba), radium (Ra), carbon (C), silver (Ag), gold (Au), lithium (Li), or sodium (Na) may be used to dope the doped compound semiconductor layer 108 to make it p-type doped, and the doping concentration is between approximately 1 x 10⁻⁶. 15 cm -3 To approximately 1x10 25 cm -3 between.

[0038] Next, as Figure 5 As illustrated, an undoped first capping layer 110 is formed on a doped compound semiconductor layer 108. Although the undoped first capping layer 110 is referred to herein as an "undoped" first capping layer, it should be understood that a minimum or baseline level of doping exists due to the inevitable introduction of some foreign material during other inherent epitaxial processes. Generally, the undoped first capping layer 110 has a doping density of less than 5 x 10⁻⁶.17 cm -3 The doping concentration is [not specified]. However, it is still desirable for the first capping layer 110 to remain undoped. In one embodiment, "undoped" first capping layer 110 means that the first capping layer 110 has not been implanted with other elements, such as group III-V semiconductors, using diffusion and ion implantation methods.

[0039] In subsequent processes for forming the gate and source / drain structures, high-temperature environments and high-energy plasma sources are typically required. However, in these high-temperature and high-energy processes, the bonds of the doped compound semiconductor layer 108 on its surface are easily disrupted, resulting in numerous charged traps, which in turn affect the performance of the fabricated semiconductor device. Therefore, an undoped first capping layer 110 is provided above the doped compound semiconductor layer 108 to protect the underlying doped compound semiconductor layer 108 from damage caused by the high temperature and high energy of subsequent processes, thereby improving the process uniformity and hysteresis of the semiconductor device and enabling the semiconductor device to provide a higher saturation current.

[0040] In some embodiments, the undoped first capping layer 110 comprises a silicon-containing material. In embodiments where the undoped first capping layer 110 comprises a silicon-containing material, the silicon-containing material may be a silicon-containing semiconductor material, such as silicon or silicon carbide, and may be single crystal, polycrystalline, or amorphous. In a preferred embodiment, it may be low-temperature polycrystalline silicon. In some other embodiments, the silicon-containing material may also include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, metal silicides, or combinations thereof.

[0041] In the p-type doping process for forming the doped compound semiconductor layer 108, due to the low activation rate of the doped material, the unactivated dopants will generate many charged defects in the doped compound semiconductor layer 108, thereby affecting the performance of the fabricated semiconductor device. Therefore, if the undoped first capping layer 110 includes a silicon-containing semiconductor material, it can not only protect the underlying doped compound semiconductor layer 108 from damage caused by the high temperature and high energy of subsequent processes, but the silicon-containing semiconductor material can also compensate for the aforementioned unactivated dopants, further improving the process uniformity and hysteresis of the semiconductor device and enabling the semiconductor device to provide a higher saturation current. In addition, compared to the p-type doping of the doped compound semiconductor layer 108, the silicon-containing semiconductor material in the undoped first capping layer 110 is an n-type semiconductor material, so the undoped first capping layer 110 can form an NP junction with the doped compound semiconductor layer 108. This NP junction is reverse biased when the semiconductor device is turned on (i.e., when the gate voltage is greater than 0), which can reduce the gate leakage current of the semiconductor device and increase the gate breakdown voltage.

[0042] In some embodiments, the thickness of the undoped first capping layer 110 is between about 1 nm and 100 nm. The undoped first capping layer 110 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable method, or a combination thereof. For example, CVD processes may include low-pressure CVD (LPCVD), low-temperature CVD (LTCVD), rapid thermal CVD (RTCVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD). For example, PVD processes may include sputtering, evaporation, or pulsed laser deposition (PLD).

[0043] Next, as Figure 6As illustrated, a gate auxiliary layer 112 is formed on an undoped first capping layer 110. In some embodiments, the material of the gate auxiliary layer 112 may be a conductive material such as a metal, a metal nitride, a semiconductor material, or other suitable conductive material. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), or a combination thereof, while the semiconductor material may be polycrystalline silicon or polycrystalline germanium. The gate auxiliary layer 112 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable method, or a combination thereof. For example, CVD processes may include low-pressure CVD, low-temperature CVD, rapid thermal CVD, plasma-enhanced CVD, or atomic layer deposition (ALD). For example, PVD processes may include sputtering, evaporation, or pulsed laser deposition.

[0044] Next, refer to Figure 7 The doped compound semiconductor layer 108, the undoped first capping layer 110, and the gate auxiliary layer 112 are patterned to expose a portion of the barrier layer 104. The patterning process includes photolithography and etching. In some embodiments, the photolithography process may include photoresist coating, soft baking, hard baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying, or other suitable processes. In some embodiments, the etching process may include dry etching, wet etching, or a combination thereof. For example, dry etching may include reactive ion etching (RIE) or plasma etching.

[0045] After patterning the above film layer, as Figure 8As illustrated, a passivation layer 114 is formed on the exposed barrier layer 104, covering a patterned doped compound semiconductor layer 108, an undoped first capping layer 110, and a gate auxiliary layer 112. In some embodiments, the passivation layer may include silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, fluorinated carbon, parylene, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), other insulating materials, or combinations thereof. The passivation layer 114 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or combinations thereof.

[0046] For example, in some embodiments, a passivation layer 114 may be blanket-formed over the barrier layer 104, the doped compound semiconductor layer 108, the undoped first capping layer 110, and the gate auxiliary layer 112, and then excess material in the passivation layer 114 may be removed using a suitable planarization process to give the passivation layer 114 a flat upper surface. In some embodiments, the planarization process may include chemical mechanical polishing (CMP), mechanical polishing, grinding, etching, or a combination thereof.

[0047] Next, as Figure 9 As illustrated, an opening 115a exposing the gate auxiliary layer 112 and an opening 115b exposing the barrier layer 104 are formed in the passivation layer using a patterning process. Opening 115b is located on both sides of opening 115a. Openings 115a and 115b will be used for the subsequently formed gate and source / drain structures. (Refer to...) Figure 10A A gate 116 is formed in opening 115a, passing through passivation layer 114 and directly contacting gate auxiliary layer 112. A source / drain structure 120 is formed in opening 115b, passing through passivation layer 114 and directly contacting barrier layer 104. In some embodiments, gate auxiliary layer 112 and source / drain structure 120 are formed together in the same process, but this is not a limitation. In other embodiments, gate auxiliary layer 112 and source / drain structure 120 may be formed separately in different processes.

[0048] In some embodiments, the gate 116 may include conductive materials such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), metal oxides, metal alloys, other suitable conductive materials, or combinations thereof. The gate 116 and the gate auxiliary layer 112 described above are collectively referred to herein as the gate structure 118, as follows: Figure 10A As illustrated in the figure. The materials and processes used to form the source / drain structure 120 may be similar to or the same as those used for the gate auxiliary layer 112, and will not be described again here.

[0049] like Figure 10A As illustrated, the semiconductor device of this embodiment includes a substrate 100, a buffer layer 103 on the substrate 100, a channel layer 102 on the buffer layer 103, a barrier layer 104 on the channel layer 102, a doped compound semiconductor layer 108 on a portion of the barrier layer 104, an undoped first capping layer 110 on the doped compound semiconductor layer 108, a passivation layer 114 on the barrier layer 104, a gate structure 118 on the undoped first capping layer 110, and source / drain structures 120 on both sides of the gate structure 118, wherein the source / drain structures 120 pass through the passivation layer 104 and directly contact the barrier layer 104. Furthermore, the semiconductor device further includes a channel region 106 located in the channel layer 102 and adjacent to the interface between the channel layer 102 and the barrier layer 104. In these embodiments, the gate structure 118 includes a gate auxiliary layer 112 and a gate 116, wherein the gate auxiliary layer 112 is located on an undoped first capping layer 110, and the gate 116 is located on the gate auxiliary layer 112.

[0050] exist Figures 1 to 9 and Figure 10AIn the illustrated embodiment, by providing an undoped first capping layer between the gate structure of the semiconductor device and the underlying doped compound semiconductor layer, the underlying doped compound semiconductor layer can be protected from damage caused by the high temperature and high energy of subsequent processes, thus preventing the formation of numerous charged defects. Furthermore, in the above embodiment, the undoped first capping layer comprises a silicon-containing semiconductor material. Besides protecting the underlying doped compound semiconductor layer, the silicon-containing semiconductor material can also compensate for the unactivated dopants in the doped compound semiconductor layer. Experiments have shown that by providing a capping layer with silicon-containing semiconductors on the doped compound semiconductor layer, the process uniformity of the semiconductor device can be improved by approximately 2 to 5 times, the hysteresis of the semiconductor device can be reduced by approximately 10 times, and the semiconductor device can provide more than twice the saturation current. Moreover, compared to the doped compound semiconductor layer, the silicon-containing semiconductor material is an n-type semiconductor, allowing the undoped first capping layer to form an NP junction with the doped compound semiconductor layer. This NP junction is reverse biased when the semiconductor device is on-state (i.e., when the gate voltage is greater than 0), which can reduce the gate leakage current of the semiconductor device and increase the gate breakdown voltage.

[0051] Figure 10B This is a cross-sectional view of a semiconductor device according to other embodiments of the present invention. In these embodiments, the film stack formed by the doped compound semiconductor 108, the undoped first capping layer 110, and the gate structure 118 further includes a second capping layer 111. The second capping layer 111 is located between the undoped first capping layer 110 and the gate structure 118. More specifically, the undoped first capping layer 110 is first formed on the doped compound semiconductor layer 108, and then the second capping layer 111 is formed on the undoped first capping layer 110. In a preferred embodiment, the doped compound semiconductor 108, the undoped first capping layer 110, and the second capping layer 111 may be patterned simultaneously such that the vertical projected areas of the doped compound semiconductor 108, the undoped first capping layer 110, and the second capping layer 111 are the same. Compared to the undoped first capping layer 110, the second capping layer 111 can not only further protect the doped compound semiconductor layer 108 during the process, but also compensate for defects of electrons or holes generated in subsequent processes. An inverse diode is formed at the interface between the first capping layer 110 and the doped compound semiconductor 108, thereby reducing the gate leakage current of the semiconductor device and increasing the gate breakdown voltage.

[0052] In some embodiments, the second capping layer 111 and the undoped first capping layer 110 are formed of different materials. For example, according to some embodiments of the invention, the material of the second capping layer 111 includes alumina, aluminum nitride, or a combination thereof. The second capping layer 111 can be formed using chemical vapor deposition, physical vapor deposition, any other suitable method, or a combination thereof. In some embodiments, the thickness of the second capping layer 111 is between about 1 nm and 100 nm.

[0053] In summary, the semiconductor device provided by the embodiments of the present invention, by providing an undoped capping layer between the gate structure and the underlying doped compound semiconductor layer, protects the doped compound semiconductor layer from damage caused by the high temperature and high energy of the process, thereby improving the process uniformity and hysteresis of the semiconductor device and enabling the semiconductor device to provide a higher saturation current. Furthermore, the silicon-containing semiconductor material in the capping layer not only compensates for charge defects in the doped compound semiconductor layer but also allows the capping layer and the doped compound semiconductor layer to form an NP junction, thereby reducing the gate leakage current of the semiconductor device and increasing the gate breakdown voltage.

[0054] The foregoing outlines the features of several embodiments of the present invention to facilitate a better understanding of the viewpoints of these embodiments by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A buffer layer is located on the substrate; A channel layer is located on the buffer layer; A barrier layer is located on the channel layer, wherein a channel region is located in the channel layer and is adjacent to an interface between the channel layer and the barrier layer; A doped compound semiconductor layer is located on a portion of the barrier layer; An undoped first capping layer is located on the doped compound semiconductor layer; A gate structure is located on the undoped first capping layer; as well as A source / drain structure is located on both sides of the gate structure. The undoped first capping layer is silicon, or includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or a combination thereof. The gate structure is in direct contact with the undoped first capping layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The gate structure further includes a gate auxiliary layer and a gate, wherein the gate auxiliary layer is located on the undoped first capping layer and the gate is located on the gate auxiliary layer.

3. The semiconductor device as claimed in claim 1, characterized in that, It further includes a passivation layer located on the barrier layer, wherein the source / drain structure passes through the passivation layer and directly contacts the barrier layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the undoped first capping layer is between 1 nm and 100 nm.

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