Display device

Abstract

A display device is disclosed. The display device includes: a subpixel including a light-emitting unit and a driving transistor, the light-emitting unit including a first electrode, a second electrode, and a plurality of light-emitting elements connected between the first and second electrodes; the driving transistor configured to supply a driving current to the light-emitting unit; a detector electrically connected to the light-emitting unit to detect a short circuit in the plurality of light-emitting elements; and a blocking controller configured to control blocking of the driving current based on an output of the detector. Consequently, power consumption of the display device can be improved.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0045270, filed on April 14, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device and a driving method of the display device, and more particularly, to a display device capable of emitting light by using ultra-small light-emitting elements having a nanometer-level or micrometer-level size and a driving method of the display device. Background Art

[0003] With the development of information technology, the importance of display devices that can be a connecting medium between users and information has been emphasized. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices has been increasing.

[0004] Organic light emitting display devices emit light using organic light emitting diodes (OLEDs), which are formed using organic materials. As time passes or as a driving period accumulates, the organic light emitting diodes may deteriorate or their light emission efficiency may decrease.

[0005] Recently, in order to solve the above-mentioned problems of organic light-emitting diodes, research has been conducted by using inorganic materials in light-emitting elements. For example, research has been conducted on display devices that have nanometer or micrometer-scale dimensions and emit light by using ultra-small light-emitting elements formed of inorganic materials.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not form the prior art. Summary of the Invention

[0007] One or more aspects of the present disclosure are to provide a display device capable of improving power consumption by blocking a driving current of a sub-pixel that may be viewed as a so-called dark spot from the outside.

[0008] One or more aspects of the present disclosure are to provide a driving method of a display device.

[0009] One or more aspects of the present disclosure are not limited to the above-described aspects and may be variously extended without departing from the spirit and scope of the present disclosure.

[0010] According to one or more aspects of the present disclosure, a display device is provided.

[0011] According to one or more example embodiments, a display device may include: a sub-pixel including a light-emitting unit and a driving transistor, the light-emitting unit including a first electrode, a second electrode, and a plurality of light-emitting elements connected between the first electrode and the second electrode, the driving transistor being configured to supply a driving current to the light-emitting unit; a detector electrically connected to the light-emitting unit to detect a short circuit in the plurality of light-emitting elements; and a blocking controller configured to control blocking of the driving current based on an output of the detector.

[0012] In one or more example embodiments, each of the plurality of light emitting elements includes an inorganic light emitting diode having a nanoscale or microscale size.

[0013] In one or more example embodiments, the light emitting unit may include a plurality of groups each including a plurality of light emitting elements connected in parallel to each other, and the plurality of groups may be connected in series to each other between the first electrode and the second electrode.

[0014] In one or more example embodiments, the detector includes at least one comparator configured to compare a reference voltage with a voltage at at least one of the first electrode or nodes connecting the plurality of groups in series.

[0015] In one or more example embodiments, the at least one comparator may include a main comparator electrically connected to the first electrode to compare the voltage of the first electrode with a first reference voltage.

[0016] In one or more example embodiments, the first reference voltage may be determined by using a value corresponding to the number of the plurality of groups.

[0017] In one or more example embodiments, the first reference voltage may be determined by multiplying the number of the plurality of groups by a set ratio (eg, a predetermined ratio).

[0018] In one or more example embodiments, the main comparator may include an amplifier having a first input terminal for receiving the voltage of the first electrode, a second input terminal for receiving a first reference voltage, and an output terminal for outputting a result of the comparison of the voltage of the first electrode with the first reference voltage as one of a low level signal and a high level signal.

[0019] In one or more example embodiments, the blocking controller may output a turn-off signal to block the driving current through the blocking control line based on the output of the main comparator when the voltage of the first electrode is lower than the first reference voltage.

[0020] In one or more example embodiments, the sub-pixel may further include a blocking transistor configured to be turned off in response to a turn-off signal.

[0021] In one or more exemplary embodiments, the blocking transistor may be electrically connected to a gate electrode of the driving transistor to turn off the driving transistor in response to a turn-off signal.

[0022] In one or more example embodiments, the blocking transistor may be located in a path in which the driving current flows from the first power source to the second power source via the driving transistor.

[0023] In one or more example embodiments, the at least one comparator may further include an auxiliary comparator electrically connected to the corresponding node to compare the voltage of the corresponding node with a second reference voltage.

[0024] In one or more example embodiments, the blocking controller may output a turn-off signal that blocks the driving current through a blocking control line based on outputs of the main comparator and the auxiliary comparator.

[0025] In one or more example embodiments, the blocking controller may be configured to output the cutoff signal by performing a logical OR operation on outputs of the main comparator and the auxiliary comparator.

[0026] One or more example embodiments of the present disclosure provide a driving method of a display device.

[0027] In one or more example embodiments, a driving method of a display device may include: sensing at least one voltage of a light-emitting unit including a first electrode, a second electrode, and a plurality of light-emitting elements connected between the first electrode and the second electrode; comparing the sensed at least one voltage with a reference voltage; and generating a cutoff signal for blocking a driving current supplied to the light-emitting unit in response to a result of the comparison.

[0028] In one or more example embodiments, each of the light emitting elements may be an inorganic light emitting diode having a nanometer-scale or micrometer-scale size.

[0029] In one or more example embodiments, the light emitting unit may include a plurality of groups each including a plurality of light emitting elements connected in parallel to each other, and the plurality of groups may be connected in series to each other between the first electrode and the second electrode.

[0030] In one or more example embodiments, the comparing may include comparing the voltage of the first electrode with a first reference voltage.

[0031] In one or more example embodiments, the comparing may further include comparing a voltage of a node connecting the plurality of groups in series with a second reference voltage.

[0032] According to the display device and the driving method of the display device according to the present disclosure, power consumption can be improved by detecting a short circuit occurring between multiple light-emitting elements included in a light-emitting unit of a sub-pixel and blocking the driving current of the sub-pixel according to whether a short circuit is detected or the proportion of the short-circuited light-emitting elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagrams illustrating a display device according to one or more example embodiments of the present disclosure are shown.

[0034] Figure 2 Shown according to Figure 1 A top plan view of the display panel.

[0035] Figure 3 and Figure 4 A perspective view and a cross-sectional view illustrating a light emitting element according to one or more example embodiments of the present disclosure are respectively illustrated.

[0036] Figures 5A to 5C Shows the Figure 2 Circuit diagram of an example of a sub-pixel.

[0037] Figure 6 Schematic diagrams are shown for describing a situation where a dark spot occurs in a light emitting unit according to one or more example embodiments of the present disclosure.

[0038] Figure 7 Shown is a schematic diagram further illustrating a detector and a blocking controller according to one or more example embodiments of the present disclosure.

[0039] Figures 8A to 8C shows the Figure 7 A circuit diagram of a sub-pixel to which a blocking transistor of a cut-off signal is added.

[0040] Figure 9 A flowchart illustrating a driving method of a display device according to one or more example embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0041] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. As those skilled in the art will realize, the described embodiments can be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0042] In order to clearly describe the present disclosure, parts not related to the description are omitted, and the same reference numerals refer to the same or similar components throughout the specification. Therefore, the above reference numerals may be used in other drawings.

[0043] In addition, since the sizes and thicknesses of the components shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity.

[0044] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, a first element, component, region, layer, or part discussed herein may be referred to as a second element, component, region, layer, or part without departing from the scope of the present disclosure.

[0045] For ease of description, spatial relative terms such as "under...", "below...", "below...", "below...", "above...", "on...", etc. may be used herein to describe the relationship between an element or feature and another (other) element or feature as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, such spatial relative terms are intended to encompass different orientations of the device in use or in operation. For example, if the device in the figure is flipped, an element described as "under" or "below" or "below" other elements or features will then be positioned as "above" the other elements or features. Thus, the example terms "under..." and "below..." can encompass both above and below orientations. The device can be positioned otherwise (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. In one or more exemplary embodiments, it will also be understood that when a layer is referred to as being "between" two layers, that layer can be the only layer between the two layers, or one or more example intermediate layers may also be present.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize.

[0047] As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "one (kind / one)" are also intended to include the plural forms. It will also be understood that when the term "including" and / or its variations are used in this specification, the description indicates the presence of the stated features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. Expressions such as "at least one (kind / one) in..." modify the entire list of elements when following a list of elements, without modifying the individual elements in the list. In addition, when describing embodiments of the present disclosure, the use of "can" refers to "one or more embodiments of the present disclosure." In addition, the term "exemplary" is intended to indicate an example or explanation. As used herein, the term "using" and its variations can be considered to be synonymous with the term "utilizing" and its variations, respectively.

[0048] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, the element or layer can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.

[0049] Figure 1 Schematic diagrams illustrating a display device according to one or more example embodiments of the present disclosure are shown.

[0050] Reference Figure 1 , the display device DD may include a display panel 100 , a timing controller 200 , a scan driver 300 , a light emission driver 400 , a data driver 500 , and a power management unit 600 .

[0051] The display panel 100 may include a plurality of pixels PX[i,j]. The pixels PX[i,j] may include p rows (p is a positive integer) and q columns (q is a positive integer). The pixels PX[i,j] located in the same row (hereinafter, may also be referred to as a horizontal line) may be connected to the same scan line and the same emission control line. In one or more example embodiments, the pixels PX[i,j] located in the same column (hereinafter, may also be referred to as a vertical line) may be connected to the same data line. For example, the pixel PX[i,j] located in the i-th row (i is a positive integer less than or equal to p) and the j-th column (j is a positive integer less than or equal to q) may be connected to the i-th scan line SL[i] and the i-th emission control line EL[i], and may also be connected to the j-th data line DL[j].

[0052] The timing controller 200 may generate a scan drive control signal SCS, a data drive control signal DCS, and an emission control signal ECS in response to a synchronization signal supplied from the outside. The scan drive control signal SCS may be supplied to the scan driver 300, the data drive control signal DCS may be supplied to the data driver 500, and the emission control signal ECS may be supplied to the light emission driver 400. In one or more example embodiments, the timing controller 200 may generate image data RGB based on input image data supplied from the outside, and may supply the generated image data RGB to the data driver 500.

[0053] The scan drive control signal SCS may include a scan start signal and a clock signal. The scan start signal may be a signal for controlling the first timing of the scan signal. The clock signal may be used to shift the scan start signal.

[0054] The emission control signal ECS may include an emission start signal and a clock signal. The emission start signal may control the first timing of the emission signal. The clock signal may be used to shift the emission start signal.

[0055] The data drive control signal DCS may include a source start pulse and a clock signal. The source start pulse may control the starting point of data sampling. The clock signal may be used to control the sampling operation.

[0056] The scan driver 300 may receive a scan drive control signal SCS from the timing controller 200 and may sequentially supply scan signals to the scan lines SL[1], SL[2], ..., and SL[p] based on the scan drive control signal SCS. When the scan signals are sequentially supplied, pixels PX[i, j] are selected in units of horizontal lines (or pixel rows), and data signals may be supplied to the selected pixels PX[i, j].

[0057] The scan driver 300 may include a scan stage configured in the form of a shift register. The scan driver 300 may generate a scan signal by sequentially transmitting a scan start signal to a next scan stage in the form of an on-level pulse under the control of a clock signal.

[0058] The light emission driver 400 may receive an emission control signal ECS from the timing controller 200 and may sequentially supply emission signals to the emission control lines EL[1], EL[2], ..., and EL[p] based on the emission control signal ECS. The emission signal may be used to control the emission time of the pixel PX[i, j]. For this purpose, the emission signal may be set to have a bandwidth wider than that of the scan signal.

[0059] The data driver 500 may receive a data driving control signal DCS and image data RGB from the timing controller 200. The data driver 500 may supply data voltages (or data signals) to pixels PX[i,j] located on a horizontal line selected by a scan signal through data lines DL[1], DL[2], ..., and DL[q] based on the image data RGB. To this end, the data driver 500 may supply data voltages to the data lines DL[1], DL[2], ..., and DL[q] in synchronization with the scan signal.

[0060] The power management unit 600 can supply the voltage of the first power supply VDD, the voltage of the second power supply VSS, and the voltage of the initialization power supply Vint to the display panel 100. The first power supply VDD and the second power supply VSS can generate voltages for driving a plurality of light-emitting elements included in each pixel PX[i, j] (or included in a sub-pixel) of the display panel 100. In one or more example embodiments, the voltage of the second power supply VSS may be lower than the voltage of the first power supply VDD. For example, the voltage of the first power supply VDD may be a positive voltage, and the voltage of the second power supply VSS may be a negative voltage. The driving transistor and / or the light-emitting element included in the pixel PX[i, j] may be initialized by the voltage of the initialization power supply Vint.

[0061] Although Figure 1 , a light emission driver 400 for supplying an emission signal is shown, but depending on the circuit structure of sub-pixels SPX1, SPX2, and SPX3 to be described later, the light emission driver 400 may be omitted, or a second scan driver similar to the scan driver 300 and outputting a second scan signal may be added.

[0062] Figure 2 Shown according to Figure 1 A top plan view of the display panel.

[0063] Reference Figure 2The display panel 100 may include a base layer SUB1 (or substrate) and pixels PX[i,j] located on the base layer SUB1. In one or more example embodiments, the display panel 100 and the base layer SUB1 may include a display area DA in which an image is displayed and a non-display area NDA other than the display area DA.

[0064] According to one or more example embodiments, the display area DA may be located in a central area of ​​the display panel 100, and the non-display area NDA may be located along an edge (e.g., periphery) of the display panel 100 to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0065] The base layer SUB1 may constitute a base member of the display panel 100. For example, the base layer SUB1 may constitute a base member of a lower panel (eg, the lower panel of the display panel 100).

[0066] According to one or more example embodiments, the base layer SUB1 may be a rigid substrate or a flexible substrate. For example, the base layer SUB1 may be a rigid substrate made of glass or tempered glass, or a flexible substrate made of a plastic or metal film. In one or more example embodiments, the base layer SUB1 may be a transparent substrate, a translucent substrate, an opaque substrate, or a reflective substrate.

[0067] The base layer SUB1 may include a display area DA in which the pixels PX[i, j] are located, and a non-display area NDA corresponding to a remaining area other than the display area DA. The non-display area NDA may be located on at least one side of the display area DA. Various wirings and / or built-in circuit units connected to the pixels PX[i, j] in the display area DA may be located in the non-display area NDA.

[0068] A pixel PX[i,j] may include a plurality of sub-pixels. For example, the pixel PX[i,j] may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. According to one or more example embodiments, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of different colors. For example, the first sub-pixel SPX1 may be a red sub-pixel emitting red light, the second sub-pixel SPX2 may be a green sub-pixel emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel emitting blue light.

[0069] In one or more example embodiments, each of the sub-pixels SPX1, SPX2, and SPX3 may be formed by using a light emitting unit LSU (see FIG. Figure 5A ) and emit light, and the light emitting unit LSU may include a plurality of light emitting elements LD (see Figure 5A For example, each of the light emitting elements LD has a size as small as nanometer to micrometer level and may be a light emitting diode (eg, an inorganic light emitting diode), and the light emitting elements LD may be connected to each other in series and / or in parallel.

[0070] Hereinafter, the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may be collectively referred to as sub-pixels SPX.

[0071] Figure 3 and Figure 4 A perspective view and a cross-sectional view illustrating a light emitting element according to one or more example embodiments of the present disclosure are respectively illustrated.

[0072] Reference Figure 3 and Figure 4 The light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 located between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be formed as a stacked body in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked in one direction.

[0073] According to one or more example embodiments, the light emitting element LD may have a rod shape extending in one direction. The light emitting element LD may have a first end portion and a second end portion along the one direction.

[0074] According to one or more example embodiments, one of the first and second semiconductor layers 11 and 13 may be located at a first end of the light emitting element LD, and the other may be located at a second end of the light emitting element LD.

[0075] According to one or more example embodiments, the light emitting element LD may be a light emitting diode (LED) manufactured to have a rod shape. In one or more example embodiments, the rod shape includes a rod-like shape or a strip-like shape (such as a cylinder or a polygonal prism) that is longer in the longitudinal direction than in the width direction (i.e., its aspect ratio is greater than 1), and its cross-sectional shape is not particularly limited. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of the cross section).

[0076] According to one or more example embodiments, the light emitting element LD may have a size as small as nanometer to micrometer scale, for example, a diameter D and / or a length L ranging from about 100 nm to about 10 μm. However, the size of the light emitting element LD may be variously changed according to the design conditions of the display device DD using the light emitting element LD.

[0077] The first semiconductor layer 11 may include at least one n-type semiconductor material. For example, the first semiconductor layer 11 may include a semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor material doped with a first conductive dopant such as Si, Ge, or Sn.

[0078] The active layer 12 is located on the first semiconductor layer 11 and can be formed in a single quantum well structure or a multi-quantum well structure. In one or more example embodiments, a cladding layer doped with a conductive dopant can be formed at the upper and / or lower portion of the active layer 12. For example, the cladding layer can be formed as an AlGaN layer or an InAlGaN layer. According to one or more example embodiments, the active layer 12 can be formed using a material such as AlGaN or AlInGaN, and various other materials can constitute the active layer 12. For example, the active layer 12 can be located between the first semiconductor layer 11 and the second semiconductor layer 13 described below.

[0079] When a voltage equal to or greater than a threshold voltage is applied to opposite ends of the light-emitting element LD, the light-emitting element LD can emit light while electron-hole pairs are recombined in the active layer 12. By controlling light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source for various light-emitting elements included in pixels of the display device DD.

[0080] The second semiconductor layer 13 is located on the active layer 12 and may include a semiconductor material of a different type from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 includes at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor material doped with a second conductive dopant such as Mg.

[0081] According to one or more example embodiments, a first length L1 of the first semiconductor layer 11 may be longer than a second length L2 of the second semiconductor layer 13 .

[0082] According to one or more example embodiments, the light emitting element LD may further include an insulating film INF disposed on a surface thereof. The insulating film INF may be located on the surface of the light emitting element LD to surround at least the outer peripheral surface (e.g., outer circumferential surface) of the active layer 12 and may also be located to surround regions of the first semiconductor layer 11 and the second semiconductor layer 13.

[0083] According to one or more example embodiments, the insulating film INF may expose opposite ends of the light emitting element LD having different polarities. For example, the insulating film INF may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 located at opposite ends of the light emitting element LD in the longitudinal direction (e.g., both surfaces (i.e., the upper surface and the lower surface) of a cylinder) without covering them. In some other example embodiments, the insulating film INF may expose opposite ends of the light emitting element LD having different polarities and side portions of the semiconductor layers 11 and 13 adjacent to the opposite ends thereof.

[0084] According to one or more example embodiments, the insulating film INF may include at least one insulating material among silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), and titanium dioxide (TiO 2 ).

[0085] In one or more example embodiments, the light emitting element LD may further include additional components in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF. For example, the light emitting element LD may include one or more phosphor layers, an active layer, a semiconductor material layer, and / or an electrode layer located at a first end of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0086] When a voltage equal to or greater than a threshold voltage is applied to opposite ends of the light emitting element LD, the light emitting element LD can emit light while electron-hole pairs are combined in the active layer 12 .

[0087] Figures 5A to 5C Shows the Figure 2 Circuit diagram of an example of a sub-pixel.

[0088] Figures 5A to 5C One or more example embodiments of a circuit diagram of a sub-pixel SPX are shown, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be implemented to have the same circuit diagram as that according to FIG. Figures 5A to 5C The form of the sub-pixel SPX is the same as the form.

[0089] exist Figures 5A to 5C In the example, the light emitting element LD can be a reference Figures 3 and 4 Inorganic light-emitting diodes having nanoscale or microscale dimensions are described.

[0090] Hereinafter, on the premise that the sub-pixel SPX is located in the i-th row and the j-th column of the display area DA, the data line DL[j] connected to the sub-pixel SPX may be the j-th data line DL[j], the scan line SL[i] connected to the sub-pixel SPX may be the i-th scan line SL[i], and the emission control line EL[i] connected to the sub-pixel SPX may be the i-th emission control line EL[i].

[0091] Reference Figures 5A to 5C The sub-pixel SPX may include a light emitting unit LSU and a driving transistor for supplying a driving current to the light emitting unit LSU. The light emitting unit LSU includes a first electrode AE, a second electrode CE, and a plurality of light emitting elements LD connected between the first electrode AE ​​and the second electrode CE. Hereinafter, the driving transistor may alternatively be referred to as a first transistor T1.

[0092] The light emitting unit LSU may include a first electrode AE ​​electrically connected to a first power source VDD and a second electrode CE electrically connected to a second power source VSS. The light emitting unit LSU may emit light having a brightness corresponding to the driving current by using the light emitting element LD. Thus, an image may be displayed in the display area DA of the display panel 100.

[0093] The first transistor T1 (eg, a driving transistor) may be electrically connected between a first power source VDD and a second power source VSS to generate a driving current corresponding to a data signal (or data voltage) and supply the generated driving current to the light emitting unit LSU.

[0094] Reference Figure 5A , the sub-pixel SPX may include a first transistor T1, a second transistor T2, a storage capacitor Cst, and a light emitting unit LSU.

[0095] In one or more example embodiments, a first transistor T1 (e.g., a driving transistor) may be included between a first power supply VDD and a first electrode AE ​​of the light emitting unit LSU and connected to a gate electrode of the first node N1. For example, the first transistor T1 may be connected between the first power supply VDD and the first electrode AE ​​of the light emitting unit LSU, and the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may be turned on in response to a voltage applied to the first node N1, thereby generating a driving current.

[0096] The second transistor T2 may be included between the data line DL[j] and the first node N1 and connected to the gate electrode of the scan line SL[i]. For example, the second transistor T2 may be connected between the data line DL[j] and the first node N1, and the gate electrode of the second transistor T2 may be connected to the scan line SL[i]. The second transistor T2 may be turned on in response to a scan signal supplied through the scan line SL[i] to transmit the data signal supplied through the data line DL[j] to the first node N1. The second transistor T2 may also be referred to as a switching transistor.

[0097] The storage capacitor Cst may be connected between the first node N1 and the second node N2. Thus, the storage capacitor Cst may store a voltage applied between the first node N1 and the second node N2. Figure 5A , the second node N2 may be the same node as the node connected to the second electrode of the first transistor T1.

[0098] The light emitting unit LSU may be connected between the second node N2 and the second power source VSS. Figure 5A Unlike what is shown in FIG, the light emitting unit LSU may be connected between the first power source VDD and the first electrode of the first transistor T1.

[0099] Reference Figure 5B , the sub-pixel SPX may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and a light emitting unit LSU.

[0100] The first transistor T1 may be connected between a first power supply VDD and the light emitting unit LSU. For example, a first electrode (e.g., a source electrode) of the first transistor T1 may be connected to the first power supply VDD via a fifth transistor T5, and a second electrode (e.g., a drain electrode) of the first transistor T1 may be connected to the first electrode AE ​​of the light emitting unit LSU via a sixth transistor T6. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may be turned on in response to a voltage applied to the first node N1 to supply a driving current to the light emitting unit LSU.

[0101] The second transistor T2 may be connected between the j-th data line DL[j] and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line SL[i]. When a scan signal having a gate-on voltage (e.g., a low voltage level) is supplied from the i-th scan line SL[i], the second transistor T2 may be turned on to transmit the data signal supplied through the j-th data line DL[j] to the first electrode of the first transistor T1.

[0102] The third transistor T3 may be connected between the second electrode (e.g., the drain electrode) of the first transistor T1 and the first node N1. The third transistor T3 may include a gate electrode connected to the i-th scan line SL[i]. When a scan signal having a gate-on voltage (e.g., a low voltage level) is supplied from the i-th scan line SL[i], the third transistor T3 may be turned on to electrically connect the gate electrode (e.g., the first node N1) of the first transistor T1 and the second electrode of the first transistor T1, thereby operating the first transistor T1 in a diode-type manner (e.g., the first transistor T1 is diode-connected).

[0103] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. A gate electrode of the fourth transistor T4 may be connected to the previous scan line SL[i-1]. When a scan signal having a gate-on voltage (e.g., a low voltage level) is supplied to the previous scan line SL[i-1], the fourth transistor T4 may be turned on to transmit the voltage of the initialization power supply Vint to the first node N1. Here, the voltage of the initialization power supply Vint may be less than or equal to the lowest voltage of the data signal.

[0104] The fifth transistor T5 may be connected between the first power supply VDD and the first electrode of the first transistor T1. The fifth transistor T5 may include a gate electrode connected to the i-th emission control line EL[i]. When an emission control signal having a gate-on voltage (e.g., a low-level voltage) is supplied to the i-th emission control line EL[i], the fifth transistor T5 may be turned on to apply the voltage of the first power supply VDD to the first electrode of the first transistor T1.

[0105] The sixth transistor T6 may be connected between the first transistor T1 and the first electrode AE ​​of the light emitting unit LSU. The sixth transistor T6 may include a gate electrode connected to the i-th emission control line EL[i]. When an emission signal having a gate-on voltage (e.g., a low voltage level) is supplied via the i-th emission control line EL[i], the sixth transistor T6 may be turned on to transmit the driving current of the first transistor T1 to the light emitting unit LSU.

[0106] The seventh transistor T7 may be connected between the first electrode AE ​​(or the second node N2) of the light emitting unit LSU and the initialization power supply Vint. The seventh transistor T7 may include a gate electrode connected to the subsequent scan line SL[i+1]. When a scan signal having a gate-on voltage (e.g., a low voltage level) is supplied to the subsequent scan line SL[i+1], the seventh transistor T7 may be turned on to transmit the voltage of the initialization power supply Vint to the first electrode AE ​​of the light emitting unit LSU. Therefore, when a scan signal having a gate-on voltage (e.g., a low voltage level) is supplied to the scan line SL[i+1], the first electrode AE ​​of the light emitting unit LSU may be initialized to the voltage of the initialization power supply Vint. In one or more example embodiments, the gate electrode of the seventh transistor T7 may be connected to the i-th scan line SL[i], and when the scan signal is supplied to the i-th scan line SL[i], the seventh transistor T7 may be turned on to apply the voltage of the initialization power supply Vint to the first electrode AE ​​of the light emitting unit LSU.

[0107] The storage capacitor Cst may be connected between the first power source VDD and the first node N1. The storage capacitor Cst may store the data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first transistor T1 during each frame period.

[0108] The light emitting unit LSU may be connected between the second node N2 and the second power source VSS.

[0109] Reference Figure 5C , the sub-pixel SPX may include first, second and third transistors T1, T2 and T3, a storage capacitor Cst and a light emitting unit LSU.

[0110] The first and second transistors T1 and T2 and the storage capacitor Cst are respectively connected to the reference Figure 5A The described first and second transistors T1 and T2 and the storage capacitor Cst are substantially the same or similar, and thus overlapping descriptions will not be repeated.

[0111] The third transistor T3 may be connected between the j-th sensing line SEN[j] and the second node N2 and may be connected to the second scan line SL2[i]. Here, the second scan line SL2[i] may be the j-th scan line SL[j] or the j+1-th scan line SL[j+1], or although Figure 1 Although not shown in the figure, the second scan line SL2[i] may be a line to which a second scan signal output from a second scan driver different from the scan driver 300 is supplied.

[0112] The light emitting unit LSU may be connected between the second node N2 and the second power source VSS.

[0113] The third transistor T3 may be turned on in response to a second scan signal of a gate-on voltage transmitted from the second scan line SL2[i] to electrically connect the j-th sensing line SEN[j] to the second node N2. For example, when the third transistor T3 is turned on, the driving current flowing through the first transistor T1 (or the voltage of the second electrode of the first transistor T1) may be supplied to a sensing module inside the display device DD or a sensing device outside the display device DD via the j-th sensing line SEN[j]. The sensing module may sense characteristics of the first transistor T1 (e.g., threshold voltage and mobility) based on the driving current supplied via the j-th sensing line SEN[j].

[0114] In one or more example embodiments, in addition to the light emitting unit LSU, Figures 5A to 5C The transistor and the storage capacitor Cst in the sub-pixel SPX shown in FIG. 4 may be referred to as a pixel circuit PXC, and the pixel circuit PXC may be located on a layer different from that of the light emitting unit LSU in the base layer SUB1 .

[0115] exist Figures 5A to 5C , at least one of the transistors shown as an n-type transistor among the transistors included in the pixel circuit PXC may be changed to a p-type transistor, and at least one of the transistors shown as a p-type transistor may be changed to an n-type transistor.

[0116] Figure 6 Schematic diagrams are shown for describing a situation where a dark spot occurs in a light emitting unit according to one or more example embodiments of the present disclosure.

[0117] Reference Figure 6 , shows in detail the Figures 5A to 5C A circuit of the light emitting unit LSU connected between the second node N2 and the second power supply VSS in the sub-pixel SPX.

[0118] The light emitting unit LSU may include a plurality of groups GR1, GR2, ..., and GRN, each of which is formed by groups of light emitting elements connected in parallel (or includes light emitting elements connected in parallel). For example, the light emitting unit LSU may include a first group GR1 to an Nth group GRN (N is a natural number of 1 or greater), wherein k light emitting elements are connected in parallel to each other in each of the first group GR1 to the Nth group GRN (k is a natural number of 1 or greater). In one or more example embodiments, the first group GR1 to the Nth group GRN may be connected in series with each other between the first electrode AE ​​of the light emitting unit LSU and the second electrode CE of the light emitting unit LSU.

[0119] exist Figures 5A to 5C, the light emitting elements LD included in the light emitting unit LSU are shown to be connected in a direction along which current flows from the first power supply VDD to the second power supply VSS (hereinafter referred to as a forward direction). However, due to errors in a process of aligning the light emitting elements LD in the forward direction, some of the light emitting elements LD may be connected in a direction opposite to the forward direction (hereinafter referred to as a reverse direction).

[0120] For example, Figure 6 As shown in FIG, some light emitting elements DA1, DB1, and DNk may be aligned in the forward direction, but some light emitting elements DN1, DAk, and DBk may be aligned in the reverse direction. In one or more example embodiments, the light emitting element LD connected in the forward direction may be an effective light emitting element, and the light emitting element LD connected in the reverse direction may not emit light.

[0121] In addition, some of the light emitting elements LD may be short-circuited to not emit light. Figure 6 When at least one light emitting element in the first group GR1 of light emitting elements connected in parallel to each other is short-circuited, all light emitting elements DA1, ..., and DAk belonging to the first group GR1, which is the same as the short-circuited first group GR1 of light emitting elements, do not emit light. In one or more example embodiments, when at least one light emitting element in the second group GR2 of light emitting elements connected in parallel to each other is short-circuited, all light emitting elements DB1, ..., and DBk belonging to the second group GR2, which is the same as the short-circuited second group GR2 of light emitting elements, do not emit light.

[0122] Therefore, when at least one light emitting element LD in each of the groups GR1, GR2, . . . and GRN is short-circuited, all light emitting elements LD included in the light emitting unit LSU do not emit light, and the sub-pixel SPX having such a light emitting unit LSU is visually recognized as a dark spot from the outside.

[0123] However, even when a short circuit occurs between the light emitting elements LD so that the light emitting unit LSU does not emit light, a constant current flows through the driving transistor T1 (eg, Figures 5A to 5C ) flows between the first power source VDD and the second power source VSS, thus unnecessarily consuming power of the display device DD.

[0124] Figure 7 Shown is a schematic diagram further illustrating a detector and a blocking controller according to one or more example embodiments of the present disclosure.

[0125] In one or more example embodiments, the display device DD may include the detector 1000 and the blocking controller 2000. The detector 1000 may be included in the display device DD (or in the pixel circuits PXC of the subpixels SPX) as many as the number of subpixels SPX included in the display device DD.

[0126] The detector 1000 may be electrically connected to the light emitting unit LSU to detect a short circuit in the light emitting element LD. For example, the detector 1000 may include at least one comparator for comparing a reference voltage with a voltage of at least one of the first electrode AE ​​or nodes N(1), N(2), ..., and N(N-1) for connecting the groups GR1, GR2, ..., and GRN in series.

[0127] The at least one comparator may include a main comparator MCP electrically connected to the first electrode AE ​​to compare the voltage of the first electrode AE ​​with a first reference voltage Vref1 .

[0128] The main comparator MCP may include an amplifier (AMP) having a first input terminal for receiving the voltage of the first electrode AE, a second input terminal for receiving the first reference voltage Vref1, and an output terminal for outputting a result of the comparison between the voltage of the first electrode AE ​​and the first reference voltage Vref1 performed at the amplifier. For example, the output terminal of the amplifier of the main comparator MCP may output one of a low-level signal and a high-level signal. For example, the main comparator MCP may output a high-level signal when the voltage of the first electrode AE ​​is greater than the first reference voltage Vref1, and may output a low-level signal when the voltage of the first electrode AE ​​is less than the first reference voltage Vref1.

[0129] The first reference voltage Vref1 may be determined as a value corresponding to the number of groups GR1, GR2, ..., and GRN. For example, when the number of groups GR1, GR2, ..., and GRN is N, the first reference voltage Vref1 may be determined by using Equation 1 below.

[0130] Vref1 = N × VLD + V_VSS (Equation 1)

[0131] 1, the first reference voltage Vref1 may be a value calculated by adding the voltage V_VSS of the second power source VSS to a value obtained by multiplying the number N of groups GR1 , GR2 , . . . , and GRN by a reference voltage VLD applied to one light emitting element LD.

[0132] When the voltage of the first electrode AE ​​is lower than the first reference voltage Vref1, it can be determined that at least one of the groups GR1, GR2, ..., and GRN is short-circuited. Therefore, when the voltage of the first electrode AE ​​is lower than the first reference voltage Vref1, the blocking controller 2000 can block the driving current based on the output of the main comparator MCP. For example, when the main comparator MCP outputs a low-level signal, the blocking controller 2000 can block the driving current.

[0133] In one or more example embodiments, the first reference voltage Vref1 may be determined by using Equation 2 below.

[0134] Vref1 = N × VLD × p + V_VSS (Equation 2)

[0135] 2, the first reference voltage Vref1 may be a value calculated by adding the voltage V_VSS of the second power supply VSS to a value obtained by multiplying the number N of groups by the reference voltage VLD applied to one light emitting element LD and a ratio p (eg, a set ratio or a predetermined ratio p).

[0136] Unlike Equation 1, in Equation 2, by additionally multiplying by a ratio p (e.g., a set ratio or a predetermined ratio p), the driving current may not be blocked when the number of short-circuited groups among the groups GR1, GR2, ... and GRN is relatively small, and the driving current may be blocked when the number of short-circuited groups among the groups GR1, GR2, ... and GRN is relatively large.

[0137] At least one comparator may further include an auxiliary comparator CCP, which is electrically connected to the corresponding nodes N(1), N(2), ... and N(N-1) that connect the groups GR1, GR2, ... and GRN in series to compare the voltages of the nodes N(1), N(2), ... and N(N-1) with the second reference voltage Vref2.

[0138] In one or more example embodiments, each of the auxiliary comparators CCP may have a first input terminal for receiving a voltage of one of nodes N(1), N(2), ..., and N(N-1), a second input terminal for receiving a second reference voltage Vref2, and an output terminal for outputting a result of a comparison performed at the amplifier between the voltage received through the first input terminal and the second reference voltage Vref2. For example, the output terminal of the amplifier of each of the auxiliary comparators CCP may output a low-level signal or a high-level signal. For example, the auxiliary comparator CCP may output a high-level signal when the voltage received through the first input terminal is greater than the second reference voltage Vref2, and may output a low-level signal when the voltage received through the first input terminal is less than the second reference voltage Vref2.

[0139] The second reference voltage Vref2 can be determined based on a node electrically connected to the first input terminal of the auxiliary comparator CCP. For example, when the auxiliary comparator CCP is connected to the first node N(1) connecting the first group GR1 and the second group GR2 in series, the second reference voltage Vref2_1 received by the auxiliary comparator CCP can be determined by using the following equation 3.

[0140] Vref2_1 = Vref1 - VLD = (N-1) × VLD + V_VSS (Equation 3)

[0141] Referring to Equation 3, the second reference voltage Vref2_1 of the first node N(1) may be a value obtained by subtracting the reference voltage VLD applied to the one light emitting element LD from the first reference voltage Vref1 according to Equation 1. Assuming that the first reference voltage Vref1 is defined by Equation 1, the second reference voltage Vref2_1 of the first node N(1) may be expressed as a value obtained by adding the voltage V_VSS of the second power supply VSS to a value obtained by multiplying the reference voltage VLD applied to the one light emitting element LD by N-1 times.

[0142] In one or more example embodiments, when the auxiliary comparator CCP is connected to the second node N(2) for connecting the second group GR2 and the third group in series, the second reference voltage Vref2 of the second node N(2) may be a value obtained by subtracting twice the reference voltage VLD applied to the one light emitting element LD from the first reference voltage Vref1 according to Equation 1. Assuming that the first reference voltage Vref1 is defined by Equation 1, the second reference voltage Vref2 of the second node N(2) may be a value obtained by adding the voltage V_VSS of the second power supply VSS to a value obtained by multiplying the reference voltage VLD applied to the one light emitting element LD by N-2 times.

[0143] When the auxiliary comparator CCP is connected to the N-1th node N(N-1) for connecting the N-1th group and the N-group GRN in series, the second reference voltage Vref2_N-1 of the N-1th node N(N-1) may be a value obtained by subtracting N-1 times the reference voltage VLD applied to the one light emitting element LD from the first reference voltage Vref1 according to Equation 1. Assuming that the first reference voltage Vref1_ is defined by Equation 1, the second reference voltage Vref2_N-1 of the N-1th node N(N-1) may be a value obtained by adding the reference voltage VLD applied to the one light emitting element LD and the voltage V_VSS of the second power supply VSS.

[0144] When the detector 1000 includes the auxiliary comparator CCP and the main comparator MCP, the blocking controller 2000 may output the cutoff signal COS through the blocking control line COL based on the outputs of the main comparator MCP and the auxiliary comparator CCP. For example, when at least one of the outputs of the main comparator MCP and the auxiliary comparator CCP is a low-level signal, the blocking controller 2000 may output the cutoff signal COS through the blocking control line COL.

[0145] In one or more example embodiments, the blocking controller 2000 may include an OR operation circuit to output the cutoff signal COS by performing a logical OR operation on the outputs of the main comparator MCP and the auxiliary comparator CCP. Here, the OR operation circuit may be replaced with a NAND operation circuit that performs a logical NAND operation and outputs a signal according to an implementation method (for example, according to the type of the blocking transistor CTR described later or the output level of the comparator).

[0146] Figures 8A to 8C shows the Figure 7 A circuit diagram of a sub-pixel to which a blocking transistor of a cut-off signal is added.

[0147] As reference Figure 7 As described above, when the off signal COS is supplied through the blocking control line COL, the driving current of the sub-pixel SPX can be blocked. To this end, the sub-pixel SPX may further include a blocking transistor CTR that is turned off in response to the off signal COS through the blocking control line COL.

[0148] Reference Figure 8A , shows where a blocking transistor CTR is added to the Figure 5A The sub-pixel SPX shown in FIG. Figure 8B , shows where a blocking transistor CTR is added to the Figure 5B The sub-pixel SPX shown in FIG. Figure 8C , shows where a blocking transistor CTR is added to the Figure 5C The sub-pixel SPX shown in FIG.

[0149] The blocking transistor CTR may be electrically connected to the gate electrode of the driving transistor (eg, the first transistor T1) to turn off the driving transistor in response to a turn-off signal COS through the blocking control line COL. Figures 8A to 8CThe blocking transistor CTR may be included between the first node N1 and the gate electrode of the first transistor T1 and connected to the gate electrode of the blocking control line COL. For example, the blocking transistor CTR may be connected between the first node N1 and the gate electrode of the first transistor T1, and the gate electrode of the blocking transistor CTR may be connected to the blocking control line COL. In some embodiments, when a high-level cut-off signal COS is supplied via the blocking control line COL, the blocking transistor CTR may be turned off. Therefore, the gate-on level data signal may not be transmitted to the gate electrode of the first transistor T1, and the first transistor T1 may be turned off to interrupt the driving current.

[0150] According to another example embodiment, the blocking transistor CTR may be connected to a path where the driving current flows from the first power source VDD to the second power source VSS via the first transistor T1. Figures 8A to 8C The blocking transistor CTR may also be included between the second electrode (or second node N2) of the first transistor T1 and the first electrode AE ​​of the light emitting unit LSU and connected to the gate electrode of the blocking control line COL. For example, the blocking transistor CTR may be electrically connected between the second electrode (or second node N2) of the first transistor T1 and the first electrode AE ​​of the light emitting unit LSU, and the gate electrode of the blocking transistor CTR may be connected to the blocking control line COL. In addition, in some embodiments, when a high-level cut-off signal COS is supplied via the blocking control line COL, the blocking transistor CTR may be turned off. Therefore, because the path through which the driving current flows is blocked, the driving current can be blocked.

[0151] exist Figures 8A to 8C In the figure, assuming that the cutoff signal is a high-level gate-off signal, the blocking transistor CTR is shown as a p-type transistor. However, when the cutoff signal COS is a low-level gate-off signal, the blocking transistor CTR may be implemented as an n-type transistor. In one or more example embodiments, the blocking transistor CTR may be replaced by various types of switching elements that receive the cutoff signal COS and form an open circuit in response to the cutoff signal COS.

[0152] Figure 9 A flowchart illustrating a driving method of a display device according to one or more example embodiments of the present disclosure is shown.

[0153] Reference Figure 9 , a driving method of a display device may include: sensing at least one voltage of a light-emitting unit including a first electrode, a second electrode, and a plurality of light-emitting elements connected between the first electrode and the second electrode (S100); comparing the sensed at least one voltage with a reference voltage (S110); and generating a cutoff signal for blocking a driving current supplied to the light-emitting unit in response to a comparison result (S120).

[0154] For example, refer to Figure 9 , a driving method of a display device may include: sensing at least one voltage of a light-emitting unit having a first electrode, a second electrode, and a plurality of light-emitting elements connected between the first electrode and the second electrode (S100); comparing the sensed at least one voltage with a reference voltage (S110); and generating a cutoff signal for blocking a driving current supplied to the light-emitting unit in response to a comparison result (S120).

[0155] Each of the light emitting elements may be an inorganic light emitting diode having a nanometer-scale or micrometer-scale size.

[0156] The light emitting unit may include a plurality of groups, each group including a plurality of light emitting elements connected in parallel to each other, and the groups may be connected in series to each other between the first electrode and the second electrode.

[0157] The comparing step S110 may include comparing the voltage of the first electrode with a first reference voltage.

[0158] The comparing step S110 may further include comparing a voltage of a node connecting the plurality of groups in series with a second reference voltage.

[0159] In one or more example embodiments, the above-mentioned driving method of the display device may include referring to Figures 1 to 8C The operation of the display device DD is described below, and additional description will be omitted to prevent duplicate description.

[0160] Although the exemplary embodiments of the present disclosure have been particularly shown and described with reference to the accompanying drawings, the specific terms used herein are for the purpose of describing the present disclosure only and are not intended to define their meanings or to limit the scope of the disclosure set forth in the claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments of the present disclosure are possible. Therefore, the true technical protection scope of the present disclosure should be determined based on the technical spirit of the appended claims.

Claims

1. A display device, comprising: The sub-pixel includes: a light emitting unit including a first electrode, a second electrode, and a plurality of light emitting elements connected between the first electrode and the second electrode; and a driving transistor configured to supply a driving current to the light emitting unit; a detector electrically connected to the light emitting unit to detect a short circuit among the plurality of light emitting elements; and a blocking controller configured to control blocking of the driving current based on an output of the detector, wherein the light emitting unit includes a plurality of groups, each of the plurality of groups includes a plurality of light emitting elements connected in parallel to each other, and the plurality of groups are connected in series to each other between the first electrode and the second electrode, and The detector includes at least one comparator configured to compare a reference voltage with a voltage at at least one of the first electrodes or nodes connecting the plurality of groups in series.

2. The display device according to claim 1, wherein The at least one comparator includes a main comparator electrically connected to the first electrode to compare a voltage of the first electrode with a first reference voltage.

3. The display device according to claim 2, wherein: The first reference voltage is determined by using a value corresponding to the number of the plurality of groups.

4. The display device according to claim 2, wherein The first reference voltage is determined by multiplying the number of the plurality of groups by a set ratio.

5. The display device according to claim 2, wherein The main comparator includes an amplifier having a first input terminal for receiving the voltage of the first electrode, a second input terminal for receiving the first reference voltage, and an output terminal for outputting the result of the comparison between the voltage of the first electrode and the first reference voltage as one of a low level signal and a high level signal. The display device according to claim 2 , wherein: The blocking controller outputs a cutoff signal for blocking the driving current through a blocking control line based on an output of the main comparator when the voltage of the first electrode is lower than the first reference voltage.

7. The display device according to claim 6, wherein: The sub-pixel further includes a blocking transistor configured to be turned off in response to the turn-off signal.

8. The display device according to claim 7, wherein: The blocking transistor is electrically connected to a gate electrode of the driving transistor to turn off the driving transistor in response to the turn-off signal.

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