Display device

Abstract

The disclosure relates to a display device. The display device includes a display panel including: a plurality of pixels for displaying an image; a gate driver for driving the pixels; a first pad portion electrically connected to the pixels; and a second pad portion electrically connected to the gate driver. The gate driver includes: a plurality of stages for generating gate signals to be supplied to the pixels; k clock wirings for supplying k clock signals to the plurality of stages; and k clock bar wirings for supplying k clock bar signals to the plurality of stages (wherein k is 1 or a natural number greater than 1), and the second pad portion includes: k clock pads respectively electrically connected to the k clock wirings; and k clock bar pads respectively electrically connected to the k clock bar wirings. The k clock wirings and the k clock bar wirings are disposed in a first order, and the k clock pads and the k clock bar pads are disposed in a second order different from the first order.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0049436, filed on April 23, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present invention generally relate to display devices, and more specifically, to display devices having improved display quality with a gate driver embedded in a display panel. Background Technology

[0004] Typically, a display device includes a display panel, which includes multiple gate lines, multiple data lines, and multiple pixels connected to the gate lines and data lines. Gate drivers that provide gate signals to the gate lines and data drivers that output data signals to the data lines are connected to the display panel.

[0005] Gate drivers can be directly embedded in the display panel using thin-film technology. A gate driver consists of multiple stages and multiple wirings that provide gate drive signals to the stages.

[0006] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] The display device constructed according to the principles and embodiments of the present invention can improve display quality by eliminating horizontal line trailing.

[0008] For example, if clock wiring and clock bar wiring are set alternately, the amplitude of the ripple voltage generated in the reference voltage can be reduced, thereby reducing or preventing horizontal line trailing on the display panel screen and improving display quality.

[0009] Furthermore, when clock wiring and clock bar wiring are alternately arranged, the length difference between the bridge wiring electrically connected to the clock wiring to which the clock signal is applied and the bridge wiring electrically connected to the clock bar wiring to which the clock signal is applied decreases. When the length difference between the bridge wirings decreases, the difference between the parasitic capacitances formed between the bridge wirings and the reference electrode decreases, and therefore, the amplitude of the ripple voltage generated in the reference voltage can be reduced.

[0010] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0011] According to an aspect of the present application, a display device includes a display panel including: a plurality of pixels for displaying an image; a gate driver for driving the pixels; a first pad portion electrically connected to the pixels; and a second pad portion electrically connected to the gate driver. The gate driver includes: a plurality of stages for generating gate signals to be supplied to the pixels; k clock wirings for supplying k clock signals to the plurality of stages; and k clock bar wirings for supplying k clock bar signals to the plurality of stages (where k is 1 or a natural number greater than 1), and the second pad portion includes: k clock pads electrically connected to the k clock wirings, respectively; and k clock bar pads electrically connected to the k clock bar wirings, respectively. The k clock wirings and the k clock bar wirings are disposed in a first order, and the k clock pads and the k clock bar pads are disposed in a second order different from the first order.

[0012] A first clock wiring for receiving a first clock signal among the k clock wirings can be disposed adjacent to a first clock bar wiring for receiving a first clock bar signal among the k clock bar wirings, the first clock bar signal having a phase opposite to a phase of the first clock signal.

[0013] The first clock bar wiring can be disposed between the first clock wiring and a second clock wiring for receiving a second clock signal delayed from the first clock signal among the k clock wirings.

[0014] The display panel can further include an intermediate wiring portion electrically connecting the second pad portion and the gate driver. The intermediate wiring portion can include: k first intermediate wirings for electrically connecting the k clock pads to the k clock wirings, respectively; and k second intermediate wirings for electrically connecting the k clock bar pads to the k clock bar wirings, respectively.

[0015] At least one of the k first intermediate wirings can cross at least one of the k second intermediate wirings.

[0016] The k first intermediate wirings can be disposed on a first layer, and each of the k second intermediate wirings can include: a lower wiring disposed on the first layer; and an upper wiring disposed on a second layer different from the first layer.

[0017] At least one of the k first intermediate wirings can cross an upper wiring of at least one of the k second intermediate wirings.

[0018] The intermediate wiring portion can further include a contact portion to which the lower wiring and the upper wiring are connected.

[0019] The lower wiring and the upper wiring can be directly connected in the contact portion.

[0020] The contact portion can include a bridge electrode connecting the lower wiring and the upper wiring.

[0021] The gate driver can further include k first bridge wirings for connecting the k clock wirings to the plurality of stages, and k second bridge wirings for connecting the k clock wirings to the plurality of stages.

[0022] A first clock wiring of the k clock wirings for receiving a first clock signal can be disposed adjacent to a first clock strip wiring of the k clock strip wirings for receiving a first clock strip signal having a phase opposite to a phase of the first clock signal.

[0023] The first clock strip wiring can be disposed between the first clock wiring and a second clock wiring of the k clock wirings for receiving a second clock signal delayed from the first clock signal.

[0024] A first bridge wiring of the k first bridge wirings connected to the first clock wiring can be longer than a second bridge wiring of the k second bridge wirings connected to the first clock strip wiring, and a first bridge wiring of the k first bridge wirings connected to the second clock wiring can be shorter than the second bridge wiring connected to the first clock strip wiring.

[0025] According to another aspect of the present disclosure, a display device includes a display panel including a plurality of pixels for displaying an image, a gate driver for driving the pixels, a first pad portion electrically connected to the pixels, and a second pad portion electrically connected to the gate driver. The gate driver includes a plurality of stages for generating a gate signal to be applied to the pixels, k clock wirings for applying k clock signals to the plurality of stages, and k clock strip wirings for applying k clock strip signals to the plurality of stages (where k is 1 or a natural number greater than 1), and the second pad portion includes k clock pads respectively electrically connected to the k clock wirings, and k clock strip pads respectively electrically connected to the k clock strip wirings. A first clock wiring of the k clock wirings for receiving a first clock signal is disposed adjacent to a first clock strip wiring of the k clock strip wirings for receiving a first clock strip signal having a phase opposite to a phase of the first clock signal, and a first clock pad of the k clock pads electrically connected to the first clock wiring is disposed adjacent to a second clock pad of the k clock pads for receiving a second clock signal delayed from the first clock signal.

[0026] The display device can further include a flexible film coupled to a side of the display panel. The flexible film is electrically connected to the first pad portion and the second pad portion.

[0027] The display panel can further include an intermediate wiring portion connecting the second pad portion and the gate driver. The intermediate wiring portion can include: k first intermediate wirings for electrically connecting the k clock pads to the k clock wirings, respectively; and k second intermediate wirings for electrically connecting the k clock strip pads to the k clock strip wirings, respectively.

[0028] At least one of the k first intermediate wirings can cross at least one of the k second intermediate wirings.

[0029] The k first intermediate wirings can be disposed on a first layer, and each of the k second intermediate wirings can include: a lower wiring disposed on the first layer; and an upper wiring disposed on a second layer different from the first layer.

[0030] At least one of the k first intermediate wirings can cross an upper wiring of at least one of the k second intermediate wirings.

[0031] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application.

[0033] FIG. 1 is a plan view of an embodiment of a display device constructed in accordance with the principles of the application.

[0034] FIG. 2A is a plan view of a display panel shown in FIG. 1

[0035] FIG. 2B is a cross-sectional view taken along the line BB-BB' of FIG. 2A

[0036] FIG. 3A is a block diagram of a first gate driver shown in FIG. 1

[0037] FIG. 3B is a waveform diagram of first to fourth clock signals and first to fourth clock strip signals applied to the first gate driver of FIG. 3A

[0038] FIG. 4 is a circuit diagram of an embodiment of a first stage of FIG. 3A

[0039] FIG. 5 is a circuit diagram of an embodiment of a first stage of FIG. 2A ​​​​​An enlarged plan view of the first embodiment of part AA shown.

[0040] FIG. 6A yes FIG. 5 A magnified view of part A1.

[0041] FIG. 6B It is along FIG. 6A The cross-sectional view taken from line I-I'.

[0042] FIG. 6C yes FIG. 5 A magnified plan view of part A2.

[0043] FIG. 6D It is along FIG. 6C The cross-sectional view taken from line II-II'.

[0044] FIG. 7 yes FIG. 2A An enlarged plan view of the second embodiment of part AA shown.

[0045] FIG. 8A yes FIG. 7 A partial enlarged plan view of A3.

[0046] FIG. 8B It is along FIG. 8A The cross-sectional view taken from line III-III'.

[0047] FIG. 9 yes FIG. 2A An enlarged plan view of the third embodiment of part AA shown.

[0048] FIG. 10A yes FIG. 9 Enlarged plan view of part A4 of the embodiment.

[0049] FIG. 10B It is along FIG. 10A A cross-sectional view taken from line IV-IV'.

[0050] FIG. 10C It is along FIG. 10A A cross-sectional view taken from line V-V'.

[0051] FIG. 11A yes FIG. 9 An enlarged plan view of another embodiment of part A4.

[0052] FIG. 11B It is along FIG. 11A The cross-sectional view taken from line VI-VI'.

[0053] FIG. 11C It is along FIG. 11A The cross-sectional view taken from line VII-VII'.

[0054] FIG. 12 is FIG. 2A enlarged plan view of a fourth embodiment of the portion AA shown in FIG. 15B. DETAILED DESCRIPTION

[0055] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of an apparatus or method that employs one or more of the inventive concepts disclosed herein. However, it will be apparent to one skilled in the art that various embodiments can be practiced without these specific details or in an implementation that utilizes one or more equivalent settings. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various example embodiments. Further, various embodiments can differ from one another substantially but not necessarily in every way. For example, a particular shape, configuration, and / or property of an embodiment can be used or implemented in another embodiment without departing from the inventive concepts.

[0056] Unless otherwise indicated, the illustrated embodiments are to be understood as providing examples of the various features of the inventive concepts that can be implemented in practice. Thus, unless otherwise indicated, the features, components, modules, layers, films, panels, regions, and / or aspects of each embodiment (hereinafter referred to as "elements") can be additionally combined, separated, interchanged, and / or rearranged, and / or expressed by other terminology in an alternative embodiment.

[0057] The use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, of the elements of the drawings. As the use of cross-hatching and / or shading is not meant to be a literal property of the elements, unless otherwise indicated, the presence or absence of cross-hatching and / or shading is not intended to convey or dictate any preference or requirement for particular materials, material properties, dimensions, proportions, commonality of elements between illustrations, and / or any other characteristic, attribute, property, etc., of the elements. Further, in the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. When embodiments can be practiced differently, a particular sequence of processes can be performed other than as described. For example, two consecutively described processes can be performed at substantially the same time or in the reverse order as described. Moreover, the same reference numerals are used to denote like elements throughout the specification and figures.

[0058] When an element such as a layer, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. In this specification, the term "connected" can mean physically, electrically, and / or fluidly connected, with or without intervening elements. Further, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system such as the x, y, and z axes, and can be interpreted in a broad sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any one of X, Y, Z, or an arbitrary combination of two or more of X, Y, and Z (for example, such as XYZ, XYY, YZ, and ZZ). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0059] Although the terms "first", "second", etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0060] Spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper", "on", "over", "side", and "sides" (as in "sidewall") can be used herein for descriptive purposes, and, thereby, to describe one element's relationship to another element(s) as depicted in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. Additionally, devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, spatially relative descriptors used herein can be interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms "including," "containing," or "comprising" in this specification, and in the claims that follow, means "including, but not limited to," and not "ending with" or "consisting of," unless otherwise defined in the specification. It will be further understood that the terms "substantially," "approximately," and other like terms, as used herein, are used in a permissible sense of approximation, and thus are used to account for inherent variations and / or imperfections that can occur in measurements, calculations, and / or other provided values that would be recognized by those of ordinary skill in the art.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0063] FIG. 1 is a plan view of an embodiment of a display device constructed in accordance with the principles of the present application. FIG. 2A is FIG. 1 is a plan view of a display panel shown in FIG. 2B is a cross-sectional view taken along the line FIG. 2A BB-BB' of

[0064] Referring to FIG. 1 and FIG. 2A , a display device DD includes a display panel DP for displaying an image and a panel driver for driving the display panel DP. The panel driver can include a gate driver GDC and a data driver DDC.

[0065] The display panel DP includes a display area DA for displaying an image and a non-display area NDA adjacent to the display area DA. The display area DA is an area in which an image is substantially displayed, and the non-display area NDA is a bezel area in which an image is not displayed. Although FIG. 1 shows a structure in which the non-display area NDA is disposed to surround the display area DA, embodiments are not limited thereto. The non-display area NDA can be disposed only at at least one side of the display area DA.

[0066] The display panel DP includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX11 to PXnm. The plurality of gate lines GL1 to GLn extend in a first direction DR1 and are arranged in parallel to each other in a second direction DR2 intersecting the first direction DR1. The second direction DR2 can be orthogonal to the first direction DR1. The plurality of data lines DL1 to DLm can be arranged in parallel in the first direction DR1 and can extend in the second direction DR2.

[0067] The plurality of pixels PX11 to PXnm can be provided in the display area DA in the first direction DR1 and the second direction DR2. The plurality of pixels PX11 to PXnm can be provided in a matrix form. Each of the plurality of pixels PX11 to PXnm can be electrically connected to one of the plurality of gate lines GL1 to GLn and one of the plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm is turned on by a gate signal applied from a corresponding one of the gate lines GL1 to GLn and receives a data voltage from a corresponding one of the data lines DL1 to DLm to display an image of a desired gray scale.

[0068] The gate driver GDC sequentially outputs gate signals to the gate lines GL1 to GLn. Accordingly, the plurality of pixels PX11 to PXnm can be sequentially scanned row by row by the gate signals. The gate driver GDC can include a first gate driver GDC1 and a second gate driver GDC2. The first gate driver GDC1 can be electrically connected to one end of the gate lines GL1 to GLn, and the second gate driver GDC2 can be electrically connected to the other end of the gate lines GL1 to GLn. Each of the first gate driver GDC1 and the second gate driver GDC2 can include a shift register sequentially outputting gate signals. The first gate driver GDC1 and the second gate driver GDC2 can operate simultaneously to output gate signals to the same gate line at the same time. Accordingly, each of the gate lines GL1 to GLn can receive gate signals from the first gate driver GDC1 and the second gate driver GDC2 through both ends of the gate line.

[0069] FIG. 1 and FIG. 2A A structure in which the two gate drivers GDC1 and GDC2 are electrically connected to both ends of the gate lines GL1 to GLn is shown, but embodiments are not limited thereto. That is, a structure in which only one of the first gate driver GDC1 and the second gate driver GDC2 is electrically connected to the gate lines GL1 to GLn can be employed.

[0070] The first gate driver GDC1 and the second gate driver GDC2 can be embedded in the display panel DP. In other words, the first gate driver GDC1 and the second gate driver GDC2 can be formed in a non-display area NDA of the display panel DP by a thin film process, in which the pixels PX11 to PXnm are formed in a display area DA of the display panel DP.

[0071] The data driver DDC converts an image signal into a data voltage, and applies the data voltage to the data lines DL1 to DLm of the display panel DP. The data driver DDC can include a plurality of data driving chips DIC1 to DIC4. Each of the plurality of data driving chips DIC1 to DIC4 is electrically connected to a corresponding data line among the data lines DL1 to DLm. Although four data driving chips DIC1 to DIC4 are shown in FIG. 1 The number of the data driving chips DIC1 to DIC4 is not particularly limited and can be variously changed.

[0072] The display apparatus DD can further include a plurality of flexible films CF1 to CF4 and a printed circuit board PCB. The plurality of flexible films CF1 to CF4 can be provided between the display panel DP and the printed circuit board PCB, and can electrically connect the display panel DP and the printed circuit board PCB. One end of each of the flexible films CF1 to CF4 is coupled to the display panel DP, and the other end of each of the flexible films CF1 to CF4 is coupled to the printed circuit board PCB.

[0073] In FIG. 1 a structure in which the data driving chips DIC1 to DIC4 are mounted on the flexible films CF1 to CF4, respectively, is shown, but the embodiment is not limited thereto. That is, the data driving chips DIC1 to DIC4 can be directly mounted on the display panel DP in a chip on glass (COG) method.

[0074] Various circuits for generating various control signals and power signals required to drive the display panel DP and the panel driver can be provided on the printed circuit board PCB.

[0075] Referring to FIG. 2A , the display panel DP can further include a first pad portion PD1 and a second pad portion PD2. The first pad portion PD1 and the second pad portion PD2 are disposed in the non-display area NDA. The first pad portion PD1 can include a plurality of data pads electrically connected to the data lines DL1 to DLm connected with the pixels PX11 to PXnm. The first pad portion PD1 can be coupled to the flexible films CF1 to CF4 to receive the data voltage from the data driving chips DIC1 to DIC4 mounted on the flexible films CF1 to CF4.

[0076] The second pad portion PD2 includes a first drive pad portion PD2_1 electrically connected to the first gate driver GDC1 and a second drive pad portion PD2_2 electrically connected to the second gate driver GDC2. The first drive pad portion PD2_1 includes a plurality of first drive pads for providing a first gate driving signal to the first gate driver GDC1, and the second drive pad portion PD2_2 includes a plurality of second drive pads for providing a second gate driving signal to the second gate driver GDC2.

[0077] The second pad portion PD2 can be connected to some of the flexible films CF1 to CF4. The first drive pad portion PD2_1 is connected to the first flexible film CF1 among the flexible films CF1 to CF4, and the second drive pad portion PD2_2 is connected to the fourth flexible film CF4 among the flexible films CF1 to CF4. The first gate driving signal can be a signal output from a first data driving chip DIC1 mounted on the first flexible film CF1, or a signal provided from a printed circuit board PCB. The second gate driving signal can be a signal output from a fourth data driving chip DIC4 mounted on the fourth flexible film CF4, or a signal provided from the printed circuit board PCB.

[0078] The display panel DP further includes an intermediate wiring portion CLP electrically connecting the second pad portion PD2 to the gate drivers GDC. The intermediate wiring portion CLP can include a first intermediate wiring portion CLP1 and a second intermediate wiring portion CLP2. The first intermediate wiring portion CLP1 electrically connects the first drive pad portion PD2_1 to the first gate driver GDC1, and the second intermediate wiring portion CLP2 electrically connects the second drive pad portion PD2_2 to the second gate driver GDC2.

[0079] Reference will be made later to FIG. 5 to FIG. 12 The second pad portion PD2 and the intermediate wiring portion CLP will be described in detail.

[0080] A backlight unit for providing light to the display panel DP can be further included in the display apparatus DD. In the case where the display panel DP is a liquid crystal display panel that does not emit light by itself, the backlight unit can be disposed on a rear surface of the liquid crystal display panel to provide light to the liquid crystal display panel. Each of the pixels PX11 to PXnm can display an image having a desired gray scale by adjusting a degree of transmission of light provided from the backlight unit.

[0081] Reference will be made later to FIG. 2A and FIG. 2BThe display panel DP includes a first display substrate FS, a second display substrate SS, and a liquid crystal layer LC. The first display substrate FS includes a first base substrate BS1 and a pixel layer PP disposed on the first base substrate BS1. The pixel layer PP may include thin-film transistors constituting each of pixels PX11 to PXnm, pixel electrodes, and multiple insulating layers. The pixel layer PP may be provided corresponding to the display area DA of the display panel DP. A first gate driver GDC1 and a second gate driver GDC2 are disposed on the first base substrate BS1 corresponding to the non-display area NDA.

[0082] The second display substrate SS includes a second base substrate BS2 and a reference electrode RE. The second base substrate BS2 is disposed facing the first base substrate BS1. A liquid crystal layer LC is disposed between the first display substrate FS and the second display substrate SS. The reference electrode RE is disposed on the second base substrate BS2 facing the pixel electrode, and the liquid crystal layer LC is disposed between the first display substrate FS and the second display substrate SS. For example, the liquid crystal layer LC is disposed between the reference electrode RE and the pixel layer PP. A reference voltage is provided to the reference electrode RE. The reference electrode RE can be disposed on the entire rear surface of the second base substrate BS2. Therefore, the reference electrode RE can face the first gate driver GDC1 and the second gate driver GDC2 in the non-display area NDA. The second display substrate SS may further include a color filter layer and a black matrix layer.

[0083] The display panel DP further includes a sealant SLT disposed in the non-display area NDA to connect the first display substrate FS and the second display substrate SS. The space between the first display substrate FS and the second display substrate SS can be sealed by the sealant SLT. The first gate driver GDC1 and the second gate driver GDC2 can overlap with the sealant SLT.

[0084] FIG. 3A yes FIG. 1 The block diagram of the first gate driver shown is as follows, and FIG. 3B Is applied to FIG. 3A Waveforms of the first to fourth clock signals and the first to fourth clock bar signals of the first gate driver. FIG. 4 yes FIG. 3A The circuit diagram of the first-level embodiment.

[0085] Despite FIG. 3A A block diagram of the first gate driver GDC1 is shown, but the second gate driver GDC2 has a configuration similar to that of the first gate driver GDC1. Therefore, refer to... FIG. 3A The configuration of the first gate driver GDC1 is described, and the configuration of the second gate driver GDC2 will be omitted to avoid redundancy.

[0086] ReferenceFIG. 3A The first gate driver GDC1 can include a plurality of stages connected in dependence on each other. The stages can be electrically connected to the gate lines GL1 to GLn (shown in FIG. 1), respectively. FIG. 2A The plurality of stages can output gate signals to the gate lines GL1 to GLn, respectively.

[0087] Hereinafter, FIG. 3A The first stage SRC1 to the eighth stage SRC8 among the plurality of stages are exemplarily shown in FIG. 1. Although the first stage SRC1 to the eighth stage SRC8 are shown, further stages can be provided in substantially the same configuration.

[0088] Each of the first stage SRC1 to the eighth stage SRC8 (hereinafter, referred to as stages SRC1 to SRC8) includes an input terminal IN, a control terminal CT, a clock terminal CK, a first voltage terminal V1, a second voltage terminal V2, a reset terminal SP, an output terminal OUT, and a carry terminal CR.

[0089] The carry terminal CR of each of the stages SRC1 to SRC8 is electrically connected to the input terminal IN of the next stage. The i-th stage can output an i-th carry signal through the carry terminal CR. Here, i is defined as a natural number. The input terminal IN of the first stage SRC1 receives a vertical start signal that starts driving of the first gate driver GDC1 through a start signal line STVL, instead of a carry signal of a previous stage. The input terminal IN of each of the stages SRC2 to SRC8 after the first stage SRC1 receives a carry signal of the previous stage. The input terminal IN of the i-th stage is electrically connected to the carry terminal CR of the (i-1)-th stage. For example, the input terminal IN of the second stage SRC2 receives a carry signal of the first stage SRC1, and the input terminal IN of the third stage SRC3 receives a carry signal of the second stage SRC2.

[0090] This configuration is merely an example, and the input terminal IN of the i-th stage can be electrically connected to a carry terminal of the previous stage, for example, a carry terminal of the (i-1)-th stage, the (i-2)-th stage, or the (i-3)-th stage, etc.

[0091] The control terminal CT of the i-th stage is electrically connected to the carry terminal CR of the (i+1)-th stage, and receives a carry signal of the (i+1)-th stage. For example, the control terminal CT of the first stage SRC1 receives a carry signal of the second stage SRC2, and the control terminal CT of the second stage SRC2 receives a carry signal of the third stage SRC3.

[0092] The clock terminal CK of the i-th stage receives a corresponding signal among a plurality of clock signals and a plurality of clock bar signals through a plurality of clock wirings (e.g., first to fourth clock wirings CKL1 to CKL4) and a plurality of clock bar wirings (e.g., first to fourth clock bar wirings CKBL1 to CKBL4). The plurality of clock signals can be first to fourth clock signals CK1 to CK4, and the plurality of clock bar signals can be first to fourth clock bar signals CKB1 to CKB4. However, the number of the plurality of clock signals CK1 to CK4 and the number of the plurality of clock bar signals CKB1 to CKB4 are not limited thereto and can have various values.

[0093] In detail, referring to FIG. 3B , the first period P1 can be a period in which the level of each of the first to fourth clock signals CK1 to CK4 becomes a high voltage, and the second period P2 can be a period in which the level of each of the first to fourth clock signals CK1 to CK4 becomes a low voltage. Also, the first period P1 can be a period in which the level of each of the first to fourth clock bar signals CKB1 to CKB4 becomes a low voltage, and the second period P2 can be a period in which the level of each of the first to fourth clock bar signals CKB1 to CKB4 becomes a high voltage. That is, the first clock signal CK1 and the first clock bar signal CKB1 have a phase difference of about 180 degrees, and the second clock signal CK2 and the second clock bar signal CKB2 have a phase difference of about 180 degrees. The third clock signal CK3 and the third clock bar signal CKB3 have a phase difference of about 180 degrees, and the fourth clock signal CK4 and the fourth clock bar signal CKB4 have a phase difference of about 180 degrees. The periods in which the first to fourth clock signals CK1 to CK4 are at a high voltage, respectively, can overlap each other, and the periods in which the first to fourth clock bar signals CKB1 to CKB4 are at a high voltage, respectively, can overlap each other.

[0094] According to an embodiment, the first to fourth clock signals CK1 to CK4 are respectively supplied to clock terminals CK of the first to fourth stages SRC1 to SRC4. Accordingly, the first to fourth stages SRC1 to SRC4 sequentially output the first to fourth gate signals to their output terminals OUT in response to the first to fourth clock signals CK1 to CK4. The output terminals OUT of the first to fourth stages SRC1 to SRC4 are respectively connected to the first to fourth gate lines GL1 to GL4. Thereafter, the first to fourth clock bar signals CKB1 to CKB4 are respectively supplied to clock terminals CK of the fifth to eighth stages SRC5 to SRC8. Accordingly, the fifth to eighth stages SRC5 to SRC8 sequentially output the fifth to eighth gate signals to their output terminals OUT in response to the first to fourth clock bar signals CKB1 to CKB4. The output terminals OUT of the fifth to eighth stages SRC5 to SRC8 are respectively connected to the fifth to eighth gate lines GL5 to GL8.

[0095] The above-described operation method can be repeatedly performed in units of eight stages. When the number of clock signals is k and the number of clock bar signals is k, the operation can be repeatedly performed in units of 2k stages. Here, k can be a natural number of 1 or more.

[0096] The first gate driver GDC1 includes a plurality of clock lines and a plurality of clock bar lines. A plurality of clock signals are respectively supplied to corresponding stages among a plurality of stages through the plurality of clock lines. The plurality of clock lines can be four clock lines (hereinafter referred to as first to fourth clock lines CKL1 to CKL4), and the plurality of clock bar lines can be four clock bar lines (hereinafter referred to as first to fourth clock bar lines CKBL1 to CKBL4). First to fourth clock signals CK1 to CK4 are respectively supplied to first to fourth stages SRC1 to SRC4 through the first to fourth clock lines CKL1 to CKL4. First to fourth clock bar signals CKB1 to CKB4 are respectively supplied to fifth to eighth stages SRC5 to SRC8 through the first to fourth clock bar lines CKBL1 to CKBL4. When the number of clock signals is k and the number of clock bar signals is k, the first gate driver GDC1 includes k clock lines and k clock bar lines.

[0097] A first discharge voltage is supplied to a first voltage terminal V1 of each of the stages SRC1 to SRC8 through a first voltage line VL1, and a second discharge voltage is supplied to a second voltage terminal V2 of each of the stages SRC1 to SRC8 through a second voltage line VL2. For example, the first and second discharge voltages can be supplied at a level lower than a ground voltage.

[0098] For example, the level of the first discharge voltage can be higher than the level of the second discharge voltage. The first discharge voltage can be set to about -10V to about -5V, and the second discharge voltage can be set to about -16V to about -10V. As another example, the first discharge voltage and the second discharge voltage can have substantially the same voltage level.

[0099] The first gate driver GDC1 further includes a first voltage line VL1 and a second voltage line VL2. The first discharge voltage is supplied to the stages SRC1 to SRC8 through the first voltage line VL1, and the second discharge voltage is supplied to the stages SRC1 to SRC8 through the second voltage line VL2. The number of the discharge voltages supplied to each of the stages SRC1 to SRC8 is not limited thereto. That is, only one of the first discharge voltage and the second discharge voltage can be supplied to each of the stages SRC1 to SRC8, or a third discharge voltage can be further supplied in addition to the first discharge voltage and the second discharge voltage.

[0100] A reset signal can be provided to a reset terminal SP of each of the stages SRC1 to SRC8. The reset signal can be a vertical start signal. The vertical start signal is provided to the reset terminals SP of the stages SRC1 to SRC8 through a start signal line STVL. For example, in one frame period, the vertical start signal has a low voltage in a period other than a period in which the first gate line GL1 operates. Accordingly, the stages SRC1 to SRC8 can be reset in a period in which the first stage SRC1 operates. However, the reset period of the stages SRC1 to SRC8 is not limited thereto. In other words, when a separate reset signal different from the vertical start signal is provided to the reset terminal SP, the reset period of the stages SRC1 to SRC8 can be changed.

[0101] Referring to FIG. 4 , the first stage SRC1 includes a first output unit 111, a second output unit 112, a first discharge unit 113, a second discharge unit 114, a control unit 115, a switching unit 116, and a reset unit 117. Although the circuit configuration of the first stage SRC1 among the plurality of stages is shown in FIG. 4 , the other stages also have the same circuit configuration as the first stage SRC1.

[0102] The first output unit 111 is electrically connected to the output terminal OUT and outputs the first gate signal through the output terminal OUT. The second output unit 112 is electrically connected to the carry terminal CR and outputs the first carry signal through the carry terminal CR. The first gate signal is applied to the first gate line GL1, and the first carry signal is provided to the next stage (i.e., the second stage SRC2). The first output unit 111 can include a first output transistor T1 electrically connected to the clock terminal CK, the first node NQ, and the output terminal OUT. The second output unit 112 can include a second output transistor T13 electrically connected to the clock terminal CK, the first node NQ, and the carry terminal CR.

[0103] The control unit 115 controls the operations of the first output unit 111 and the second output unit 112. The control unit 115 turns on the first output unit 111 and the second output unit 112 in response to an input signal provided to the input terminal IN, and turns off the first output unit 111 and the second output unit 112 in response to a control signal provided to the control terminal CT. Here, the input signal can be a carry signal or a vertical start signal provided from a previous stage. The control signal can be a carry signal provided from a next stage. The control unit 115 includes a first control transistor T4 and a second control transistor T6. The first control transistor T4 is electrically connected to the input terminal IN and the first node NQ, and the second control transistor T6 is electrically connected to the control terminal CT, the first node NQ, and the second voltage terminal V2. The second control transistor T6 can lower the potential of the first node NQ to the second discharge voltage in response to the control signal.

[0104] The first discharge unit 113 lowers the potential of the output terminal OUT to the first discharge voltage, and the second discharge unit 114 lowers the potential of the carry terminal CR to the second discharge voltage. The first discharge unit 113 includes a first discharge transistor T2 and a second discharge transistor T3. The first discharge transistor T2 is electrically connected to the control terminal CT, the output terminal OUT, and the first voltage terminal V1, and the second discharge transistor T3 is electrically connected to the second node NA, the output terminal OUT, and the first voltage terminal V1. The second discharge unit 114 includes a third discharge transistor T12 electrically connected to the second node NA, the carry terminal CR, and the second voltage terminal V2.

[0105] The switching unit 116 controls the operations of the first discharge unit 113 and the second discharge unit 114. The switching unit 116 provides a switching signal for turning on and off the first discharge unit 113 and the second discharge unit 114 to the second node NA. The switching unit 116 includes first to fourth switching transistors T10, T7, T9, and T8.

[0106] The reset unit 117 can reset the voltage level of the first node NQ to the second discharge voltage. The reset unit 117 can include a reset transistor T5 electrically connected to the reset terminal SP, the first node NQ, and the second voltage terminal V2. The signal applied to the reset terminal SP can be a vertical start signal.

[0107] The circuit configuration of each of the plurality of stages is not limited to FIG. 4 the circuit configuration illustrated in

[0108] FIG. 5 is FIG. 2A an enlarged plan view of the first embodiment of the portion AA illustrated in FIG. 6A is FIG. 5 an enlarged view of the portion A1 of FIG. 6B is a cross-sectional view taken along the line I-I' of FIG. 6A FIG. 6C is FIG. 5 an enlarged plan view of the portion A2 of FIG. 6D is a cross-sectional view taken along the line II-II' of FIG. 6C

[0109] Referring to FIG. 2A , FIG. 5 and FIG. 6A , the first gate driver GDC1 includes a plurality of stages and a plurality of signal wirings disposed adjacent to the plurality of stages. The plurality of signal wirings can include a plurality of clock wirings, a plurality of clock bar wirings, a first voltage wiring VL1 and a second voltage wiring VL2, and a start signal wiring STVL. The plurality of clock wirings can be a first clock wiring CKL1 to a fourth clock wiring CKL4, and the plurality of clock bar wirings can be a first clock bar wiring CKBL1 to a fourth clock bar wiring CKBL4.

[0110] As illustrated in FIG. 5 , the first clock wiring CKL1 and the first clock bar wiring CKBL1 are disposed adjacent to each other, and the second clock wiring CKL2 and the second clock bar wiring CKBL2 are disposed adjacent to each other. In addition, the third clock wiring CKL3 and the third clock bar wiring CKBL3 are disposed adjacent to each other, and the fourth clock wiring CKL4 and the fourth clock bar wiring CKBL4 are disposed adjacent to each other. The plurality of clock wirings and the plurality of clock bar wirings can be disposed in a first order. Here, the first order refers to an order in which the first clock wiring CKL1, the first clock bar wiring CKBL1, the second clock wiring CKL2, the second clock bar wiring CKBL2, the third clock wiring CKL3, the third clock bar wiring CKBL3, the fourth clock wiring CKL4, and the fourth clock bar wiring CKBL4 are sequentially disposed. When k clock wirings and k clock bar wirings are provided, the first order can be an order in which the k clock wirings and the k clock bar wirings are alternately disposed.​​

[0111] The first clock wiring CKL1 to the fourth clock wiring CKL4 and the first clock strip wiring CKBL1 to the fourth clock strip wiring CKBL4 can be disposed on the same layer and can be formed of the same material. The first clock wiring CKL1 to the fourth clock wiring CKL4 and the first clock strip wiring CKBL1 to the fourth clock strip wiring CKBL4 can be formed of a first metallic material.

[0112] Multiple signal cables pass through FIG. 2A The first drive pad portion PD2_1 shown receives a first gate drive signal from an external source. The first drive pad portion PD2_1 may include multiple clock pads and multiple clock strip pads. FIG. 5 The first voltage pad VP1 and the second voltage pad VP2 shown are... FIG. 5 The start signal pad STP is shown in the diagram. For example, refer to... FIG. 5 Multiple clock pads can be the first clock pad CKP1 to the fourth clock pad CKP4, and multiple clock strip pads can be the first clock strip pad CKBP1 to the fourth clock strip pad CKBP4.

[0113] like FIG. 5 As shown, the first clock pads CKP1 to the fourth clock pads CKP4 are arranged adjacent to each other. The first clock pads CKP1 and the second clock pads CKP2 are adjacent to each other, the second clock pads CKP2 and the third clock pads CKP3 are adjacent to each other, and the third clock pads CKP3 and the fourth clock pads CKP4 are adjacent to each other. The first clock strip pads CKBP1 to the fourth clock strip pads CKBP4 are arranged adjacent to each other. The first clock strip pads CKBP1 and the second clock strip pads CKBP2 are adjacent to each other, the second clock strip pads CKBP2 and the third clock strip pads CKBP3 are adjacent to each other, and the third clock strip pads CKBP3 and the fourth clock strip pads CKBP4 are adjacent to each other. That is, multiple clock pads and multiple clock strip pads can be arranged in a second order different from the first order. Here, the second sequence refers to the order in which the first clock pad CKP1, the second clock pad CKP2, the third clock pad CKP3, the fourth clock pad CKP4, the first clock strip pad CKBP1, the second clock strip pad CKBP2, the third clock strip pad CKBP3, and the fourth clock strip pad CKBP4 are set. When k clock pads and k clock strip pads are provided, the second sequence can be the order in which the k clock pads are set first, and then the k clock strip pads are set. The k clock pads and k clock strip pads do not need to be set alternately.

[0114] The first to fourth clock pads CKP1 to CKP4 are provided on the first layer, and the first to fourth clock bar pads CKBP1 to CKBP4 are provided on the second layer. Here, the first layer can be the first base substrate BS1 illustrated in FIG. 6B , and the second layer can be the gate insulating layer GIL illustrated in FIG. 6B . The first to fourth clock pads CKP1 to CKP4 can be formed of a first metal material, and the first to fourth clock bar pads CKBP1 to CKBP4 can be formed of a second metal material. The first metal material and the second metal material can be the same material or different materials from each other.

[0115] Referring to FIG. 2A and FIG. 5 , the first intermediate wiring portion CLP1 is provided between the first drive pad portion PD2_1 and the first gate driver GDC1 and electrically connects the first drive pad portion PD2_1 to a signal wiring of the first gate driver GDC1. Specifically, as illustrated in FIG. 5 , the first intermediate wiring portion CLP1 can include a plurality of clock intermediate wirings, a plurality of clock bar intermediate wirings, a first voltage intermediate wiring VCL1 and a second voltage intermediate wiring VCL2, and a start signal intermediate wiring STCL. Referring to FIG. 6A , the plurality of clock intermediate wirings can be first to fourth clock intermediate wirings CL1 to CL4, and the plurality of clock bar intermediate wirings can be first to fourth clock bar intermediate wirings CBL1 to CBL4.

[0116] The first to fourth clock intermediate wirings CL1 to CL4 electrically connect the first to fourth clock wirings CKL1 to CKL4 with the first to fourth clock pads CKP1 to CKP4. The first to fourth clock intermediate wirings CL1 to CL4 are provided on the same layer as a layer on which the first to fourth clock wirings CKL1 to CKL4 are provided. The first to fourth clock intermediate wirings CL1 to CL4 can be integrally formed with the first to fourth clock wirings CKL1 to CKL4. The first to fourth clock intermediate wirings CL1 to CL4 and the first to fourth clock wirings CKL1 to CKL4 can be formed of a first metal material.

[0117] The first to fourth clock bar intermediate wirings CBL1 to CBL4 connect the first to fourth clock bar wirings CKBL1 to CKBL4 with the first to fourth clock bar pads CKBP1 to CKBP4. Referring to FIG. 6AThe first clock bar's intermediate routing CBL1 includes a first upper routing CBL1_1 and a first lower routing CBL1_2. The second clock bar's intermediate routing CBL2 includes a second upper routing CBL2_1 and a second lower routing CBL2_2. The third clock bar's intermediate routing CBL3 includes a third upper routing CBL3_1 and a third lower routing CBL3_2. The fourth clock bar's intermediate routing CBL4 includes a fourth upper routing CBL4_1 and a fourth lower routing CBL4_2.

[0118] The first upper wiring CBL1_1 to the fourth upper wiring CBL4_1 are disposed on a different layer than the layer on which the first lower wiring CBL1_2 to the fourth lower wiring CBL4_2 are disposed. The first upper wiring CBL1_1 to the fourth upper wiring CBL4_1 may be disposed on a second layer, and the first lower wiring CBL1_2 to the fourth lower wiring CBL4_2 may be disposed on a first layer. Here, the first layer may be a first substrate BS1, and the second layer may be a gate insulating layer GIL.

[0119] Reference FIG. 6A The first upper wiring CBL1_1 to the fourth upper wiring CBL4_1 are electrically connected to the first lower wiring CBL1_2 to the fourth lower wiring CBL4_2 respectively through the first contact portion CNT1. The first contact portion CNT1 may include the first contact hole CNT1_1 to the fourth contact hole CNT1_4. The first upper wiring CBL1_1 and the first lower wiring CBL1_2 are directly connected through the first contact hole CNT1_1, and the second upper wiring CBL2_1 and the second lower wiring CBL2_2 are directly connected through the second contact hole CNT1_2. The third upper wiring CBL3_1 and the third lower wiring CBL3_2 are directly connected through the third contact hole CNT1_3, and the fourth upper wiring CBL4_1 and the fourth lower wiring CBL4_2 are directly connected through the fourth contact hole CNT1_4.

[0120] like FIG. 6B As shown, a first lower wiring CBL1_2 is disposed on a first substrate BS1 and is covered by a gate insulating layer GIL. A first contact hole CNT1_1 is provided in the gate insulating layer GIL to expose a portion of the first lower wiring CBL1_2. A first upper wiring CBL1_1 is disposed on the gate insulating layer GIL. The first upper wiring CBL1_1 partially overlaps with the first lower wiring CBL1_2, and is directly connected to the first lower wiring CBL1_2 through the first contact hole CNT1_1 in the overlapping portion of the first upper wiring CBL1_1 and the first lower wiring CBL1_2.

[0121] Despite FIG. 6BOnly the configuration of the first clock bar middle wiring CBL1 is shown, but each of the second to fourth clock bar middle wirings CBL2 to CBL4 has the same configuration as the first clock bar middle wiring CBL1, and to avoid redundancy, the repeated description will be omitted.

[0122] Referring again to FIG. 6A , the first upper wiring CBL1_1 can cross the second to fourth clock middle wirings CL2 to CL4. The second upper wiring CBL2_1 can cross the third and fourth clock middle wirings CL3 and CL4, and the third upper wiring CBL3_1 can cross the fourth clock middle wiring CL4.

[0123] Referring to FIG. 6C and FIG. 6D , the plurality of clock wirings and the plurality of clock bar wirings are electrically connected to the stages SRC1 to SRC8 through a plurality of bridge wirings. The plurality of bridge wirings can include first to eighth bridge wirings BL1 to BL8. Referring to FIG. 5 and FIG. 6C , the first to fourth bridge wirings BL1 to BL4 electrically connect the first to fourth clock wirings CKL1 to CKL4 to the first to fourth stages SRC1 to SRC4, respectively. The fifth to eighth bridge wirings BL5 to BL8 electrically connect the first to fourth clock bar wirings CKBL1 to CKBL4 to the fifth to eighth stages SRC5 to SRC8, respectively.

[0124] The first to eighth bridge wirings BL1 to BL8 are disposed on a layer different from a layer on which the first to fourth clock wirings CKL1 to CKL4 and the first to fourth clock bar wirings CKBL1 to CKBL4 are disposed. The first to fourth clock wirings CKL1 to CKL4 and the first to fourth clock bar wirings CKBL1 to CKBL4 are disposed on a first layer, and the first to eighth bridge wirings BL1 to BL8 are disposed on a second layer. The first layer can be the first base substrate BS1, and the second layer can be the gate insulating layer GIL.

[0125] Referring to FIG. 5 and FIG. 6C , the first clock wiring CKL1 is disposed adjacent to the first clock bar wiring CKBL1. The first clock bar wiring CKBL1 can be disposed between the first clock wiring CKL1 and the second clock wiring CKL2. For example, as FIG. 6CAs shown in FIG. 1, the first clock line CKL1 is spaced apart from the first stage SRC1 by a first distance L1, and the first clock bar line CKBL1 is spaced apart from the fifth stage SRC5 by a second distance L2. The first distance L1 is greater than the second distance L2. The second clock line CKL2 can be spaced apart from the second stage SRC2 by a third distance L3. The third distance L3 can be less than the first distance L1 and the second distance L2. Accordingly, the length L1 of the first bridge line BL1 is longer than the lengths L3 and L2 of the second bridge line BL2 and the fifth bridge line BL5, and the length L2 of the fifth bridge line BL5 is longer than the length L3 of the second bridge line BL2.

[0126] As described above, since the clock lines and the clock bar lines are alternately arranged, a difference in length between the bridge line connected to the clock line to which the clock signal is applied and the bridge line connected to the clock bar line to which the clock bar signal is applied can be reduced. In particular, a difference in length between the first bridge line BL1 and the fifth bridge line BL5 connected to the first clock line CKL1 and the first clock bar line CKBL1 disposed at the outermost side, respectively, is reduced. When the difference in length between the first bridge line BL1 and the fifth bridge line BL5 increases, a first parasitic capacitance formed between the first bridge line BL1 and the reference electrode RE (shown in FIG. 1) and a second parasitic capacitance formed between the fifth bridge line BL5 and the reference electrode RE increase. FIG. 2B As the difference between the first parasitic capacitance and the second parasitic capacitance decreases, an amplitude of a ripple voltage generated in a reference voltage can be reduced. The difference between the first parasitic capacitance and the second parasitic capacitance can be reduced to a level of about 8.0070E-14.

[0127] As described above, since the clock lines and the clock bar lines are alternately arranged, an amplitude of a ripple voltage generated in a reference voltage can be reduced, and thus, a phenomenon of horizontal line tailing on a screen of the display panel DP can be reduced or prevented.

[0128] Referring to FIG. 6C , the first bridge line BL1 to the fourth bridge line BL4 are connected to the first clock line CKL1 to the fourth clock line CKL4, respectively, through the first contact electrode CTE1 to the fourth contact electrode CTE4. The fifth bridge line BL5 to the eighth bridge line BL8 are connected to the first clock bar line CKBL1 to the fourth clock bar line CKBL4, respectively, through the fifth contact electrode CTBE1 to the eighth contact electrode CTBE4.

[0129] As FIG. 6DAs shown in FIG. 1A, the first contact electrode CTE1 is disposed on the third layer covering the first bridge wiring BL1. The third layer can be the protection layer PL. The first bridge contact hole B_CNT1 exposing the first clock wiring CKL1 is provided in the protection layer PL and the gate insulation layer GIL, and the second bridge contact hole B_CNT2 exposing the first bridge wiring BL1 is provided in the protection layer PL. The first contact electrode CTE1 can be connected to the first clock wiring CKL1 and the first bridge wiring BL1 through the first bridge contact hole B_CNT1 and the second bridge contact hole B_CNT2, respectively. In this way, the first clock wiring CKL1 and the first bridge wiring BL1 can be electrically connected through the first contact electrode CTE1.

[0130] Each of the remaining clock wirings CKL2 to CKL4 and clock bar wirings CKBL1 to CKBL4 can also be electrically connected to a corresponding one of the bridge wirings BL2 to BL8 in the manner described above.

[0131] FIG. 7 is FIG. 2A is an enlarged plan view of a second embodiment of the portion AA shown in FIG. 1A. FIG. 8A is FIG. 7 is an enlarged plan view of the portion A3 of FIG. 1A, and FIG. 8B is a cross-sectional view taken along line III-III’ of FIG. 1A. However, the same reference numerals are assigned to elements among the elements of FIG. 1A that are the same as the elements shown in FIG. 1A, and detailed descriptions thereof will be omitted in order to avoid redundancy. FIG. 8A FIG. 7 to FIG. 8B FIG. 5 to FIG. 6B

[0132] Referring to FIGS. 1A and 1B, the first clock bar intermediate wiring CBL1 includes a first upper wiring CBL1_1 and a first lower wiring CBL1_2. The second clock bar intermediate wiring CBL2 includes a second upper wiring CBL2_1 and a second lower wiring CBL2_2. The third clock bar intermediate wiring CBL3 includes a third upper wiring CBL3_1 and a third lower wiring CBL3_2. The fourth clock bar intermediate wiring CBL4 includes a fourth upper wiring CBL4_1 and a fourth lower wiring CBL4_2. FIG. 7 FIG. 8A The first upper wiring CBL1_1 to the fourth upper wiring CBL4_1 are disposed on a layer different from a layer on which the first lower wiring CBL1_2 to the fourth lower wiring CBL4_2 are disposed. The first upper wiring CBL1_1 to the fourth upper wiring CBL4_1 can be disposed on a second layer, and the first lower wiring CBL1_2 to the fourth lower wiring CBL4_2 can be disposed on a first layer. Here, the first layer can be the first base substrate BS1, and the second layer can be the gate insulation layer GIL.

[0133] Referring to FIGS. 1A and 1B, the first clock bar intermediate wiring CBL1 includes a first upper wiring CBL1_1 and a first lower wiring CBL1_2. The second clock bar intermediate wiring CBL2 includes a second upper wiring CBL2_1 and a second lower wiring CBL2_2. The third clock bar intermediate wiring CBL3 includes a third upper wiring CBL3_1 and a third lower wiring CBL3_2. The fourth clock bar intermediate wiring CBL4 includes a fourth upper wiring CBL4_1 and a fourth lower wiring CBL4_2.

[0134] Referring to FIGS. 1A and 1B, the first clock bar intermediate wiring CBL1 includes a first upper wiring CBL1_1 and a first lower wiring CBL1_2. The second clock bar intermediate wiring CBL2 includes a second upper wiring CBL2_1 and a second lower wiring CBL2_2. The third clock bar intermediate wiring CBL3 includes a third upper wiring CBL3_1 and a third lower wiring CBL3_2. The fourth clock bar intermediate wiring CBL4 includes a fourth upper wiring CBL4_1 and a fourth lower wiring CBL4_2.​​​​FIG. 8A The first upper wiring CBL1_1 to the fourth upper wiring CBL4_1 are respectively connected to the first lower wiring CBL1_2 to the fourth lower wiring CBL4_2 via the second contact portion CNT2. The second contact portion CNT2 may include the first upper contact hole CNT2_11 to the fourth upper contact hole CNT2_41 and the first lower contact hole CNT2_12 to the fourth lower contact hole CNT2_42.

[0135] The second contact portion CNT2 further includes first bridge electrodes BE11 to fourth bridge electrodes BE14. First bridge electrodes BE11 to fourth bridge electrodes BE14 are provided on a third layer. The third layer may be a protective layer PL. The first bridge electrode BE11 is connected to the first upper wiring CBL1_1 and the first lower wiring CBL1_2 respectively through a first upper contact hole CNT2_11 and a first lower contact hole CNT2_12. FIG. 8B As shown, a first upper contact hole CNT2_11 is provided in the protective layer PL to expose the first upper wiring CBL1_1, and a first lower contact hole CNT2_12 is provided in the protective layer PL and the gate insulating layer GIL to expose the first lower wiring CBL1_2. Therefore, the first upper wiring CBL1_1 and the first lower wiring CBL1_2, provided on different layers, can be electrically connected via the first bridge electrode BE11. When viewed in a plane, the first upper wiring CBL1_1 and the first lower wiring CBL1_2 may not overlap each other.

[0136] The second bridge electrode BE12 is connected to the second upper wiring CBL2_1 and the second lower wiring CBL2_2 through the second upper contact hole CNT2_21 and the second lower contact hole CNT2_22, respectively. The third bridge electrode BE13 is connected to the third upper wiring CBL3_1 and the third lower wiring CBL3_2 through the third upper contact hole CNT2_31 and the third lower contact hole CNT2_32, respectively. The fourth bridge electrode BE14 is connected to the fourth upper wiring CBL4_1 and the fourth lower wiring CBL4_2 through the fourth upper contact hole CNT2_41 and the fourth lower contact hole CNT2_42, respectively.

[0137] Because the connection structure from the second bridge electrode BE12 to the fourth bridge electrode BE14 is FIG. 8B The connection structure of the first bridge electrode BE11 shown is similar, so to avoid redundancy, the description of the connection structure of the second bridge electrode BE12 to the fourth bridge electrode BE14 will be omitted.

[0138] FIG. 9 yes FIG. 2A An enlarged plan view of the third embodiment of part AA shown. FIG. 10A yes FIG. 9 An enlarged plan view of a portion of the embodiment on page A4, and FIG. 10B It is alongFIG. 10A a cross-sectional view taken along the line IV-IV' of FIG. 4. FIG. 10C is a cross-sectional view taken along the line V-V' of FIG. 5. However, the same reference numerals are assigned to elements identical to those shown in FIG. 10A FIG. 9 to FIG. 10C among the elements shown in FIG. 5 to FIG. 6B and a detailed description thereof will be omitted in order to avoid redundancy.

[0139] Referring to FIG. 2A , FIG. 9 and FIG. 10A , a first intermediate wiring part CLP1 is disposed between the first driving pad part PD2_1 and the first gate driver GDC1 and electrically connects the first driving pad part PD2_1 to a signal wiring of the first gate driver GDC1. Specifically, as shown in FIG. 9 , the first intermediate wiring part CLP1 can include a plurality of clock intermediate wirings, a plurality of clock bar intermediate wirings, a first voltage intermediate wiring VCL1 and a second voltage intermediate wiring VCL2, and a start signal intermediate wiring STCL. Referring to FIG. 10A , the plurality of clock intermediate wirings can be a first clock intermediate wiring CL1 to a fourth clock intermediate wiring CL4, and the plurality of clock bar intermediate wirings can be a first clock bar intermediate wiring CBL1 to a fourth clock bar intermediate wiring CBL4.

[0140] The first clock intermediate wiring CL1 to the fourth clock intermediate wiring CL4 connect the first clock wiring CKL1 to the fourth clock wiring CKL4 with the first clock pad CKP1 to the fourth clock pad CKP4. Each of the first clock intermediate wiring CL1 to the fourth clock intermediate wiring CL4 can have a double layer structure. Specifically, referring to FIG. 10A , the first clock intermediate wiring CL1 includes a first lower conductive layer CL1_1 and a first upper conductive layer CL1_2, and the second clock intermediate wiring CL2 includes a second lower conductive layer CL2_1 and a second upper conductive layer CL2_2. The third clock intermediate wiring CL3 includes a third lower conductive layer CL3_1 and a third upper conductive layer CL3_2, and the fourth clock intermediate wiring CL4 includes a fourth lower conductive layer CL4_1 and a fourth upper conductive layer CL4_2.

[0141] The first lower conductive layer CL1_1 to the fourth lower conductive layer CL4_1 are disposed on layers different from layers on which the first upper conductive layer CL1_2 to the fourth upper conductive layer CL4_2 are disposed. The first lower conductive layer CL1_1 to the fourth lower conductive layer CL4_1 are directly connected to the first clock pad CKP1 to the fourth clock pad CKP4.

[0142] ​The first to fourth clock strip middle wires CBL1 to CBL4 connect the first to fourth clock strip wires CKBL1 to CKBL4 with the first to fourth clock strip pads CKBP1 to CKBP4. Each of the first to fourth clock strip middle wires CBL1 to CBL4 can have a double-layer structure. Specifically, referring to FIG. 10A , the first clock strip middle wire CBL1 includes a fifth upper conductive layer CBL11 and a fifth lower conductive layer CBL12, and the second clock strip middle wire CBL2 includes a sixth upper conductive layer CBL21 and a sixth lower conductive layer CBL22. The third clock strip middle wire CBL3 includes a seventh upper conductive layer CBL31 and a seventh lower conductive layer CBL32, and the fourth clock strip middle wire CBL4 includes an eighth upper conductive layer CBL41 and an eighth lower conductive layer CBL42.

[0143] The fifth to eighth lower conductive layers CBL12 to CBL42 are disposed on layers different from the layers on which the fifth to eighth upper conductive layers CBL11 to CBL41 are disposed. The fifth to eighth upper conductive layers CBL11 to CBL41 are directly connected to the first to fourth clock strip pads CKBP1 to CKBP4.

[0144] The fifth to seventh upper conductive layers CBL11 to CBL31 can cross the second to fourth lower conductive layers CL2_1 to CL4_1. Specifically, referring to FIG. 10A , the fifth upper conductive layer CBL11 crosses the second to fourth lower conductive layers CL2_1 to CL4_1, the sixth upper conductive layer CBL21 crosses the third and fourth lower conductive layers CL3_1 and CL4_1, and the seventh upper conductive layer CBL31 crosses the fourth lower conductive layer CL4_1.

[0145] The first to eighth lower conductive layers CL1_1 to CL4_1 and CBL12 to CBL42 are connected to the first to eighth upper conductive layers CL1_2 to CL4_2 and CBL11 to CBL41, respectively, through third contact portions CNT3. The third contact portions CNT3 include first to eighth sub-contact portions CNT3_1 to CNT3_8.

[0146] FIG. 10BThe structure of the first sub-contact portion CNT3_1 is shown. A first lower conductive layer CL1_1 is provided on the first substrate BS1, and a first upper conductive layer CL1_2 is disposed on the gate insulating layer GIL. The first sub-contact portion CNT3_1 includes a first sub-contact hole CNT3_11 and a second sub-contact hole CNT3_12. The first sub-contact hole CNT3_11 and the second sub-contact hole CNT3_12 are provided in the gate insulating layer GIL to expose the first lower conductive layer CL1_1. The first upper conductive layer CL1_2 is directly connected to the first lower conductive layer CL1_1 through the first sub-contact hole CNT3_11 and the second sub-contact hole CNT3_12.

[0147] Because the structures of the third sub-contact portion CNT3_3, the fifth sub-contact portion CNT3_5, and the seventh sub-contact portion CNT3_7 are similar to the structure of the first sub-contact portion CNT3_1, the description of the structures of the third sub-contact portion CNT3_3, the fifth sub-contact portion CNT3_5, and the seventh sub-contact portion CNT3_7 is omitted to avoid redundancy.

[0148] FIG. 10C The structure of the second sub-contact portion CNT3_2 is shown. A fifth lower conductive layer CBL12 is provided on the first substrate BS1, and a fifth upper conductive layer CBL11 is disposed on the gate insulating layer GIL. The second sub-contact portion CNT3_2 includes a third sub-contact hole CNT3_21 and a fourth sub-contact hole CNT3_22. The third and fourth sub-contact holes CNT3_21 and CNT3_22 are provided in the gate insulating layer GIL to expose the fifth lower conductive layer CBL12. The fifth upper conductive layer CBL11 is directly connected to the fifth lower conductive layer CBL12 through the third and fourth sub-contact holes CNT3_21 and CNT3_22.

[0149] Because the structures of the fourth sub-contact portion CNT3_4, the sixth sub-contact portion CNT3_6, and the eighth sub-contact portion CNT3_8 are similar to the structure of the second sub-contact portion CNT3_2, the description of the structures of the fourth sub-contact portion CNT3_4, the sixth sub-contact portion CNT3_6, and the eighth sub-contact portion CNT3_8 is omitted to avoid redundancy.

[0150] FIG. 11A yes FIG. 9 An enlarged plan view of another embodiment of part A4. FIG. 11B It is along FIG. 11A The cross-sectional view taken from line VI-VI', and FIG. 11C It is along FIG. 11A The cross-sectional view taken from line VII-VII'.

[0151] Reference FIG. 11A to FIG. 11CThe first to eighth lower conductive layers CL1_1 to CL4_1 and CBL12 to CBL42 are connected to the first to eighth upper conductive layers CL1_2 to CL4_2 and CBL11 to CBL41, respectively, through fourth contact portions CNT4. The fourth contact portions CNT4 include first to eighth sub-contact portions CNT4_1 to CNT4_8. First to eighth bridge electrodes BE21 to BE28 are provided to the first to eighth sub-contact portions CNT4_1 to CNT4_8, respectively.

[0152] FIG. 11B The structure of the first sub-contact portion CNT4_1 is illustrated. The first lower conductive layer CL1_1 is provided on the first base substrate BS1, and the first upper conductive layer CL1_2 is disposed on the gate insulating layer GIL. The first sub-contact portion CNT4_1 includes a first sub-contact hole CNT4_11, a second sub-contact hole CNT4_12, and the first bridge electrode BE21. The first sub-contact hole CNT4_11 is provided in the protective layer PL to expose the first upper conductive layer CL1_2. The second sub-contact hole CNT4_12 is provided in the protective layer PL and the gate insulating layer GIL to expose the first lower conductive layer CL1_1.

[0153] The first bridge electrode BE21 is connected to the first lower conductive layer CL1_1 and the first upper conductive layer CL1_2 through the first sub-contact hole CNT4_11 and the second sub-contact hole CNT4_12. Thus, the first lower conductive layer CL1_1 and the first upper conductive layer CL1_2 are electrically connected to each other through the first bridge electrode BE21.

[0154] Since the structures of the third sub-contact portion CNT4_3, the fifth sub-contact portion CNT4_5, and the seventh sub-contact portion CNT4_7 are similar to that of the first sub-contact portion CNT4_1, the description of the structures of the third sub-contact portion CNT4_3, the fifth sub-contact portion CNT4_5, and the seventh sub-contact portion CNT4_7 is omitted to avoid redundancy.

[0155] FIG. 11CThe structure of the second sub-contact portion CNT4_2 is shown. The fifth lower conductive layer CBL12 is provided on the first base substrate BS1, and the fifth upper conductive layer CBL11 is provided on the gate insulating layer GIL. The second sub-contact portion CNT4_2 includes a third sub-contact hole CNT4_21, a fourth sub-contact hole CNT4_22, a fifth sub-contact hole CNT4_23, and a second bridge electrode BE22. The third sub-contact hole CNT4_21 is provided in the gate insulating layer GIL to expose the fifth lower conductive layer CBL12. The fifth upper conductive layer CBL11 is directly connected to the fifth lower conductive layer CBL12 through the third sub-contact hole CNT4_21. The fourth sub-contact hole CNT4_22 and the fifth sub-contact hole CNT4_23 are provided in the protective layer PL to expose the fifth upper conductive layer CBL11. The second bridge electrode BE22 is directly connected to the fifth upper conductive layer CBL11 through the fourth sub-contact hole CNT4_22 and the fifth sub-contact hole CNT4_23. The second bridge electrode BE22 can be omitted.

[0156] The structures of the fourth sub-contact portion CNT4_4, the sixth sub-contact portion CNT4_6, and the eighth sub-contact portion CNT4_8 are similar to the structure of the second sub-contact portion CNT4_2, and thus, for the sake of avoiding redundancy, the description of the structures of the fourth sub-contact portion CNT4_4, the sixth sub-contact portion CNT4_6, and the eighth sub-contact portion CNT4_8 will be omitted.

[0157] FIG. 12 is FIG. 2A an enlarged plan view of the fourth embodiment of the portion AA shown in FIG. 17. However, the same reference numerals are assigned to elements that are the same as those shown in FIG. 12 FIG. 17 among the elements shown in FIG. 5 FIG. 18, and for the sake of avoiding redundancy, detailed descriptions thereof will be omitted.

[0158] Referring to FIG. 12 , the first gate driver GDC1 further includes a compensation portion DCP to compensate for a length difference between the bridge wirings. The compensation portion DCP can be disposed in the interval space SA between the fourth clock bar wiring CKBL4 and the second voltage wiring VL2. However, the position of the compensation portion DCP is not limited thereto. For example, the compensation portion DCP can be disposed between the first voltage wiring VL1 and the stages SRC1 to SRC8.

[0159] The compensation portion DCP includes a plurality of compensation patterns. The plurality of compensation patterns can include first to eighth compensation patterns CP1 to CP4 and CBP1 to CBP4 connected to the first to eighth bridge wirings BL1 to BL8, respectively.

[0160] The length of each of the compensation patterns can be inversely proportional to the length of the corresponding one of the bridge wires. That is, when the length of one of the bridge wires is long, the length of the compensation pattern connected thereto can be short, and when the length of the bridge wire is short, the length of the compensation pattern connected thereto can be long. Accordingly, the sum of the length of the first compensation pattern CP1 and the length of the first bridge wire BL1 can be the same as the sum of the length of the second compensation pattern CP2 and the length of the second bridge wire BL2. By connecting the compensation patterns having different lengths to the bridge wires, respectively, the length difference between the bridge wires can be compensated for.

[0161] According to the principles and embodiments of the present application exemplified above, since the clock wires and the clock bar wires are alternately arranged, the length difference between the bridge wires electrically connected to the clock wires to which the clock signal is applied and the bridge wires electrically connected to the clock bar wires to which the clock bar signal is applied can be reduced.

[0162] When the length difference between the bridge wires is reduced, the difference between the parasitic capacitances formed between the bridge wires and the reference electrode is reduced, and thus the amplitude of the moire voltage generated in the reference voltage can be reduced.

[0163] As described above, since the clock wires and the clock bar wires are alternately arranged, the amplitude of the moire voltage generated in the reference voltage can be reduced, and thus the appearance of horizontal line tailing on the screen of the display panel can be prevented, thereby improving the display quality.

[0164] Although specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but is defined only by the appended claims as supported by the full scope of equivalents throughout various modifications and equivalent arrangements.

Claims

1. A display device including a display panel, the display panel comprising: Multiple pixels are used to display the image; A gate driver for driving the pixel; The first pad portion is electrically connected to the pixel; as well as The second pad portion is electrically connected to the gate driver. The gate driver includes: Multiple stages for generating the gate signal to be provided to the pixel; k clock lines are used to provide k clock signals to the multiple stages; and k clock strips are used to provide k clock strip signals to the multiple stages, where k is a natural number of 1 or greater than 1. The second pad portion includes: k clock pads are electrically connected to the k clock traces, respectively; and k clock strip pads are electrically connected to the k clock strip traces, and Specifically, the k clock traces and the k clock strip traces are arranged in a first order, and the k clock pads and the k clock strip pads are arranged in a second order different from the first order. Wherein, the first clock line for receiving the first clock signal and the second clock line for receiving the second clock signal are respectively located on both sides of the first clock line for receiving the first clock signal and are arranged adjacent to the first clock line. The first clock signal has a phase out of phase with respect to the first clock signal, and the second clock signal is delayed from the first clock signal. Among the k clock pads, the first clock pad that is electrically connected to the first clock wiring is positioned closer to the second clock pad that is electrically connected to the second clock wiring than the first clock pad that is electrically connected to the first clock wiring.

2. The display device according to claim 1, wherein, The display panel further includes an intermediate wiring portion for electrically connecting the second pad portion and the gate driver. The intermediate wiring portion includes: k first intermediate wirings are used to electrically connect the k clock pads to the k clock wirings respectively; and k second intermediate wirings are used to electrically connect the k clock strip pads to the k clock strip wirings respectively.

3. The display device according to claim 2, wherein, At least one of the k first intermediate wirings intersects with at least one of the k second intermediate wirings.

4. The display device according to claim 3, wherein, The k first intermediate wirings are arranged on the first layer, and Each of the k second intermediate wirings includes: The lower wiring is disposed on the first layer; and The upper wiring is set on a second layer, which is different from the first layer.

5. The display device according to claim 4, wherein, At least one of the k first intermediate wirings intersects with the upper wiring of at least one of the k second intermediate wirings.

6. The display device according to claim 4, wherein, The intermediate wiring portion further includes a contact portion, and the lower wiring and the upper wiring are connected to the contact portion.

7. The display device according to claim 6, wherein, The lower wiring and the upper wiring are directly connected in the contact portion.

8. The display device according to claim 6, wherein, The contact portion includes a bridge electrode for connecting the lower wiring and the upper wiring.

9. The display device according to claim 1, wherein, The gate driver further includes: k first bridge wirings are used to connect the k clock wirings to the plurality of stages; and k second bridge wirings are used to connect the k clock strip wirings to the plurality of stages.

10. The display device according to claim 9, wherein, The first bridge wiring in the k first bridge wirings that connects to the first clock wiring is longer than the second bridge wiring in the k second bridge wirings that connects to the first clock wiring. The first bridge wiring in the k first bridge wiring that connects to the second clock wiring is shorter than the second bridge wiring that connects to the first clock wiring.

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