Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate; forming a gate structure on the substrate; forming source-drain openings in the substrate on both sides of the gate structure; forming a first inhibition layer in the substrate, wherein the first inhibition layer has a first ion; forming a source-drain doping layer in the source-drain opening, wherein the source-drain doping layer has a second ion, wherein the first ion and the second ion are of the same type, and the atomic number of the first ion is greater than the atomic number of the second ion. Since, among ions of the same type, ions with larger atomic numbers have lower diffusion coefficients and correspondingly lower diffusion rates, in subsequent annealing treatment, the diffusion rate of the second ion is suppressed by the first ion with a lower diffusion rate, thereby reducing the diffusion of the first ion to the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] MOS (Metal-Oxide-Semiconductor) transistor is one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, wherein the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; lightly doped regions located on the semiconductor substrate on both sides of the gate structure and source and drain regions located on the semiconductor substrate on both sides of the gate structure.

[0003] The method for forming the MOS transistor is as follows: providing a semiconductor substrate, forming a gate structure on the surface of the semiconductor substrate, the gate structure comprising a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; forming an offset sidewall on the surface of the sidewall of the gate structure, using the offset sidewall and the gate structure as a mask, performing a lightly doped drain (LDD) injection into the semiconductor substrate on both sides of the gate structure to form a lightly doped region; forming a gap sidewall on the surface of the offset sidewall; using the gate structure, the offset sidewall and the gap sidewall as a mask, performing a source and drain region injection process into the semiconductor substrate on both sides of the gate structure to form a source and drain region.

[0004] However, the performance and reliability of the MOS transistor formed in the prior art are poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; source-drain openings located in the substrate on both sides of the gate structure; a first inhibition layer located in the substrate, the first inhibition layer surrounds the source-drain openings, and the first inhibition layer has first ions; a source-drain doping layer located in the source-drain openings, the source-drain doping layer has second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions.

[0007] Optionally, it also includes: a side wall located on the substrate.

[0008] Optionally, the substrate has a plurality of fins separated from each other, the gate structure and the sidewalls span across the fins, and the gate structure and the sidewalls cover a portion of the top and sidewall surfaces of the fins.

[0009] Optionally, the first ion and the second ion are N-type ions; the first ion is an arsenic ion, and the second ion is a phosphorus ion.

[0010] Optionally, the first ion and the second ion are P-type ions; the first ion is an indium ion, and the second ion is a boron ion.

[0011] Optionally, the source / drain openings expose a portion of the bottom surface of the sidewall.

[0012] Optionally, it further includes: a second inhibition layer located on the sidewalls and bottom surfaces of the source and drain openings, the second inhibition layer contains the first ions, and the source and drain doping layers are located on the second inhibition layer.

[0013] Optionally, the thickness of the second inhibition layer is 5 angstroms to 30 angstroms, and the doping dose of the first ion in the second inhibition layer is 1E19 atom / cm 3 ~1E21atom / cm 3 .

[0014] Optionally, the doping dose of the second ion is 1E17atom / cm 3 ~1E21atom / cm 3 .

[0015] Correspondingly, the present invention also provides a method for forming any of the above-mentioned semiconductor structures, comprising: providing a substrate; forming a gate structure on the substrate; forming source and drain openings in the substrate on both sides of the gate structure respectively; forming a first inhibition layer in the substrate, the first inhibition layer surrounding the source and drain openings, the first inhibition layer having first ions; forming a source and drain doping layer in the source and drain openings, the source and drain doping layer having second ions, the first ions being of the same type as the second ions, and the atomic number of the first ions being greater than the atomic number of the second ions.

[0016] Optionally, the method further includes: forming a sidewall on the substrate.

[0017] Optionally, the substrate has a plurality of fins separated from each other, the gate structure and the sidewalls span across the fins, and the gate structure and the sidewalls cover a portion of the top and sidewall surfaces of the fins.

[0018] Optionally, the first ion and the second ion are N-type ions; the first ion is an arsenic ion, and the second ion is a phosphorus ion.

[0019] Optionally, the first ion and the second ion are P-type ions; the first ion is an indium ion, and the second ion is a boron ion.

[0020] Optionally, the method for forming the first inhibition layer includes: performing the first ion implantation on the source / drain openings to form the first inhibition layer.

[0021] Optionally, the parameters of the first ion implantation include: an implantation angle of 75° to 80°.

[0022] Optionally, before performing the first ion implantation on the source / drain opening, the method further includes: forming a barrier layer on the bottom surface of the source / drain opening; and removing the barrier layer after the first ion implantation.

[0023] Optionally, the material of the barrier layer includes organic material.

[0024] Optionally, the process of removing the barrier layer includes one or more combinations of a wet etching process and a dry etching process.

[0025] Optionally, the method further includes: etching the sidewall surface exposed by the source / drain openings until the source / drain openings expose a portion of the bottom surface of the sidewall.

[0026] Optionally, the process of etching the source / drain openings includes one or more combinations of a wet etching process and a dry etching process.

[0027] Optionally, after forming the first inhibition layer in the substrate and before forming the source-drain doping layer in the source-drain opening, the method further includes: forming a second inhibition layer on the sidewalls and bottom surfaces of the source-drain opening, wherein the second inhibition layer is doped with the first ions.

[0028] Optionally, the process of forming the second inhibition layer on the surface of the source / drain opening includes an epitaxial process, and the first ion doping process includes an in-situ doping process.

[0029] Optionally, the thickness of the second inhibition layer is 5 angstroms to 30 angstroms, and the doping dose of the first ion in the second inhibition layer is 1E19 atom / cm 3 ~1E21atom / cm 3 .

[0030] Optionally, the doping dose of the second ion is 1E17atom / cm 3 ~1E21atom / cm 3 .

[0031] Optionally, the method for forming a source-drain doped layer in the source-drain opening includes: forming an epitaxial layer in the source-drain opening using an epitaxial growth process; in-situ doping the epitaxial layer during the epitaxial growth process, doping the second ions into the epitaxial layer to form the source-drain doped layer.

[0032] Optionally, after forming the source-drain doping layer, the method further includes: annealing the source-drain doping layer.

[0033] Optionally, the annealing treatment includes a laser annealing process.

[0034] Optionally, the annealing treatment is performed at a temperature of 1000°C to 1500°C.

[0035] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0036] In the semiconductor structure of the technical solution of the present invention, a first inhibition layer is located in the substrate, the first inhibition layer surrounds the source-drain opening, and there are first ions in the first inhibition layer; a source-drain doping layer is located in the source-drain opening, and there are second ions in the source-drain doping layer, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions. Since among ions of the same type, the diffusion coefficient of ions with larger atomic numbers is lower, and the corresponding diffusion rate is also lower, therefore, in the subsequent annealing treatment, the diffusion rate of the second ions is suppressed by the first ions with lower diffusion rate, thereby reducing the diffusion of the first ions to the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0037] Furthermore, the source-drain opening exposes a portion of the bottom surface of the sidewall, the source-drain opening in the structure is enlarged, and the volume of the corresponding source-drain doped layer is also enlarged. Since the contact between the plug formed in the subsequent process and the source-drain doped layer is a full-coverage contact, that is, the plug fully covers the surface of the source-drain doped layer, the surface area of ​​the source-drain doped layer is large and the contact area with the plug is correspondingly large, which can reduce the contact resistance of the formed semiconductor structure, thereby improving the performance of the device.

[0038] Furthermore, through the second inhibition layer located on the sidewalls and bottom surface of the source and drain openings, the second inhibition layer has the first ions, and the source and drain doping layer is located on the second inhibition layer. The first ions in the second inhibition layer can further inhibit the diffusion rate of the second ions, thereby reducing the diffusion of the first ions into the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0039] In the method for forming a semiconductor structure of the technical solution of the present invention, a first inhibition layer is formed in the substrate, the first inhibition layer surrounds the source-drain opening, and the first inhibition layer contains first ions; a source-drain doping layer is formed in the source-drain opening, the source-drain doping layer contains second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions. Since the diffusion coefficient of ions with larger atomic numbers is lower among ions of the same type, and the corresponding diffusion rate is also lower, in the subsequent annealing process, the diffusion rate of the second ions is suppressed by the first ions with lower diffusion rate, thereby reducing the diffusion of the first ions to the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0040] Furthermore, before the first ion implantation is performed on the source / drain opening, a barrier layer is formed on the bottom surface of the source / drain opening. The barrier layer can ensure that during the first ion implantation, the first ions are diffused more into the substrates on both sides corresponding to the sidewall surfaces of the source / drain opening, and the first ions are diffused less into the substrate below corresponding to the bottom of the source / drain opening. In the subsequent annealing process, the area of ​​the source / drain doping region finally formed is increased, thereby improving the electrical performance of the finally formed semiconductor structure.

[0041] Furthermore, by etching the side wall surface exposed by the source / drain opening until the source / drain opening exposes a portion of the bottom surface of the side wall, the source / drain opening in this method is increased, and the volume of the corresponding source / drain doping layer is also increased. Since the contact between the plug formed in the subsequent process and the source / drain doping layer is a full-coverage contact, that is, the plug fully covers the surface of the source / drain doping layer, the surface area of ​​the source / drain doping layer is larger and the contact area with the plug is correspondingly larger, the contact resistance of the formed semiconductor structure can be reduced, thereby improving the performance of the device.

[0042] Furthermore, after forming the first inhibition layer in the substrate and before forming the source-drain doping layer in the source-drain opening, the method further includes: forming a second inhibition layer on the surface of the source-drain opening, wherein the second inhibition layer contains the first ions. The first ions in the second inhibition layer can further inhibit the diffusion rate of the second ions, thereby reducing the diffusion of the first ions into the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0043] Furthermore, the source-drain doped layer is subjected to an annealing treatment, and the annealing treatment is used to activate second ions in the source-drain doped layer and diffuse the second ions toward the fin, thereby forming a source-drain doped region.

[0044] Furthermore, the temperature range of the annealing treatment is 1000° C. to 1500° C. The annealing treatment in the temperature range of 1000° C. to 1500° C. can ensure that the second ions in the source-drain doping layer are completely activated, while also preventing the second ions from excessively diffusing into the channel region, thereby affecting the electrical properties of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 to Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0046] Figures 3 to 12 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0047] As described in the background art, the performance and reliability of the MOS transistor formed in the prior art are relatively poor, which will be described in detail below with reference to the accompanying drawings.

[0048] Figure 1 to Figure 2 It is a schematic diagram of the structures of various steps in the formation process of a semiconductor structure.

[0049] Please refer to Figure 1 , providing a substrate 100 having a plurality of mutually discrete fins 101 thereon; forming a gate structure 102 on the substrate 100 , wherein the gate structure 102 spans across the fins 101 and covers a portion of the top surface of the fins 101 and the sidewall surface of the fins 101 .

[0050] Please refer to Figure 2 , forming source and drain openings in the fins on both sides of the gate structure 102; forming a source and drain doping layer 103 in the source and drain openings, wherein the source and drain doping layer 103 has first ions.

[0051] In the above embodiment, after forming the source-drain doping layer 103 in the source-drain opening, the source-drain doping layer 103 needs to be annealed. The annealing is used to activate the first ions in the source-drain doping layer 103 and diffuse the first ions into the fin 101, thereby forming a source-drain doping region.

[0052] However, during the diffusion of the first ions, some of the first ions will diffuse into the channel region. Since the ions doped in the channel region are of the opposite type to the first ions, the channel region will be shortened and a short channel effect will occur. The short channel effect will cause the threshold voltage of the transistor to drift, the cutoff current to increase, or even breakdown. These problems seriously affect the electrical performance of the integrated circuit and even cause the entire circuit to fail.

[0053] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein a first inhibition layer is formed in the substrate, and the first inhibition layer surrounds the source and drain openings. In a subsequent annealing process, the first inhibition layer is used to block the first ions in the source and drain doping layers from diffusing to the channel region, thereby reducing the length of the channel region and improving the electrical performance of the final semiconductor structure.

[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0055] Figures 3 to 12 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0056] Please refer to Figure 3 , providing a substrate 200.

[0057] In this embodiment, the material of the substrate 200 is single crystal silicon. In other embodiments, the semiconductor substrate 100 may also be polycrystalline silicon or amorphous silicon. The material of the semiconductor substrate 100 may also be semiconductor materials such as germanium, silicon germanium, and gallium arsenide.

[0058] Please continue to refer to 3. In this embodiment, the substrate 200 has a plurality of separate fins 201.

[0059] In this embodiment, the fin 201 is formed by patterning the substrate 200. In other embodiments, the fin may be formed by forming a fin material layer on the substrate and then patterning the fin material layer.

[0060] In this embodiment, the material of the fin 201 is single crystal silicon. In other embodiments, the material of the fin may also be single crystal silicon germanium or other semiconductor materials.

[0061] In other embodiments, the substrate may also be a structure without the fin.

[0062] Please refer to Figure 4 , a gate structure 202 is formed on the substrate 200 .

[0063] In this embodiment, the method further includes: forming a sidewall spacer 203 on the substrate 200 .

[0064] In this embodiment, the gate structure 202 and the sidewall 203 span across the fin 201 , and the gate structure 202 and the sidewall 203 cover a portion of the top surface of the fin 201 and the sidewall surface of the fin 201 . The sidewall 203 is located on both sidewalls of the gate structure 202 .

[0065] In this embodiment, the gate structure 202 includes a gate dielectric layer 204 spanning the fin 201 and a gate electrode layer 205 located on the gate dielectric layer 204 .

[0066] The gate dielectric layer 204 is made of silicon oxide or a high-K (K greater than 3.9) dielectric material. The gate electrode layer 205 is made of polysilicon or metal. In this embodiment, the gate dielectric layer 204 is made of silicon oxide, and the gate electrode layer 205 is made of polysilicon.

[0067] In this embodiment, the top surface of the gate structure 202 further has a gate protection layer 206 .

[0068] The gate protection layer 206 is made of SiN, SiBCN, SiCN or SiBN. In this embodiment, the gate protection layer 206 is made of SiN.

[0069] In this embodiment, after forming the gate structure 202, the sidewall spacer 203 is formed on the sidewall of the fin 201. The method of forming the sidewall spacer 203 includes: forming a sidewall spacer material layer (not shown) on the fin 201 and the gate structure 202; etching back the sidewall spacer material layer until the top surface of the gate structure 202 is exposed, thereby forming the sidewall spacer 203.

[0070] The function of the sidewall spacer 203 is to define the relative position of the subsequently formed source / drain doping layer and the gate structure 202 .

[0071] The process for forming the sidewall material layer is a deposition process, such as a plasma chemical vapor deposition process, an atomic layer deposition process, or a low-pressure chemical vapor deposition process. In this embodiment, the process for forming the sidewall material layer is an atomic layer deposition process, and the process parameters include: using an organic precursor gas containing Si and O, a temperature of 80 degrees Celsius to 700 degrees Celsius, a pressure of 5 mtorr to 20 torr, and a deposition number of 5 to 50 times.

[0072] The material of the spacer material layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon nitride. In this embodiment, the material of the spacer material layer is silicon oxide.

[0073] Please refer to Figure 5 , source and drain openings 207 are respectively formed in the substrate 200 on both sides of the gate structure 202 .

[0074] In this embodiment, the source-drain openings 207 are specifically formed in the fins 201 on both sides of the gate structure 202 , and the source-drain openings 207 are used for subsequently forming source-drain doping layers.

[0075] The method for forming the source-drain opening 207 includes: forming a mask layer (not shown) on the substrate 200; forming a patterned layer (not shown) on the mask layer, wherein the patterned layer exposes a portion of the top surface of the mask layer; etching the mask layer and the fin 201 using the patterned layer as a mask to form the source-drain opening 207 in the fin 201; after forming the source-drain opening 207, removing the mask layer and the patterned layer.

[0076] The process used for etching the mask layer and the fins includes: a dry etching process or a wet etching process. In this embodiment, the process for etching the mask layer and the fins is a wet etching process.

[0077] The material of the mask layer includes silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide. In this embodiment, the material of the mask layer is silicon nitride.

[0078] In this embodiment, the material of the patterned layer includes photoresist, and the process of removing the patterned layer includes an ashing process.

[0079] Please refer to Figure 6 After the source / drain openings 207 are formed, a barrier layer 208 is formed on the bottom surface of the source / drain openings 207 .

[0080] In this embodiment, the function of the blocking layer 208 is to ensure that in the subsequent first ion injection process, the first ions are diffused more into the substrates 200 on both sides corresponding to the side wall surfaces of the source / drain opening 207, and the first ions are reduced from diffusing more into the lower substrate 200 corresponding to the bottom of the source / drain opening 207. In the subsequent annealing treatment, the area of ​​the source / drain doping region finally formed is increased, thereby improving the electrical performance of the finally formed semiconductor structure.

[0081] In this embodiment, the material of the barrier layer 208 includes organic material.

[0082] Please refer to Figure 7 After forming the barrier layer 208 , the sidewall surface exposed by the source / drain opening 207 is etched until the source / drain opening 207 exposes a portion of the bottom surface of the sidewall 203 .

[0083] In this embodiment, by etching the side wall surface exposed by the source / drain opening 207 until the source / drain opening 207 exposes a portion of the bottom surface of the side wall 203, this method increases the size of the source / drain opening 207. In the subsequent process, the volume of the corresponding source / drain doped layer is also increased. Since the contact between the plug formed in the subsequent process and the source / drain doped layer is a full-coverage contact, that is, the plug fully covers the surface of the source / drain doped layer, the surface area of ​​the source / drain doped layer is larger and the contact area with the plug is correspondingly larger, the contact resistance of the formed semiconductor structure can be reduced, thereby improving the performance of the device.

[0084] In this embodiment, the process of etching the source-drain opening 207 is a wet etching process. In other embodiments, the process of etching the source-drain opening may also be a dry etching process or a combination of a dry etching process and a wet etching process.

[0085] Please refer to Figure 8 A first inhibition layer 209 is formed in the substrate 200 at the sidewalls and bottom of the source / drain opening 207 , and the first inhibition layer 209 surrounds the source / drain opening 207 . The first inhibition layer 209 has first ions.

[0086] By forming a first inhibition layer 209 in the substrate 200, the first inhibition layer 209 surrounds the source-drain opening 207, and the first inhibition layer contains first ions; in the subsequent process, it also includes: forming a source-drain doping layer in the source-drain opening 207, the source-drain doping layer contains second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions. Since the diffusion coefficient of the ions with a larger atomic number is also lower among the ions of the same type, and the corresponding diffusion rate is also lower, therefore, in the subsequent annealing process, the diffusion rate of the second ions is suppressed by the first ions with a lower diffusion rate, thereby reducing the diffusion of the first ions to the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0087] In this embodiment, the method for forming the first inhibition layer 209 includes: performing the first ion implantation on the source / drain opening 207 to form the first inhibition layer 209 .

[0088] In this embodiment, the implantation angle of the first ions is 75° to 80°, where the implantation angle is the angle between the implantation direction and the top surface of the substrate 200 .

[0089] Please refer to Fig. 9 After forming the first inhibition layer 209, the barrier layer 208 is removed.

[0090] The process of removing the barrier layer 208 includes one or more combinations of a wet etching process and a dry etching process. In this embodiment, the process of removing the barrier layer 208 adopts a wet etching process.

[0091] Please refer to Fig.10 After removing the barrier layer 208 , a second inhibition layer 210 is formed on the sidewalls and bottom surfaces of the source / drain opening 207 , and the second inhibition layer 210 is doped with the first ions.

[0092] The first ions in the second inhibition layer 210 can further suppress the diffusion rate of the second ions, thereby reducing the diffusion of the first ions into the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0093] In this embodiment, the process of forming the second inhibition layer 210 on the surface of the source / drain opening 207 includes an epitaxial process, and the first ion doping process includes an in-situ doping process.

[0094] In this embodiment, the thickness of the second inhibition layer 210 is 5 angstroms to 30 angstroms, and the doping dose of the first ions in the second inhibition layer 210 is 1E19 atom / cm 3 ~1E21atom / cm 3 .

[0095] Please refer to Fig.11 A source-drain doping layer 211 is formed in the source-drain opening 207 , and the source-drain doping layer 211 has second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions.

[0096] In this embodiment, the first ion and the second ion are N-type ions; the first ion is an arsenic ion, and the second ion is a phosphorus ion. In other embodiments, the first ion and the second ion may also be P-type ions; the first ion is an indium ion, and the second ion is a boron ion.

[0097] In this embodiment, the method for forming the source-drain doped layer 211 in the source-drain opening 207 includes: forming an epitaxial layer in the source-drain opening 207 using an epitaxial growth process; in-situ doping the epitaxial layer during the epitaxial growth process, doping the second ions into the epitaxial layer to form the source-drain doped layer 211.

[0098] In this embodiment, the doping dose of the second ions in the source-drain doping layer 211 is 1E17 atom / cm 3 ~1E21atom / cm 3 .

[0099] Please refer to Fig.12 After forming the source-drain doping layer 211 , the source-drain doping layer 211 is annealed.

[0100] The purpose of annealing the source-drain doped layer 211 is to activate the second ions in the source-drain doped layer 211 through the annealing process and diffuse the second ions into the fin, thereby forming source-drain doped regions.

[0101] The annealing process includes a laser annealing process; the annealing temperature is 1000° C. to 1500° C. In this embodiment, the annealing temperature is 1200° C. to 1500° C.

[0102] Annealing treatment at a temperature range of 1000° C. to 1500° C. can ensure that the second ions in the source-drain doping layer 211 are completely activated, while also preventing the second ions from excessively diffusing into the channel region, thereby affecting the electrical properties of the ultimately formed semiconductor structure.

[0103] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.11 , including: a substrate 200; a gate structure 202 and a sidewall 203 located on the substrate 200; source and drain openings located in the substrate 200 on both sides of the gate structure 202; a first inhibition layer 209 located in the substrate 200 at the sidewalls and bottom of the source and drain openings, the first inhibition layer 209 surrounds the source and drain openings, and the first inhibition layer 209 has first ions; a source and drain doping layer 211 located in the source and drain openings, the source and drain doping layer 211 has second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions.

[0104] Through the first inhibition layer 209 located in the substrate 200, the first inhibition layer 209 surrounds the source-drain opening 207, and the first inhibition layer 209 contains first ions; the source-drain doping layer 211 located in the source-drain opening 207, the source-drain doping layer 211 contains second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions. Since among the same type of ions, the diffusion coefficient of the ions with larger atomic numbers is lower, and the corresponding diffusion rate is also lower, therefore, in the subsequent annealing process, the diffusion rate of the second ions is suppressed by the first ions with lower diffusion rate, thereby reducing the diffusion of the first ions to the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0105] In this embodiment, the doping dose of the second ion is 1E17atom / cm 3 ~1E21atom / cm 3 .

[0106] In this embodiment, the substrate 200 has a plurality of separate fins 201 , the gate structure 202 and the sidewall spacer 203 span the fins 201 , and the gate structure 202 and the sidewall spacer 203 cover a portion of the top and sidewall surfaces of the fins 201 .

[0107] In this embodiment, the first ion and the second ion are N-type ions; the first ion is an arsenic ion, and the second ion is a phosphorus ion. In other embodiments, the first ion and the second ion may also be P-type ions; the first ion is an indium ion, and the second ion is a boron ion.

[0108] In this embodiment, the source / drain openings expose a portion of the bottom surface of the sidewall spacer 203 .

[0109] A portion of the bottom surface of the sidewall 203 is exposed through the source / drain opening, the source / drain opening in the structure is enlarged, and the volume of the corresponding source / drain doped layer 211 is also enlarged. Since the contact between the plug formed in the subsequent process and the source / drain doped layer is a full-coverage contact, that is, the plug fully covers the surface of the source / drain doped layer 211, the surface area of ​​the source / drain doped layer 211 is large, and the contact area with the plug is correspondingly large, which can reduce the contact resistance of the formed semiconductor structure, thereby improving the performance of the device.

[0110] In this embodiment, it also includes: a second inhibition layer 210 located on the sidewalls and bottom surfaces of the source / drain openings, the second inhibition layer 210 has the first ions therein, and the source / drain doping layer 211 is located on the second inhibition layer 210 .

[0111] The first ions in the second inhibition layer 210 can further suppress the diffusion rate of the second ions, thereby reducing the diffusion of the first ions into the channel region, reducing the length of the channel region, and improving the electrical performance of the final semiconductor structure.

[0112] In this embodiment, the thickness of the second inhibition layer 210 is 5 angstroms to 30 angstroms, and the doping dose of the first ion in the second inhibition layer 210 is 1E19 atom / cm 3 ~1E21atom / cm 3 .

[0113] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a gate structure located on the substrate; Source and drain openings located in the substrate on both sides of the gate structure, the source and drain openings being U-shaped; a first inhibition layer located in the substrate, the first inhibition layer is in a U-shape and surrounds the source-drain opening, and the first inhibition layer has first ions therein, and the first inhibition layer is formed by implanting the first ions into the source-drain opening; a second inhibition layer located on the sidewalls and bottom surfaces of the source / drain openings, the second inhibition layer having the first ions therein, a source / drain doping layer located on the second inhibition layer, and the second inhibition layer being U-shaped and located on the first inhibition layer; A source-drain doping layer is located in the source-drain opening, wherein the source-drain doping layer has second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions, and the first ions with a lower diffusion rate suppress the diffusion rate of the second ions, thereby reducing the diffusion of the first ions into the channel region.

2. The semiconductor structure according to claim 1, wherein: Also includes: A sidewall is located on the substrate.

3. The semiconductor structure according to claim 2, wherein: The substrate is provided with a plurality of fins separated from each other. The gate structure and the sidewalls span across the fins, and the gate structure and the sidewalls cover a portion of the top of the fins and the sidewall surfaces of the fins.

4. The semiconductor structure according to claim 1, wherein: The first ion and the second ion are N-type ions; the first ion is an arsenic ion, and the second ion is a phosphorus ion.

5. The semiconductor structure according to claim 1, wherein: The first ions and the second ions are P-type ions; the first ions are indium ions, and the second ions are boron ions.

6. The semiconductor structure according to claim 2, wherein: The source / drain openings expose a portion of the bottom surface of the sidewall.

7. The semiconductor structure according to claim 1, wherein: The thickness of the second inhibition layer is 5 angstroms to 30 angstroms, and the doping dose of the first ion in the second inhibition layer is 1E19 atom / cm 2 ~1E21atom / cm 2 .

8. The semiconductor structure according to claim 1, wherein: The doping dose of the second ion is 1E17atom / cm 2 ~1E21atom / cm 2 .

9. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a gate structure on the substrate; Forming source and drain openings in the substrate at both sides of the gate structure respectively, wherein the source and drain openings are U-shaped; A first inhibition layer is formed in the substrate, the first inhibition layer is in a U-shape and surrounds the source / drain opening, and the first inhibition layer has first ions; wherein, The method for forming the first inhibition layer includes: performing the first ion implantation on the source / drain opening to form the first inhibition layer; After forming the first inhibition layer in the substrate, forming a second inhibition layer on the sidewalls and bottom surfaces of the source / drain openings, wherein the second inhibition layer is doped with the first ions and is U-shaped and located on the first inhibition layer; A source-drain doping layer is formed in the source-drain opening, wherein the source-drain doping layer has second ions, the first ions are of the same type as the second ions, and the atomic number of the first ions is greater than the atomic number of the second ions, and the first ions having a lower diffusion rate suppress the diffusion rate of the second ions, thereby reducing the diffusion of the first ions into the channel region.

10. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: A sidewall spacer is formed on the substrate.

11. The method for forming a semiconductor structure according to claim 10, wherein: The substrate is provided with a plurality of fins separated from each other. The gate structure and the sidewalls span across the fins, and the gate structure and the sidewalls cover a portion of the top and sidewall surfaces of the fins.

12. The method for forming a semiconductor structure according to claim 9, wherein: The first ion and the second ion are N-type ions; the first ion is an arsenic ion, and the second ion is a phosphorus ion.

13. The method for forming a semiconductor structure according to claim 9, wherein: The first ions and the second ions are P-type ions; the first ions are indium ions, and the second ions are boron ions.

14. The method for forming a semiconductor structure according to claim 9, wherein: The implantation angle of the first ions is 75° to 80°, and the implantation angle is the angle between the implantation direction and the top surface of the substrate.

15. The method for forming a semiconductor structure according to claim 9, wherein: Before performing the first ion implantation on the source / drain opening, the method further includes: forming a barrier layer on the bottom surface of the source / drain opening; and removing the barrier layer after the first ion implantation.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the barrier layer includes an organic material.

17. The method for forming a semiconductor structure according to claim 15, wherein: The process of removing the barrier layer includes one or more combinations of a wet etching process and a dry etching process.

18. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: The sidewall surface exposed by the source / drain opening is etched until the source / drain opening exposes a portion of the bottom surface of the sidewall.

19. The method for forming a semiconductor structure according to claim 18, wherein: The process of etching the source / drain openings includes one or more combinations of a wet etching process and a dry etching process.

20. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the second inhibition layer on the surface of the source / drain opening includes an epitaxial process, and the first ion doping process includes an in-situ doping process.

21. The method for forming a semiconductor structure according to claim 9, wherein: The thickness of the second inhibition layer is 5 angstroms to 30 angstroms, and the doping dose of the first ion in the second inhibition layer is 1E19 atom / cm 2 ~1E21atom / cm 2 .

22. The method for forming a semiconductor structure according to claim 9, wherein: The doping concentration of the second ion is 1E17atom / cm 3 ~1E21atom / cm 3 .

23. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming a source-drain doped layer in the source-drain opening comprises: forming an epitaxial layer in the source-drain opening by using an epitaxial growth process; in-situ doping the epitaxial layer during the epitaxial growth process, doping the second ions into the epitaxial layer to form the source-drain doped layer.

24. The method for forming a semiconductor structure according to claim 9, wherein: After forming the source-drain doping layer, the method further includes: performing annealing treatment on the source-drain doping layer.

25. The method for forming a semiconductor structure according to claim 24, wherein: The annealing treatment includes a laser annealing process.

26. The method for forming a semiconductor structure according to claim 24, wherein: The temperature of the annealing treatment is 1000°C to 1500°C.

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