Light emitting element and method for manufacturing the same

Abstract

A light emitting element and a method for manufacturing the same are disclosed. The light emitting element includes a semiconductor stack including a first semiconductor layer, an active region, a second semiconductor layer, and an exposed region including an upper surface of the first semiconductor layer and a sidewall of the semiconductor stack; a first protective layer covering the exposed region and the semiconductor stack; a dielectric material stack on the semiconductor stack including a plurality of dielectric material pairs alternately stacked by dielectric materials with different refractive indexes and one or more first openings; and a metal structure on the first reflective structure filling the one or more first openings and electrically connected to the second semiconductor layer. The first protective layer includes a first portion on the upper surface of the first semiconductor layer of the exposed region and having a first thickness, and a second portion on the second semiconductor layer and having a second thickness. The first thickness is less than the second thickness.

Description

Technical Field

[0001] The present invention relates to a light-emitting element, and more specifically, to a light-emitting element that enhances brightness. Background Technology

[0002] Solid-state light-emitting elements, such as light-emitting diodes (LEDs), have low power consumption, low heat generation, long lifespan, small size, fast response speed, and good photoelectric properties, such as stable emission wavelength. Therefore, they have been widely used in household appliances, indicator lights, and optoelectronic products.

[0003] Existing light-emitting diodes (LEDs) comprise a substrate, an n-type semiconductor layer, an active region, and a p-type semiconductor layer formed on the substrate, as well as p- and n-electrodes formed on the p-type and n-type semiconductor layers, respectively. When an LED is energized through the electrodes and subjected to a specific forward bias voltage, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer recombine in the active region to emit light. However, as LEDs are applied to various optoelectronic products, the brightness specifications of LEDs are also increasing. Improving their brightness is one of the research and development goals of those skilled in the art. Summary of the Invention

[0004] This invention discloses a light-emitting element comprising a semiconductor stack, which sequentially includes a first semiconductor layer, an active region, and a second semiconductor layer, wherein the first semiconductor layer includes a first semiconductor layer upper surface; an exposed region located within the semiconductor stack, exposing the upper surface of the first semiconductor layer; a first protective layer covering the exposed region and a portion of the second semiconductor layer; a first reflective structure located on the second semiconductor layer, including one or more first openings; and a second reflective structure located on the first reflective structure, electrically connected to the second semiconductor layer via the first openings; wherein a portion of the first protective layer is located above the upper surface of the first semiconductor layer and has a first thickness, and another portion of the first protective layer is located above the second semiconductor layer and has a second thickness, wherein the first thickness is less than the second thickness.

[0005] This invention discloses a light-emitting element comprising a semiconductor stack, sequentially including a first semiconductor layer, an active region, and a second semiconductor layer, wherein the first semiconductor layer includes a first semiconductor layer upper surface; an exposed region located within the semiconductor stack, exposing the upper surface of the first semiconductor layer; a first protective layer covering the exposed region and a portion of the second semiconductor layer; an etch stop layer located on the second semiconductor layer; a first reflective structure located on the etch stop layer, including one or more first openings, the first openings exposing the etch stop layer; a second reflective structure located on the first reflective structure, electrically connected to the etch stop layer and the second semiconductor layer via the first openings; an electrode located on the first protective layer; a second protective layer located on the electrode, covering the exposed region, including a second opening exposing the electrode; and a bonding pad connected to the electrode via the second opening. Attached Figure Description

[0006] Figure 1A This is a top view of light-emitting elements 1 and 2 according to an embodiment of the present invention;

[0007] Figure 1B This is a cross-sectional view of the light-emitting element 1 according to an embodiment of the present invention;

[0008] Figure 1C This is a partial cross-sectional view of the light-emitting element 1 according to an embodiment of the present invention;

[0009] Figure 1D This is a cross-sectional view of the light-emitting element 2 according to an embodiment of the present invention;

[0010] Figure 1E This is a partial cross-sectional view of the light-emitting element 2 according to an embodiment of the present invention;

[0011] Figures 2A to 2H This is a top view of each stage in a method for manufacturing a light-emitting element 1 according to an embodiment of the present invention;

[0012] Figures 3A to 3F This is a cross-sectional view of each stage in a method for manufacturing a light-emitting element 1 according to an embodiment of the present invention;

[0013] Figures 4A to 4C This is a cross-sectional view of a portion of the manufacturing process of a light-emitting element 1 according to an embodiment of the present invention;

[0014] Figure 5A and Figure 5B This is a cross-sectional view of a portion of the manufacturing process of a light-emitting element 1 according to an embodiment of the present invention;

[0015] Figure 6A and Figure 6B This is a partially enlarged cross-sectional view of the first reflective structure in the light-emitting element 1 according to an embodiment of the present invention;

[0016] Figures 7A to 7IThis is a top view of each stage in a method for manufacturing a light-emitting element 2 according to an embodiment of the present invention;

[0017] Figures 8A to 8G This is a cross-sectional view of each stage in a method for manufacturing a light-emitting element 2 according to an embodiment of the present invention;

[0018] Figures 9A to 9C This is a cross-sectional view of a portion of the manufacturing process of the light-emitting element 2 according to an embodiment of the present invention;

[0019] Figure 10A and Figure 10B This is a cross-sectional view of a portion of the manufacturing process of the light-emitting element 2 according to an embodiment of the present invention;

[0020] Figure 11 This is a schematic diagram of a light-emitting device 3 according to an embodiment of the present invention;

[0021] Figure 12 This is a schematic diagram of a light-emitting device 4 according to an embodiment of the present invention.

[0022] Symbol Explanation

[0023] 1, 2 Light-emitting elements

[0024] 3, 4 Light-emitting devices

[0025] 10 substrate

[0026] 10a Substrate Top Surface

[0027] 12 Semiconductor stack

[0028] 121 First Semiconductor Layer

[0029] 121a First semiconductor layer upper surface

[0030] 122 Second Semiconductor Layer

[0031] 123 Active Region

[0032] 18 Transparent conductive layer

[0033] 180° transparent conductive layer opening

[0034] 26 Etching Stop Layer

[0035] 28. Exposure Area

[0036] 20 First Electrode

[0037] 30 Second electrode

[0038] 36 Second Reflection Structure

[0039] 360° Second Reflection Structure Opening

[0040] 27 Lasers

[0041] 23a Lower protective layer

[0042] 23b Upper protective layer

[0043] 23 First protective layer

[0044] 230, 231 First protective layer opening

[0045] 232 Opening of the upper protective layer

[0046] 25 Second protective layer

[0047] 251, 252 Second protective layer openings

[0048] 50 First Reflection Structure

[0049] 50a, 50b, 50c, 50d, first sublayer, second sublayer, third sublayer, fourth sublayer 501, 502 First Reflection Structure Opening

[0050] 51 Carrier Board

[0051] 511 and 512 gaskets

[0052] 53 Insulation section

[0053] 54 Reflective Structure

[0054] 602 lampshade

[0055] 604 reflector

[0056] 606 Bearing Unit

[0057] 608 light-emitting units

[0058] 610 Light-emitting module

[0059] 612 lamp holder

[0060] 614 heatsink

[0061] 616 Connecting part

[0062] 618 Electrical connection element

[0063] Thicknesses of t1, t1', T, and T'

[0064] MS high platform

[0065] ISO Aisle Area Detailed Implementation

[0066] In the following description, exemplary embodiments of the present invention will be illustrated in detail to enable those skilled in the art to fully understand the spirit of the invention. The present invention is not limited to the following embodiments, but may be implemented in other forms. In this specification, some identical symbols denote elements having the same or similar structure, function, or principle, and can be deduced by those skilled in the art from the teachings of this specification. For the sake of brevity, elements with the same symbols will not be repeated.

[0067] Figure 1A This shows a top view of a light-emitting element 1 according to an embodiment of the present invention. Figures 2A to 2H The top view shows each stage of a method for manufacturing a light-emitting element 1 according to an embodiment of the present invention; Figures 3A to 3F Cross-sectional views of each stage in the manufacturing method of light-emitting element 1 are shown. The manufacturing method of light-emitting element 1 is described in detail below. First, refer to... Figure 2A and Figure 3A A semiconductor stack 12 is formed above the substrate 10, and a lower protective layer 23a is formed on the semiconductor stack 12. Next, referring to… Figure 2B and Figure 3A A transparent conductive layer 18 is formed on the semiconductor stack 12. Figure 3A show Figure 2A and Figure 2B After the steps are completed, a cross-sectional view is taken along line segment A-A'. The substrate 10 can be a wafer, which together with the semiconductor stack 12 formed thereon constitutes a semiconductor wafer. The semiconductor wafer is separated into multiple light-emitting elements 1 after subsequent dicing and fabrication processes. The following embodiment illustrations and descriptions will use a single light-emitting element 1 as an example.

[0068] The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for growing gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate 10 includes an upper surface 10a. The substrate 10 may be a patterned substrate, i.e., the substrate 10 has a patterned structure (not shown) on its upper surface 10a. In one embodiment, light emitted from the semiconductor stack 12 can be refracted and / or reflected by the patterned structure of the substrate 10, thereby improving the brightness of the light-emitting element. Furthermore, the patterned structure mitigates or suppresses misalignment between the substrate 10 and the semiconductor stack 12 caused by lattice mismatch, thereby improving the epitaxial quality of the semiconductor stack 12.

[0069] In one embodiment of this application, the method for forming a semiconductor stack 12 on a substrate 10 includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation.

[0070] A buffer structure (not shown), a first semiconductor layer 121, an active region 123, and a second semiconductor layer 122 are sequentially formed on a substrate 10. The buffer structure, the first semiconductor layer 121, the active region 123, and the second semiconductor layer 122 constitute a semiconductor stack 12. The buffer structure can reduce the aforementioned lattice mismatch and suppress dislocations, thereby improving epitaxial quality. The material of the buffer layer includes GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes multiple sublayers (not shown). The sublayers may be made of the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the first sublayer is grown by sputtering and the second sublayer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The third sublayer is grown by MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second, and third sublayers include the same material, such as AlN, or different materials, such as AlN, GaN, or AlGaN. In one embodiment of this application, the first semiconductor layer 121 and the second semiconductor layer 122, such as cladding layers or confinement layers, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 121 is an n-type semiconductor, and the second semiconductor layer 122 is a p-type semiconductor. An active region 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. Electrons and holes combine in the active region 123 under the drive of an electric current, converting electrical energy into light energy to emit light. The wavelength of the light emitted by the light-emitting element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 12.

[0071] The material of semiconductor stack 12 includes Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)The active region 123 is a III-V group semiconductor material, where 0 ≤ x, y ≤ 1; x + y ≤ 1. Depending on the material of the active region, when the semiconductor stack 12 is made of the AlInGaP series, it can emit red light with wavelengths between 610 nm and 650 nm, or yellow light with wavelengths between 550 nm and 570 nm. When the semiconductor stack 12 is made of the InGaN series, it can emit blue or deep blue light with wavelengths between 400 nm and 490 nm, or green light with wavelengths between 490 nm and 550 nm. When the semiconductor stack 12 is made of the AlGaN series, it can emit UV light with wavelengths between 400 nm and 250 nm. The active region 123 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The active region 123 can be an i-type, p-type, or n-type semiconductor.

[0072] Next, the step of forming an exposed area 28 is carried out. See [link / reference] Figure 3A In this step, a portion of the active region 123 and the first semiconductor layer 121 is removed downwards from the upper surface of the second semiconductor layer 122, exposing the upper surface 121a of the first semiconductor layer and forming an exposed region 28. See also Figure 2A Relative to exposed region 28, other regions of the semiconductor stack 12 form a raised platform MS. In this embodiment, exposed region 28 includes a surrounding region around the semiconductor stack 12 and an internal region distributed within the semiconductor stack 12. Each exposed region 28 includes a sidewall formed by the side surface of the semiconductor stack 12 and a bottom formed by the upper surface 121a of the first semiconductor layer. Then, in one embodiment, a portion of the first semiconductor layer 121 outside the surrounding region of the semiconductor stack 12 is further removed, exposing the upper surface 10a of the substrate, forming a walkway region ISO. The walkway region ISO separates and defines a plurality of light-emitting units 1 and serves as the location of pre-cutting lines (not shown) in subsequent dicing processes. In one embodiment, as... Figure 2A As shown, the outline of the platform MS is wavy, sawtooth, square wave or other non-linear pattern. The light extraction efficiency of the light-emitting element 1 can be improved by designing the pattern of the platform MS outline.

[0073] Next, refer to the same method. Figure 2A and Figure 3AA lower protective layer 23a is formed on the exposed area 28. The lower protective layer 23a covers the bottom, sidewalls, and part of the second semiconductor layer 122 of the exposed area 28. The lower protective layer 23a is transparent to light emitted from the semiconductor stack 12, and its material is a non-conductive material, including organic or inorganic materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide, or fluorocarbon polymer. Inorganic materials include, for example, silicone, glass, or dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), niobium oxide (Nb₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂) x Materials include magnesium fluoride (MgF2) and aluminum oxide (Al2O3). The lower protective layer 23a can be formed by methods such as atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. In another embodiment, the lower protective layer 23a further covers the sidewalls of the first semiconductor layer 121 around the semiconductor stack 12.

[0074] To clearly show the top view of each stage in the manufacturing process of the light-emitting element 1, Figures 2B to 2H It can only show the layers formed by the current step and the MS platform, or it can show the layers formed by the previous step.

[0075] After the lower protective layer 23a is formed, refer to Figure 2B and Figure 3A The step of forming a transparent conductive layer 18 is performed. Figure 2BOnly the upper semiconductor layer (MS) and the transparent conductive layer 18 are shown. The transparent conductive layer 18 covers the upper surface of the second semiconductor layer 122 and is in electrical contact with the second semiconductor layer 122, including an opening 180 correspondingly formed on the exposed area 28. The transparent conductive layer 18 can be a metal or a transparent conductive material. The metal can be selected from a thin metal layer with light transmittance, and the transparent conductive material is transparent to the light emitted from the active area 123, including materials such as graphene, indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc oxide (ZnO), or indium zinc oxide (IZO). In one embodiment, the transparent conductive layer 18 covers a portion of the lower protective layer 23a. In another embodiment, the transparent conductive layer 18 does not cover the lower protective layer 23a. In another embodiment, the transparent conductive layer 18 can be formed first, and then the lower protective layer 23a can be formed.

[0076] Next, refer to Figure 2C , Figure 3B and Figure 3C The first reflective structure 50 is formed by implementing the following steps. Figure 3B show Figures 2A to 2C After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 2C Only the raised platform MS and the first reflective structure 50 are shown. The first reflective structure 50 is first formed on the upper surface of the second semiconductor layer 122. Then, using fabrication processes such as developing and etching, mutually separated openings 501 and 502 are formed in the first reflective structure 50. The position of opening 501 corresponds to the exposed area 28 and the transparent conductive layer opening 180. Opening 502 is distributed on the second semiconductor layer 122 and exposes the transparent conductive layer 18 below it.

[0077] In one embodiment, Figure 6A This shows a partially enlarged cross-sectional view of the first reflective structure 50, which is formed by alternating stacking of one or more pairs of materials with different refractive indices. In this embodiment, as... Figure 5A As shown, the first reflective structure 50 comprises a set of material layers, such as dielectric materials, consisting of alternating stacks of a first sublayer 50a and a second sublayer 50b. A first sublayer 50a and a second sublayer 50b form a dielectric material pair. The first sublayer 50a has a higher refractive index than the second sublayer 50b, and in one embodiment, the first sublayer 50a has a smaller thickness than the second sublayer 50b. Dielectric materials include, for example, silicon oxide, silicon nitride, silicon oxynitride, niobium oxide, hafnium oxide, titanium oxide, magnesium fluoride, aluminum oxide, etc. By selecting materials with different refractive indices and combining their thicknesses, a material stack is formed to constitute the first reflective structure 50, providing reflection functionality for light within a specific wavelength range, such as a distributed Bragg reflector (DBR).

[0078] In one embodiment, the first reflective structure 50 may further include layers other than the first sublayer 50a and the second sublayer 50b. For example, the first reflective structure 50 may further include a bottom layer (not shown) located between the first sublayer 50a (and / or the second sublayer 50b) and the semiconductor stack 12. That is, the bottom layer is formed first on the semiconductor stack 12, and then the first sublayer 50a and the second sublayer 50b are formed. The bottom layer is a non-conductive material, comprising organic or inorganic materials, wherein the inorganic material may be a dielectric material. The thickness of the bottom layer is greater than the thickness of the first sublayer 50a and the second sublayer 50b. In one embodiment, the bottom layer is formed differently from the first sublayer 50a and the second sublayer 50b; for example, the bottom layer is formed by chemical vapor deposition (CVD), more preferably by plasma-enhanced chemical vapor deposition (PECVD). The first sublayer 50a and the second sublayer 50b are formed by sputtering.

[0079] In another embodiment, such as Figure 6B As shown, the first reflective structure 50 comprises multiple sets of material stacks. The first set of material stacks consists of alternating stacks of a first sublayer 50a and a second sublayer 50b, and the second set of material stacks consists of alternating stacks of a third sublayer 50c and a fourth sublayer 50d. In one embodiment, the second set of material stacks is, for example, a dielectric material, consisting of a third sublayer 50c and a fourth sublayer 50d forming a dielectric material pair. The third sublayer 50c has a higher refractive index than the fourth sublayer 50d, and in one embodiment, the third sublayer 50c has a smaller thickness than the fourth sublayer 50d. The third sublayer 50c has a different thickness than the first sublayer 50a, and the third sublayer 50c and the first sublayer 50a can be made of the same material or different materials. The fourth sublayer 50d has a different thickness than the second sublayer 50b, and the fourth sublayer 50d and the second sublayer 50b can be made of the same material or different materials.

[0080] In another embodiment, the first reflective structure 50 may further include an upper layer (not shown) located on the first sub-layer 50a (and / or the second sub-layer 50b) on the opposite side of the second semiconductor layer 122. That is, the first sub-layer 50a and the second sub-layer 50b are formed on the semiconductor stack 12 first, and then the upper layer is formed. The upper layer is a non-conductive material, comprising organic or inorganic materials, wherein the inorganic material may be a dielectric material. The thickness of the upper layer is greater than the thickness of the first sub-layer 50a and the second sub-layer 50b. In one embodiment, the upper layer is formed differently from the first sub-layer 50a and the second sub-layer 50b; for example, the upper layer is formed by chemical vapor deposition, more preferably by plasma-enhanced chemical vapor deposition (PECVD). The first sub-layer 50a and the second sub-layer 50b are formed by sputtering.

[0081] In another embodiment, the first reflective structure 50 includes multiple material stacks and a bottom layer and / or an upper layer. In another embodiment, prior to forming the first reflective structure 50, a uniform dense layer (not shown) is formed on a surface of the substrate 10 and the semiconductor stack 12 by atomic deposition to directly cover the surface of the semiconductor stack 12. In one embodiment, the dense layer can more densely cover and fill surface defects of the semiconductor stack 12, preventing moisture intrusion. The material of the dense layer includes inorganic materials, such as silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, yttrium oxide, lanthanum oxide, tantalum oxide, silicon nitride, aluminum nitride, or silicon oxynitride. In this embodiment, the interface between the dense layer and the semiconductor stack 12 includes a metal element and oxygen, wherein the metal element includes aluminum, hafnium, tantalum, zirconium, yttrium, lanthanum, or tantalum. The dense layer includes a thickness between Between, preferably in between.

[0082] In one embodiment, the thickness of the first reflective structure 50 is between 0.3 μm and 6 μm. In another embodiment, the angle between the sidewalls of the first reflective structure 50, such as the sidewalls of openings 501 and 502, and the inner angle of the transparent conductive layer 18 is between 5 degrees and 80 degrees.

[0083] In one embodiment, the first reflective structure 50 does not have an opening 502 between adjacent openings 501.

[0084] In another embodiment, the first reflective structure 50 is not as... Figure 2C Instead of having multiple openings 501, 502, they are distributed as multiple separate islands (not shown) on the second semiconductor layer 122.

[0085] Next, refer to Figure 2D and Figure 3C The second reflection structure 36 is formed by implementing the following steps. Figure 3C show Figures 2A to 2D After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 2D Only the raised platform MS and the second reflective structure 36 are shown. The second reflective structure 36 is formed on the transparent conductive layer 18 and the first reflective structure 50, and is electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 through the opening 502 of the first reflective structure 50. It includes a plurality of openings 360 corresponding to the openings 501 of the first reflective structure 50, formed on the exposed area 28. The second reflective structure 36 includes a metal structure, which may include a single layer of metal or a stack formed of multiple layers of metal. In one embodiment, the second reflective structure 36 includes a barrier layer (not shown) and a reflective layer (not shown). The barrier layer is formed and covers the reflective layer, and the barrier layer can prevent the migration, diffusion or oxidation of the metal elements of the reflective layer. The material of the reflective layer includes a metal material with high reflectivity to the light emitted by the semiconductor stack 12, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), or alloys or stacks of the above materials. The barrier layer is made of materials including chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. In one embodiment, when the barrier layer is a metal stack, it is formed by alternating stacks of two or more metals, such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn. In another embodiment (not shown), the first reflective structure 50 comprises a plurality of islands distributed on the second semiconductor layer 122, and the second reflective structure 36 is electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 via gaps between the islands.

[0086] Next, refer to Figure 2E and Figure 3D The upper protective layer 23b is formed by performing the following steps. Figure 3D show Figures 2A to 2E After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 2E Only the platform MS, the second reflective structure 36, and the upper protective layer 23b are shown. The upper protective layer 23b is formed on the second reflective structure 36, covering part of the upper surface of the second reflective structure 36, and covering the lower protective layer 23a. In and near the exposed area 28, the upper protective layer 23b overlaps and connects with the lower protective layer 23a.

[0087] The upper protective layer 23b includes openings 230, 231, and 232. (See reference...) Figure 2EMultiple openings 230 are spaced apart around the upper protective layer 23b, exposing the bottom of the exposed area 28 around the semiconductor stack 12, which is the upper surface 121a of the first semiconductor layer. Their function and corresponding cross-sectional structure will be described in detail later. Multiple openings 231 are disposed within the exposed area 28 inside the semiconductor stack 12, exposing the bottom of the exposed area 28 and the upper surface 121a of the first semiconductor layer. Opening 232 exposes the second reflective structure 36. In this embodiment, only a single opening 232 is shown; however, the invention is not limited to this, and the upper protective layer 23b may contain multiple openings 232 to expose the second reflective structure 36 respectively. In one embodiment, an insulating material is first formed to cover the second reflective structure 36 and the exposed area 28, and then openings 230, 231, and 232 are formed using methods such as developing and etching to form the upper protective layer 23b. Simultaneously with the formation of openings 230 and 231, the lower protective layer 23a directly below the openings 230 and 231 is also removed. The upper protective layer 23b and the lower protective layer 23a constitute a first protective layer 23. The upper protective layer 23b and the lower protective layer 23a can be made of the same material or different materials. That is, the first protective layer 23 has a plurality of openings 230 spaced around it, exposing the upper surface 121a of the first semiconductor layer, and a plurality of openings 231 disposed in the exposure area 28 inside the semiconductor stack 12, exposing the bottom of the upper surface 121a of the first semiconductor layer in the exposure area 28. The upper protective layer 23b is transparent to light emitted from the semiconductor stack 12, and its material is a non-conductive material, including organic or inorganic materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyimide, polyetherimide, or fluorocarbon polymer. Inorganic materials include silicone, glass, or dielectric materials. Dielectric materials include, for example, silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), niobium oxide (Nb₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂) xMaterials used include magnesium fluoride (MgF2) and aluminum oxide (Al2O3). The lower protective layer 23a can be formed using methods such as atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. Since the first protective layer 23 covers the sidewalls of the exposed area 28, i.e., the sidewalls of the semiconductor stack 12, it protects the semiconductor stack 12 and prevents potential damage to it during subsequent fabrication processes. In another embodiment, the upper protective layer 23b also covers the sidewalls of the first semiconductor layer 121 around the semiconductor stack 12.

[0088] Next, refer to Figure 2F and Figure 3E Then, perform an electrode formation step. Figure 3E show Figures 2A to 2F After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 2F Only the platform MS, the upper protective layer 23b, and the electrodes are shown. The electrodes include a first electrode 20 and a second electrode 30. The first electrode 20 covers the upper protective layer 23b and, through openings 230 and 231 in the upper protective layer 23b, contacts and electrically connects to the first semiconductor layer 121 at the bottom of the exposed area 28. The second electrode 30 is separate from the first electrode 20 and is formed in an opening 232 in the upper protective layer 23b, contacting the second reflective structure 36 and electrically connecting to the second semiconductor layer 122. The electrodes contain metallic materials, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials.

[0089] Next, refer to Figure 2G Then, implement the second protective layer formation step. (Refer to...) Figure 2H Implement a pad formation step. Figure 3F show Figures 2A to 2G After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 2G Only the platform MS, the first electrode 20, the second electrode 30, and the second protective layer 25 are shown.

[0090] A second protective layer 25 is formed on the first electrode 20, the second electrode 30, and the exposed area 28, and extends to cover the sidewalls and the channel area ISO of the first semiconductor layer 121. The second protective layer 25 includes openings 251 and 252, wherein opening 251 exposes the first electrode 20 and opening 252 exposes the second electrode 30. In this embodiment, only a single opening 251 and a single opening 252 are shown; however, the invention is not limited thereto, and the upper protective layer 23b may include multiple openings 251 and 252. The material of the second protective layer 25 includes non-conductive materials, comprising organic or inorganic materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide, or fluorocarbon polymer. Inorganic materials include silicone, glass, or dielectric materials, such as silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), niobium oxide (Nb₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂) x Materials used include magnesium fluoride (MgF2), aluminum oxide (Al2O3), etc. In one embodiment, the second protective layer 25 is formed by alternating stacks of one or more pairs of materials with different refractive indices. By selecting materials with different refractive indices and designing their thickness, the second protective layer 25 forms a reflective structure that provides reflection of light within a specific wavelength range, such as a distributed Bragg reflector. In one embodiment, similar to the first reflective structure 50, the second protective layer 25 comprises one or more sets of material stacks, along with a bottom layer and / or an upper layer. In one embodiment, the second protective layer 25 with a distributed Bragg reflector covers the sidewall of the semiconductor stack 12 located in the walkway region ISO, which facilitates light extraction near the walkway region ISO and enhances the brightness of the light-emitting element 1. In one embodiment, the second protective layer 25 with a distributed Bragg reflector comprises m pairs of dielectric materials, and the first reflective structure 50 comprises n pairs of dielectric materials, where m is greater than n. In one embodiment, the thickness of the second protective layer is greater than the thickness of the first reflective structure 50.

[0091] In one embodiment, the thickness of the second protective layer 25 can be from 1 μm to 6 μm. If the thickness of the second protective layer 25 is less than 1 μm, the thinner thickness may weaken the insulation and moisture resistance of the second protective layer 25, reducing the reliability of the light-emitting element 1. In one embodiment, the thickness of the second protective layer 25 is greater than the thickness of the upper protective layer 23b.

[0092] Next, refer to Figure 2H A first solder pad 80a and a second solder pad 80b are formed in openings 251 and 252, respectively. Figure 2H Only the platform MS, first electrode 20, second electrode 30, second protective layer 25, and solder pads are shown. First solder pad 80a is connected to first electrode 20 and electrically connected to first semiconductor layer 121. Second solder pad 80b is connected to second electrode 30 and electrically connected to second semiconductor layer 122. First solder pad 80a and second solder pad 80b contain metallic materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or layers or alloys of these materials. First solder pad 80a and second solder pad 80b can consist of a single layer or multiple layers. For example, first solder pad 80a and second solder pad 80b may include Ti / Au, Ti / Pt / Au, Cr / Au, Cr / Pt / Au, Ni / Au, Ni / Pt / Au, or Cr / Al / Cr / Ni / Au. After the subsequent dicing process is completed and the independent light-emitting element 1 is formed, the first solder pad 80a and the second solder pad 80b are flip-chip bonded to the circuitry on a carrier board (not shown) to achieve connection with external electronic components or an external power supply. In another embodiment, the first solder pad 80a and / or the second solder pad 80b may further cover the second protective layer 25. In another embodiment, the first solder pad 80a and / or the second solder pad 80b may avoid the exposed area 28 being distributed in the internal region within the semiconductor stack 12 to prevent possible delamination between the solder pads and the interfaces of the semiconductor stack 12 due to height differences. The surfaces of the first solder pad 80a and the second solder pad 80b have multiple recesses (not shown) corresponding to the openings 502 of the first reflective structure 50. These recesses can improve the bonding force between the solder pads and the carrier board in subsequent packaging processes, thereby improving the manufacturing yield.

[0093] Finally, along the walkway area ISO, that is, around each light-emitting element 1, the semiconductor wafer is divided to form a plurality of light-emitting elements 1. In one embodiment, as... Figure 3FAs shown, the lower surface of the substrate 10 is irradiated with a laser 27, which is focused inside the substrate 10, causing a modified region (not shown) to be formed inside the substrate 10. Cracks are then formed along the crystal plane of the substrate 10 from the modified region to separate each light-emitting element 1. However, the cutting method in this embodiment is not limited to this, and any other method suitable for cutting a wafer into light-emitting elements may also be applied.

[0094] In one embodiment, Figures 4A to 4C In the manufacturing method of display light-emitting element 1, in the process of display light-emitting element 1 Figures 2A to 2E The section view along "AA" in the steps. Figure 4A The lower protective layer 23a, the transparent conductive layer 18, and the material layer of the first reflective structure 50 are formed on the semiconductor stack 12. The thickness of the lower protective layer 23a in the exposed area 28 is t1. Next, referring to... Figure 4B The first reflective structure 50 material layer is etched to form openings 501 and 502, and the material layer above the exposed area 28 is removed. The etching includes dry etching, such as inductively coupled plasma (ICP) etching. In one embodiment, the etching includes a combination of dry and wet etching. When etching the first reflective structure 50 material layer to form opening 502, the second semiconductor layer 122 is not damaged by etching because the transparent conductive layer 18 covers it. In one embodiment, the transparent conductive layer 18 can serve as an etching stop layer. When etching the first reflective structure 50 material layer to form opening 501 and removing the material layer above the exposed area 28, the first semiconductor layer 121 at the bottom of the exposed area 28 is not damaged by etching because the lower protective layer 23a covers it. After the etching of the first reflective structure 50 is completed, the lower protective layer 23a located in the exposed area 28 has a thickness t1'. The thickness t1' is greater than... Furthermore, the thickness t1' is less than the thickness t1. By covering the exposed area 28 with the lower protective layer 23a to protect the first semiconductor layer 121, it can be ensured that the opening 501 of the first reflective structure 50 can be fully opened, that no material layer remains above the exposed area 28, and that the first semiconductor layer 121 is not damaged. In another embodiment, not all the material layers of the first reflective structure 50 on the exposed areas 28 are removed, but only the material layers of the first reflective structure 50 on the exposed areas 28 located inside the semiconductor stack 12 are removed.

[0095] Next, refer to Figure 4C The second reflective structure 36, the upper protective layer 23b, and the openings 231, 232, and 230 (not shown) of the upper protective layer are formed in sequence. Figure 4CThe upper protective layer 23b and the lower protective layer 23a constitute the first protective layer 23. The upper protective layer 23b is superimposed on and connected to the lower protective layer 23a on the exposed area 28 and the second semiconductor layer 122 near the exposed area 28. While forming the openings 230 and 231, the lower protective layer 23a directly below the openings 230 and 231 is also removed. That is, the first protective layer 23 has multiple openings 230 spaced around it, exposing the upper surface 121a of the first semiconductor layer, and multiple openings 231 disposed within the exposed area 28 inside the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. The thickness of the first protective layer 23 above the bottom of the exposed area 28 (i.e., the sum of the thickness t1' of the lower protective layer 23a and the thickness of the upper protective layer 23b in the exposed area 28) is T, and the thickness of the first protective layer 23 on the second semiconductor layer 122 (i.e., the sum of the thickness of the lower protective layer 23a and the thickness of the upper protective layer 23b here) is T', where T is less than T'. In one embodiment, the difference between T and T' is greater than... In another embodiment, the difference between T and T' is greater than In one embodiment, the thickness t1' of the lower protective layer 23a located in the exposed region 28 is less than the thickness t1 of the lower protective layer 23a located on the upper surface of the second semiconductor layer 122. Next, according to the aforementioned... Figures 2F to 2H The steps in the diagram are used to complete the light-emitting element 1.

[0096] Figure 5A and Figure 5B Display respectively Figures 2A to 2F After completing the steps, draw a cross-sectional view along line segments B-B' and C-C'. Refer to... Figure 2F and Figure 5A The first electrode 20 contacts the upper surface 121a of the first semiconductor layer exposed by the opening 230 of the first protective layer 23. (Refer to...) Figure 2F and Figure 5B In the area without openings 230, the first protective layer 23 covers the exposed area 28 around the semiconductor stack 12, preventing the first electrode 20 from contacting the upper surface 121a of the first semiconductor layer. In this way, around the semiconductor stack 12, the first electrode 20 contacts the upper surface 121a of the first semiconductor layer at intervals through the spaced openings 230, allowing current to diffuse uniformly around the semiconductor stack 12.

[0097] Figure 1A This shows a top view of the light-emitting element 1 manufactured according to the manufacturing method of this embodiment. Figure 1B show Figure 1A Cross-sectional view along line segment A-A'. Figure 1C show Figure 1B A magnified view of a portion of the image.

[0098] Reference Figure 1A , Figure 1B and Figure 1C The light-emitting element 1 includes a substrate 10, a semiconductor stack 12 located on the substrate 10, an exposed area 28 including a surrounding region around the semiconductor stack 12 and an internal region distributed within the semiconductor stack 12, exposing the upper surface 121a of a first semiconductor layer, a transparent conductive layer 18 located on a second semiconductor layer 122, a first reflective structure 50 located on the transparent conductive layer 18, including multiple openings 502 exposing the transparent conductive layer 18, and a second reflective structure 36 located on the first reflective structure 50, electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 via the openings 502 of the first reflective structure. The second reflective structure 36 and the first reflective structure 50 form an omnidirectional reflector (ODR), improving light reflection and the brightness of the light-emitting element 1. A first protective layer 23 covers the exposed area 28 and extends to cover part of the upper surface of the second semiconductor layer 122. The first protective layer 23 includes a lower protective layer 23a and an upper protective layer 23b. The lower protective layer 23a contacts the semiconductor stack 12. More specifically, the lower protective layer 23a contacts the sidewalls and part of the bottom of the exposed area 28. The upper protective layer 23b extends from the exposed area 28 to cover the second reflective structure 36, including an opening 232 exposing the second reflective structure 36. Furthermore, the first protective layer 23 includes an opening 231 located in the exposed area 28 within the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. In one embodiment, the first protective layer 23 further includes an opening 230 located in the exposed area 28 surrounding the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. The thickness of the first protective layer 23 above the bottom of the exposed area 28 is T, and the thickness of the first protective layer 23 on the second semiconductor layer 122 is T', where T is less than T'. In one embodiment, the difference between T and T' is greater than... In another embodiment, the difference between T and T' is greater than

[0099] The first electrode 20 covers the first protective layer 23 and is electrically connected to the first semiconductor layer 121 via openings 231 and 230 in the first protective layer. The second electrode 30 is separate from the first electrode 20, contacts the second reflective structure 36 via an upper protective layer opening 232, and is electrically connected to the second semiconductor layer 122. In one embodiment, the second electrode 30 is located in the upper protective layer opening 232. In another embodiment, the second electrode 30 is located in the upper protective layer opening 232 and extends further onto the upper protective layer 23b. The second protective layer 25 is located on the first electrode 20 and the second electrode 30, including an opening 251 exposing the first electrode 20 and an opening 252 exposing the second electrode 30. Figure 1BAs shown, the second protective layer 25 further covers the sidewalls surrounding the semiconductor stack 12 and the upper surface 10a of the substrate. In one embodiment, the second protective layer 25 includes a distributed Bragg reflector structure, which can increase light reflection around the semiconductor stack 12 and improve the brightness of the light-emitting element 1. The first pad 80a is located at the opening 251 and contacts the first electrode 20. The second pad 80b is located at the opening 252 and contacts the second electrode 30.

[0100] Figure 1A This shows a top view of a light-emitting element 2 according to an embodiment of this application. Figures 7A to 7I Top views showing the various stages of a method for manufacturing a light-emitting element 2 according to an embodiment of this application; Figures 8A to 8G Cross-sectional views of each stage in the manufacturing process of light-emitting element 2 are shown. The manufacturing process of light-emitting element 2 is detailed below. Some manufacturing processes and structures of light-emitting element 2 are similar to those of light-emitting element 1. For similar manufacturing processes and structures, please refer to the description and drawings of light-emitting element 1, which will not be repeated here. The differences will be explained in detail later. First, refer to... Figures 7A to 7B and Figure 8A The steps are as follows Figures 2A to 2B and Figure 3A As explained above, it will not be repeated here.

[0101] Next, refer to Figure 7C and Figure 8B Then, an etch stop layer 26 is formed. Figure 8B show Figures 7A to 7C After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 7C Only the platform MS, transparent conductive layer 18, and etch stop layer 26 are shown. An etch stop material layer (not shown) is first formed on the upper surface of the transparent conductive layer 18. Then, the etch stop layer 26 is formed on the upper surface of the transparent conductive layer 18 using a fabrication process such as development etching or lift-off. The etch stop layer 26 consists of multiple island-like structures that are separated from each other.

[0102] In one embodiment, the etch stop layer 26 comprises a metal, the metal material comprising a reflective metal with high reflectivity to the light emitted by the light-emitting element 2, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), or an alloy or stack of the above materials.

[0103] In one embodiment, the etch stop layer 26 includes a barrier layer (not shown) and a contact layer (not shown). The contact layer is located between the transparent conductive layer 18 and the barrier layer, and the barrier layer can prevent the migration, diffusion, or oxidation of metal elements in the contact layer. The material of the contact layer includes a metal material with high reflectivity to light emitted by the semiconductor stack 12, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), or alloys or stacks of the above materials. The material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. In one embodiment, when the barrier layer is a metal stack, the barrier layer is formed by alternating stacking of two or more metals, such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn, etc.

[0104] Next, refer to Figure 7D and Figure 8C The first reflective structure 50 is formed by implementing the following steps. Figure 8C show Figures 7A to 7D After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 7D Only the raised platform MS and the first reflective structure 50 are shown. First, a reflective material layer is formed on the upper surface of the second semiconductor layer 122. Then, using fabrication processes such as developing and etching, mutually separated openings 501 and 502 are formed in the reflective material layer to form the first reflective structure 50. The position of opening 501 corresponds to the exposed area 28 and the transparent conductive layer opening 180. Opening 502 is distributed on the second semiconductor layer 122, exposing the etch stop layer 26 beneath it. The material, stacking, thickness, and formation method of the first reflective structure 50 are described in detail below. Figures 6A to 6B As explained above, it will not be repeated here.

[0105] In one embodiment, the etch stop layer 26 includes a central portion exposed by the opening 502 and an edge portion overlapping with the first reflective structure 50. During the development and etching of the first reflective structure 50, over-etching may occur to the central portion of the etch stop layer 26, resulting in the thickness of the central portion of the etch stop layer 26 being less than that of the edge portion of the etch stop layer 26.

[0106] Next, refer to Figure 7E and Figure 8D The second reflection structure 36 is formed by implementing the following steps. Figure 8D show Figures 7A to 7E After completing the steps, a cross-sectional view along line segment A-A' is obtained. Figure 7EOnly the raised platform MS and the second reflective structure 36 are shown. The second reflective structure 36 is formed on the transparent conductive layer 18, the etch stop layer 26, and the first reflective structure 50. It is electrically connected to the etch stop layer 26, the transparent conductive layer 18, and the second semiconductor layer 122 through the opening 502 of the first reflective structure 50, and includes a plurality of openings 360 corresponding to the openings 501 of the first reflective structure 50, formed on the exposed area 28. The second reflective structure 36 includes a metal structure, which may include a single metal layer or a stack of multiple metal layers. In one embodiment, the ratio of the projected area of ​​the second semiconductor layer 122 on the substrate 10 to the projected area of ​​the second reflective structure 36 on the substrate 10 is 100% to 120%. By adjusting the area of ​​the second reflective structure 36 to be close to the projected area of ​​the second semiconductor layer 122 on the substrate 10, the reflective area of ​​the second reflective structure 36 is increased, thereby improving the light extraction efficiency of the light-emitting element. The materials, stacking, thickness, and formation methods of the second reflective structure 36, etc., are as follows: Figure 2D and Figure 3C As explained above, it will not be repeated here.

[0107] Finally, refer to Figures 7F to 7I and Figures 8E to 8G The steps are as follows Figures 2E to 2H and Figures 3D to 3F As explained above, it will not be repeated here.

[0108] In one embodiment, Figures 9A to 9C In the manufacturing method of display light-emitting element 2, Figures 7A to 7F The section view along "AA" in the steps. Figure 9A The lower protective layer 23a, the transparent conductive layer 18, the etch stop layer 26, and the first reflective structure 50 are formed on the semiconductor stack 12. A portion of the material layer of the first reflective structure 50 is formed on the lower protective layer 23a located in the exposed region 28, and the thickness of the lower protective layer 23a in the exposed region 28 is t1. Next, referring to... Figure 9BThe first reflective structure 50 material layer is etched to form openings 501 and 502, and the first reflective structure 50 material layer above the exposed area 28 is removed. The etching includes dry etching, such as inductively coupled plasma (ICP) etching. In one embodiment, the etching includes a combination of dry etching and wet etching. When etching the first reflective structure 50 material layer to form opening 502, the transparent conductive layer 18 is not damaged by etching because the etch stop layer 26 covers it. When etching the first reflective structure 50 material layer to form opening 501 and removing the first reflective structure 50 above the exposed area 28, the first semiconductor layer 121 at the bottom of the exposed area 28 is not damaged by etching because the lower protective layer 23a covers the exposed area 28. After the etching of the first reflective structure 50 is completed, the lower protective layer 23a located in the exposed area 28 has a thickness t1'. The thickness t1' is greater than... Furthermore, the thickness t1' is less than the thickness t1. By covering the exposed area 28 with the lower protective layer 23a to protect the first semiconductor layer 121, it can be ensured that the opening 501 of the first reflective structure 50 can be fully opened, no material layer remains above the exposed area 28, and the first semiconductor layer 121 is not damaged. In another embodiment, not all material layers of the first reflective structure 50 on the exposed areas 28 are removed, but only the first reflective structures 50 located in the exposed areas 28 within the semiconductor stack 12 are removed. See reference. Figure 9C The stacking relationship between the first protective layer 23 and other layers, and the thickness differences at different locations, such as Figure 4C As explained above, it will not be repeated here.

[0109] Figure 10A and Figure 10B Display respectively Figures 7A to 7G After the steps are completed, Figure 7G Cross-sectional views along line segments B-B' and C-C'. (Refer to...) Figure 7G and Figures 10A to 10B The stacking positional relationship of the first electrode 20, the first protective layer 23, and the semiconductor stack 12 is as follows: Figure 2F and Figures 5A to 5B As explained above, it will not be repeated here.

[0110] Figure 1A This shows a top view of the light-emitting element 2 manufactured according to the manufacturing method of this embodiment. Figure 1D show Figure 1A Cross-sectional view along line segment A-A'. Figure 1E show Figure 1D A magnified view of a portion of the image.

[0111] Reference Figure 1A , Figure 1D and Figure 1E The light-emitting element 2 includes a substrate 10, a semiconductor stack 12 located on the substrate 10, an exposed area 28 including a surrounding region around the semiconductor stack 12 and an internal region distributed within the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer, a transparent conductive layer 18 located on the second semiconductor layer 122, an etch stop layer 26 located on the transparent conductive layer 18 and including multiple isolated island structures, a first reflective structure 50 located on the transparent conductive layer 18 and the etch stop layer 26, including multiple openings 502 exposing the etch stop layer 26, and a second reflective structure 36 located on the first reflective structure 50, electrically connected to the etch stop layer 26, the transparent conductive layer 18, and the second semiconductor layer 122 via the openings 502 of the first reflective structure. The second reflective structure 36 and the first reflective structure 50 form an omnidirectional reflector (ODR), improving light reflection and the brightness of the light-emitting element 2. However, the stacking relationship of the first protective layer 23 with other layers and the thickness relationship at different locations, as well as the stacking relationship of the first electrode 20, the second electrode 30, the first solder pad 80a and the second solder pad 80b with other layers, have been as follows: Figure 1B and Figure 1C As explained above, it will not be repeated here.

[0112] Figure 11 This is a schematic diagram of a light-emitting device 3 according to an embodiment of the present invention. The light-emitting elements 1 and 2 from the aforementioned embodiment are mounted as flip chips on a first pad 511 and a second pad 512 of a carrier plate 51. The first pad 511 and the second pad 512 are electrically insulated from each other by an insulating portion 53 containing insulating material. In flip chip mounting, the substrate 10, facing upwards from the pad forming surface, serves as the primary light-emitting surface. To increase the light extraction efficiency of the light-emitting device 3, a reflective structure 54 can be provided around the light-emitting elements 1 and 2.

[0113] Figure 12 This is a schematic diagram of a light-emitting device 4 according to an embodiment of the present invention. The light-emitting device 4 includes a lampshade 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616, and an electrical connection element 618. The light-emitting module 610 includes a support portion 606, and a plurality of light-emitting units 608 are located on the support portion 606, wherein the plurality of light-emitting units 608 may be light-emitting elements 1, 2, or light-emitting device 3 in the aforementioned embodiments.

[0114] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art to which this application pertains may modify and vary the above embodiments without departing from the technical principles and spirit of this application. All equivalent variations and modifications made to the shape, structure, features, and spirit described in the claims of this application should be included within the scope of the claims of this application.

Claims

1. A light-emitting element, characterized in that, Include: A semiconductor stack includes a first semiconductor layer, an active region, a second semiconductor layer, and an exposed region, wherein the exposed region includes the upper surface of the first semiconductor layer and the sidewalls of the semiconductor stack. A first protective layer covers the exposed area and the semiconductor stack; A first dielectric material stack, located on the semiconductor stack, includes multiple dielectric material pairs formed by alternating stacking of dielectric materials with different refractive indices and one or more first openings. as well as A metal structure is located on the first dielectric material stack, and one or more first openings are filled to be electrically connected to the second semiconductor layer. The first protective layer comprises a first portion located on the upper surface of the first semiconductor layer in the exposed area and having a first thickness, and a second portion located on the second semiconductor layer and having a second thickness, wherein the first thickness is less than the second thickness.

2. The light-emitting element as claimed in claim 1, wherein: The first protective layer includes a lower protective layer and an upper protective layer, the lower protective layer contacting the semiconductor stack; and The first dielectric material stack is located between the lower protective layer and the upper protective layer.

3. The light-emitting element as claimed in claim 2, wherein the metal structure is located below the upper protective layer.

4. The light-emitting element of claim 1 further comprises a first electrode located on the first protective layer; and the first protective layer includes one or more third openings located in the exposed area, and the first electrode contacts the upper surface of the first semiconductor layer via the one or more third openings.

5. A light-emitting element, comprising: A semiconductor stack includes a first semiconductor layer, an active region, a second semiconductor layer, and an exposed region, wherein the exposed region includes the upper surface of the first semiconductor layer and the sidewalls of the semiconductor stack. The lower protective layer covers the semiconductor stack and the exposed area; A first dielectric material stack covering the semiconductor stack includes multiple dielectric material pairs formed by alternating stacking of dielectric materials with different refractive indices and one or more first openings. A metal structure is located on the first dielectric material stack, and one or more first openings are filled to be electrically connected to the second semiconductor layer. An upper protective layer, covering the semiconductor stack and the metal structure, includes multiple second openings to expose the exposed area and the metal structure respectively; and The first electrode is located on the upper protective layer; The first dielectric material stack is located between the upper protective layer and the lower protective layer. One of the plurality of second openings in the upper protective layer includes a second inclined sidewall. The first electrode conformally covers the second inclined sidewall and contacts the exposed area.

6. The light-emitting element as claimed in claim 1 or 5, further comprising an etch stop layer located between the second semiconductor layer and the first dielectric material stack, and the one or more first openings exposing the etch stop layer.

7. The light-emitting element of claim 6, wherein the etch stop layer comprises a transparent conductive layer or a metal structure.

8. The light-emitting element as described in claim 2 or 5, further comprising: The second electrode is located on the upper protective layer; A second protective layer, located on the second electrode, covering the exposed area, includes a second opening exposing the second electrode; and The solder pad is connected to the second electrode through the second opening.

9. The light-emitting element of claim 8, further comprising a substrate located beneath the semiconductor stack; wherein the semiconductor stack includes semiconductor stack sidewalls connected to the substrate, and the second protective layer covers the semiconductor stack sidewalls.

10. The light-emitting element of claim 8, wherein the second protective layer comprises a second dielectric material stack, the second dielectric material stack comprising a plurality of dielectric material pairs formed by alternating stacking of dielectric materials with different refractive indices; The second protective layer contains m pairs of dielectric materials, and the first dielectric material stack contains n pairs of dielectric materials, where m is greater than n.

11. The light-emitting element as claimed in claim 1 or 5, wherein, viewed from above, the exposed area comprises a plurality of first exposed areas located in the inner region of the semiconductor stack and a plurality of second exposed areas located in the surrounding region of the semiconductor stack.

12. The light-emitting element of claim 11, wherein, viewed from above, the distribution density of the first opening located between two adjacent first exposure areas is less than the distribution density of the first opening in other areas.

13. The light-emitting element as claimed in claim 1 or 5, wherein the first opening includes a first inclined sidewall having an angle between 5 degrees and 80 degrees.

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