An inertial navigation system and multiple DSP program storage method and module thereof

Abstract

The invention discloses an inertial navigation system and a method and module for storing multiple DSP programs thereof. The multiple DSP programs are stored in multiple sectors of a FLASH chip. During storage, the DSP programs are prevented from being erased due to a communication failure between the DSP chip and a host computer, and the DSP programs cannot be updated online, which is disadvantageous for engineering applications. The high-order address end of the FLASH chip is controlled by an FPGA chip, thereby controlling the switching of the starting address for loading the DSP program. A reset signal is sent to the DSP chip at the same time, so that the DSP chip can reload the second, third, ..., and Nth DSP programs from different addresses, thereby ensuring that in a complex application environment, when the inertial navigation system encounters an abnormal loading and starting of the first DSP program, the second, third, ..., and Nth DSP programs can be loaded and started in sequence, thereby improving the reliability of the inertial navigation system.

Description

Technical Field

[0001] The invention belongs to navigation signal processing technology, and in particular relates to an inertial navigation system and a method and module for storing multiple DSP programs thereof. Background Art

[0002] DSP circuit is the core component of inertial navigation products (hereinafter referred to as "INS"). INS has the function of real-time measurement of apparent velocity increment, angle increment and instantaneous angular velocity along the INS body coordinate system, and transmits attitude information to external devices in the form of digital quantity for control. The external output of attitude information by the INS depends on the DSP circuit. Most of the DSP circuits of the INS adopt the DSP+FPGA design method, in which FPGA is mainly responsible for gyro plus table signal acquisition and the realization of the underlying communication interface, and DSP is mainly responsible for signal processing and the realization of navigation algorithm flow. The two cooperate to complete the design of the entire system.

[0003] DSP has a fast operating frequency, and the program code can run at high speed in its internal RAM. However, after the system is powered off, the program in the RAM will automatically disappear. The program code must be reloaded into the RAM after the next power-on reset. Therefore, most DSP chips have a Bootloader startup loading process, which is the startup process of loading the program code from the peripheral to the internal RAM. It mainly includes the following steps:

[0004] (1) After power-on, the FPGA outputs a reset signal to the DSP to start the ROM program built into the DSP;

[0005] (2) The ROM program reads the hardware configuration status and selects the set loading method;

[0006] (3) The ROM program reads the secondary boot program according to the loading method;

[0007] (4) Run the secondary startup program;

[0008] (5) Secondary startup program reads the application;

[0009] (6) Complete the startup and start running the application.

[0010] The DSP program code is stored in only one copy in the off-chip FLASH, which can be started, loaded and run normally. In the face of the complex application environment of the inertial group, once the DSP program is abnormal during the startup process, the entire inertial group will be paralyzed and unable to output attitude information. Summary of the invention

[0011] The purpose of the present invention is to provide an inertial navigation system and a method and module for storing multiple DSP programs thereof, so as to solve the problem that the inertial navigation system is in a paralyzed state and has poor reliability when an abnormality occurs in a DSP program during startup.

[0012] The present invention solves the above technical problems through the following technical solutions: a method for storing multiple DSP programs of an inertial navigation system, wherein the data end, address end and control end of a DSP chip are respectively connected to the data end, address end and control end of an FPGA chip; the data end, low-order address end and control end of the DSP chip are also respectively connected to the data end, low-order address end and control end of a FLASH chip, and the high-order address end of the FLASH chip is connected to the IO port of the FPGA chip, and the storage method comprises:

[0013] Step 1: The DSP chip obtains a program download instruction, and erases multiple sectors in the FLASH chip for caching multiple DSP program files according to the program download instruction;

[0014] Step 2: The DSP chip receives multiple copies of the DSP program files with checksums by frame, and burns the multiple copies of the DSP program files into the cache sector of the FLASH chip by frame;

[0015] Step 3: Erasing multiple sectors in the FLASH chip for storing multiple DSP program files;

[0016] Step 4: Move multiple copies of the DSP program files from the cache sector of the FLASH chip to the corresponding storage sector for storage.

[0017] In the present invention, multiple DSP program files are stored in different sectors of the FLASH chip. When the first DSP program encounters a startup exception, the second, third, ..., Nth DSP program can be loaded and started in sequence, thereby improving the reliability of the inertial group; setting a cache sector can prevent the DSP program from being erased due to communication failure when the DSP chip and the host computer transmit and communicate multiple DSP program files, and the DSP program cannot be updated remotely online, which is not conducive to engineering applications.

[0018] Furthermore, the storage method further includes:

[0019] Step 5: The FPGA chip initializes the high address end of the FLASH chip and selects the sector storing the DSP program file;

[0020] Step 6: Load the DSP program file of the sector from the FLASH chip to the internal RAM of the DSP chip;

[0021] Step 7: Determine whether the DSP program is loaded and started successfully. If yes, the DSP program loading and starting is completed;

[0022] Otherwise, the FPGA chip assigns a value to the high four-bit address end of the FLASH chip, switches to the next sector in the FLASH chip where the DSP program file is stored, and generates a reset signal to the DSP chip, and then goes to step 6.

[0023] When there are multiple DSP program files stored in the FLASH chip, if the first DSP program fails to load and start, other DSP programs can be loaded and started until the DSP program loading and starting is completed, thus avoiding abnormal problems during the DSP program startup process in complex application environments and improving the reliability of the inertial group.

[0024] Furthermore, in step 7, the specific implementation process of determining whether the DSP program is loaded and started successfully is as follows:

[0025] Step 7.1: The DSP chip determines whether the DSP program is loaded successfully. If so, the DSP program is verified, and verification success information or verification failure information is written to the program verification status address according to the verification result;

[0026] Otherwise, the DSP chip cannot write verification success information or verification failure information to the program verification status address;

[0027] Step 7.2: The FPGA chip monitors whether there is verification success information at the program verification status address. If so, the DSP program loading and starting is successful; otherwise, the DSP program loading and starting fails.

[0028] The next DSP program will be loaded and started in two cases: the first case is that the check code calculated by the DSP chip is inconsistent with the check code stored in the FLASH chip, that is, the check fails; the second case is that the DSP program cannot be loaded into the internal RAM of the DSP chip, the DSP program fails to load successfully and cannot run, and the DSP chip cannot send check success information or check failure information to the FPGA chip.

[0029] The present invention also provides a multi-copy DSP program storage module of an inertial navigation system, comprising a DSP chip, a FLASH chip and an FPGA chip; the data end, the address end and the control end of the DSP chip are respectively connected to the data end, the address end and the control end of the FPGA chip; the data end, the low-order address end and the control end of the DSP chip are also respectively connected to the data end, the low-order address end and the control end of the FLASH chip, and the high-order address end of the FLASH chip is connected to the IO port of the FPGA chip;

[0030] The DSP chip is used to obtain a program download instruction, and erase multiple sectors in the FLASH chip for caching multiple DSP program files according to the program download instruction; to receive multiple DSP program files with checksums by frame, and burn multiple DSP program files to the cache area of ​​the FLASH chip by frame; to erase multiple sectors in the FLASH chip for storing multiple DSP program files; and to move multiple DSP program files from the cache sector of the FLASH chip to the corresponding storage sector;

[0031] The FLASH chip is used for caching multiple DSP program files and storing multiple DSP program files.

[0032] Furthermore, the FPGA chip is used to initialize the high address end of the FLASH chip and select the sector storing the DSP program file; to monitor whether the DSP program is loaded and started successfully, and to assign a value to the high four-bit address end of the FLASH chip when the DSP program fails to load and start, and switch to the next sector storing the DSP program file in the FLASH chip, and generate a reset signal to the DSP chip;

[0033] The DSP chip is also used to load the DSP program file of the sector from the FLASH chip to the internal RAM of the DSP chip; and to determine whether the DSP program is loaded successfully.

[0034] Furthermore, the DSP chip is specifically used to: determine whether the DSP program is loaded successfully, if so, perform verification on the DSP program, and write verification success information or verification failure information to the program verification status address according to the verification result; otherwise, verification success information or verification failure information cannot be written to the program verification status address.

[0035] The present invention also provides an inertial navigation system, comprising a plurality of DSP program storage modules as described above.

[0036] Beneficial Effects

[0037] Compared with the prior art, the advantages of the present invention are:

[0038] The invention provides an inertial navigation system and a method and module for storing multiple DSP programs thereof. The multiple DSP programs are stored in multiple sectors of a FLASH chip. During storage, the DSP programs are prevented from being erased due to a communication failure between the DSP chip and a host computer by caching sectors, and the DSP programs cannot be updated online remotely, which is not conducive to engineering applications. The high-order address end of the FLASH chip is controlled by an FPGA chip, thereby controlling the switching of the starting address for loading the DSP program. A reset signal is sent to the DSP chip at the same time, so that the DSP chip can reload the second, third, ..., and Nth DSP programs from different addresses, ensuring that in a complex application environment, when the inertial navigation system encounters an abnormal loading and starting of the first DSP program, the second, third, ..., and Nth DSP programs can be loaded and started in sequence, thereby improving the reliability of the inertial navigation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 This is a block diagram of the DSP+FPGA+FLASH interface relationship of the inertial group in an embodiment of the present invention;

[0041] Figure 2 is a flow chart of a method for storing multiple DSP programs in an embodiment of the present invention;

[0042] Figure 3 This is a flow chart of FPGA controlling multiple DSP programs to load and start in sequence in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following is a clear and complete description of the technical solutions in the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0045] Taking FT-C6713J / 400 as an example, the DSP chip has 20 address lines and 32 data lines; taking JFM29LV641RH as an example, the FLASH chip has a capacity of 8MB, 22 address lines and 16 data lines. FPGA chip and FLASH chip are peripherals in different areas of DSP chip. Figure 1 As shown in FIG. 1 , the data end, address end and control end of the DSP chip are respectively connected to the data end, address end and control end of the FPGA chip, and the data end, low 18-bit address end and control end of the DSP chip are also respectively connected to the data end, low 18-bit address end and control end of the FLASH chip, and the high 4-bit address end of the FLASH chip is connected to the IO port of the FPGA chip, rather than directly connected to the DSP chip. In this way, the high address line of the FLASH chip can be controlled by the FPGA chip, thereby accessing the high address sector of the FLASH. In this embodiment, 4 high address lines connect the FLASH chip to the FPGA chip, so that the FLASH can be divided into 16 sectors, and multiple DSP programs can be stored in different sectors of the FLASH chip. The address allocation table of the 16 sectors of the FLASH chip is shown in Table 1. The FLASH chip is a peripheral device in the CE1 area of ​​the DSP chip. According to the address allocation of the peripheral space of the DSP chip, the starting address of the CE1 area is 0x90000000, and the address range is 0x90000000~0x9FFFFFFF.

[0046] Table 1 FLASH sector address allocation and storage content

[0047]

[0048] Take the storage of three DSP programs as an example. Figure 2 As shown, a method for storing multiple DSP programs of an inertial navigation system provided in this embodiment includes the following steps:

[0049] Step 1: The DSP chip receives the program download instruction sent by the host computer, and erases the three sectors in the FLASH chip used to cache three DSP program files according to the program download instruction, namely the 3rd, 4th, and 5th sectors in Table 1;

[0050] Step 2: The host computer transmits three copies of the DSP program files with the checksum to the DSP chip frame by frame, and the DSP chip burns the three copies of the DSP program files into the cache sectors of the FLASH chip frame by frame, i.e., sectors 3, 4, and 5 in Table 1;

[0051] Step 3: After all DSP program files are cached, erase the three sectors in the FLASH chip used to store multiple DSP program files, i.e. sectors 0, 1, and 2 in Table 1;

[0052] Step 4: Move the three DSP program files from the cache sectors (sectors 3, 4, and 5) of the FLASH chip to the corresponding storage sectors for storage (sectors 0, 1, and 2).

[0053] The cache sector is used to avoid the DSP program being erased due to a failure when the DSP chip and the host computer are communicating with multiple DSP program files, and the DSP program cannot be updated remotely online, which is not conducive to engineering applications. After the DSP program is burned (or stored), the DSP chip reads out three DSP program files from the corresponding address space of the FLASH chip for comparison to ensure the correctness of the three DSP programs and prepare for the subsequent loading and startup of the three DSP programs.

[0054] The startup of different DSP programs is to control the assignment of the high 4-bit address lines of the FLASH chip through the FPGA chip, thereby controlling the switching of the starting address of the DSP program loading, and outputting a reset signal to the DSP chip. When the first DSP program fails to load, the DSP chip reloads the second and third DSP programs from different addresses. The specific loading and startup process is as follows: Figure 3 As shown, the storage method also includes:

[0055] Step 5: The FPGA chip initializes the high address end of the FLASH chip (i.e., assigns 0 to the high four address lines of the FLASH chip), and selects the 0th sector where the DSP program file is stored.

[0056] Step 6: Load the DSP program file of the sector from the FLASH chip to the internal RAM of the DSP chip.

[0057] Step 7: The DSP chip determines whether the DSP program is loaded successfully. If so, the DSP program is verified and the verification success information 0x55 or the verification failure information 0xAA is written to the program verification status address *checkdata according to the verification result; otherwise, the DSP chip cannot write the verification success information or the verification failure information to the program verification status address *checkdata.

[0058] Step 8: The FPGA chip monitors whether the program check status address *checkdata has the check success information 0x55. If so, the DSP program loading and starting is successful, and the DSP program loading and starting is completed; otherwise, the DSP program loading and starting fails (other DSP programs need to be loaded and started separately), and go to step 9.

[0059] In this embodiment, the FPGA chip sets a 5S counter. If the verification success information 0x55 is not detected within 5S, it means that the DSP program loading and startup fails. At this time, a JudgeSig signal falling edge is generated. After the FPGA chip detects the JudgeSig signal falling edge, it assigns values ​​to the high four address lines of the FLASH chip.

[0060] Step 9: The FPGA chip assigns a value to the high four-bit address end of the FLASH chip (i.e., FLASHADDR=FLASHADDR+1), switches to the first sector in the FLASH chip where the DSP program file is stored, and generates a reset signal to the DSP chip, and goes to step 6 until the DSP program is loaded and started successfully.

[0061] FLASHADDR indicates: the value of the 4 high-bit address lines of FLASH; *checkdata=0x55 indicates: the DSP chip program verification is successful and can run normally, and the second and third DSP programs are not started; the falling edge of the JudgeSig signal indicates: the FPGA chip has not detected that the program verification status address is 0x55.

[0062] Initialization of the high address end of the FLASH chip, i.e., FLASHADDR=0, indicates that the 0th sector of the FLASH is selected. After the inertial module is powered on, the first DSP program is loaded from the 0th sector of the FLASH chip by default. If the first DSP program can run normally, it means that the DSP chip verification has passed, and 0x55 (*checkdata=0x55) is written to the program verification status address *checkdata. The inertial module will not start the second and third programs. The inertial module will start the second or third DSP program only in the following two situations:

[0063] (1) After the inertial module is powered on, the first DSP program is successfully loaded from the FLASH chip to the internal RAM of the DSP chip. The check program function of the DSP program is first run, that is, the DSP chip reads the currently running DSP program from the FLASH chip and calculates the check code. If the calculated check code is inconsistent with the check code stored in the FLASH chip, the DSP chip sends a program check failure message to the FPGA chip, that is, the DSP chip writes 0xAA to the program check status address *checkdata (*checkdata=0xAA);

[0064] (2) After the inertial group is powered on, the first DSP program cannot be loaded from the FLASH chip into the internal RAM of the DSP chip. The loading fails and the program cannot be run. The DSP chip cannot send the program verification failure information to the FPGA chip.

[0065] In both cases, the DSP chip will not write 0x55 to the program check status address *checkdata, that is, Figure 3 The condition that *checkdata=0x55 is judged not satisfied.

[0066] The FPGA chip is designed to generate a JudgeSig signal falling edge if it does not detect 0x55 at the program check status address *checkdata within 5 seconds. After detecting the JudgeSig signal falling edge, the FPGA chip controls the switching of the large sectors of the FLASH chip, that is, assigning the high 4-bit address lines of the FLASH chip to the address for storing the second DSP program. Since the starting addresses of different large sectors of the FLASH differ by only 1, Figure 3 In the example, FLASHADDR=FLASHADDR+1 can realize the switch from sector 0 to sector 1, or from sector 1 to sector 2. After detecting the falling edge of the JudgeSig signal, a reset signal is also generated to the DSP chip, so that the DSP chip reloads the second DSP program to a different address area of ​​FLASH. After the FPGA chip detects the falling edge of the JudgeSig signal, it is also necessary to clear the count value of the 5s counter and count again to prepare for the loading of the third DSP program. If the loading of the second DSP program fails, the loading and startup process of the third DSP program is consistent with the above description.

[0067] like Figure 3 As shown, this embodiment also provides a plurality of DSP program storage modules of an inertial navigation system, including a DSP chip, a FLASH chip and an FPGA chip; the data end, address end and control end of the DSP chip are respectively connected to the data end, address end and control end of the FPGA chip; the data end, low-order address end and control end of the DSP chip are also respectively connected to the data end, low-order address end and control end of the FLASH chip, and the high-order address end of the FLASH chip is connected to the IO port of the FPGA chip.

[0068] The DSP chip is used to obtain program download instructions, and erase multiple sectors in the FLASH chip for caching multiple DSP program files according to the program download instructions issued by the upper computer; to receive multiple DSP program files with checksums by frame, and burn multiple DSP program files to the cache area of ​​the FLASH chip by frame; and to erase multiple sectors in the FLASH chip for storing multiple DSP program files; to move multiple DSP program files from the cache sector of the FLASH chip to the corresponding storage sector; and also to load the DSP program file of the sector from the FLASH chip to the internal RAM of the DSP chip; and to determine whether the DSP program is loaded successfully.

[0069] When checking whether the DSP program is loaded successfully, the DSP chip is specifically used to: determine whether the DSP program is loaded successfully. If so, perform verification on the DSP program, and write verification success information or verification failure information to the program verification status address according to the verification result; otherwise, it is impossible to write verification success information or verification failure information to the program verification status address.

[0070] FLASH chip is used to cache multiple DSP program files; it is used to store multiple DSP program files.

[0071] The FPGA chip is used to initialize the high address end of the FLASH chip and select the sector where the DSP program file is stored. It is used to monitor whether the DSP program is loaded and started successfully, and to assign a value to the high four-bit address end of the FLASH chip when the DSP program fails to load and start, and switch to the next sector in the FLASH chip where the DSP program file is stored, and generate a reset signal to the DSP chip.

[0072] What is disclosed above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, which should be covered within the protection scope of the present invention.

Claims

1. A method for storing multiple DSP programs of an inertial navigation system, characterized in that: The data end, address end and control end of the DSP chip are respectively connected to the data end, address end and control end of the FPGA chip; the data end, low-order address end and control end of the DSP chip are also respectively connected to the data end, low-order address end and control end of the FLASH chip, and the high-order address end of the FLASH chip is connected to the IO port of the FPGA chip. The storage method includes: Step 1: The DSP chip obtains a program download instruction, and erases multiple sectors in the FLASH chip for caching multiple DSP program files according to the program download instruction; Step 2: The DSP chip receives multiple copies of the DSP program files with checksums by frame, and burns the multiple copies of the DSP program files into the cache sector of the FLASH chip by frame; Step 3: Erasing multiple sectors in the FLASH chip for storing multiple DSP program files; Step 4: moving multiple copies of the DSP program files from the cache sector of the FLASH chip to the corresponding storage sector for storage; Step 5: The FPGA chip initializes the high address end of the FLASH chip and selects the sector storing the DSP program file; Step 6: Load the DSP program file of the sector from the FLASH chip to the internal RAM of the DSP chip; Step 7: Determine whether the DSP program is loaded and started successfully. If yes, the DSP program loading and starting is completed; Otherwise, the FPGA chip assigns a value to the high four-bit address end of the FLASH chip, switches to the next sector in the FLASH chip where the DSP program file is stored, and generates a reset signal to the DSP chip, and then goes to step 6.

2. The method for storing multiple DSP programs as claimed in claim 1, wherein: In step 7, the specific implementation process of determining whether the DSP program is loaded and started successfully is as follows: Step 7.1: The DSP chip determines whether the DSP program is loaded successfully. If so, the DSP program is verified, and verification success information or verification failure information is written to the program verification status address according to the verification result; Otherwise, the DSP chip cannot write verification success information or verification failure information to the program verification status address; Step 7.2: The FPGA chip monitors whether there is verification success information at the program verification status address. If so, the DSP program loading and starting is successful; otherwise, the DSP program loading and starting fails.

3. A multiple DSP program storage module for an inertial navigation system, characterized in that: It comprises a DSP chip, a FLASH chip and an FPGA chip; the data end, address end and control end of the DSP chip are respectively connected to the data end, address end and control end of the FPGA chip; the data end, low-order address end and control end of the DSP chip are also respectively connected to the data end, low-order address end and control end of the FLASH chip, and the high-order address end of the FLASH chip is connected to the IO port of the FPGA chip; The DSP chip is used to obtain a program download instruction, and erase multiple sectors in the FLASH chip for caching multiple DSP program files according to the program download instruction; and is used to receive multiple DSP program files with checksums by frame, and burn multiple DSP program files by frame into the cache area of ​​the FLASH chip; Used to erase multiple sectors in the FLASH chip for storing multiple DSP program files; and used to move multiple DSP program files from the cache sectors of the FLASH chip to corresponding storage sectors; also used to load the DSP program files of the sectors from the FLASH chip to the internal RAM of the DSP chip; and used to determine whether the DSP program is loaded successfully; The FLASH chip is used to cache multiple DSP program files; Used to store multiple DSP program files; The FPGA chip is used to initialize the high address end of the FLASH chip and select the sector storing the DSP program file; it is used to monitor whether the DSP program is loaded and started successfully, and when the DSP program fails to load and start, assign a value to the high four-bit address end of the FLASH chip, switch to the next sector storing the DSP program file in the FLASH chip, and generate a reset signal to the DSP chip.

4. The multiple DSP program storage module as claimed in claim 3, characterized in that: The DSP chip is specifically used to: determine whether the DSP program is loaded successfully, and if so, perform a DSP program check, and write a check success message or a check failure message to the program check status address according to the check result; Otherwise, the verification success information or verification failure information cannot be written to the program verification status address.

5. An inertial navigation system, characterized in that: Includes multiple DSP program storage modules as described in claim 3 or 4.

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