Data driven apparatus and data driven system

Abstract

The present disclosure provides a data driving apparatus and a data driving system. The present disclosure relates to a data driving apparatus, a data processing apparatus, and a system for driving a display apparatus, and more particularly, to a data driving apparatus, a data processing apparatus, and a system for automatically optimizing a configuration of an equalizer of a data driving apparatus in a display apparatus.

Description

Technical Field

[0001] This disclosure relates to techniques for driving display devices. Background Technology

[0002] Generally, the display panel of a display device is configured with multiple pixels arranged in a matrix, and each pixel includes sub-pixels such as R (red), G (green), and B (blue). Furthermore, each sub-pixel emits light with a grayscale value corresponding to the image data and displays the image on the display panel.

[0003] Here, the display device may include a data processing unit called a "timing controller" and a data driving unit called a "source driver," and image data is sent from the data processing unit to the data driving unit. The image data is transmitted as a digital signal, and the data driving unit converts the received image data as a digital signal into analog voltage and drives each pixel, i.e., the display panel.

[0004] As mentioned above, in order to drive the display panel, the data driving device must receive various types of signals from the data processing device.

[0005] Here, the data driving device may include an equalizer that can enhance signal reception performance by adjusting the signal received from the data processing device.

[0006] Equalizers in data-driven devices can adjust signals in various ways. For example, an equalizer can adjust the amplitude of a signal. Specifically, an equalizer can adjust the amplitude of a signal by multiplying it by a predetermined gain.

[0007] Here, if the equalizer gain is too low, the signal amplitude may be reduced. In this case, inter-symbol interference (ISI) may occur, which could degrade the signal reception performance of the data drive device.

[0008] On the other hand, if the equalizer gain is too high, the noise components included in the signal may be amplified, which may reduce the signal reception performance of the data drive device.

[0009] As mentioned above, if the equalizer gain is inappropriate, the signal reception performance of the data drive device will be degraded. Therefore, it is necessary to always configure the gain appropriately.

[0010] Traditionally, engineers manually determine the gain settings for properly configuring the equalizer, or specific settings are sent unilaterally from the signal transmitting device (e.g., a data processing device) and then determined. However, this traditional approach may require more effort than is needed to configure the equalizer, or it may degrade the accuracy of the equalizer configuration. Summary of the Invention

[0011] In this context, in one aspect, the present disclosure provides a technique for automatically optimizing the configuration of an equalizer in a data-driven device in a display apparatus.

[0012] To this end, in one aspect, this disclosure provides a data-driven apparatus comprising: a communication circuit including an equalizer and configured to receive a first data signal containing a plurality of EQ configuration information for configuring the equalizer, and then to receive an EQ training signal during a plurality of time intervals, wherein the EQ is the equalizer; and a control circuit configured to evaluate the reception performance of the communication circuit for the EQ training signal in each of the plurality of time intervals by changing the configuration of the equalizer in each time interval according to the respective EQ configuration information, and to select optimal EQ configuration information based on the evaluation results.

[0013] The first data signal may also include information related to the quantity of EQ configuration information, and the control circuit may identify the quantity of time intervals by using the information related to the quantity of EQ configuration information.

[0014] The communication circuit can receive the first data signal via a low-speed data communication protocol, and can also receive the EQ training signal via a high-speed data communication protocol different from the low-speed data communication protocol.

[0015] The EQ training signal may include a training sequence repeated in each time interval, and the training sequence may include a blank signal for distinguishing the time intervals from each other, an EQ clock training signal set at the end of the blank signal, and an EQ test signal set at the end of the EQ clock training signal.

[0016] In the blank signal reception interval of a training sequence, the communication circuit can initialize the clock trained in the training sequence preceding the training sequence, and in the EQ clock training signal reception interval of the training sequence, the communication circuit can perform clock training again.

[0017] The first data signal and the EQ training signal may be sent from the data processing device, and when initializing the clock and re-performing clock training, the level of the lock signal sent from the data driving device to the data processing device may be kept constant.

[0018] The EQ test signal may include a PRBS mode, and the control circuit can calculate the bit error rate for the PRBS mode in each time interval, and can select the EQ configuration information corresponding to the time interval with the minimum bit error rate among the multiple time intervals as the optimal EQ configuration information, where PRBS is a pseudo-random binary sequence.

[0019] The EQ test signal may include test data encoded using the DC balanced code method, and the control circuit may check whether there are any errors in the test data in each time interval, and may select the EQ configuration information corresponding to the time interval with the smallest number of errors in the test data among the plurality of time intervals as the optimal EQ configuration information.

[0020] When the communication circuit receives the blank signal, the control circuit can change the configuration of the equalizer.

[0021] When a signal with a predetermined voltage level is received during a predetermined time or longer, the communication circuit can initialize the clock and maintain the blank signal at a constant voltage level during the predetermined time.

[0022] In another aspect, this disclosure provides a data-driven device comprising: a communication circuit including an equalizer and configured to receive a first data signal and then receive an EQ training signal, the first data signal containing a plurality of EQ configuration information for configuring the equalizer, the EQ training signal including a blank signal having a predetermined level, an EQ clock training signal disposed at the end of the blank signal, and an EQ test signal disposed at the end of the EQ clock training signal, wherein EQ is an equalizer; and a control circuit configured to, when the communication circuit receives the EQ test signal, divide the reception time of the EQ test signal into a plurality of time intervals, evaluate the reception performance of the communication circuit for the EQ training signal in each of the plurality of time intervals by changing the configuration of the equalizer in each of the time intervals according to the respective EQ configuration information, and select the optimal EQ configuration information based on the evaluation results.

[0023] The first data signal may also include information related to the amount of EQ configuration information, and the control circuit may determine the number of time intervals to match the amount of EQ configuration information.

[0024] Each of the multiple EQ configuration information can include the gain level of the equalizer, and the control circuit can set the gain level of the equalizer differently in different time intervals according to each EQ configuration information.

[0025] In another aspect, this disclosure provides a data-driven system, comprising: a data processing device configured to generate a first data signal including a plurality of EQ configuration information, transmit the first data signal, generate an EQ training signal, and transmit the EQ training signal during a plurality of time intervals, wherein the EQ is an equalizer, and the EQ configuration information is configuration information of the equalizer; and a data driving device including the equalizer and configured to receive the EQ training signal during the plurality of time intervals after receiving the first data signal, evaluate the reception performance for the EQ training signal by changing the configuration of the equalizer in each of the plurality of time intervals according to the respective EQ configuration information, select optimal EQ configuration information according to the evaluation result, and then configure the equalizer according to the optimal EQ configuration information.

[0026] The data processing device can send a first data signal to the data driving device via a low-speed data communication protocol, and can also send the EQ training signal to the data driving device via a high-speed data communication protocol different from the low-speed data communication protocol.

[0027] The data processing device can send a communication signal with a communication frequency corresponding to the high-speed data communication protocol to the data driving device before sending the EQ training signal. The data driving device can receive the communication signal, train the clock included in the communication signal by changing the configuration value of the oscillator included in the internal circuit at each predetermined time, and determine the optimal configuration value for the communication frequency based on the training result of the clock.

[0028] The configuration values ​​may include any one of the oscillator's reference current value, reference voltage value, and gain.

[0029] The EQ training signal may include a training sequence repeated in each time interval. The training sequence may include a blank signal for distinguishing the time intervals from each other, an EQ clock training signal set at the end of the blank signal, and an EQ test signal set at the end of the EQ clock training signal. In the blank signal receiving interval of a training sequence, the data driving device may initialize the clock trained in the training sequence preceding the training sequence, and in the EQ clock training signal receiving interval of the training sequence, the data driving device may perform clock training again.

[0030] The data driving device can initialize the clock when a signal with a predetermined voltage level is received during a predetermined time or longer period.

[0031] The data driving device can receive signals with a predetermined voltage level for a predetermined time or longer in each time interval to initialize the clock.

[0032] In another aspect, this disclosure provides a data processing apparatus, comprising: a control circuit for storing a plurality of EQ (equalizer) configuration information; and a communication circuit configured to generate a first data signal including the plurality of EQ configuration information, transmit the first data signal via a second communication protocol, and, after generating an EQ training signal for an equalizer of a data driving device, transmit an EQ training signal to the data driving device via a first communication protocol, wherein the first communication protocol is different from the second communication protocol.

[0033] The EQ training signal may include a training sequence repeated in each time interval, and the training sequence may include a blank signal for distinguishing the time intervals from each other, an EQ clock training signal placed at the end of the blank signal, and an EQ test signal placed at the end of the EQ clock training signal.

[0034] The EQ training signal may include a blank signal with a predetermined level, an EQ clock training signal set at the end of the blank signal, and an EQ test signal set at the end of the EQ clock training signal.

[0035] As described above, according to this disclosure, since the data-driven device can automatically optimize the equalizer configuration, it can improve the accuracy of the equalizer configuration and execute the equalizer configuration efficiently. Attached Figure Description

[0036] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment.

[0037] Figure 2 and Figure 3 This is a diagram illustrating the configuration of a system according to an embodiment.

[0038] Figure 4 This is a diagram illustrating the configuration of a first data-driven communication circuit according to an embodiment.

[0039] Figure 5 and Figure 6 This is a diagram illustrating the signal sequence of an equalizer for configuring a first data-driven communication circuit according to an embodiment.

[0040] Figure 7 This is a diagram illustrating a signal sequence for further configuring the first data-driven communication circuit according to an embodiment.

[0041] Figure 8This is a flowchart illustrating the process for configuring an equalizer in a data-driven device according to an embodiment. Detailed Implementation

[0042] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment.

[0043] Reference Figure 1 The display device 100 may include a display panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140, etc.

[0044] Multiple data lines DL and multiple gate lines GL can be arranged on the display panel 110, and multiple pixels can be arranged on the display panel 110. A pixel may include multiple subpixels SP. Here, a subpixel can be R (red), G (green), B (blue), and W (white), etc. A pixel can be configured as an RGB subpixel SP, an RGBG subpixel SP, or an RGBW subpixel SP, etc. In the following description, for ease of description, the case where a pixel includes RGB subpixels will be used.

[0045] The data driving device 120, the gate driving device 130, and the data processing device 140 are devices for generating signals for displaying images on the display panel 110.

[0046] The gate driving device 130 can provide a gate driving signal having an on-state voltage or an off-state voltage to the gate line GL. When the gate driving signal with an on-state voltage is provided to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. Conversely, when the gate driving signal with an off-state voltage is provided to the sub-pixel SP, the connection between the sub-pixel SP and the data line DL is released. The gate driving device 130 may be referred to as a "gate driver".

[0047] The data driving device 120 can provide a data voltage Vp to the sub-pixel SP via the data line DL. The data voltage Vp provided to the data line DL can be provided to the sub-pixel SP according to the gate driving signal. The data driving device 120 can be referred to as a "source driver".

[0048] The data drive device 120 may include at least one integrated circuit, which may be connected to the bonding pads of the panel 110 via tape auto-bonding (TAB) or glass flip-chip (COG) bonding, or may be formed directly on the panel 110. According to an embodiment, the integrated circuit may be formed by integration onto the panel 110. Alternatively, the data drive device 120 may be implemented via thin-film flip-chip (COF).

[0049] The data processing device 140 can provide control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 can send a gate control signal GCS to the gate driving device 130 to start scanning. Additionally, the data processing device 140 can output image data to the data driving device 120. Furthermore, the data processing device 140 can send data control signals to control the data driving device 120 to provide a data voltage Vp to each sub-pixel SP. The data processing device 140 can be referred to as a "timing controller".

[0050] Figure 2 This is a diagram illustrating the configuration of a system according to an embodiment.

[0051] Reference Figure 2 The system may include at least one data processing device 140 and multiple data driving devices 120a, 120b, 120c and 120d.

[0052] The data processing device 140 can be mounted on the first printed circuit board (PCB) PCB1. In addition, the data processing device 140 can be connected to a plurality of data driving devices 120a, 120b, 120c and 120d via the first communication line LN1 and the second communication line LN2.

[0053] The first communication line LN1 and the second communication line LN2 can be guided to a plurality of data driving devices 120a, 120b, 120c and 120d via the first PCB PCB1 and the second PCB PCB2. The first PCB PCB1 and the second PCB PCB2 can be connected by a first film FL1 made of flexible material, and the first communication line LN1 and the second communication line LN2 can extend from the first PCB PCB1 to the second PCB PCB2 via the first film FL1.

[0054] Data driving devices 120a, 120b, 120c, and 120d can each be disposed on the second film FL2 in the form of a chip-on-film (COF). The second film FL2 can be a support substrate made of a flexible material for connecting the second PCB PCB2 to the panel 110, and the first communication line LN1 and the second communication line LN2 can extend through the second film FL2 to each of the data driving devices 120a, 120b, 120c, and 120d on the second PCB PCB2.

[0055] The first communication line LN1 can be connected one-to-one with the data processing device 140 and the data driving devices 120a, 120b, 120c and 120d.

[0056] Additionally, the second communication line LN2 can connect data driving devices 120a, 120b, 120c, and 120d to each other, or connect data driving device 120d to data processing device 140 without overlapping with the first communication line LN1 on the panel. For example, the first data driving device 120a can be connected to the second data driving device 120b via the second communication line LN2, and the second data driving device 120b can be connected to the third data driving device 120c via the second communication line LN2. In this case, the second data driving device 120b and the third data driving device 120c can be connected to different second PCBs PCB2. Therefore, the second communication line LN2 disposed therebetween can pass through the second PCB PCB2, the first film FL1, and the first PCB PCB1, thereby connecting the second data driving device 120b and the third data driving device 120c. The third data driving device 120c can be connected to the fourth data driving device 120d via the second communication line LN2, and the fourth data driving device 120d can be connected to the data processing device 140 via the second communication line LN2.

[0057] As described above, the data processing device 140 and the data driving devices 120a, 120b, 120c and 120d can communicate with each other via the first communication line LN1 and the second communication line LN2.

[0058] Here, the data processing device 140 can send image data to the data driving devices 120a, 120b, 120c and 120d via the first communication line LN1.

[0059] In an embodiment, data driving devices 120a, 120b, 120c, and 120d can automatically optimize the equalizer configuration using signals sent from data processing device 140 before receiving image data from data processing device 140.

[0060] On the other hand, such as Figure 3 As shown, the data processing device 140 may include a data processing control circuit 342, a first data processing communication circuit 344, and a second data processing communication circuit 346.

[0061] In addition, the data driving device 120 may include a data driving control circuit 322, a first data driving communication circuit 324, and a second data driving communication circuit 326.

[0062] The first data processing communication circuit 344 and the first data driving communication circuit 324 can be connected via the first communication line LN1. Additionally, the first data processing communication circuit 344 can send the main communication signal MLP to the first data driving communication circuit 324 via the first communication line LN1.

[0063] The second data processing communication circuit 346 and the second data driving communication circuit 326 can be connected via the second communication line LN2. Additionally, the second data driving communication circuit 326 can send an auxiliary communication signal ALP to the second data processing communication circuit 346 via the second communication line LN2.

[0064] Figure 4 This is a diagram illustrating the configuration of a first data-driven communication circuit according to an embodiment.

[0065] Reference Figure 4 The first data-driven communication circuit 324, i.e. the first communication circuit 324 of the data-driven device 120, may include an equalizer 410, a clock recovery circuit 420, a byte alignment circuit 430, and a pixel alignment circuit 440.

[0066] The equalizer 410 can be connected to the first communication line LN1 and can control the main communication signal MLP received through the first communication line LN1.

[0067] Specifically, when the signal passes through the first communication line LN1, distortion may occur in the main communication signal MLP. This may result in attenuation (or pulse dispersion) of the high-frequency components of the main communication signal MLP, as well as inter-symbol interference (ISI). The equalizer 410 can reproduce the high-frequency components in the distorted main communication signal MLP (or remove the pulse dispersion from it), thereby reducing inter-symbol interference.

[0068] The equalizer 410 can send the adjusted main communication signal MLP to the clock recovery circuit 420, the byte alignment circuit 430, and / or the pixel alignment circuit 440, thereby enhancing the receiving performance of the first communication circuit 224.

[0069] The equalizer 410 can adjust the main communication signal MLP according to the configuration.

[0070] For example, equalizer 410 can determine the amplification amount in the main communication signal MLP based on the configured gain. In other words, the configuration values ​​for configuring equalizer 410 can include the gain level for configuring the gain of equalizer 410.

[0071] The configuration values ​​of the equalizer 410 can be stored in the data processing device 140.

[0072] In addition, when power is applied to the display device 100, the configuration values ​​of the equalizer 410, etc., can be sent to the first data driving communication circuit 324 of the data driving device 120 through the first data processing communication circuit 344 of the data processing device 140.

[0073] The clock recovery circuit 420 can receive the clock pattern via the main communication signal MLP and perform clock training according to the clock pattern. In this case, the clock training performance of the clock recovery circuit 420 may be affected by the adjustment of the main communication signal MLP by the equalizer 410.

[0074] The byte alignment circuit 430 and pixel alignment circuit 440 can train link clocks such as symbol clocks and pixel clocks based on the link data, and can align image data byte by byte (e.g., symbol by symbol) and pixel by pixel based on the link clocks. Here, the link training performance or link recovery performance of the byte alignment circuit 430 and pixel alignment circuit 440 may also be affected by the adjustment of the main communication signal MLP by the equalizer 410.

[0075] As described above, the receiving performance of the first data-driven communication circuit 324, i.e. the clock training performance of the clock recovery circuit 420, and the link training or link recovery performance of the byte alignment circuit 430 and the pixel alignment circuit 440 may be affected by the configuration of the equalizer 410.

[0076] Here, the main communication signal MLP received by the equalizer 410 through the first communication line LN1 may have distortions that occur therein, depending on the characteristics of the first communication line LN1.

[0077] Furthermore, due to environmental factors (e.g., temperature rise within the display device 100, static electricity, etc.) and physical deterioration of the first communication line LN1, the characteristics of the first communication line LN1 may frequently change. Consequently, the signal distortion pattern in the main communication signal MLP may also frequently change.

[0078] As mentioned above, if the signal distortion form in the main communication signal MLP changes frequently, the configuration of the equalizer 410 must also be changed frequently to match the changed signal distortion form.

[0079] In this regard, in the embodiment, the configuration of equalizer 410 can be performed automatically through the following configuration.

[0080] Figure 5 and Figure 6 This is a diagram illustrating the signal sequence of the equalizer configuration in the first communication circuit according to an embodiment.

[0081] First, refer to Figure 5When the drive voltage VCC is supplied to the data processing device 140 and the data drive device 120, the first data processing communication circuit 344 of the data processing device 140 can operate within a predetermined time (e.g., within...). Figure 5 In command mode, the second protocol signal PS2 is sent to the first data drive communication circuit 324 of the data drive device 120.

[0082] After sending the second protocol signal PS2, the first data processing communication circuit 344 can send the first protocol signal PS1. For example, the first data processing communication circuit 344 can... Figure 5 In the automatic training mode, the first protocol signal PS1 is sent.

[0083] Here, the second protocol signal PS2 or the first protocol signal PS1 is a main communication signal MLP transmitted through the first communication line LN1, and can be adjusted between the data processing device 140 and the data driving device 120 based on the second communication protocol and the first communication protocol.

[0084] Furthermore, the communication frequency of the first protocol signal PS1 can be ten times or more than ten times the communication frequency of the second protocol signal PS2. Based on this characteristic, the first protocol signal PS1 can be classified as a high-speed data communication protocol, and the second protocol signal PS2 can be classified as a low-speed data communication protocol.

[0085] Since high-speed data communication may have a higher data loss rate than low-speed data communication, the first data processing communication circuit 344 can send various configuration information of the data driving device 120 required for high-speed data communication to the first data driving communication circuit 324 through the second protocol signal PS2.

[0086] In other words, the data processing device 140 can send various configuration information of the data driving device 120 required for high-speed data communication to the data driving device 120 through low-speed data communication with a low data loss rate, thereby enabling the data driving device 120 to accurately receive the configuration information.

[0087] In this embodiment, the data processing control circuit 342 of the data processing device 140 can store multiple equalizer (EQ) configuration information and can control the first data processing communication circuit 344. Here, the values ​​of the multiple EQ configuration information can be determined by conducting multiple experiments on the signal distortion of the frequently changing main communication signal MLP.

[0088] The first data processing communication circuit 344 can generate a second protocol signal PS2, which includes multiple EQ configuration information, under the control of the data processing control circuit 342.

[0089] In addition, the first data processing communication circuit 344 can... Figure 5 In the CFG data interval, a second protocol signal PS2, including multiple EQ configuration information, is sent to the first data drive communication circuit 324. Hereinafter, the second protocol signal PS2, including multiple EQ configuration information, will be referred to as the "first data signal".

[0090] In an embodiment, the multiple EQ configuration information may include multiple gain levels of the equalizer 410 that are different from each other. For example, if the multiple EQ configuration information is first EQ configuration information and second EQ configuration information, the first EQ configuration information may include a first gain level, and the second EQ configuration information may include a second gain level that is different from the first gain level. Each of the multiple EQ configuration information may also include tap coefficients of the equalizer 410.

[0091] On the other hand, the first data drive communication circuit 324, connected to the first data processing communication circuit 344 via the first communication line LN1, can receive the first data signal via the second communication protocol. Additionally, the data drive control circuit 322 can store multiple EQ configuration information in an auxiliary storage medium (e.g., registers).

[0092] Here, in addition to multiple EQ configuration information, the first data signal may also include information related to the number of EQ configuration information. For example, if there are 8 EQ configuration information, the information related to the number could be "8". Furthermore, the first data signal may also include default EQ configuration information, scrambling information, and line polarity information, etc.

[0093] The data-driven control circuit 322 can also store information related to the amount of EQ configuration information in an auxiliary storage medium, and can configure the equalizer 410 to default using the first data signal. Additionally, other circuit components for high-speed data communication can be configured. Here, the default EQ configuration information may include the default gain level of the equalizer 410 for high-speed data communication, and the scrambling information may include information indicating whether the data is scrambled when the data processing device 140 sends data to the data-driven device 120. Furthermore, the line polarity information may include information indicating the polarity of the first line in a pixel.

[0094] On the other hand, after completing the transmission and reception of the first data signal, i.e., after the end of the CFG data interval, the first data processing communication circuit 344, under the control of the data processing control circuit 342, can send a second protocol signal PS2, including a termination message, to the first data driving communication circuit 324 during the CFG complete interval. Here, the termination message can be a message indicating the termination of communication of the second protocol signal PS2, and the data driving control circuit 322 can recognize the termination message in the second protocol signal PS2 received from the first data driving communication circuit 324, and can terminate the communication according to the second protocol (low-speed data communication protocol).

[0095] On the other hand, in the preamble interval before the CFG data interval, the second protocol signal PS2 may include a low-speed data communication clock signal, and the data driving device 120, i.e. the first data driving communication circuit 324, may use the low-speed data communication clock signal to perform clock training for low-speed data communication.

[0096] Here, the auxiliary communication signal ALP can be maintained at a low level until clock training for the low-speed data communication clock is completed, and can be changed to a high level when the clock training is completed. In other words, after the drive voltage VCC is supplied, the second data drive communication circuit 326 can maintain the auxiliary communication signal ALP at a low level under the control of the data drive control circuit 322, and can switch the auxiliary communication signal ALP to a high level in the preamble interval when clock training for the low-speed data communication clock is completed. In addition, the first data processing communication circuit 344 can send the first data signal after the auxiliary communication signal ALP changes to a high level. Here, the auxiliary communication signal ALP can be called a "lock signal", and can be controlled by... Figure 2 The second communication line LN2 in the circuit is sent to the second data processing communication circuit 346.

[0097] If an internal anomaly exists, or if an unplanned communication error occurs after the auxiliary communication signal ALP is changed to a high level, the data drive control circuit 322 can change the auxiliary communication signal ALP to a low level. For example, if no signal is received in the CFG data interval or the CFG completion interval, or if the clock is corrupted, the data drive device 120 can change the auxiliary communication signal ALP to a low level.

[0098] As described above, after the low-speed data communication between the data processing device 140 and the data driving device 120 terminates, the first data processing communication circuit 344 can generate an EQ training signal as a first protocol signal, and can send the EQ training signal to the first data driving communication circuit 324 through the first communication line LN1. Here, the first data processing communication circuit 344 can send the EQ training signal during multiple time intervals (EQ training intervals).

[0099] In an embodiment, such as Figure 5 As shown, the EQ training signal may include a training sequence repeated for each time interval. Additionally, the training sequence may be configured as a blank signal H with a predetermined level (e.g., a high level), an EQ clock training signal EQCP placed at the end of the blank signal, and an EQ test signal EQTP placed at the end of the EQ clock training signal EQCP. Here, the blank signal H may be a signal used to distinguish between the time intervals.

[0100] The EQ test signal EQTP can include a pseudo-random binary sequence (PRBS) mode. Here, the PRBS mode can be implemented as PRBS7 mode, PRBS9 mode, and PRBS10 mode, etc.

[0101] The EQ test signal EQTP can include test data encoded using the DC balanced code method. Here, the test data encoded using the DC balanced code method can include multiple code groups with the same number of "0"s and "1"s.

[0102] The first data-driven communication circuit 324 can receive EQ training signals during multiple time intervals. Here, the EQ training signals may be distorted when passing through the first communication line LN1.

[0103] When the first data-driven communication circuit 324 receives the EQ training signal, the data-driven control circuit 322 can change the configuration of the equalizer 410 according to multiple EQ configuration information for each time interval during multiple time intervals. Here, the data-driven control circuit 322 can evaluate the reception performance of the first data-driven communication circuit 324 for the EQ training signal by changing the configuration of the equalizer 410 for each time interval in the multiple time intervals.

[0104] In addition, the optimal configuration information can be selected from multiple EQ configuration information based on the evaluation results of each time interval.

[0105] For example, if there are N time intervals (where N is a natural number), and if the EQ training signal includes the first training sequence to the Nth training sequence, then the first data-driven communication circuit 324 can receive the first training sequence in the first time interval. In this case, the first data-driven communication circuit 324 receives the blank signal H of the first training sequence in the interval T. EQ_Setup In this process, the data-driven control circuit 322 can use the first EQ configuration information from multiple EQ configuration information to configure the equalizer 410.

[0106] Subsequently, the first data-driven communication circuit 324 can receive the EQ clock training signal EQCP of the first training sequence within the interval T. EQ_CT Clock training for testing equalizer 410 is performed. Here, clock training can be performed by clock recovery circuit 420.

[0107] The first data-driven communication circuit 324, which has recovered its clock through clock training, can receive the EQ test signal EQTP via the equalizer 410 configured using the first EQ configuration information, and can recover the data in the EQ test signal EQTP. Here, data recovery can be performed by the byte alignment circuit 430 and the pixel alignment circuit 440.

[0108] If the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can control the EQ test signal EQTP during the receiving time T. EQ_Test During this process, it is checked whether the PRBS pattern included in the recovered data matches the previously stored bitstream, and the bit error rate of the EQ test signal EQTP can be identified accordingly.

[0109] If the EQ test signal EQTP includes test data encoded using the DC balanced code method, then the data drive control circuit 322 can control the EQ test signal EQTP during the receiving time T. EQ_Test During this process, the number of "0"s and "1"s in the code blocks of the recovered data is identified, and this can be used to identify whether there are data errors in the EQ test signal EQTP. Here, the DC balanced code method can be an 8B10B encoding / decoding method.

[0110] The data-driven control circuit 322 can evaluate the receiving performance of the first data-driven communication circuit 324 for the first EQ configuration information by using the bit error rate of the EQ test signal as described above or information related to whether there are data errors in the EQ test signal.

[0111] After the first training sequence is completed, the first data-driven communication circuit 324 can receive the second training sequence during the second time interval.

[0112] When the first data-driven communication circuit 324 receives the blank signal H of the second training sequence, the data-driven control circuit 322 can identify the start of the second time interval and can use the second EQ configuration information from among multiple EQ configuration information to configure the equalizer 410. In other words, the equalizer 410 configured with the first EQ configuration information can be changed to be configured with the second EQ configuration information.

[0113] The first data-driven communication circuit 324 can initialize the clock recovered in the first training sequence during the blank signal receiving interval of the second training sequence.

[0114] Subsequently, the first data-driven communication circuit 324 and the data-driven control circuit 322 can use the EQ clock training signal and EQ test signal of the second training sequence to perform clock retraining and to evaluate the receiving performance of the first data-driven communication circuit 324.

[0115] As described above, if the clock is initialized with a blank signal H in each training sequence, the clock recovery performance can be equal in each training sequence, thus enabling a more accurate evaluation of the receiving performance of the first data-driven communication circuit 324.

[0116] On the other hand, when clock initialization and clock retraining are performed via the first data-driven communication circuit 324, the lock signal sent from the second data-driven communication circuit 326 to the second data-processing communication circuit 346 can be maintained at the existing level (e.g., high level).

[0117] Generally, when the first data-driven communication circuit 324 initializes the clock, the lock signal changes from a high level to a low level. Here, as described above, if clock initialization and clock retraining are performed for each of multiple time intervals, the level of the lock signal must also be changed for each time interval. In this case, frequent changes in the level of the lock signal may increase the likelihood of errors occurring when transmitting the lock signal. Therefore, in this embodiment, the level of the lock signal can be maintained at an existing level (e.g., a high level), independent of the aforementioned clock initialization and clock retraining, thereby reducing the likelihood of errors occurring when transmitting the lock signal.

[0118] The data-driven control circuit 322 can evaluate the receiving performance of the first data-driven communication circuit 324 for each of the multiple EQ configuration information by repeatedly performing the above process for each of the multiple time intervals.

[0119] In addition, the data-driven control circuit 322 can select the EQ configuration information that can achieve the best reception performance from multiple EQ configuration information as the optimal EQ configuration information, and can complete the configuration of the equalizer 410 according to the optimal EQ configuration information.

[0120] The data-driven control circuit 322 can identify the number of time intervals using previously stored information related to the amount of EQ configuration information. In other words, the data-driven control circuit 322 can identify the number of repetitions of the training sequence included in the EQ training signal using information related to the amount of EQ configuration information.

[0121] For example, if the information related to the quantity of EQ configuration information is "8", then the data-driven control circuit 322 can identify the number of time intervals, that is, it can identify... Figure 5 The training sequence shown is repeated 8 times. Therefore, the data-driven control circuit 322 can change the configuration of the equalizer 410 for each of the eight time intervals based on multiple equalizer configuration information, and can then terminate the operation of changing the configuration of the equalizer 410.

[0122] When the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can select the EQ configuration information corresponding to the time interval with the minimum bit error rate from multiple time intervals as the optimal EQ configuration information.

[0123] When the EQ test signal EQTP includes test data encoded by the DC balanced code method, the data drive control circuit 322 can select the EQ configuration information corresponding to the time interval with the fewest errors occurring in the test data from multiple time intervals as the optimal EQ configuration information.

[0124] As described above, when the data driving device 120 completes the configuration of the equalizer 410 according to the optimal EQ configuration information, the data processing control circuit 342 can process the image data and send the image data to the first data driving communication circuit 324 through the first data processing communication circuit 344.

[0125] In other words, the data processing device 140 and the data driving device 120 can perform communication (display mode) to receive image data.

[0126] Above, the configuration of the training sequence, which includes repeating the EQ training signal in each time interval, has been described, namely, the configuration of repeating the blank signal, the EQ training signal, and the EQ test signal in each time interval.

[0127] The following section describes the configuration of the EQ training signal, which includes a blank signal, an EQ clock training signal, and an EQ test signal.

[0128] Reference Figure 6 As described above, after the low-speed data communication between the data processing device 140 and the data driving device 120 terminates, the first data processing communication circuit 344 can generate an EQ training signal as a first protocol signal, and can send the EQ training signal to the first data driving communication circuit 324 through the first communication line LN1. Here, the first data processing communication circuit 344 can send the EQ training signal during multiple time intervals (EQ training intervals).

[0129] In an embodiment, such as Figure 6 As shown, the EQ training signal can be configured as a blank signal H with a predetermined level (e.g., high level), an EQ clock training signal EQCP set at the end of the blank signal H, and an EQ test signal EQTP set at the end of the EQ clock training signal EQCP.

[0130] exist Figure 5 In this context, the EQ training signal has a pattern of repeating the blank signal H, the EQ clock training signal EQCP, and the EQ test signal EQTP for each time interval in multiple time intervals. Figure 6 In this context, the EQ training signal can be configured such that the blank signal H persists for the first time T. IDLE Then the EQ clock training signal EQCP lasts for a second time T. EQ_CT Furthermore, the EQ test signal EQTP lasts for the third time T. EQ_T .

[0131] In other words, in the embodiments, instead of repeating the EQ training sequence in each time interval, the EQ training signal may have a pattern that includes an EQ training sequence.

[0132] Here, the third time T EQ_TEST_1 To T EQ_TEST_N It can be faster than the first time T IDLE Second time T EQ_CT long.

[0133] exist Figure 6 In addition, the EQ test signal EQTP can also include a pseudo-random binary sequence (PRBS) pattern.

[0134] In addition, the EQ test signal EQTP can include test data encoded using the DC balanced code method.

[0135] On the other hand, when the first data-driven communication circuit 324 receives the EQ training signal, the data-driven control circuit 322 can activate the third time T. EQ_T The configuration of equalizer 410 is changed at the beginning or later based on multiple EQ configuration information. Here, the data-driven control circuit 322 can store unit time interval information and can predetermine the third time by multiplying information related to the number of EQ configuration information by the unit time interval information.

[0136] In addition, the data-driven control circuit 322 can subdivide the third time into multiple time intervals.

[0137] For example, if the information related to the quantity of EQ configuration information is "8", and if the unit time interval information is 5ms, then the data-driven control circuit 322 can determine the third time as 40ms.

[0138] In addition, the data-driven control circuit 322 can subdivide the third time into eight time intervals.

[0139] Subsequently, the data-driven control circuit 322 can target multiple time intervals T. EQ_TEST_1 To T EQ_TEST_N The configuration of equalizer 410 is changed according to multiple EQ configuration information for each time interval. Here, the data-driven control circuit 322 can evaluate the reception performance of the first data-driven communication circuit 324 for the EQ training signal by changing the configuration of equalizer 410 for each time interval.

[0140] In addition, the data-driven control circuit 322 can select the optimal EQ configuration information from multiple EQ configuration information based on the evaluation results for each time interval.

[0141] For example, if the EQ training signal includes the first time T IDLE Second time T EQ_CT and the third time T EQ_T And if the third time is divided into the first time interval T EQ_TEST_1 up to the Nth time interval T EQ_TEST_N Then the first data-driven communication circuit 324 can be in the first time T IDLE During this period, a blank signal H is received. The data-driven control circuit 322 can receive the blank signal H at the first time T. IDLE It remains idle during this period.

[0142] Subsequently, the first data-driven communication circuit 324 can be activated at the second time T. EQ_CT During this period, the EQ clock training signal EQCP is received, and clock training for testing the equalizer 410 can be performed. Here, clock training can be performed through the clock recovery circuit 420.

[0143] In addition, the first data-driven communication circuit 324 can be used in the third time T EQ_T During this period, the EQ test signal EQTP is received.

[0144] Here, the data-driven control circuit 322 can operate in the first time interval T. EQ_TEST_1 At the start time, the first EQ configuration information from multiple EQ configuration information is used to configure equalizer 410.

[0145] In addition, the first data-driven communication circuit 324 can operate in the first time interval T. EQ_TEST_1 During this period, the equalizer 410, configured using the first EQ configuration information, receives the EQ test signal EQTP and can recover data based on the EQ test signal EQTP. Here, data recovery can be performed by the byte alignment circuit 430 and the pixel alignment circuit 440.

[0146] When the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can check for the first time interval T. EQ_TEST_1 The recovered data includes PRBS patterns that match the previously stored bitstream, and this can be used to identify the first time interval T. EQ_TEST_1 The bit error rate of the received EQ test signal EQTP during the period.

[0147] If the EQ test signal EQTP includes test data encoded using the DC balanced code method, then the data drive control circuit 322 can operate in the first time interval T. EQ_TEST_1 During this period, the number of "0"s and "1"s in the code blocks of the recovered data is identified, and this can be used to identify the first time interval T. EQ_TEST_1 The system checks whether data errors exist in the received EQ test signal EQTP during the period. Here, the DC balanced code method can be an 8B10B encoding / decoding method.

[0148] The data-driven control circuit 322 can evaluate the receiving performance of the first data-driven communication circuit 324 for the first EQ configuration information by using the bit error rate of the EQ test signal as described above or information related to whether there are data errors in the EQ test signal.

[0149] After the first time interval T EQ_TEST_1 Subsequently, the data-driven control circuit 322 can operate in the second time interval T. EQ_TEST_2 At the start time, the second EQ configuration information is used to configure equalizer 410.

[0150] In addition, the first data-driven communication circuit 324 can operate in the second time interval T. EQ_TEST_2During this period, the equalizer 410 configured using the second EQ configuration information receives the EQ test signal and can recover data based on the EQ test signal EQTP.

[0151] When the EQ test signal EQTP includes the PRBS mode, the data drive control circuit 322 can check the second time interval T. EQ_TEST_2 The recovered data includes PRBS patterns that match the previously stored bitstream, and this can be used to identify the second time interval T. EQ_TEST_2 The bit error rate of the received EQ test signal EQTP during the period.

[0152] If the EQ test signal EQTP includes test data encoded using the DC balanced code method, then the data drive control circuit 322 can operate in the second time interval T. EQ_TEST_2 During this period, the number of "0"s and "1"s in the code blocks of the recovered data is identified, and this can be used to identify the second time interval T. EQ_TEST_2 Check if there are any data errors in the EQ test signal EQTP received during the period.

[0153] The data-driven control circuit 322 can evaluate the receiving performance of the first data-driven communication circuit 324 for the second EQ configuration information by using the bit error rate of the EQ test signal as described above or information related to whether there are data errors in the EQ test signal.

[0154] The data-driven control circuit 322 can be controlled by targeting the third time T. EQ_T The above process is repeated for each subdivided interval to evaluate the receiving performance of the first data-driven communication circuit 324 for each EQ configuration information in the multiple EQ configuration information.

[0155] In addition, the data-driven control circuit 322 can select the EQ configuration information that can achieve the best reception performance from multiple EQ configuration information as the optimal EQ configuration information, and can complete the configuration of the equalizer 410 according to the optimal EQ configuration information.

[0156] The data drive unit 120 (which has configured the equalizer 410 according to the optimal EQ configuration information as described above) can perform communication (display mode) for receiving image data from the data processing unit 140.

[0157] As described above, when power is applied to the display device 100, the data driving device 120 can evaluate the reception performance for the EQ training signal by changing the configuration of the equalizer 410 for each time interval according to multiple EQ configuration information, and can configure the equalizer 410 using the EQ configuration information that achieves the optimal reception performance from among the multiple EQ configuration information. Therefore, when power is applied, the configuration of the equalizer 410 can be automatically optimized according to the signal distortion form of the main communication signal MLP, wherein the signal distortion form of the main communication signal MLP changes according to the characteristics of the first communication line LN1.

[0158] On the other hand, in the embodiment, when the data processing device 140 and the data driving device 120 send and receive the second protocol signal PS2, the communication frequency of the second protocol signal PS2, i.e., the communication frequency of low-speed data communication, can be predetermined.

[0159] In addition, the clock recovery circuit 420, which is an internal circuit of the data drive device 120, can be configured to conform to the communication frequency of the second protocol signal PS2.

[0160] On the other hand, the communication frequency of the first protocol signal PS1, i.e. the communication frequency of high-speed data communication, may not be predetermined.

[0161] Therefore, before sending and receiving the EQ training signal as the first protocol signal PS1, the data processing device 140 and the data driving device 120 can... Figure 7 The pre-clock training section shown configures the internal circuitry to conform to the communication frequency of the first protocol signal PS1.

[0162] Specifically, the data processing device 140 may send a first protocol signal PS1, including the training clock mode TR_CLK, to the data driving device 120 during the pre-clock training interval. Hereinafter, the first protocol signal PS1 sent to the data driving device 120 during the pre-clock training interval will be referred to as the "communication signal".

[0163] The data-driven device 120 can subdivide the pre-clock training interval into multiple time intervals (e.g., Figure 7 T1 to T n Training is performed for the training clock mode TR_CLK included in the communication signal by changing the configuration value of the oscillator (not shown) included in the clock recovery circuit 420 for each subdivided time interval.

[0164] Additionally, the data driving device 120 can select an optimal configuration value based on the training results of the training clock mode TR_CLK, and can use this optimal configuration value to configure an oscillator (not shown). The configuration value of the oscillator (not shown) may include any one of the oscillator's (not shown) reference current value, reference voltage value, and gain.

[0165] Here, the oscillator (not shown) is a circuit whose characteristics change according to the communication frequency, and if any of the reference current, reference voltage and gain of the oscillator (not shown) are changed, the frequency of the oscillation signal output from the oscillator (not shown) may also change.

[0166] This oscillation signal can be used to train the clock pattern TR_CLK.

[0167] Therefore, in the embodiment, the oscillator (not shown) can be configured with the optimal configuration value as described above, so that the clock recovery circuit 420 can operate in a manner that conforms to the communication frequency of the first protocol signal PS1.

[0168] The processing of the equalizer 410 in the configuration data driving device 120 will be described below.

[0169] Figure 8 This is a flowchart illustrating the process for configuring an equalizer in a data-driven device according to an embodiment.

[0170] Reference Figure 8 When the drive voltage VCC is supplied to the data processing device 140 and the data driving device 120, the data driving device 120 can receive a first data signal from the data processing device 140 (S810). This first data signal is a second protocol signal PS2 that includes multiple EQ configuration information. Here, the multiple EQ configuration information may include different gain levels of the equalizer 410, and the first data signal can be transmitted through the first communication line LN1. In addition, the first data signal may also include information related to the number of EQ configuration information.

[0171] The data drive device 120 can store multiple EQ configuration information included in the first data signal (S820).

[0172] Subsequently, the data driving device 120 can receive the EQ training signal as the first protocol signal PS1 from the data processing device 140 (S830). Here, the EQ training signal may include, for example, Figure 5The training sequence shown is repeated for each time interval, and the training sequence can be configured as a blank signal H with a predetermined level (e.g., high level), an EQ clock training signal EQCP set at the end of the blank signal, and an EQ test signal EQTP set at the end of the EQ clock training signal EQCP.

[0173] In addition, such as Figure 6 As shown, the EQ training signal can be configured as a blank signal H with a predetermined level (e.g., high level), an EQ clock training signal EQCP set at the end of the blank signal H, and an EQ test signal EQTP set at the end of the EQ clock training signal EQCP.

[0174] The data-driven device 120 can change the configuration of the equalizer 410 according to multiple EQ configuration information for each predetermined time interval, and can evaluate the reception performance of the EQ training signal for each predetermined time interval (S840 and S850). Here, when the EQ training signal includes a training sequence, the data-driven device 120 can change the configuration of the equalizer 410 at or after the time when the EQ training signal is initially received.

[0175] In addition, when the EQ training signal includes a blank signal H, an EQ clock training signal EQCP, and an EQ test signal EQTP, the data driving device 120 can change the configuration of the equalizer 410 at or after the time the EQ test signal EQTP is received.

[0176] The data driving device 120 can repeat steps S840 and S850 until the reception of the EQ training signal is terminated (S860).

[0177] When the reception of the EQ training signal is terminated, the data driving device 120 can select the optimal EQ configuration information from multiple EQ configuration information based on the evaluation results for each time interval (S870).

[0178] Subsequently, the data drive unit 120 can configure the equalizer (S880) using the optimal EQ configuration information. Accordingly, the data drive unit 120 can appropriately cancel the signal distortion of the main communication signal MLP transmitted through the first communication line LN1.

[0179] Cross-reference to related applications

[0180] This application claims priority to Korean Patent Application No. 10-2020-0052575, filed on April 29, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A data driving device comprising: a communication circuit including an equalizer, and configured to receive a first data signal containing a plurality of EQ configuration information for configuring the equalizer, and then receive an EQ training signal during a plurality of time intervals, wherein EQ is an equalizer; and a control circuit configured to evaluate a reception performance of the communication circuit for the EQ training signal in each of the plurality of time intervals by changing a configuration of the equalizer according to each of the EQ configuration information, and select an optimal EQ configuration information according to an evaluation result, wherein each of the plurality of EQ configuration information includes a gain level of the equalizer, and the control circuit sets the gain level of the equalizer differently in each of the time intervals according to each of the EQ configuration information. The first data signal further includes information about a number of the EQ configuration information, and the control circuit identifies the number of the time intervals by the information about the number of the EQ configuration information.

2. The data driving apparatus of claim 1, wherein, The EQ training signal includes a training sequence repeated in each of the time intervals, and the training sequence includes a blank signal for distinguishing each of the time intervals from each other, an EQ clock training signal provided at an end of the blank signal, and an EQ test signal provided at an end of the EQ clock training signal.

3. The data driving apparatus of claim 1, wherein, In a blank signal reception interval of one training sequence, the communication circuit initializes a clock trained in a training sequence preceding the one training sequence, and in an EQ clock training signal reception interval of the one training sequence, the communication circuit performs clock training again.

4. The data driving apparatus of claim 3, wherein, The first data signal and the EQ training signal are transmitted from a data processing device, and a level of a lock signal transmitted from the data driving device to the data processing device is maintained constant when initializing the clock and performing the clock training again.

5. The data driving apparatus of claim 4, wherein, The EQ test signal includes a PRBS pattern, and the control circuit calculates a bit error rate for the PRBS pattern in each of the time intervals, and selects an EQ configuration information corresponding to a time interval having a minimum bit error rate among the plurality of time intervals as the optimal EQ configuration information, wherein PRBS is a pseudo-random binary sequence.

6. The data driving apparatus of claim 3, wherein, The EQ test signal includes test data encoded in a DC-balanced code method, and the control circuit checks whether there is any error in the test data in each of the time intervals, and selects an EQ configuration information corresponding to a time interval having a minimum number of errors in the test data among the plurality of time intervals as the optimal EQ configuration information.

7. The data driving apparatus of claim 3, wherein, The control circuit changes the configuration of the equalizer when the communication circuit receives the blank signal.

8. The data driving apparatus of claim 3, wherein, The communication circuit initializes the clock and maintains the blank signal at a constant voltage level during a predetermined time or longer when a signal having a predetermined voltage level is received during the predetermined time.

9. The data driving apparatus of claim 3, wherein, 10. A data driving device comprising: ​ communication circuitry including an equalizer, and configured to receive a first data signal containing a plurality of EQ configuration information for configuring the equalizer, and then receive an EQ training signal during a plurality of time intervals, wherein EQ is an equalizer; and control circuitry configured to evaluate reception performance of the communication circuitry for the EQ training signal in each of the plurality of time intervals by changing the configuration of the equalizer in each time interval according to each EQ configuration information, and select an optimal EQ configuration information according to the evaluation result, wherein the communication circuitry receives the first data signal through a low-speed data communication protocol, and receives the EQ training signal through a high-speed data communication protocol different from the low-speed data communication protocol.

11. A data driving apparatus comprising: communication circuitry including an equalizer, and configured to receive a first data signal containing a plurality of EQ configuration information for configuring the equalizer, and then receive an EQ training signal, the EQ training signal including a blank signal having a predetermined level, an EQ clock training signal disposed at the end of the blank signal, and an EQ test signal disposed at the end of the EQ clock training signal, wherein EQ is an equalizer; and control circuitry configured to divide a reception time of the EQ test signal into a plurality of time intervals when the communication circuitry receives the EQ test signal, evaluate reception performance of the communication circuitry for the EQ training signal in each of the plurality of time intervals by changing the configuration of the equalizer in each time interval according to each EQ configuration information, and select an optimal EQ configuration information according to the evaluation result.

12. The data driving apparatus of claim 11, wherein, the first data signal further includes information about the number of EQ configuration information, and wherein the control circuitry determines the number of time intervals to conform to the number of EQ configuration information.

13. The data driving apparatus of claim 11, wherein, each of the plurality of EQ configuration information includes a gain level of the equalizer, and the control circuitry sets the gain level of the equalizer differently in each time interval according to each EQ configuration information.

14. A data driving system comprising: data processing apparatus configured to generate a first data signal including a plurality of EQ configuration information, transmit the first data signal, generate an EQ training signal, and transmit the EQ training signal during a plurality of time intervals, wherein EQ is an equalizer, and the EQ configuration information is configuration information of the equalizer; and data driving apparatus including the equalizer, and configured to receive the EQ training signal during the plurality of time intervals after receiving the first data signal, evaluate reception performance for the EQ training signal by changing the configuration of the equalizer in each of the plurality of time intervals according to each EQ configuration information, select an optimal EQ configuration information according to the evaluation result, and then configure the equalizer according to the optimal EQ configuration information, wherein the EQ training signal includes a training sequence repeated in each time interval, wherein the training sequence includes a blank signal for distinguishing each time interval from each other, an EQ clock training signal provided at the end of the blank signal, and an EQ test signal provided at the end of the EQ clock training signal.

15. The data driven system of claim 14, wherein, The data processing device transmits a first data signal to the data driving device through a low-speed data communication protocol, and transmits the EQ training signal to the data driving device through a high-speed data communication protocol different from the low-speed data communication protocol.

16. The data driven system of claim 15, wherein, The data processing device transmits a communication signal having a communication frequency corresponding to the high-speed data communication protocol to the data driving device before transmitting the EQ training signal, and the data driving device receives the communication signal, trains a clock included in the communication signal by changing a configuration value of an oscillator included in an internal circuit every predetermined time, and determines an optimal configuration value for the communication frequency according to a training result of the clock.

17. The data driven system of claim 16, wherein, The configuration value includes any one of a reference current value, a reference voltage value, and a gain of the oscillator.

18. The data driven system of claim 14, wherein, The data driving device initializes a clock trained in a training sequence before one training sequence in a blank signal reception interval of the one training sequence, and performs clock training again in an EQ clock training signal reception interval of the one training sequence.

19. The data driven system of claim 14, wherein, The data driving device initializes a clock in a case where a signal having a predetermined voltage level is received during a predetermined time or more.

20. The data driven system of claim 19, wherein, The data driving device receives a signal having a predetermined voltage level for a predetermined time or more in each time interval to initialize a clock.

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