Device and method for post-packaging repair protection

Abstract

Disclosed herein is an apparatus and method for post-package repair protection. A device may enter a PPR mode to repair one or more memory addresses by blowing a fuse. However, if the device receives a row activation ACT signal while in the PPR mode, the fuse may be blown incorrectly. When the memory is in the PPR mode, if an ACT signal is received, a PPR mask circuit may provide a PPR mask signal. The PPR mask signal may suppress further provision of an ACT signal. In some embodiments, the memory may further include a PPR functional circuit that may monitor one or more signals used as part of a PPR operation. If these signals are in an illegal state, the PPR functional circuit may suppress the PPR operation to prevent damage to the fuse array.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, to semiconductor memory devices. Background Art

[0002] Specifically, the present disclosure relates to memory, such as dynamic random access memory (DRAM). Information can be stored in memory cells, which can be organized into rows (word lines) and columns (bit lines). At various times in the manufacture and use of a memory device, one or more memory cells may fail (e.g., become unable to store information, inaccessible by the memory device, etc.) and may require repair.

[0003] The memory device may perform repair operations on a row-by-row basis. Rows containing failed memory cells (which may be referred to as defective rows, bad rows, or failed rows) may be identified. The memory device may contain additional memory rows (which may also be referred to as redundant rows) that may be used in repair operations. During the repair operation, addresses associated with the defective rows may be redirected so that the addresses instead point to redundant rows. Some defective rows may not be identified (and / or may not become defective) until after the device is packaged, and a post-package repair (PPR) operation may be used to redirect memory addresses from defective rows to redundant rows. It is important to ensure that the device does not execute "illegal" commands while in PPR mode, as these commands may result in unintentional changes to the device. Summary of the invention

[0004] In one aspect, the present application provides a device comprising: a command decoder configured to provide a row activation signal in response to a row activation command; and a mask circuit configured to provide a mask signal at a valid level upon receiving the row activation signal when the device is in a post-packaging repair (PPR) mode, wherein the command decoder is further configured to not provide the row activation signal when the mask signal is valid.

[0005] On the other hand, the present application further provides a device comprising: a storage library comprising word lines and redundant word lines associated with row addresses; a fuse logic circuit configured to blow one or more fuses to remap the row address to the redundant word line as part of a post-package repair (PPR) operation performed when the device is in a PPR mode; and a command decoder configured to receive a row activation command and provide a row activation signal when the device is not in the PPR mode, and further configured to not provide the row activation signal when the device is in the PPR mode.

[0006] On the other hand, the present application further provides a method comprising: entering a post-packaging repair (PPR) mode of a memory device, and providing a PPR mode signal at a valid level when the memory device is in the PPR mode; receiving a first row activation command and providing a row activation signal; activating a PPR mask signal based on a mask circuit of the memory receiving the row activation signal when the PPR mode signal is at a valid level; and receiving a second row activation command but not providing the row activation signal in response to the PPR mask signal being valid. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of a memory with an ACT mask circuit according to some embodiments of the present disclosure.

[0009] Figure 3 is a schematic diagram of a PPR controller circuit according to some embodiments of the present disclosure.

[0010] Figure 4 is a schematic diagram of a PPR ACT mask circuit according to some embodiments of the present disclosure.

[0011] Figure 5 is a timing diagram of the operation of the PPR Act Mask circuit according to some embodiments of the present disclosure.

[0012] Figures 6A to 6C is a timing diagram that models the timing of various signals involved in the PPR Act Mask circuit according to some embodiments of the present disclosure.

[0013] Figure 7 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0014] Figure 8 is a schematic diagram of a PPR functional circuit according to some embodiments of the present disclosure.

[0015] Fig. 9 is a schematic diagram of library PPR address logic according to some embodiments of the present disclosure.

[0016] Fig.10 is a schematic diagram of a PPR functional circuit according to some embodiments of the present disclosure.

[0017] Fig.11 is a timing diagram of signals of a memory device having a PPR function circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part of the present system and method, and the accompanying drawings illustrate by way of illustration specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized, and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the sake of clarity, when the detailed description of certain features is obvious to those skilled in the art, it will not be discussed so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be regarded as having a limiting meaning, and the scope of the present disclosure is defined only by the appended claims.

[0019] A semiconductor memory device may store information in a plurality of memory cells. The information may be stored as a binary code, and each memory cell may store a single bit of information as a logic high (e.g., "1") or a logic low (e.g., "0"). Memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). The memory may also be organized into one or more memory banks, each of which may include a plurality of rows and columns. During operation, a memory device may receive a command and an address specifying one or more rows and one or more columns, and then execute the command on the memory cell at the intersection of the specified row and column (and / or along the entire row / column). The command may include a row activation command, such as an ACT command, which may cause a row activation (or ACT) signal to be provided in the memory, which may cause one (or more) rows to be activated.

[0020] Some memory cells may be defective, and rows containing defective memory cells may generally be referred to as defective rows (or bad rows or defective rows). Defective rows may be unable to store information and / or may become otherwise inaccessible to the memory device. In some cases, memory rows may become defective (and / or may be identified as defective) after the memory device is packaged (e.g., sealed in a chip package). The memory device may perform one or more types of post-package repair (PPR) operations to address defective rows.

[0021] The memory bank may typically include a plurality of additional memory rows, which may typically be referred to as redundant rows. During a repair operation, a row address associated with a defective row may be redirected so that it is instead associated with one of the redundant rows. The repair operation may involve storing the updated row address information in a non-volatile form in the memory (e.g., in a manner that is maintained even when the memory device is powered off). For example, a memory device may include a fuse set, which may include fuses (and / or antifuses) that may have a permanently changeable state (e.g., when the fuse / antifuse is "blown"). The state of the fuses / antifuses in the fuse set may partially determine which addresses are associated with which memory rows. During a PPR operation, the memory may enter a PPR mode and may receive a command indicating which fuses are to be blown (e.g., the address in the fuse set and the address of the defective row). Under normal operation, an ACT command may not be received during a PPR operation. However, in certain failure states, the memory device may be in a PPR mode while still providing an ACT signal. In PPR mode, these ACT signals may cause unintentional damage to the fuse array (eg, blowing fuses that were not expected to blow). Therefore, it is important to protect the memory from ACT commands and signals during PPR mode.

[0022] The present disclosure relates to apparatus, systems, and methods for post-package repair protection. A memory device may include an ACT mask circuit that may provide an ACT mask signal at an active level in response to receiving a first ACT signal when the memory device is in a PPR mode. The ACT mask signal may be used to inhibit further activation of the ACT signal. For example, a command decoder of the memory may not provide any further activation of ACT as long as the signal ACT mask is valid, regardless of any ACT command received. In this way, damage may be limited to the first activation of the ACT signal. When the PPR operation ends, the ACT mask signal may be reset to an inactive level.

[0023] In some cases (e.g., failure mode), the normal order of signals in the memory may be interrupted, which may cause the ACT mask circuit to fail to correctly provide the ACT mask signal. For example, in some cases, the memory may receive a PPR mode entry signal and then receive an ACT signal, but the ACT mask circuit may not respond to the PPR mode entry signal until after responding to the ACT signal. This may allow a second ACT signal to be provided. Each ACT signal may enable one or more internal PPR signals (e.g., fuse blown signals) to become valid. In some embodiments, the PPR function circuit may monitor the internal PPR signals and may suppress the internal PPR signals if more than one signal becomes valid at the same time. This may prevent further fuse blown operations from occurring even when the ACT mask signal fails to activate correctly.

[0024] Figure 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0025] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown to include a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown as including eight memory banks BANK0-BANK7. The memory array 118 of other embodiments may include more or fewer banks. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. The selection of the word lines WL is performed by the row decoder 108, and the selection of the bit lines BL and / BL is performed by the column decoder 110. Figure 1 In the embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory bank, and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). The read data from the bit line BL or / BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 through the complementary local data line (LIOT / B), the transmission gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transmission gate TG and the complementary local data line LIOT / B, and is written into the memory cell MC coupled to the bit line BL or / BL.

[0026] The device also includes a fuse array 125, which contains a plurality of non-volatile storage elements that can store information about addresses in the memory array 118. The fuse array 125 includes non-volatile storage elements, such as fuses or antifuses. Each fuse can be in a first state of conduction, and can be "blown" to insulate the fuse instead. Each antifuse can be in a first state of non-conduction until it is blown instead to make the antifuse conductive. When blown, each fuse / antifuse can be permanently changed. Each fuse / antifuse can be regarded as a bit, which is in one state before blowing and is permanently in a second state after blowing. For example, a fuse can represent a logic low before blowing and a logic high after blowing, while an antifuse can represent a logic high before blowing and a logic low after blowing. For simplicity, the term fuse can be generally used herein to refer to an element in the fuse array 125, but it should be understood that the fuse array 125 can include fuses, antifuses, or a combination thereof.

[0027] A particular fuse set may be represented by a fuse set address, which may specify the physical location of each fuse in the set within the fuse array 125. Certain fuse sets of the fuse array may in turn encode addresses associated with one or more memory cells of the memory array 118. For example, a set of fuses may have a state representing a row address (e.g., the state of the fuse may represent a bit of a row address). The address information in the fuse array 125 may be "scanned" out to the row latches 119 along the fuse bus (FB and xFB) 128. Each row latch 119 may be associated with a particular word line of the memory array 118. In some embodiments, only redundant rows of the memory array 118 (e.g., rows designated for repair operations) may be associated with one of the row latches 119. The address stored in a given fuse / antifuse set may be scanned out from the fuse array 125 along the fuse bus 128 and may be latched by a particular row latch 119. In this way, the address stored in the fuse array 125 may be associated with a particular row of the memory array 118. The address stored in row latch 119 may then direct an access command to the word line associated with row latch 119 .

[0028] The fuse logic circuit 126 may be located along the fuse bus 128. The fuse logic circuit 126 may include a post-package repair (PPR) circuit that can be used to change the fuse array 125. For example, the PPR circuit can perform a repair in which fuses in the fuse array are blown to "repair" the row. The memory 100 can enter a PPR mode, and one or more row addresses RA associated with a defective row of the memory can be provided to the fuse logic circuit 126. The fuse logic 126 can scan the fuse array 125 to locate a disconnected redundant row (e.g., not yet used for a repair operation), and then the fuse logic 126 can blow the fuses of the fuse array 125 to assign the row address RA to the redundant row. For example, a memory bank can have an associated PPR controller circuit that can determine whether any redundant addresses for the PPR of the memory bank are available. The PPR controller circuit can send a PPR blow signal to the fuse logic 126, which can then blow the fuses in the fuse array 125 based on these signals. For example, a high voltage may then be applied to the fuse indicated by these signals, which may "blow" the fuse, changing its state.

[0029] The semiconductor device 100 can adopt multiple external terminals, including a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses and a CS signal, a clock terminal to receive clocks CK and / CK, a data terminal DQ to provide data, and a power terminal to receive power supply potentials VDD, VSS, VDDQ and VSSQ.

[0030] The clock terminal is provided with external clocks CK and / CK, which are provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 110 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuit included in the input / output circuit 122, for example, to the data receiver to time the reception of the write data.

[0031] A memory address may be provided to the C / A terminal. The memory address provided to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and provides the decoded row address XADD to the row decoder 108, and provides the decoded column address YADD to the column decoder 110. The address decoder 104 may also provide a decoded bank address BADD, which may indicate the bank of the memory array 118 containing the decoded row address XADD and the column address YADD. A command may be provided to the C / A terminal. Examples of commands include timing commands for controlling various operation timings, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0032] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry that decodes the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal that selects a word line and a column command signal that selects a bit line. In some embodiments, the command decoder 106 and the address decoder 104 may be coupled together so that the command decoder 106 indicates to the address decoder 104 what type of address is provided. In some embodiments, the command decoder 106 and the address decoder may be coupled together via the C / A input circuit 102.

[0033] The device 100 may receive an access command as a row activation command ACT. When the row activation command ACT is received, an internal row activation signal is provided to the bank address BADD and the row address XADD in time.

[0034] The device 100 may receive an access command as a read command. When the read command is received, the bank address BADD and the column address YADD are provided together with the read command in time, and the read data is read from the memory cell corresponding to the row address XADD and the column address YADD in the memory array 118. For example, the row decoder may access the word line associated with the row latch 119 having the address matching XADD. The read command is received by the command decoder 106, which provides an internal command to provide the read data from the memory array 118 to the read / write amplifier 120. The row decoder 108 may match the address XADD with the address stored in the row latch 119, and then may access the physical row associated with the row latch 119. The read data is output to the outside from the data terminal DQ via the input / output circuit 122.

[0035] The device 100 can receive an access command as a write command. When the write command is received, the write command is provided to the bank address BADD and the column address YADD in time, and the write data provided to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder provides an internal command so that the write data is received by the data receiver in the input / output circuit 122. The row decoder 108 can match the address XADD with the address stored in the row latch 119, and then access the physical row associated with the row latch 119. A write clock can also be provided to the external clock terminal for timing the reception of the write data by the data receiver of the input / output circuit 122. The write data is provided to the read / write amplifier 120 via the input / output circuit 122, and is provided to the memory array 118 by the read / write amplifier 120 to be written into the memory cell MC.

[0036] The device 100 may also receive a command that causes it to perform an automatic refresh operation. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating an automatic refresh command. In some embodiments, an automatic refresh command may be issued to the memory device 100 from the outside. In some embodiments, the automatic refresh command may be periodically generated by a component of the device. In some embodiments, the refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF may be activated once immediately after the command is input, and may thereafter be cyclically activated at a desired internal timing. Thus, the refresh operation may continue automatically. The self-refresh exit command may stop the automatic activation of the refresh signal AREF and return to an idle state.

[0037] The refresh signal AREF is provided to the refresh address control circuit 116. The refresh address control circuit 116 provides the refresh row address RXADD to the row decoder 108, and the row decoder can refresh the word line WL indicated by the refresh row address RXADD. The refresh address control circuit 116 can control the timing of the refresh operation, and can generate and provide the refresh address RXADD. The refresh address control circuit 116 can be controlled to change the details of the refresh address RXADD (for example, how to calculate the refresh address, the timing of the refresh address), or can be based on internal logic operations. In some embodiments, the refresh address control circuit 116 can perform an automatic refresh operation and a targeted refresh operation, in which the word lines of the memory array 118 are sequentially refreshed, and in which specific word lines of the memory are sequentially refreshed out of the automatic refresh operation in the targeted refresh operation.

[0038] The power supply terminals are provided with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are provided to an internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS provided to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0039] Power supply potentials VDDQ and VSSQ are also provided to the power supply terminals. The power supply potentials VDDQ and VSSQ are provided to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ provided to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS provided to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ provided to the power supply terminals may be different potentials from the power supply potentials VDD and VSS provided to the power supply terminals. The power supply potentials VDDQ and VSSQ provided to the power supply terminals are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0040] In some embodiments, the normal "operational" signals of the memory 100 may interfere with the correct operation of the PPR mode. For example, if the memory 100 receives (or incorrectly generates) an ACT command / row access signal while in PPR mode (or if the device accidentally enters PPR mode upon receiving an ACT command), the ACT command / signal may cause the fuses of the fuse array 125 to be inadvertently blown. This in turn may cause problems with the correct operation of the memory. The memory 100 may include one or more circuits that may suppress various signals to prevent the ACT command from causing inadvertent fuse blowing, as described in more detail herein.

[0041] Figure 2 is a block diagram of a memory with an ACT mask circuit according to some embodiments of the present disclosure. In some embodiments, the memory 200 may be included in Figure 1 The memory device 100 of FIG. 200 shows components that can be used in PPR mode, which can be Figure 1 is omitted, and on the contrary, Figure 1 Certain features and components shown in Figure 2 Omitted in . Figure 2 The components can be such as Figure 1 The example memory 200 shows various signals which are shown as having a certain number of bits (e.g., 18-bit row address RA<17:0>). However, it should be understood that other lengths of the various signals may be used in other embodiments.

[0042] The memory 200 includes an ACT command decoder 202 that receives command signals such as CA, CS, and a clock signal Clk. The ACT command decoder 202 can determine whether to provide an ACT command and provide an address associated with the ACT command. For example, the ACT command decoder 202 can provide a signal REXAL, which can be a pulse signal when the signal ACT goes high, as well as a row address RA and a bank address RBA. These signals can be provided to an ACT control center circuit 208, which can then provide signals to various banks (e.g., Bank0 and Bank1 as shown) and a memory array ( Figure 2 ACT control circuits 220 and 222 associated with the device (not shown).

[0043] Command and clock signals (e.g., CA, CS, and Clk) may also be provided to a mode register (MR) control circuit 204. The MR control circuit 204 may manage information stored in the mode register through, for example, mode register read and write operations. The MR control circuit 204 may receive a PPR enable signal PPREn (and / or one or more commands) that may cause the MR control circuit 204 to provide a PPR mode signal MDPPR at an active level. The PPR mode signal MDPPR at an active level may indicate that the device is in a PPR mode.

[0044] When the device 200 is not in PPR mode (e.g., MDPPR is invalid), the ACT control center circuit 208 can provide a signal RRAST based on the signal REXAL (e.g., ACT) and RBA to activate one of the group-level ACT control circuits 220 and 222. The ACT control center circuit 208 can also pass along a row address RA, which can cause the memory cells in the activated bank to be accessed. The row address RA can be stored in a row latch associated with each bank (e.g., Figure 1 The ACT control center circuit 208 may provide an idle signal IdleF, which is invalid when the device is not idle (eg, performing at least one action) and is valid when the device is idle.

[0045] In PPR mode (e.g., when signal MDPPR is active), commands may be used to retrieve information (e.g., fuse addresses) from the memory array that may be used to determine which fuses to blow. For example, each bank may be associated with a PPR controller 224 and 226. When activated (e.g., by an address in RAlatch), the PPR controller may determine whether a PPR address is available. Figure 2 In an example embodiment, there may be two PPR addresses for each library (e.g., 2 redundant rows reserved for PPR), which may be labeled PPR0 and PPR1. Redundancy control circuits 225 and 227 associated with each library may determine whether either of the addresses PPR0 or PPR1 of the library is available (e.g., not used in PPR operations to date). Redundancy control circuits 225 and 227 may provide a signal EAvailPPR, which may indicate which (if any) of the addresses PPR0 or PPR1 of the library is available. In some embodiments, signal EAvailPPR may be a two-bit signal, each bit being associated with one of row addresses PPR0 and PPR1. In some embodiments, the memory may use a first PPR address PPR0 before using a second address PPR1.

[0046] Signal EavailPPR can contribute one bit to the total availability signal PPRfzBnkOR, which has one bit (e.g., 8 bits) for each bank. In the case where any PPR fuse associated with the bank is available (e.g., in the case where any bit of EavailPPR is high for the bank), each bit of PPRfzBnkOR can be high. Signal PPRfzBnkOR can be provided to MR control circuit 204 and can be combined with enable signal PPREn (e.g., through an AND gate) to generate signal MR25OP. This can be used to tell the MR control circuit whether to enter MDPPR mode.

[0047] Various signals can be provided to the fuse control circuit 212, which can blow one or more fuses as part of the PPR operation. For example, an AND gate can combine signals PPREn, IdleF, RBA and MDPPR to generate a signal PPRRegAdd. When all signals IdleF, PPREn and MDPPR are valid, the signal PPRRegAdd can pass the library address RBA as the signal PPRRegAdd. The fuse control circuit 212 can also receive a fuse blow signal EBlowPPRRow, an enable signal MDPPR and a row address RA indicating which PPR address is disconnected. These can be used to blow the fuses in the fuse array to redirect the fuse address indicated by EBlowPPRRow associated with the library indicated by PPRRegAdd to be associated with the address RA. The fuse blow operation can occur with a timing based on a clock signal PPRclk, which is generated by the oscillator 210 when the signal MDPPR is valid.

[0048] The memory 200 may also include an ACT mask circuit 206, which may be used to protect the memory 200 in the event that the ACT signal is activated during a PPR operation. The ACT mask circuit 206 may provide a signal ACT mask. When the signal ACTMask is at an active level, the ACT command decoder 202 may be prevented from providing a subsequent activation of REXAL (which is a pulse activated in response to ACT). In other words, the signal REXAL may be suppressed and may not be provided even if a subsequent ACT command is received.

[0049] When the signal MDPPR is valid and a REXAL pulse is received, the ACT mask circuit 206 can provide the signal ActMask at an active level. The ActMask circuit 206 can continue to provide the signal ActMask at an active level until the signal PPREn indicates that the PPR operation is over. This can prevent the REXAL pulse from being provided, which can prevent the ACT command from causing unintentional operation during the PPR mode.

[0050] In some embodiments, the signal ActMask can also cause the oscillator 210 to start providing the PPR clock signal PPRclk. The fuse logic circuit 212 can perform the PPR operation using a timing based on the clock signal PPRclk. Therefore, if the signal PPRclk is not provided, the PPR operation may not be performed. This can add an additional layer of protection to help prevent the PPR operation from being performed before the ACT signal (e.g., REXAL) is properly masked. In this way, when ActMask is invalid, the fuse can be inhibited from blowing to prevent damage (e.g., accidental fuse blowing) caused by accidental activation of REXAL (e.g., ACT).

[0051] Figure 3 is a schematic diagram of a PPR controller circuit according to some embodiments of the present disclosure. In some embodiments, the PPR controller circuit 300 may be included in Figure 2 224 and / or 226 of the PPR controllers 224 and / or 226. There may be a PPR controller 300 associated with each bank of the memory device. The PPR controllers 300 may be coupled together in series. The PPR controller 300 receives a signal EBlowPPRRow_in as the signal EBlowPPRRow from the previous PPR controller in the series and provides a signal EBlowPPRRow_out, which is provided to the next PPR controller or fuse control circuit (e.g., Figure 2 The first PPR controller in the "chain" may receive an initial EBlowPPRRow signal to initialize the signal. For example, the initial EBlowPPRRow signal may have two bits at a low logic level (e.g., by coupling the EBlowPPRRow_in terminal to a ground voltage such as VSS).

[0052] Figure 3 The PPR controller 300 of EBlowPPRRow represents an embodiment in which each bank has two PPR addresses (e.g., PPR0 and PPR1). The bits of the signal EBlowPPRRow may indicate whether either of the two PPR addresses should be blown as part of the PPR operation. By linking the signal, a single two-bit signal may be provided to the fuse logic, which together with a signal indicating which bank is valid (e.g., PPRRegAdd) may allow the fuse logic to use the indicated fuse address as part of the PPR operation. In some embodiments, the signal EBlowPPRRow may include more bits. For example, in some embodiments, each bank may have more PPR addresses, and therefore more bits of the EBlowPPRRow signal. Fig. 9 An alternative PPR controller circuit of this example embodiment is described in more detail, wherein each bank is divided into two regions, each region has two PPR addresses, and the EBlowPPRRow signal has four bits.

[0053] The PPR controller 300 is controlled by an ACT control circuit (eg, Figure 2220) receives signals / RAlatch and Refresh. These signals may indicate whether the bank is excited and whether the bank has been activated to perform a refresh operation, respectively. If the bank associated with the PPR controller 300 is valid, the signal / RAlatch is provided as a negative pulse (e.g., high, low, high). If the associated bank is undergoing a refresh operation, the signal Refresh is high, otherwise it is low. These two signals are used as inputs to a NOR gate 302, which provides a high output only when the signals / RAlatch and Refresh are low (e.g., the bank is valid but not refreshed). The output of the NOR gate 302 is provided to an input terminal of a NAND gate 304, which has another input coupled to a signal MDPPR, the input indicating whether the device is in PPR mode. The NAND gate 304 provides a signal to the input of a latch circuit 306, which may be a pair of cross-coupled NAND gates. The latch 306 also has a reset terminal coupled to the signal MDPPR. Thus, latch 306 stores a low logic value only when signals / RAlatch and Refresh are low, but signal MDPPR is high, indicating that the associated bank is valid (but not refreshed) and the device is in PPR mode.

[0054] The latch outputs its stored value to the inputs of two NOR gates 314 and 316 through inverter 308. When latch 306 stores a low logic value, the output of inverter 308 will be high. The other inputs of NOR gates 314 and 316 are coupled to a bit of signal EAvailRowPPR, which indicates whether the PPR address associated with the bank is available (e.g., from Figure 2 Specifically, NOR gate 316 is coupled to the first bit of the signal (eg, EAvailRowPPR) through inverter 310. <0> ), and the input of NOR gate 314 is coupled to the output of NAND gate 312. NAND gate 312 has EAvailRowPPR (e.g., EAvailRowPPR <1> ) and the inverted first bit (eg, from inverter 310) as inputs. If the second bit of EAvailRowPPR is high, and if the first bit is low (eg, EAvailRowPPR = <0, 1>), the output of NAND gate 312 is simply low.

[0055] If either input (e.g., from inverter 308 or from inverter 310) is high, the output of first NOR gate 316 is a low logic value. Thus, if the associated bank is valid (but not refreshed) and in PPR mode, or if the first PPR address is available (e.g., EAvailRowPPR is low), first NOR gate 316 provides a low logic value. If the associated bank is valid (but not refreshed) and in PPR mode, or if the second PPR address is available (e.g., the output of NAND gate 312 is high), second NOR gate 314 provides a low logic level.

[0056] The outputs of NOR gates 316 and 314 are provided as inputs to NOR gates 319 and 318, respectively. Another input of NOR gate 319 is coupled to the first bit of EBlowPPRRow_in, and another input of NOR gate 318 is coupled to the second bit of EBlowPPRRow_in. The outputs of NOR gates 318 and 319 are coupled through inverters 320 and 321, respectively, to form the bits of output signal EBlowPPRRow_out. Thus, each bit of EBlowPPRRow_out may be high if the associated bit of EBlowPPRRow_in is high, or if the current bank is activated as part of the PPR mode and one of the PPR addresses is available.

[0057] Figure 4 is a schematic diagram of a PPR ACT mask circuit according to some embodiments of the present disclosure. In some embodiments, the circuit 400 may be included in Figure 2 The Act mask circuit 400 may provide a signal MPPRActMask (eg, Figure 2 ACTMask), which can inhibit operation when the device is in PPR mode.

[0058] The Act mask circuit 400 includes a NAND gate 402 that receives a signal REXAL (which is a pulse based on the signal ACT) and a PPR mode signal MDPPR. When both the signals REXAL and MDPPR are valid (e.g., an illegal ACT signal during the PPR mode), the NAND gate 402 provides a signal PPRACT at a low level to the input terminal Sf of the latch 404. In some embodiments, the latch 404 may include two cross-coupled NAND gates. When the latch 404 stores PPRACT at a low level, the output terminal Q of the latch 404 can provide a high level signal to the buffer 406, which can in turn provide a high level (e.g., an effective level) signal MPPRActMask. When the signal PPRACT is at a high level (e.g., indicating that at least one of REXAL and MDPPR is invalid) and the signal MDPPR is at a low level, the latch can store a low value and the MPPRActMask can be at a low level.

[0059] ACT mask circuit 400 may continue to provide signal MPPRActMask until reset. The reset terminal of latch 404 is coupled to signal MDPPR through buffer 408. Buffer 408 may help reduce noise in reset terminal Rf of latch 404. In some embodiments, buffer 408 may be omitted. When MDPPR drops to a low level, buffer 408 provides a low signal to reset terminal Rf of latch 404, which may cause latch 404 to reset, thereby causing signal MPPRActMask to return to a low logic level (e.g., invalid).

[0060] Figure 5 is a timing diagram of the operation of the PPR Act Mask circuit according to some embodiments of the present disclosure. In some embodiments, the timing diagram 500 may represent a Figure 2 206 and / or Figure 4 The operation of the ACT mask circuit of 400.

[0061] Timing diagram 500 shows a command bus, where arrows represent different commands received (e.g., in a command such as Figure 1 The timing diagram 500 also shows binary signals such as the internal PPR mode signal MDPPRE, the ACT-based pulse REXAL, the PPRACT signal (e.g., which is Figure 4 ACT mask circuit 400 inside) and PPR ACT mask signal MPPRActMask.

[0062] At an initial time t0, the memory device may receive a mode register write (MRW) signal indicating entry into PPR mode. This may cause the PPR mode signal MDPPRE to rise to an effective level. At a first time t1, the device may receive (or may internally generate) an ACT command. The ACT command at t1 causes a pulse of the signal REXAL to be generated. Therefore, since both MDPPRE and REXAL are valid (e.g., at a high level), the signal PPRACT may drop to a low logic level, which may then be stored in a latch (e.g., 404) of the PPRAct mask circuit, causing the signal MPPRActMask to rise to a valid (e.g., high) logic level. In some embodiments, the first ACT command at t1 may provide row address data to be repaired by the PPR operation.

[0063] At time t2, a second ACT signal may be received as a command. This command may be illegal because only one ACT command is allowed and an ACT command already existed at t1. However, in this case, since the signal MPPRActMask is valid, the command decoder (e.g., Figure 2 202) does not provide a REXAL pulse. In the absence of a REXAL pulse, the wrong fuse will not be blown. In this way, the blowing of an unintentional fuse can be limited to a single illegal ACT command, while subsequent ACT commands are shielded. For example, if the first ACT is a legal command, the second ACT is shielded and no fuse is accidentally blown. In some embodiments, the device may mistakenly enter PPR mode, and both ACT commands may be illegal, in which case only the ACT at t1 causes an unintentional blown fuse. Later, when the device completes the PPR operation, the signal MDPPRE may fall to a low level, which can reset the signal MPPRActMask to a low level.

[0064] Figures 6A to 6C is a timing diagram for modeling the timing of various signals involved in the PPR Act Mask circuit according to some embodiments of the present disclosure. In some embodiments, the timing diagram may represent a timing diagram such as Figure 2 206 and / or Figure 4 The operation of the ACT mask circuit 400. Timing diagrams 600a to 600c may show generally similar Figure 5 500, however, in timing diagrams 600a to 600c, different circuit conditions that may affect the timing of various signals are simulated. Figures 6A to 6C Certain voltages and certain rates and durations of signals are shown in FIG, but these are for illustrative purposes only, and other voltages and timings may be used in other example embodiments.

[0065] Fig. 6A shows a similar Figure 5 The timing diagram 600a of the behavior shown. The command to enter PPR mode is received at the initial time t0, and then the ACT command is received at t1. Figure 5 Different, in Fig. 6A In the example, the ACT command is received before the signal MDPPRE rises to the active level. However, the signal MDPPRE does rise to the high level before the pulse REXAL is provided, so the mask signal MPPRActMask is correctly activated.

[0066] Figure 6B A timing diagram 600b is shown, which shows a situation where the command pulses for MRW (e.g., PPR entry) and ACT are shortened, which may result in closer timing between MDPPRE and REXAL. In timing diagram 600b, signals MDPPRE and REXAL begin to rise to a high level at approximately the same time, however, MDPPRE rises slower than REXAL. However, the ACT mask circuit still correctly recognizes signals MDPPRE and REXAL as being valid at the same time, and correctly raises signal MPPRActMask to a high level.

[0067] Figure 6C A timing diagram 600c is shown, which represents a memory condition in which the signal MPPRActMask fails to activate correctly. Specifically, timing diagram 600c shows a memory operating outside of normal specifications. For example, a system voltage such as VPERI can be lower than the normal specification voltage. This may cause various operations to occur slower than normal. In timing diagram 600c, although command MRW (e.g., PPR enters) is received before signal ACT, signal MDPPRE does not begin to rise to a high level until after pulse REXAL. Therefore, signal MPPRActMask does not rise to a high level, and a subsequent ACT signal (e.g., a subsequent REXAL pulse) is not masked.

[0068] In some embodiments, the memory may use activation of multiple signals to activate further shield signals (and / or other methods of disabling PPR operation) to provide further protection (e.g., in conjunction with Figure 6C In some embodiments, these may be in addition to the ACT mask circuits.

[0069] Figure 7 is a block diagram of a memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 700 may include Figure 1 The memory device 700 may be substantially similar to Figure 2200, except that the memory device 700 includes an additional PPR function circuit 730, which can disable the PPR operation when an illegal combination of PPR signals is indicated. For the sake of brevity, similar descriptions of the memory device 200 will not be described. Figure 2 The features and operations of the memory device 700 are described with reference to the memory device 200 .

[0070] The memory device 730 includes a PPR functional circuit 730 that receives an EBlowPPRRow signal, which is a multi-bit signal having bits indicating which PPR addresses are available for use. The PPR functional circuit 730 provides a signal fnPPR that can be used to inhibit operation of the fuse control circuit 712 (e.g., blow a fuse) when the state of the signal EBlowPPRRow indicates an illegal operation. The signal fnPPR can generally be activated by the signal PPRen, and when the signal fnPPR is valid (e.g., at a high logic level), the PPR operation can continue. When the PPR functional circuit 730 detects an illegal operation (e.g., an illegal state of one or more signals), the signal fnPPR can be provided at an invalid level (e.g., a low logic level), which can suspend the PPR operation (e.g., by inhibiting one or more signals).

[0071] Instances of illegal operations can be Figure 6C , where the signal MPPRActMask fails to activate properly after the first ACT signal and is activated only after the second ACT signal. In this case, the two ACT signals may result in incorrect operation, which may generate an illegal state of one or more internal PPR signals. For example, under normal PPR operation, the two bits of EBlowPPRRow are not at a high logic level at the same time. However, in the case where more than one ACT signal is received in PPR mode, the two bits of EBlowPPRRow may end up being valid. The PPR function circuit 730 may use this (and / or other signal activation modes) to determine that the PPR operation is in an illegal state. When the PPR function circuit 730 determines an illegal operation, the signal fnPPR may be switched to an invalid level.

[0072] As an example of how to use the signal fnPPR to inhibit operation, in Figure 8In an example embodiment of the present invention, the signal fnPPR is provided to an AND gate along with the signals IdleF, RBA, and MDPPR. Therefore, the signal RBA is passed as the signal PPRRegAdd only when all three of fnPPR, IdleF, and MDPPR are valid. If the signal fnPPR is invalid, the signal PPRRegAdd may be invalid (e.g., all bits at a low level), and the fuse control circuit 712 may not perform any action. Other methods of inhibiting PPR operation may be used in other example embodiments.

[0073] Figure 8 is a schematic diagram of a PPR functional circuit according to some embodiments of the present disclosure. In some embodiments, the PPR functional circuit 800 may be included in Figure 7 The PPR function circuit 730 is used.

[0074] The PPR function circuit 800 includes a NAND gate 802 having an input terminal coupled to each bit of EBlowPPRRow. Therefore, if both bits of EBlowPPRRow are high (e.g., an illegal state of the signal), the NAND gate outputs a low logic level. The output of the NAND gate 802 is provided to the input terminal of a second NAND gate coupled to PPREn. If either (or both) of the inputs of the second NAND gate 804 are at a low logic level, the output of the second NAND gate 804 is high, which passes through an inverter 806 to provide a signal fnPPR. Therefore, if PPREn is high and at least one bit of EBlowPPRRow is low, the signal fnPPR is high. If both bits of EBlowPPRRow are high (or if PPREn is low), the signal fnPPR is at a low level.

[0075] In some embodiments, the memory may contain more than one PPR address per bank, and the signal EBlowPPRRow may have more than two bits. Figures 9 to 11 Such embodiments are described, as well as example modifications to the PPR controller and PPR functional circuitry that accommodate the increased number of bits of EBlowPPRRow. Such embodiments may also include a PPR Act mask circuit (e.g., Figure 2 206).

[0076] Fig. 9 is a schematic diagram of the library PPR address logic according to some embodiments of the present disclosure. In some embodiments, the library PPR address logic 900 may be similar to Figure 2 The PPR controllers 224 and 226 and / or Figure 3PPR controller 300. Bank PPR address logic 900 shows a set of banks 910 to 980, each bank is divided into two regions (e.g., 910a and 910b). For example, the two regions of the bank can be on opposite sides of the center region of the memory die. Different regions of the bank can be accessed based on a portion of the row address. For example, in Fig. 9 In the embodiment of the present invention, the 13th bit (X13) of the row address can be used to determine which area to access. In other embodiments, other ways of directing operations between banks can be used.

[0077] Each bank may have four PPR addresses, two associated with each region of the bank. For example, the first region 910a of Bank0 is associated with addresses PPR0 and PPR1, while the second region 910b of Bank0 is associated with addresses PPR2 and PPR3. Bank PPR address logic 900 provides a signal EBlowPPRRow, which is a multi-bit signal indicating which of the four PPR addresses are available for active banks. Each region of each bank provides a PPR availability signal (e.g., similar to Figures 2 to 3 EAvailRowPPR), which indicates whether the two PPR addresses of the area are available.

[0078] Similar to the previous Figure 3 The PPR controller discussed, Fig. 9 The PPR controller is connected in series with logic series 904a and 904b. Figure 3 Different, in Fig. 9 There are two such chains, a first logic family 904a coupling all signals of a first region (e.g., 910a to 980a) and a second logic family 904b coupling all signals of a second region (e.g., 910b to 980b). Each logic family 904a-b receives an availability signal from the bank of that region and provides a portion of the overall PPR fuse signal EBlowPPRRow. For example, logic family 904a provides the first and second bits of signal EBlowPPRRow, while logic family 904b provides the third and fourth bits of signal EBlowPPRRow.

[0079] Each region of each bank may be coupled to a PPR controller 906a or 906b, which may be coupled in series to form a logic family 904a or 904b, respectively. The PPR controller 906a or 906b may generally be similar to Figure 3906a. As the controllers may be substantially similar, only a single PPR controller 906a will be discussed in detail. The PPR controller 906a receives a pair of input bits from the previous PPR controller of the logic chain 904a. The PPR controller 906a is also coupled to an availability signal from an associated bank 910a. Each bit of the availability signal may be valid if the associated PPR address of the bank area 910a is ready to be blown, and each bit of the availability signal may be at a low logic level if the PPR address is not ready to be blown (e.g., because it is already in use).

[0080] Each PPR controller 906a may include a logic gate that can be used to generate a signal EBlowPPRRow_out based on EBlowPPRRow_in and an availability bit from an associated bank. Fig. 9 In , only a single NOR gate and inverter (eg, OR gate) is shown for each bit of the signal, where the signal EBlowPPRRow_out is high if the previous bit EBlowPPRRow_in or the availability signal from the associated bank is high. Fig. 9 Additional functionality is not shown, but in some embodiments, the PPR controller 906a may include Figure 3 One or more functions of the PPR controller 300. For example, the PPR controller 906a may also consider signals such as / RAlatch, Refresh, and / or MDPPR.

[0081] Similar to About Figure 3 The priority between the addresses discussed is Fig. 9 In the example, the PPR addresses may be used in a specific order. In particular, address PPR0 may be blown before address PPR1 is used for the first region of a given bank, and address PPR2 may be blown before address PPR3 is used for the second region of a given bank. Since only one of the four addresses may be blown at a time, more than one high bit from a given bank region (e.g., both bits 0 and 1, both bits 2 and 3, bits 0 and 2) may indicate an illegal operation.

[0082] Fig.10 is a schematic diagram of a PPR functional circuit according to some embodiments of the present disclosure. In some embodiments, the PPR functional circuit 1000 may be included in Figure 7 The PPR function circuit 730 of FIG. 1000 may be similar to Figure 8 The PPR function circuit 800, except that the PPR function circuit 1000 is in the example about Fig. 9The embodiment discussed operates in which there are four bits of the EBlowPPRRow signal representing two pairs of PPR addresses, each associated with a region of the bank.

[0083] The PPR function circuit 1000 includes: a NOR gate 1002, whose input terminal is coupled to EBlowPPRRow <0> and EBlowPPRRow <1> ; and NAND gate 1004, whose input terminal is coupled to EBlowPPRRow <2> and EBlowPPRRow <3> The outputs of NOR gate 1002 and NAND gate 1006 are provided to the input terminals of the NAND gate. <0> and EBlowPPRRow <1> When both are low, they provide a high logic value, and when either is high, they provide a low logic value. <2> and EBlowPPRRow <3> The NAND gate 1006 provides a low logic value when both inputs are high, and provides a high logic value when at least one of them is low. The NAND gate 1006 only provides a low value when both inputs are high. Therefore, the NAND gate 1006 only provides a low value when EBlowPPRRow <2> and EBlowPPRROw <3> When at least one of EBlowPPRRow is low and <0> and EBlowPPRRow <1> Provides a low value when both are low.

[0084] PPR functional circuit 1000 also includes NOR gate 1012, NAND gate 1014, and NAND gate 1016 that function in a similar manner to gates 1002, 1004, and 1006, respectively. However, NOR gate 1012 is coupled to EBlowPPRRow <2> and EBlowPPRRow <3> , and the NAND gate 1014 is coupled to EBlowPPRRow <0> and EBlowPPRRow <1> Therefore, the output of NAND gate 1016 is only in EBlowPPRRow <0> and EBlowPPRRow <1> When at least one of EBlowPPRRow is low and <2> and EBlowPPRRow <3> Low when both are low.

[0085] The output terminals of NAND gates 1006 and 1016 are provided to NAND gate 1020. The output of NAND gate 1020 is low only when both NAND gates 1006 and 1016 provide high logic outputs. The output of NAND gate 1020 is provided to NAND gate 1022 which is also coupled to signal PPREn. The output of NAND gate 1022 is provided through inverter 1024 to provide signal fnPPR. Therefore, in order for fnPPR to be high, PPREn must be at a high logic level and EBlowPPRRow <2> and EBlowPPRRow <3> and EBlowPPRRow <0> and EBlowPPRRow <1> In addition, in order for fnPPR to be high, only one of the pair (EBlowPPRRow <0> / EBlowPPRRow <1> One of EBlowPPRRow <2> / EBlowPPRRow <3> One of the above) can be effective immediately.

[0086] Fig.11 1100 is a timing diagram of signals of a memory device having a PPR function circuit according to some embodiments of the present disclosure. In some embodiments, the timing diagram 1100 may represent a timing diagram such as Figure 7 The timing diagram 1100 shows the signals in the memory of 700. Figure 6C The waveforms produced under the conditions discussed are those where the signal MPPRActMask fails to properly activate in response to a REXAL (e.g., ACT) pulse when MDPPR is active. However, in timing diagram 1100, the memory includes additional PPR functional circuitry (e.g., Figure 7 of 730).

[0087] At the initial time t0, the memory enters the PPR mode and the signal MDPPR rises to a high level. At the initial time, the memory also receives an ACT command, which causes a pulse of the signal REXAL. However, due to incorrect behavior (e.g., out of specification voltage), the signal MPPRActMask may be improperly maintained at a low level. In response to the ACT command, the signal EBlowPPRow <0> may become active to indicate that the first fuse address (e.g., PPR0) should be blown. This in turn activates the signal PPRRegAdd <0> However, since the signal MPPRActMask is at a low level, the PPR clock signal (eg, Figure 7 oscillator 710 provided) may remain invalid.

[0088] At a first time t1, the memory may receive another ACT command and provide a second pulse of the signal REXAL. Since this pulse of REXAL is good after MDPPR becomes valid at the initial time t0, the signal MDPPRActMask may become valid, which in turn may activate the oscillator to begin providing the signal PPRAddClk. This REXAL pulse may also cause the signal EBlowPPRRow to <2> becomes valid.

[0089] EBlowPPRRow <0> and EBlowPPRRow <2> At the same time, the PPR function circuit can reduce the signal fnPPR to an invalid level. This in turn can suppress the PPRRegAdd signal (for example, as caused by PPRRegAdd <0> Since no PPRRegAdd signal can be active while fnPPR is inactive, PPR operation can be inhibited. Later, when signal MDPPR falls to a low level, the circuit can be reset and fnPPR can return to a high logic level.

[0090] Of course, it should be understood that according to the present systems, devices and methods, any of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and / or processes, or separated and / or performed between separate devices or device parts.

[0091] Finally, the above discussion is intended only to illustrate the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that a person of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative and not intended to limit the scope of the appended claims.

Claims

1. A semiconductor device comprising: a command decoder configured to provide a row activation signal in response to a row activation command; as well as A mask circuit is configured to receive the row activation signal and further configured to provide a mask signal at a valid level when the row activation signal is received when the device is in a post-packaging repair (PPR) mode, wherein the command decoder is further configured to receive a second row activation command but not provide the row activation signal in response to the mask signal being valid when the device is in the PPR mode.

2. The semiconductor device of claim 1 , further comprising a mode control circuit configured to provide a PPR mode signal at an effective level in response to the device being in the PPR mode, wherein the mask circuit is configured to provide the mask signal at an effective level in response to receiving the row activation signal when the PPR mode signal is effective. 3 . The semiconductor device of claim 1 , further comprising an oscillator circuit configured to provide a PPR clock signal in response to the mask signal being valid. 4 . The semiconductor device of claim 3 , wherein a PPR operation is performed based in part on the PPR clock signal.

5. A semiconductor device comprising: a command decoder configured to provide a row activation signal in response to a row activation command; a mask circuit configured to provide a mask signal at an active level upon receiving the row activation signal when the device is in a post-package repair (PPR) mode, wherein the command decoder is further configured to not provide the row activation signal when the mask signal is active; as well as A PPR function circuit is configured to provide a PPR function signal at an effective level when the device is in the PPR mode, wherein when the PPR function signal is at the effective level, the PPR operation, and wherein the PPR function circuit is further configured to determine the state of the PPR fuse signal and provide the PPR fuse signal at an invalid level if the state of the PPR fuse signal indicates an illegal operation. A PPR function signal is provided, and wherein the PPR fuse signal comprises a multi-bit signal, and wherein the illegal operation is determined based on a plurality of bits of the multi-bit signal being simultaneously at a high logic level. 6 . The semiconductor device of claim 5 , wherein the command decoder is configured to provide a memory bank address, and wherein the memory bank address is suppressed by the PPR function circuit in response to the PPR function signal being at the inactive level.

7. A semiconductor device comprising: a memory bank including a word line associated with a row address and a redundant word line; a fuse logic circuit configured to blow one or more fuses to remap the row address to the redundant word line as part of a PPR operation performed when the device is in a post-package repair (PPR) mode; a command decoder configured to receive a row activation command and provide a row activation signal when the device is not in the PPR mode, and a PPR mask circuit configured to receive the row activation signal and further configured to provide a PPR mask signal at an active level in response to receiving the row activation signal when the device is in the PPR mode, wherein the command decoder is further configured to not provide the row activation signal when the device is in the PPR mode, Wherein in response to the PPR mask signal being at the active level, the command decoder is configured to inhibit the row activation signal. 8 . The semiconductor device of claim 7 , wherein the PPR mask circuit is configured to be reset and provide the PPR mask signal at an inactive level in response to the device exiting the PPR mode.

9. The semiconductor device of claim 7, further comprising a PPR controller associated with the memory bank, wherein the PPR controller is configured to provide a PPR fuse signal having a state indicating whether the redundant word line is ready for use.

10. A semiconductor device comprising: a memory bank including a word line associated with a row address and a redundant word line; a fuse logic circuit configured to blow one or more fuses to remap the row address to the redundant word line as part of a PPR operation performed when the device is in a post-package repair (PPR) mode; a command decoder configured to receive a row activation command and provide a row activation signal when the device is not in the PPR mode, a PPR mask circuit configured to provide a PPR mask signal at an active level in response to receiving the row activation signal when the device is in the PPR mode, wherein the command decoder is further configured to not provide the row activation signal when the device is in the PPR mode, wherein in response to the PPR mask signal at the active level, the command decoder is configured to suppress the row activation signal; a PPR controller associated with the memory bank, wherein the PPR controller is configured to provide a PPR fuse signal having a state indicating whether the redundant word line is ready for use; as well as a PPR functional circuit configured to determine whether the PPR fuse signal is in an illegal state, and configured to provide a PPR functional signal when the device is in the PPR mode unless the PPR fuse signal is in the illegal state, and wherein the memory bank includes a second redundant word line, and wherein the PPR fuse signal has a first bit associated with the redundant word line and a second bit associated with the second redundant word line, and wherein the PPR functional circuit is configured to determine that the PPR fuse signal is in the illegal state when the first bit and the second bit are simultaneously at a high logic level.

11. A method for operating a memory device, comprising: entering a post-package repair PPR mode of a memory device, and providing a PPR mode signal at an active level when the memory device is in the PPR mode; using a command decoder to receive a first row activation command and provide a row activation signal; activating a PPR mask signal based on a mask circuit of the memory device receiving the row activation signal at an active level when the PPR mode signal is at an active level; as well as In response to the PPR mask signal being asserted, a second row activation command is received using the command decoder without providing the row activation signal.

12. The method of claim 11, further comprising remapping a row address from a word line of the memory device to a redundant word line.

13. The method of claim 11, further comprising activating a PPR clock signal in response to the PPR mask signal being valid.

14. The method of claim 11, further comprising resetting the PPR mask signal to an inactive level in response to the memory device exiting the PPR mode.

15. A method for operating a memory device, comprising: entering a post-package repair PPR mode of a memory device, and providing a PPR mode signal at an active level when the memory device is in the PPR mode; using a command decoder to receive a first row activation command and provide a row activation signal; activating a PPR mask signal based on a mask circuit of the memory device receiving the row activation signal when the PPR mode signal is at an active level; receiving a second row activation command using the command decoder in response to the PPR mask signal being valid but without providing the row activation signal; providing a fuse blow signal to indicate which of one or more fuses of the memory device should be blown; determining whether the fuse blown signal is in an illegal state; as well as A memory bank address is inhibited if the blown fuse signal is in the illegal state, wherein the blown fuse signal is a multi-bit signal, and wherein the illegal state is determined based on multiple bits of the multi-bit signal being simultaneously at a high logic level.

16. The method of claim 15, further comprising determining which redundant rows of the memory device are available, and providing a status to the fuse blown signal based on the availability of the redundant rows.

17. The method of claim 15, further comprising blowing a selected fuse of the one or more fuses based on the fuse blow signal if the fuse blow signal is not in the illegal state.

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