Semiconductor device with standard cells with improved integration and reliability

Abstract

A semiconductor device includes a first standard cell and a second standard cell on a substrate, the first standard cell and the second standard cell having respective semiconductor elements and first interconnect lines electrically connected to the semiconductor elements. A wiring structure is provided, the wiring structure disposed on the first standard cell and the second standard cell. The wiring structure includes second interconnect lines electrically connected to the first interconnect lines. The first interconnect lines include first power transmission lines configured to supply power to the semiconductor elements and first signal transmission lines electrically coupled to the semiconductor elements. The second interconnect lines include (i) second power transmission lines electrically connected to the first power transmission lines and extending a first length, (ii) second signal transmission lines electrically connected to the first signal transmission lines, and (iii) a pin line electrically connected to the first power transmission lines, extending over a boundary between the first standard cell and the second standard cell, and extending a second length less than the first length.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0052277, filed on April 29, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The example embodiments relate to semiconductor devices used in large-scale integrated circuits. Background Technology

[0004] As the demand for high performance, high speed, and / or versatility in semiconductor devices increases, the integration level of semiconductor devices is also increasing. In response to this trend towards higher integration in semiconductor devices, active research has been conducted to improve layout design, particularly regarding more efficient wiring of interconnects that electrically connect semiconductor devices to each other on the integrated circuit substrate. Summary of the Invention

[0005] The example embodiments provide highly integrated semiconductor devices with improved integration and reliability.

[0006] According to an example embodiment, a semiconductor device includes standard cells disposed along a first direction parallel to the upper surface of a substrate and a second direction perpendicular to the first direction. Each standard cell includes an active region, a gate structure intersecting the active region, source / drain regions disposed adjacent to the active region (on both sides of the gate structure), and a first interconnect electrically connected to the active region and the gate structure. The first interconnect includes a first power transmission line and a first signal transmission line. A wiring structure is provided disposed on the upper part of the standard cell. The wiring structure includes a second interconnect electrically connected to the first interconnect, and a third interconnect disposed on the second interconnect for electrical connection to the second interconnect.

[0007] According to some embodiments, the standard unit includes a first standard unit and a second standard unit adjacent to each other in a second direction. Additionally, the second interconnect includes: (i) at least one or more second power transmission lines electrically connected to the first power transmission line and arranged along a line along all the standard units arranged in the second direction; (ii) a second signal transmission line electrically connected to the first signal transmission line and disposed on a portion of the standard unit; and (iii) a first pin wire electrically connected to the first power transmission line and disposed on the boundary between the first and second standard units to overlap the first standard unit by a first length in the second direction and to overlap the second standard unit by a second length different from the first length in the second direction.

[0008] According to a further embodiment, a semiconductor device includes first and second standard cells provided on a substrate and respectively including a semiconductor element and a first interconnection line electrically connected to the semiconductor element. A wiring structure is provided on the first and second standard cells and includes a second interconnection line electrically connected to the first interconnection line. The first interconnection line includes a first power transmission line supplying power to the semiconductor element and a first signal transmission line applying a signal to the semiconductor element. Also, the second interconnection line includes a second power transmission line electrically connected to the first power transmission line and extending a first length, a second signal transmission line electrically connected to the first signal transmission line, and a pin line electrically connected to the first power transmission line, provided on a boundary between the first and second standard cells, and extending a second length smaller than the first length.

[0009] According to a further embodiment, a semiconductor device includes standard cells provided on a substrate. The standard cells respectively include an active region, a gate structure crossing the active region, a source / drain region provided adjacent to the active region on both sides of the gate structure, and a first interconnection line including a first power transmission line electrically connected to the active region. A wiring structure is provided on an upper portion of the standard cells. The wiring structure includes a second interconnection line including a pin line electrically connected to the first power transmission line, and a third interconnection line including a third power transmission line provided on the second interconnection line to be electrically connected to the pin line. The first power transmission line extends in a first direction along a boundary of the standard cells, and the pin line is provided to pass through a boundary between the standard cells among the boundaries of the standard cells, to overlap the first and third power transmission lines, and to extend in a second direction perpendicular to the first direction. The third power transmission line overlaps the first power transmission line to extend in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects, features and advantages of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to an example embodiment;

[0012] Figure 2 is a schematic plan view of a semiconductor device according to an example embodiment;

[0013] Figure 3 is a layout view of a semiconductor device according to an example embodiment;

[0014] Figure 4A and Figure 4B is a layout view of a semiconductor device according to an example embodiment;

[0015] Figure 5 and Figure 6 is a layout diagram of a semiconductor device according to an example embodiment;

[0016] Figure 7 is a layout diagram of a semiconductor device according to an example embodiment;

[0017] Figure 8A and Figure 8B are circuit diagrams of a unit circuit provided by a standard cell included in a semiconductor device according to example embodiments, respectively;

[0018] Figures 9A to 9C is a layout diagram of a semiconductor device according to an example embodiment;

[0019] Figures 10A to 10D is a cross-sectional view illustrating a semiconductor device according to an example embodiment; and

[0020] Figure 11 is a cross-sectional view illustrating a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0022] Figure 1A and Figure 1B are flowcharts illustrating a method of designing and manufacturing a semiconductor device according to example embodiments. Referring to Figure 1A , the method of designing and manufacturing a semiconductor device can include a design operation S10 of designing a semiconductor device and a process operation S20 of manufacturing a semiconductor device. The design operation S10 of designing a semiconductor device is an operation of designing a circuit layout, and can be performed using a tool for designing a circuit. The tool can be a program including a plurality of commands executed by a processor. Accordingly, the design operation S10 of designing a semiconductor device can be a computer-implemented operation for designing a circuit. The process operation S20 of manufacturing a semiconductor device is an operation of manufacturing a semiconductor device based on a designed layout, and can be performed in a semiconductor process module.

[0023] The design operation S10 of designing a semiconductor device includes a floorplan operation S110, a power plan operation S120, a placement operation S130, a clock tree synthesis (CTS) operation S140, a routing operation S150, a staple line insertion operation S155, and a hypothesis analysis operation S160.

[0024] The floorplanning operation S110 can be an operation of performing physical design by cutting and moving a principle circuit of a logic design. In the floorplanning operation S110, a memory or a function block can be set. In this operation, for example, function blocks to be adjacently set can be identified, and a space for the function blocks can be allocated in consideration of available spaces and required performance. For example, the floorplanning operation S110 can include an operation of creating a site-row and an operation of forming a metal routing track on the created site-row. The site-row is a frame in which a standard cell stored in a cell library is to be set according to a prescribed design rule. The metal routing track is a virtual line on which an interconnect is to be formed later.

[0025] The power planning operation S120 can be an operation of setting a pattern of interconnects connecting a local power source (e.g., ground or driving voltage) to a function block. For example, a pattern of interconnects connecting a power source or ground can be generated in the form of a net, so that the power source can be uniformly supplied to the entire chip. The pattern can include a power rail, and in this operation, the pattern can be generated in the form of a net by various rules.

[0026] The placement operation S130 is an operation of placing a pattern of elements constituting a function block, and can include placing a standard cell. In detail, in an example embodiment, each standard cell can include a semiconductor element and a first interconnection line connected to the semiconductor element. The first interconnection line can include a power transmission line connecting a power source or ground, and a signal transmission line transmitting a control signal, an input signal, or an output signal. A blank area can be generated between the standard cells set in this operation, and the blank area can be filled with a filler cell. The filler cell can be a dummy area in a manner different from the standard cell including an operable semiconductor device, a unit circuit implemented with a semiconductor element, etc. Through this operation, a shape or a size for actually constructing a pattern of transistors and interconnects to be formed on a semiconductor substrate can be defined. For example, in order to actually form an inverter circuit on a semiconductor substrate, a layout pattern to be set thereon such as PMOS, NMOS, N-well, gate electrode, and interconnect can be appropriately set.

[0027] The CTS operation S140 can be an operation of generating a pattern of a signal line of a central clock related to a response time of determining performance of a semiconductor device.

[0028] The routing operation S150 can be an operation of generating a routing structure or an upper interconnection structure including a second interconnection line connecting the set standard cells. In detail, a power distribution network (PDN) can be implemented at this stage. The second interconnection line is electrically connected to the first interconnection line in the standard cell, and can electrically connect the standard cells to each other, or can be connected to a power source or ground. The second interconnection line can be constructed to be physically formed on an upper portion of the first interconnection line.

[0029] The staple line insertion operation S155 can be, for example, an operation of inserting a staple line between second interconnection lines in the wiring structure generated in the wiring operation S150. For example, the staple line can be an element connecting a first interconnection line, which is a power rail disposed below the staple line, and a third interconnection line, which is a power rail disposed on the staple line. The staple line can be called by other terms, such as a staple via, etc. For example, in a power rail, the first interconnection line can be connected to the third interconnection line through a staple line having a relatively short length. By inserting these staple lines, it is possible to advantageously reduce an ohmic drop, such as an IR drop or a resistance voltage drop, in the power rail. The design and insertion of the staple line should not overlap with other second interconnection lines for signal transmission, etc. Therefore, a design method can be applied that maximizes the insertion of the staple line while avoiding conflict with the second interconnection lines generated in the wiring operation S150.

[0030] The assumption analysis operation S160 can be an operation of verifying and correcting the generated layout. Examples of verification items can include a design rule check (DRC) for checking and verifying whether the layout is correct according to a design rule, an electrical rule check (ERC) for checking and verifying that the layout is correctly performed without electrical disconnection, a layout versus schematic (LVS) for checking and verifying that the layout matches a gate-level netlist, etc.

[0031] The process operation S20 of manufacturing the semiconductor device can include a mask generation operation S170 and a semiconductor device manufacturing operation S180.

[0032] The mask generation operation S170 can include an operation of generating mask data for forming various patterns on a plurality of layers by performing optical proximity correction (OPC) or the like on layout data generated in the design operation S10 of designing a semiconductor device, and an operation of manufacturing a mask using the mask data. The OPC can be used to correct a distortion phenomenon that can occur in a photolithography process. The mask can be manufactured by delineating a layout pattern using a chromium thin film applied on a glass or quartz substrate.

[0033] In the semiconductor device manufacturing operation S180, various types of exposure and etching processes can be repeatedly performed. Through these processes, patterns formed in the layout design can be sequentially formed on a silicon substrate. In detail, various semiconductor processes are performed on a semiconductor substrate such as a wafer using a plurality of masks to form a semiconductor device in which an integrated circuit is implemented. The semiconductor processes can include a deposition process, an etching process, an ion implantation process, a cleaning process, etc. Further, the semiconductor processes can include a packaging process of mounting the semiconductor device on a PCB and encapsulating with an encapsulation material, or can include a test process for the semiconductor device or a package thereof.

[0034] Reference Figure 1B, the method of designing and manufacturing a semiconductor device can further include a front pin line insertion operation S125 performed after the power arrangement operation S120. Accordingly, unlike Figure 1A Unlike, a pin line insertion operation S155 after the wiring operation S150 is referred to as a rear pin line insertion operation S155.

[0035] The front pin line insertion operation S125 can be an operation of first inserting a portion of a pin line after generating a pattern of interconnects connecting power or ground in the power arrangement operation S120. In this operation, some pin lines can be first generated in consideration of ohmic drop.

[0036] Next, in the rear pin line insertion operation S155, a pin line can be additionally inserted after the wiring operation S150 as described above with reference to Figure 1A Thus, the pin line inserted in the rear pin line insertion operation S155 can form an entire pin line together with the pin line inserted in the front pin line insertion operation S125.

[0037] Figure 2 is a schematic plan view of a semiconductor device according to an example embodiment. Referring to Figure 2 , the semiconductor device can include a standard cell region SC and a filler cell region FC. First through seventh standard cells SC1 through SC7 can be disposed in the standard cell region SC to implement a circuit. First through seventh filler cells FC1 through FC7 can be disposed in the filler cell region FC to form a dummy region. Figure 2 The shapes and numbers of the first through seventh standard cells SC1 through SC7 and the first through seventh filler cells FC1 through FC7 shown in FIG. 1 are provided by way of example, and can be variously changed according to example embodiments. The semiconductor device can include first power transmission lines M1(VDD) and M1(VSS), and a gate line GL.

[0038] The first power transmission lines M1(VDD) and M1(VSS) can be power supply rails, and can extend in a first direction (e.g., in an X direction). The first power transmission lines M1(VDD) and M1(VSS) can include a first high power transmission line M1(VDD) supplying a first voltage and a first low power transmission line M1(VSS) supplying a second voltage lower than the first voltage. The first high power transmission line M1(VDD) and the first low power transmission line M1(VSS) can be alternately arranged while being spaced apart from each other in a second direction (e.g., in a Y direction) crossing the first direction. For example, the first power transmission lines M1(VDD) and M1(VSS) can extend along a boundary of the standard cell region SC and the filler cell region FC, but at least one of the first power transmission lines M1(VDD) and M1(VSS) can be disposed to pass through at least one of the standard cell region SC and the filler cell region FC according to an example embodiment.

[0039] The gate lines GL can extend in the second direction, and can be disposed to be spaced apart from each other in the first direction. The gate lines GL can include gate electrodes that supply gate electrodes of the semiconductor device, and dummy gate electrodes that do not actually perform an electrical function but provide an advantageous function for layout. For example, at least a portion of the gate lines GL disposed at a boundary between the standard cell region SC and the filler cell region FC can include a dummy gate electrode.

[0040] Figure 3 is a layout diagram of a semiconductor device according to an example embodiment. Figure 3 shows a standard cell and a filler cell of a semiconductor device Figure 2 of FIG. 1. Figure 4A and Figure 4B is a diagram showing a layout of a semiconductor device according to an example embodiment. In Figure 4A , a region "A", a region "B", and a region "C" of Figure 3 are enlarged and shown.

[0041] Referring to Figure 3 , the semiconductor device 100 can include first interconnection lines M1, second interconnection lines M2, and first vias V1 vertically connecting the first interconnection lines M1 and the second interconnection lines M2. Figure 3 shows first power transmission lines M1(VDD) and M1(VSS) in the first interconnection lines M1, and second power transmission lines M2(VDD) and M2(VSS), a second signal transmission line M2(S), a first pin line M2(ST1), and second pin lines M2(ST2a) and M2(ST2b) in the second interconnection lines M2.

[0042] The first power transmission lines M1(VDD) and M1(VSS) of the first interconnection lines M1 can extend in a first direction (e.g., an X direction), as described above with reference to Figure 2 The second interconnection lines M2 can extend in a second direction (e.g., in a Y direction) that crosses or is perpendicular to the first interconnection lines M1. The second interconnection lines M2 can be included in a wiring structure above the standard cells and the filler cells, and according to an example embodiment, a portion of the second interconnection lines M2 can also be included in the standard cells. For example, the second interconnection lines M2 connecting the first interconnection lines M1 within one standard cell can be included in the standard cell.

[0043] The second power transmission lines M2(VDD) and M2(VSS) can include a second high power transmission line M2(VDD) and a second low power transmission line M2(VSS). The second high power transmission line M2(VDD) and the second low power transmission line M2(VSS) can be alternately arranged apart from each other in the X direction. The second high power transmission line M2(VDD) can be connected to the first high power transmission line M1(VDD) through the first via V1, and the second low power transmission line M2(VSS) can be connected to the first low power transmission line M1(VSS) through the first via V1.

[0044] The second power transmission lines M2(VDD) and M2(VSS) can include at least one or more lines arranged on one line along all of the standard cells arranged in the Y direction. For example, as shown in Figure 3 Each of the second power transmission lines M2(VDD) and M2(VSS) can include a line extending further than the standard cells arranged in the Y direction. For example, the second power transmission lines M2(VDD) and M2(VSS) can be provided on all of the standard cells provided in the Y direction. Accordingly, the lengths of the second power transmission lines M2(VDD) and M2(VSS) can be greater than the lengths of the second signal transmission line M2(S) and the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b). On the other hand, according to an example embodiment, each of the second power transmission lines M2(VDD) and M2(VSS) can include a plurality of lines arranged on one line in the Y direction, which will be described in more detail below with reference to Figure 7

[0045] ​The second signal transmission lines M2(S) can be disposed on the upper portion of the plurality of standard cells to electrically connect adjacent standard cells. The second signal transmission lines M2(S) can be connected to the first signal transmission lines of the first interconnection lines M1 through the first vias V1. The second signal transmission lines M2(S) can transmit control signals, input signals, or output signals. In an example embodiment, some of the second signal transmission lines M2(S) (e.g., the second signal transmission lines M2(S) connected to the first interconnection lines M1 within one standard cell) can be included in the standard cell. The length of the second signal transmission lines M2(S) can be shorter than the lengths of the second power transmission lines M2(VDD) and M2(VSS), and at least a portion of the second signal transmission lines M2(S) can have a length greater than the lengths of the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b).

[0046] The first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be spaced apart from the second power transmission lines M2(VDD) and M2(VSS) and the second signal transmission lines M2(S) in the X and Y directions, and can be disposed between the second power transmission lines M2(VDD) and M2(VSS) and the second signal transmission lines M2(S). The first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be disposed on the boundaries of the standard cells in the Y direction. In detail, the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be disposed to pass through the boundaries on the upper portions of the boundaries. Accordingly, the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can overlap the boundaries in a plan view.

[0047] The first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be connected to the first power transmission lines M1(VDD) and M1(VSS) through the first vias V1. The first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be connected to the first power transmission lines M1(VDD) and M1(VSS) through the first vias V1 in regions overlapping the first power transmission lines M1(VDD) and M1(VSS). As described above, power is mainly transmitted by the second power transmission lines M2(VDD) and M2(VSS) in the second interconnection lines M2, but the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) are also disposed, thereby reducing ohmic drops in the power transmission lines as described above.

[0048] Referring to Figure 4A, the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) can have a line shape in which a width in the Y direction is greater than a width in the X direction. A length L2 of the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) in the Y direction can be smaller than a length L1 of the standard cells SC1 and SC2 in the Y direction. The first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) can have substantially the same size, but their size is not limited thereto. The arrangement type of the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) can be different from each other based on a boundary of the first standard cell SC1 and the second standard cell SC2 adjacent to each other in the Y direction. For example, the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) can have different arrangement forms in the Y direction based on center lines of the first power transmission lines M1(VDD) and M1(VSS) disposed under and overlapping the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b).

[0049] As for the first staple line M2(ST1), a length L3 based on a boundary overlapping the first standard cell SC1 can be substantially equal to a length L4 overlapping the second standard cell SC2. In the 2-1 staple line M2(ST2a), a length L5 based on a boundary overlapping the first standard cell SC1 can be greater than a length L6 overlapping the second standard cell SC2. In contrast, in the 2-2 staple line M2(ST2b), a length L7 based on a boundary overlapping the first standard cell SC1 can be smaller than a length L8 overlapping the second standard cell SC2. For example, L6:L5 and L7:L8 can be greater than 1 / 6. For example, L6:L5 and L7:L8 can be in a range from 1:1 to 1:6, in detail, can be in a range from 1:3 to 1:4.

[0050] Referring to Figure 4B The respective arrangement positions of the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2B) can be determined in consideration of the arrangement of other second interconnection lines M2 such as the second power transmission lines M2(VDD) and M2(VSS) and the second signal transmission line M2(S).

[0051] The first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) are spaced apart from the other second interconnection lines M2 at the same pitch P1 in the X direction. In the present specification, the pitch indicates a length between centers in the X direction. Since the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) are arranged in the Y direction, the pitch P1 in the X direction can be substantially equal to the length of the first and second staple lines M2(ST1), M2(ST2a) and M2(ST2b) in the X direction. Figure 4AThe first and second staple lines M2(ST1), M2(ST2a), and M2(ST2b) have three different forms based on the boundaries of the first standard cell SC1 and the second standard cell SC2, and thus one of the three forms can be selected by considering the arrangement of the adjacent second interconnect lines M2 (e.g., the second signal transmission line M2(S)) as illustrated. Figure 4B The three forms can be selected by considering the arrangement of the adjacent second interconnect lines M2 (e.g., the second signal transmission line M2(S)) as illustrated.

[0052] In detail, Figure 4B The 2-1 staple line M2(ST2a) illustrated in FIG. 2-1 has end portions E1a and E1b that are spaced apart from end portions E2 and E3 of the second signal transmission line M2(S) adjacent to the 2-1 staple line M2(ST2a) by predetermined distances D1, D2, and D3 in the Y direction. For example, any one of the first and second staple lines M2(ST1), M2(ST2a), and M2(ST2b) can be selected so that the distances D1, D2, and D3 are greater than or equal to a critical distance. The critical distance can be determined according to the design rules of the layout. For example, the critical distance can be determined in consideration of the end portion shape RP formed when the actual layout is patterned to form a pattern in a semiconductor device. As illustrated in FIG. 2-2, when the second interconnect line M2 is patterned to have a relatively expanded shape on the end portion, the first and second staple lines M2(ST1), M2(ST2a), and M2(ST2b) can be selected and arranged in such a manner that the end portions E1a and E1b of the first and second staple lines M2(ST1), M2(ST2a), and M2(ST2b) are not arranged side by side with the end portions E2 and E3 of the other second interconnect lines M2 (e.g., the second signal transmission line M2(S) and the second power transmission lines M2(VDD) and M2(VSS)) in the X direction and can be spaced apart from the end portions E2 and E3 of the other second interconnect lines M2 (e.g., the second signal transmission line M2(S) and the second power transmission lines M2(VDD) and M2(VSS)) by predetermined distances in the Y direction, in consideration of the expanded size. Figure 4B The three forms can be selected by considering the arrangement of the adjacent second interconnect lines M2 (e.g., the second signal transmission line M2(S)) as illustrated.

[0053] In Figure 3 In the semiconductor device 100 of the example embodiment, by applying the first and second staple lines M2(ST1), M2(ST2a), and M2(ST2b) having the three types of arrangement forms, it is possible to significantly increase the number of staple lines to be inserted while maintaining the design rules related to the other second interconnect lines M2.

[0054] Figure 5 and Figure 6 is a layout diagram of a semiconductor device according to an example embodiment. Referring to FIG. 1, Figure 5The semiconductor device 100a can include a third spike line M2(ST3) in addition to the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b).

[0055] The third spike line M2(ST3) can extend beyond one standard cell, and can be connected to the first power transmission lines M1(VDD) and M1(VSS) through the first via V1. For example, the length L9 of the third spike line M2(ST3) in the Y direction can be greater than the length LI of the standard cell in the Y direction. However, not all of the third spike lines M2(ST3) should have the same length, and can have various lengths greater than the length LI of the standard cell in the Y direction.

[0056] The semiconductor device 100a is illustrated as including all of the first to third spike lines M2(ST1), M2(ST2a), M2(ST2b), and M2(ST3), but a portion thereof can be omitted. For example, the semiconductor device 100a can not include the first spike line M2(ST1), or can not include at least one of the 2-1 spike line M2(ST2a) and the 2-2 spike line M2(ST2b).

[0057] Referring to Figure 6 The semiconductor device 100b can include a fourth spike line M2(ST4) in addition to the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b). The fourth spike line M2(ST4) has substantially the same length in both directions from the center line of the standard cell in the Y direction, and can be connected to the first power transmission lines M1(VDD) and M1(VSS) through the first via V1. For example, in the Y direction in the drawing, the length L10 of the fourth spike line M2(ST4) extending upward from the center line of the standard cell is substantially the same as the length LI 1 of the fourth spike line M2(ST4) extending downward from the center line. The fourth spike line M2(ST4) crosses the boundary line of the standard cell in the Y direction, and can be provided to have various lengths within a range satisfying the above condition.

[0058] The semiconductor device 100b is illustrated as including the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) and the fourth spike line M2(ST4), but a portion thereof can be omitted, or can further include Figure 5 the third spike line M2(ST3).

[0059] Figure 7 is a layout diagram of a semiconductor device according to an example embodiment. Referring to Figure 7The semiconductor device 100c can further include third power transmission lines M3(VDD) and M3(VSS) as power supply rails. Further, in the semiconductor device 100c, the second power transmission lines M2(VDD) and M2(VSS) can be disposed differently from those in the example embodiment of Figure 3

[0060] The third power transmission lines M3(VDD) and M3(VSS) can be interconnection lines included in the third interconnection lines M3 located on the upper portion of the second interconnection lines M2. The third power transmission lines M3(VDD) and M3(VSS) can be disposed to overlap the first power transmission lines M1(VDD) and M1(VSS). The width W2 of the third power transmission lines M3(VDD) and M3(VSS) can be greater than the width W1 of the first power transmission lines M1(VDD) and M1(VSS). Thus, the third power transmission lines M3(VDD) and M3(VSS) can be disposed to overlap all of the first power transmission lines M1(VDD) and M1(VSS).

[0061] The third power transmission lines M3(VDD) and M3(VSS) can be connected to the second interconnection lines M2 through separate second vias. For example, in a region in which the third power transmission lines M3(VDD) and M3(VSS) overlap the second power transmission lines M2(VDD) and M2(VSS) and the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) in the second interconnection lines M2, the second vias can be disposed on the second interconnection lines M2. The power supply voltage supplied through the third power transmission lines M3(VDD) and M3(VSS) is transmitted to the first power transmission lines M1(VDD) and M1(VSS) through the spike lines disposed perpendicularly thereto and including the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) having a relatively short length. In the example embodiment, the above arrangement of the third power transmission lines M3(VDD) and M3(VSS) can also be applied to the example embodiments of Figure 5 Figure 6

[0062] ​​​Each of the second power transmission lines M2(VDD) and M2(VSS) can be intermittently disposed in the Y direction. Each of the second power transmission lines M2(VDD) and M2(VSS) can include a plurality of lines arranged in a line in the Y direction. For example, the second high power transmission line M2(VDD) can be arranged in a line in the Y direction while overlapping the first high power transmission line M1(VDD) disposed thereunder and the third high power transmission line M3(VDD) disposed thereover. The second low power transmission line M2(VSS) can overlap the first low power transmission line M1(VSS) disposed thereunder and the third low power transmission line M3(VSS) disposed thereover, and can be arranged in a line in the Y direction.

[0063] As described above, even when the second power transmission lines M2(VDD) and M2(VSS) are intermittently disposed, another second interconnection line M2 can not be inserted between the plurality of second power transmission lines M2(VDD) and M2(VSS) arranged in a line. In an example embodiment, respective lengths of the plurality of second power transmission lines M2(VDD) and M2(VSS) arranged in a line in the Y direction can be variously changed. For example, a length of each of the plurality of second power transmission lines M2(VDD) and M2(VSS) can be equal to or greater than a length of each of the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b). In an example embodiment, such an arrangement of the second power transmission lines M2(VDD) and M2(VSS) can also be applied to Figures 3 to 6 example embodiments.

[0064] Figure 8A and Figure 8B are circuit diagrams of a unit circuit provided by a standard cell included in a semiconductor device according to example embodiments, respectively. Referring to Figure 8A , the unit circuit can be an inverter circuit. The inverter circuit can include a pull-up device TR1 receiving a first power supply VDD and a pull-down device TR2 receiving a second power supply VSS, and a gate of the pull-up device TR1 and a gate of the pull-down device TR2 can be connected to each other to provide an input terminal IN. One of a source / drain region of the pull-up device TR1 and one of a source / drain region of the pull-down device TR2 can be connected to each other to provide an output terminal OUT.

[0065] Referring to Figure 8BThe unit circuit can be a NAND circuit. The NAND circuit can include a first pull-up device TR1 and a second pull-up device TR2, and a first pull-down device TR3 and a second pull-down device TR4 connected in series with each other. The first pull-up device TR1 and the second pull-up device TR2 can be connected to a first power supply VDD. The first pull-down device TR3 and the second pull-down device TR4 can be connected in series with each other, and the second pull-down device TR4 can be connected to a second power supply VSS.

[0066] The gate of the first pull-up device TR1 and the gate of the first pull-down device TR3 can be connected to each other to provide a first input terminal IN A , and the gate of the second pull-up device TR2 and the gate of the second pull-down device TR4 can be connected to each other to provide a second input terminal IN B . One of the source / drain regions of each of the first pull-up device TR1 and the second pull-up device TR2 and one of the source / drain regions of the first pull-down device TR3 can be connected to each other to provide an output terminal OUT. However, Figure 8A and Figure 8B The inverter circuit and the NAND circuit shown in FIGS. 1A and 1B are merely examples of the unit circuit that can be provided by the standard cell, and the standard cell can provide various circuits such as a NOR standard cell in addition to these circuits.

[0067] Figures 9A to 9C is a layout diagram of a semiconductor device according to an example embodiment. Figure 9B Further shown is a pin line in the layout of Figure 9A , and Figure 9C Further shown is a second through-connection and a third power transmission line in the layout of Figure 9B . Referring to Figure 9A , the semiconductor device 200 includes a standard cell region SC including first to sixth standard cells SC1 to SC6 and a filler cell region FC including first to sixth filler cells FC1 to FC6, which are arranged along X and Y directions. The first to sixth standard cells SC1 to SC6 are standard cells including the inverter circuit of Figure 8A , and the third and fourth standard cells SC3 and SC4 are standard cells including the NAND circuit of Figure 8B . However, the arrangement of the standard cell region SC and the filler cell region FC is an example, and various changes can be made according to example embodiments.

[0068] Each of the first standard units SC1 to the sixth standard units SC6 may include a well region such as an N-well region, a pair of active regions ACT extending in the X direction, a gate line GL extending in the Y direction, a contact CNT connected to the active region ACT and the gate line GL, a through-hole V0 connected to the contact CNT, a first interconnect M1 connected to the through-hole V0, a ​​first through-hole V1 connected to the first interconnect M1, and a second interconnect M2 connected to the first through-hole V1. The first filler units FC1 to the sixth filler units FC6 may include a pair of active regions ACT extending in the X direction, a gate line GL extending in the Y direction, a contact CNT connected to the active region ACT and the gate line GL, and a first interconnect M1. The first filler units FC1 to the sixth filler units FC6 may be regions in which dummy components or dummy semiconductor elements are disposed.

[0069] exist Figures 9A to 9C For ease of understanding, a portion of the configuration disposed above the boundary of the standard cell region SC and the filler cell region FC, and outside the standard cell region SC and the filler cell region FC, is shown together. The active region ACT may include, for example, one or more active fins extending in the X direction. The active region ACT may be disposed in well regions of different conductivity types and may be connected to the upper contact CNT. The active region ACT disposed in the N-well region NWELL has N-type conductivity, and the active region ACT not disposed in the N-well region NWELL has P-type conductivity.

[0070] In the first standard unit SC1 to the sixth standard unit SC6, regarding the source region ACT, in order to provide Figure 8A inverter circuit and Figure 8B The NAND circuit is connected to a contact CNT in one of a pair of active regions ACT via a through-hole V0 to a first high power transmission line M1 (VDD) in the first interconnect M1, and to a contact CNT in the other of the pair of active regions ACT via a through-hole V0 to a first low power transmission line M1 (VSS) in the first interconnect M1.

[0071] In the first filler unit FC1 to the sixth filler unit FC6, the active region ACT can be formed in a continuous pattern with the first standard unit SC1 to the sixth standard unit SC6 in the X direction. In an example embodiment, the active region ACT in the first filler unit FC1 to the sixth filler unit FC6 can be separated from the active region ACT of the first standard unit SC1 to the sixth standard unit SC6 by a separating layer or the like, thereby realizing a form with a dummy active region, but is not limited thereto.

[0072] The gate line GL includes a gate electrode and a dummy gate electrode, and can cross the active region ACT. The gate line GL can provide pull-up devices and pull-down devices of the inverter circuit and the NAND circuit together with the active region ACT. In Figure 8A In the inverter circuit, since the gate of the pull-up device TR1 and the gate of the pull-down device TR2 are connected to each other, the gate line GL can be shared between a pair of active regions ACT. The gate line GL can be connected to the first interconnection line M1, which can be a signal transmission line M1(S) in the first interconnection line M1, through the contact CNT. In an example embodiment, the gate line GL commonly disposed at both ends of the first to sixth standard cells SC1 to SC6 in the X direction and the gate line GL disposed in the first to sixth filler cells FC1 to FC6 can include a dummy gate electrode. Accordingly, the gate line GL disposed in the first to sixth filler cells FC1 to FC6 can be referred to as a dummy gate structure or a filler gate structure, etc. The contact CNT can connect the active region ACT and the gate line GL to the lower via V0 disposed thereon. In the first to sixth filler cells FC1 to FC6, the contact CNT can be a dummy contact not connected to the upper interconnection line (e.g., the first interconnection line M1).

[0073] The first interconnection line M1 is an interconnection line disposed on the active region ACT and the gate line GL, and can extend in the X direction. The first interconnection line M1 can include first power transmission lines M1(VDD) and M1(VSS), and a first signal transmission line M1(S). The first power transmission lines M1(VDD) and M1(VSS) can supply different first and second power supply voltages VDD and VSS to the semiconductor elements, respectively, as described above with reference to Figure 2 The signal transmission line M1(S) can be a signal transmission line for supplying a signal to the semiconductor elements, and can be electrically connected to the gate line GL.

[0074] The regions of the first interconnection line M1 located inside the first to sixth standard cells SC1 to SC6, respectively, can have the same width as each other in the Y direction, but the size of the regions is not limited thereto. For example, the entire width of each of the first power transmission lines M1(VDD) and M1(VSS) can also be the same as the width of the first signal transmission line M1(S) without considering the boundaries of the standard cells.

[0075] The first to sixth filler cells FC1 to FC6 can include first power transmission lines M1(VDD) and M1(VSS) extending from the first to sixth standard cells SC1 to SC6. The second interconnection line M2 is an interconnection disposed on the first interconnection line M1 and can extend in the Y direction. The second interconnection line M2 can be connected to the first interconnection line M1 through the first via V1. Figure 9A The second interconnection line M2 illustrated in FIG. 13 can be a part of the second signal transmission lines (e.g., lines connecting the first interconnection lines M1 to each other within each of the first to sixth standard cells SC1 to SC6).

[0076] Referring to Figure 9B , the semiconductor device 200 can further include a wiring structure disposed on the upper portions of the first to sixth standard cells SC1 to SC6 and the first to sixth filler cells FC1 to FC6. As Figure 9B illustrated, the wiring structure can include first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b). The first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) correspond to the second interconnection line M2 and can be arranged to have the same thickness and to be located at the same height as the second interconnection line M2 in the first to sixth standard cells SC1 to SC6 described above with reference to Figure 9A In an example embodiment, the semiconductor device 200 can further include second interconnection lines M2 similar to those illustrated in FIG. 13, e.g., second power transmission lines M2(VDD) and M2(VSS) and a second signal transmission line M2(S), in regions not illustrated. Figure 3

[0077] The first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be disposed to overlap boundaries between the first to sixth standard cells SC1 to SC6 and the first to sixth filler cells FC1 to FC6 adjacent to each other in the Y direction. The first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be disposed not only on the upper portion of the standard cell region SC but also on the upper portion of the filler cell region FC. Accordingly, the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b) can be disposed to overlap the first to sixth filler cells FC1 to FC6 as well as the first to sixth standard cells SC1 to SC6. For a detailed description of each of the first and second spike lines M2(ST1), M2(ST2a), and M2(ST2b), the description above with reference to Figure 3 may equally apply thereto.

[0078] Referring to Figure 9C ​The wiring structure of the semiconductor device 200 can further include a third interconnect line M3 connected to the second interconnect line M2 by a second via V2. In Figure 9C , only a third high power delivery line M3(VDD) and a third low power delivery line M3(VSS) of the third interconnect line M3 corresponding to the third power delivery lines are shown. The third power delivery lines M3(VDD) and M3(VSS) can be provided to overlap the first power delivery lines M1(VDD) and M1(VSS). The third power delivery lines M3(VDD) and M3(VSS) can be connected to the second interconnect line M2 by the second via V2 in a region overlapping the second interconnect line M2. Further, the description of the third power delivery lines M3(VDD) and M3(VSS) described above with reference to Figure 7 may be equally applied.

[0079] Figures 10A to 10D is a cross-sectional view showing a semiconductor device according to an example embodiment. Figures 10A to 10D shows cross-sections of the semiconductor device of Figure 9C taken along lines I-I', II-II', III-III', and IV-IV'. For ease of description, only main components of the semiconductor device are shown in Figures 10A to 10D . Reference is made to Figures 10A to 10D , the semiconductor device 200 includes a substrate 101, an active region ACT including an active fin 105, a device isolation layer 110, a source / drain region 120, a gate structure 140 including a gate electrode layer 145, an under-interlevel dielectric layer 130, a contact CNT, an upper-interlevel dielectric layer 150, a lower via V0, a first interconnect line M1, a first via V1 provided on the first interconnect line M1, a second interconnect line M2, a second via V2, and a third interconnect line M3. The semiconductor device 200 can further include an etch stop layer 160 provided on a lower surface of the upper-interlevel dielectric layer 150, and a barrier layer 170 provided along lower surfaces of the interconnect lines M1, M2, and M3 and the vias V0, V1, and V2. The semiconductor device 200 can include a FinFET device in which the active region ACT includes an active fin 105 having a fin structure.

[0080] The substrate 101 can have an upper surface extending in an X-direction and a Y-direction. The substrate 101 can include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The substrate 101 can be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. The substrate 101 can include doped regions such as an N-well region NWELL.

[0081] The device isolation layer 110 can define an active region ACT in the substrate 101. The device isolation layer 110 can be formed by, for example, a shallow trench isolation (STI) process. As shown in FIG. 1A, the device isolation layer 110 can include a region extending relatively deep into a lower portion of the substrate 101 between adjacent active regions ACT, but the configuration of the device isolation layer is not limited thereto. According to an example embodiment, the device isolation layer 110 can have a curved upper surface having a higher level adjacent to the active fin 105. The device isolation layer 110 can be formed of an insulating material, and can include, for example, an oxide, a nitride, or a combination thereof. Figure 10A

[0082] The active region ACT is defined by the device isolation layer 110 in the substrate 101, and can be disposed to extend in a first direction (e.g., in the X direction). The active fin 105 can have a shape protruding from the substrate 101. An upper end of the active fin 105 can be disposed to protrude to a predetermined height from an upper surface of the device isolation layer 110. The active fin 105 can be formed as a portion of the substrate 101 or can include an epitaxial layer grown from the substrate 101. For example, the active fin 105 is partially recessed on both sides of the gate structure 140, and the source / drain region 120 can be disposed on the recessed active fin 105. According to an example embodiment, the active region ACT can have a doped region including impurities. For example, the active fin 105 can include impurities diffused from the source / drain region 120 into a region in contact with the source / drain region 120. In an example embodiment, the active fin 105 can be omitted, in which case the active region ACT can have a structure having a flat upper surface.

[0083] The source / drain region 120 can be disposed on a recessed region in which the active fin 105 is recessed on both sides of the gate structure 140. The source / drain region 120 can be provided as a source region or a drain region of a transistor. In Figure 10C A cross-section of the source / drain region 120 in the X direction can have a shape with an angle. However, in an example embodiment, the source / drain region 120 can have various shapes, for example, any one of a polygonal shape, a circular shape, an elliptical shape, and a rectangular shape.

[0084] As shown in FIG. 1A, the source / drain region 120 can have a merged shape between adjacent active fins 105 in the Y direction, but the shape is not limited thereto. The source / drain region 120 can have a shape with an angle in a cross-section thereof in the Y direction. Figure 10A Figure 10A

[0085] ​​​The source / drain regions 120 can be formed of an epitaxial layer, and can include, for example, silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC). In addition, the source / drain regions 120 can further include impurities such as arsenic (As) and / or phosphorus (P). In an example embodiment, the source / drain regions 120 can include a plurality of regions including different concentrations of elements and / or doped elements.

[0086] The gate structure 140 can be disposed to extend in one direction (for example, in the Y direction) to cross the active regions ACT on the upper portions of the active fins 105. The channel regions of the transistors can be formed in the active fins 105 that cross the gate structure 140. The gate structure 140 can include a gate insulating layer 142, a gate electrode layer 145, a gate spacer layer 146, and a gate cap layer 148.

[0087] The gate insulating layer 142 can be disposed between the active fin 105 and the gate electrode layer 145. In an example embodiment, the gate insulating layer 142 can be formed of a plurality of layers, or can be disposed to extend on the side surfaces of the gate electrode layer 145. The gate insulating layer 142 can include an oxide, a nitride, or a high-k material. The high-k material can denote a dielectric material having a dielectric constant higher than that of a silicon oxide film (SiO2).

[0088] The gate electrode layer 145 can include a conductive material (for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo), etc.), or a semiconductor material such as doped polysilicon. The gate electrode layer 145 can also include two or more layers. According to the circuit configuration of the semiconductor device 200, the gate electrode layer 145 can be disposed to be divided in the Y direction between at least some adjacent transistors. For example, the gate electrode layer 145 can be divided by separate gate isolation layers.

[0089] The gate spacer layer 146 can be disposed on both sides of the gate electrode layer 145. The gate spacer layer 146 can insulate the source / drain regions 120 from the gate electrode layer 145. According to an example embodiment, the gate spacer layer 146 can have a multi-layer structure. The gate spacer layer 146 can be formed of an oxide, a nitride, and an oxynitride, and in detail, can be formed of a low dielectric constant film. The gate spacer layer 146 can include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0090] The gate cap layer 148 can be disposed on the gate electrode layer 145, and the lower surface and the side surface of the gate cap layer can be surrounded by the gate electrode layer 145 and the gate spacer layer 146, respectively. The gate cap layer 148 can be formed of, for example, an oxide, a nitride, and an oxynitride.

[0091] The lower interlayer insulating layer 130 can be disposed to cover the source / drain region 120 and the gate structure 140. The lower interlayer insulating layer 130 can include at least one of, for example, an oxide, a nitride, and an oxynitride, and can include a low dielectric constant material.

[0092] The contact CNT penetrates the lower interlayer insulating layer 130 to be connected to the source / drain region 120, or penetrates the lower interlayer insulating layer 130 and the gate cap layer 148 to be connected to the gate electrode layer 145, and can apply an electrical signal to the source / drain region 120 and the gate electrode layer 145. The contact CNT can be disposed such that the source / drain region 120 is recessed to a predetermined depth, but the configuration is not limited thereto. The contact CNT can include a conductive material (for example, a metallic material such as tungsten (W), aluminum (Al), copper (Cu)) or a semiconductor material such as doped polysilicon. According to an example embodiment, the contact CNT can include a barrier metal layer disposed along an outer surface. According to an example embodiment, the contact CNT can further include a metal semiconductor layer, for example, a silicide layer disposed at an interface in contact with the source / drain region 120 and the gate electrode layer 145.

[0093] The upper interlayer insulating layer 150 covers the contact CNT, and can be disposed at the same level as the interconnection structure including the lower via V0, the first interconnection line M1, the first via V1, the second interconnection line M2, the second via V2, and the third interconnection line M3. The upper interlayer insulating layer 150 includes a first insulating layer 152, a second insulating layer 154, a third insulating layer 156, and a fourth insulating layer 158, and the first insulating layer 152, the second insulating layer 154, the third insulating layer 156, and the fourth insulating layer 158 can be disposed at the same height level as the lower via V0, the first interconnection line M1, the first via V1, and the second interconnection line M2, and the second via V2 and the third interconnection line M3, respectively. The upper interlayer insulating layer 150 can be formed of silicon oxide or a low dielectric constant material. The upper interlayer insulating layer 150 can include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0094] The etching stop layer 160 can be disposed on respective lower surfaces of the first insulating layer 152, the second insulating layer 154, the third insulating layer 156, and the fourth insulating layer 158. The etching stop layer 160 can serve as an etching stop layer in an etching process for forming the lower via V0, the first interconnection line M1, the first via V1, and the second via V2. The etching stop layer 160 can include a high-k material, and can include, for example, silicon nitride or aluminum oxide.

[0095] The lower via V0, the first interconnection line M1, the first via V1, the second interconnection line M2, the second via V2, and the third interconnection line M3 constituting the interconnection structure can be sequentially stacked and disposed from the lower portion. The first interconnection line M1, the second interconnection line M2, and the third interconnection line M3 can have a relatively greater thickness as being disposed on a higher upper portion, but the configuration is not limited thereto. The interconnection structure can respectively include an electrically conductive material. For example, the interconnection structure can respectively include at least one of aluminum (Al), copper (Cu), and tungsten (W).

[0096] The barrier layer 170 can be disposed in the interconnection structure along lower surfaces of the interconnection lines M1, M2, and M3 and the vias V0, V1, and V2. In detail, the barrier layer 170 can be disposed along lower surfaces and side surfaces of each of the lower via V0, the first interconnection line M1, the first via V1, the second interconnection line M2, the second via V2, and the third interconnection line M3. In detail, the barrier layer 170 can continuously extend from a side surface and a lower surface of the second interconnection line M2 along a side surface of the first via V1 to a lower surface of the first via V1, as shown in Figure 10D The barrier layer 170 can continuously extend from a side surface and a lower surface of the third interconnection line M3 along a side surface of the second via V2 to a lower surface of the second via V2. When the lower via V0 and the first interconnection line M1 are respectively formed in a single damascene process, and the first via V1 and the second interconnection line M2 and the second via V2 and the third interconnection line M3 are respectively formed in a dual damascene process, the arrangement of the barrier layer 170 as described above is provided. The barrier layer 170 can include at least one of titanium (Ti), tantalum (Ta), cobalt (Co), titanium nitride (TiN), and tantalum nitride (TaN).

[0097] As shown in Figure 10D The second interconnection line M2 disposed to pass through a boundary of the first standard cell SC1 and the fourth standard cell SC4 adjacent to each other in the Y direction can be a 2-1 spike line M2 (ST2a), as shown in Figure 9A Thus, as described above with reference to Figure 4A , a length L5 of the second interconnection line M2 overlapping the first standard cell SC1 can be greater than a length L6 of the second interconnection line M2 overlapping the fourth standard cell SC4. The second interconnection line M2 can connect the first interconnection line M1 corresponding to the first low power transmission line M1 (VSS) disposed therebelow and the third interconnection line M3 corresponding to the third low power transmission line M3 (VSS) disposed thereabove. For example, the second interconnection line M2 as the 2-1 spike line M2 (ST2a) extends relatively short in the Y direction, and can connect the first interconnection line M1 and the third interconnection line M3 as power rails extending in an X direction perpendicular to the Y direction.

[0098] Figure 11This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 11 It shows the relationship with Figure 10C The corresponding area. (Refer to...) Figure 11 The semiconductor device 200a may further include a plurality of channel layers 115 disposed on the active region ACT and spaced apart from each other in the vertical direction, and an inner spacer layer 118 disposed between the plurality of channel layers 115 and parallel to the gate electrode layer 145. The semiconductor device 200a may include a gate-around transistor, wherein a gate structure 140a is disposed between the active fin 105 and the channel layers 115 and between the plurality of nanosheet-like channel layers 115. For example, the semiconductor device 200a may include a multi-bridge channel FET (MBCFET) provided through the channel layers 115, the source / drain regions 120, and the gate structure 140a. TM A transistor with a ) structure.

[0099] Multiple channel layers 115 may be disposed on the active region ACT in a direction perpendicular to the upper surface of the active fin 105 (e.g., in the Z direction) and spaced apart from each other. The channel layers 115 may be spaced apart from the upper surface of the active fin 105 while being connected to the source / drain region 120. The channel layers 115 may have the same or similar width as the active fin 105 in the Y direction and the same or similar width as the gate structure 140a in the X direction. However, according to an example embodiment, the channel layers 115 may also have a reduced width, such that the side surfaces of the channel layers are located below the gate structure 140a in the X direction.

[0100] Multiple channel layers 115 can be formed of semiconductor materials and may include at least one of, for example, silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel layers 115 can be formed of, for example, the same material as the substrate 101. In exemplary embodiments, the number and shape of the channel layers 115 constituting a channel structure can vary considerably. For example, according to an exemplary embodiment, the channel layers may also be located in the region of the active fin 105 contact gate electrode layer 145.

[0101] A gate structure 140a can be disposed on the active fin 105 and the plurality of channel layers 115, extending while intersecting with the active fin 105 and the plurality of channel layers 115. The channel region of the transistor can be formed in the active fin 105 and the channel layer 115 intersecting with the gate structure 140a. In this embodiment, a gate insulating layer 142 can be disposed not only between the active fin 105 and the gate electrode layer 145, but also between the plurality of channel layers 115 and the gate electrode layer 145. The gate electrode layer 145 can be disposed on the active fin 105, extending to the upper portion of the plurality of channel layers 115 while filling the spaces between the plurality of channel layers 115. The gate electrode layer 145 can be spaced apart from the plurality of channel layers 115 by the gate insulating layer 142.

[0102] The inner spacer layer 118 may be disposed parallel to the gate electrode layer 145 among the plurality of channel layers 115. The gate electrode layer 145 may be spaced apart from and electrically isolated from the source / drain region 120 by the inner spacer layer 118. The inner spacer layer 118 may have a flat side surface facing the gate electrode layer 145, or a convex shape facing the gate electrode layer 145. The inner spacer layer 118 may be formed of oxides, nitrides, and oxynitrides, and specifically, may be formed of a low dielectric constant film. According to an exemplary embodiment, the inner spacer layer 118 may be omitted.

[0103] In the example embodiment, there is an MBCFET. TM The semiconductor device 200a with the structure can also be used with Figures 10A to 10D The semiconductor device 200 is additionally disposed together with the above reference. Figures 9A to 9C The semiconductor device described herein. Furthermore, in an example embodiment, the semiconductor device may also include a vertical field-effect transistor (vertical FET), wherein an active region extending vertically to the upper surface of the substrate 101 and a gate structure surrounding the active region are disposed in at least one region.

[0104] As described above, according to the example embodiment, by arranging the pin wires in an optimized manner in the second interconnect, a semiconductor device with improved integration and reliability can be provided.

[0105] Although exemplary embodiments have been described and illustrated above, it will be apparent to those skilled in the art that modifications and alterations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A plurality of standard cells are arranged on the upper surface of a substrate along a first direction and along a second direction perpendicular to the first direction. Each of the plurality of standard cells includes: an active region, a gate structure on the active region, source / drain regions extending adjacent to the active region and on both sides of the gate structure, and a first interconnect including a first power transmission line and a first signal transmission line; and A wiring structure disposed on the plurality of standard units, the wiring structure including a second interconnection electrically connected to the first interconnection; The plurality of standard units include a first standard unit and a second standard unit, wherein the first standard unit and the second standard unit extend adjacent to each other in the second direction; and The second interconnect includes: At least one or more second power transmission lines are electrically connected to the first power transmission line and are arranged along a line along all the standard units arranged in the second direction; A second signal transmission line, electrically connected to the first signal transmission line, and disposed on a portion of the plurality of standard units; and A first pin wire, electrically connected to the first power transmission line, is disposed on the boundary between the first standard unit and the second standard unit, such that it overlaps the first standard unit by a first length in the second direction and overlaps the second standard unit by a second length different from the first length in the second direction.

2. The semiconductor device according to claim 1, wherein, The first nail has a third length in the second direction, and the plurality of standard units have a fourth length in the second direction that is greater than the third length.

3. The semiconductor device according to claim 1, wherein, The second length is greater than the first length, and the ratio of the first length to the second length is greater than 1 / 6.

4. The semiconductor device according to claim 1, wherein, The first power transmission line extends in the first direction; and wherein the second power transmission line, the second signal transmission line, and the first pin line extend in the second direction.

5. The semiconductor device of claim 4, further comprising a third power transmission line extending in the first direction, the third power transmission line being electrically connected to the second power transmission line and the first pin wire.

6. The semiconductor device according to claim 5, wherein, The third power transmission line is configured to overlap with the entire first power transmission line.

7. The semiconductor device according to claim 4, wherein, The end of the first nail wire is spaced apart in the second direction from the end of the second power transmission line or the end of the second signal transmission line that is adjacent to the first nail wire in the first direction.

8. The semiconductor device according to claim 1, wherein, The wiring structure further includes a through-hole member that vertically connects the first interconnect and the second interconnect; and wherein the first spiked wire is connected to the first power transmission line through the through-hole member in the area overlapping with the first power transmission line.

9. The semiconductor device according to claim 1, wherein, The first power transmission line includes a high power rail and a low power rail alternately arranged in the second direction, the high power rail and the low power rail being configured to supply different first power supply voltages and second power supply voltages, respectively; and wherein the second power transmission line includes a second high power transmission line electrically connected to the high power rail and a second low power transmission line electrically connected to the low power rail.

10. The semiconductor device according to claim 1, wherein, The second interconnect further includes a second spike wire electrically connected to the first power transmission line and overlapping the first standard unit and the second standard unit by substantially the same length, respectively.

11. The semiconductor device according to claim 1, wherein, The second interconnect also includes a third pin wire that is electrically connected to the first power transmission line and extends beyond one of the plurality of standard units.

12. The semiconductor device according to claim 1, wherein, The second interconnect also includes a fourth pin wire that is electrically connected to the first power transmission line and extends substantially the same length from the center line of one of the plurality of standard units.

13. The semiconductor device of claim 1, further comprising filler units disposed between at least portions of the plurality of standard cells, each including a filler active region extending from the active region of the at least portion of the plurality of standard cells, a filler gate structure intersecting the filler active region, and a first interconnect extending from the plurality of standard cells; and in, The second interconnect further includes a fifth pin wire electrically connected to the first power transmission line and disposed on the boundary between the filler units adjacent to each other along the second direction or on the boundary between the filler units and at least a portion of the plurality of standard units.

14. A semiconductor device, comprising: The first standard unit and the second standard unit include, on a substrate, respective semiconductor elements and a first interconnect line electrically connected to the semiconductor elements; as well as A wiring structure is disposed on the first standard unit and the second standard unit, the wiring structure including a second interconnection line electrically connected to the first interconnection line; The first interconnect includes a first power transmission line configured to supply power to the semiconductor element and a first signal transmission line electrically coupled to the semiconductor element; and The second interconnect includes: A second power transmission line is electrically connected to the first power transmission line and extends a first length; A second signal transmission line is electrically connected to the first signal transmission line; and A nail wire, electrically connected to the first power transmission line, is disposed on the boundary between the first standard unit and the second standard unit, and extends a second length less than the first length.

15. The semiconductor device according to claim 14, wherein, The first power transmission line extends along the boundary of the first standard unit and the second standard unit in a first direction; and wherein the spiked wire overlaps with the first power transmission line and extends in a second direction perpendicular to the first direction.

16. The semiconductor device according to claim 14, wherein, The second signal transmission line has a third length that is less than the first length and greater than the second length.

17. The semiconductor device according to claim 14, wherein, The wiring structure further includes a through-hole member that vertically connects the first interconnect and the second interconnect, and a barrier layer extending from the side and bottom surfaces of the second interconnect to the side and bottom surfaces of the through-hole member.

18. The semiconductor device according to claim 14, wherein, The nail wire overlaps the first standard unit by a fourth length in its extension direction, and overlaps the second standard unit by a fifth length different from the fourth length.

19. A semiconductor device, comprising: Multiple standard cells are disposed on a substrate. Each of the multiple standard cells includes an active region, a gate structure located on the active region, source / drain regions located on both sides of the gate structure and adjacent to the active region, and a first interconnect including a first power transmission line. as well as A wiring structure located on the plurality of standard units, the wiring structure including a second interconnect and a third interconnect, the second interconnect including a pin wire electrically connected to the first power transmission line, and the third interconnect including a third power transmission line disposed on the second interconnect to be electrically connected to the pin wire; Wherein, the first power transmission line extends along the boundary of the plurality of standard units in a first direction; The pin line is configured to pass through the boundary between the standard units in the boundary of the plurality of standard units, overlap with the first power transmission line and the third power transmission line, and extend in a second direction perpendicular to the first direction; Wherein, the third power transmission line overlaps with the first power transmission line to extend in the first direction; and The nail line is asymmetrically arranged in the second direction relative to the boundary located between the standard units.

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