Image sensor

Abstract

An image sensor is disclosed, comprising: a substrate including an active pixel region and an inactive pixel region, having an area smaller than the active pixel region; a plurality of active pixels, each of the plurality of active pixels including a first transmission transistor, a first reset transistor, a first drive transistor, and a first selection transistor in the active pixel region; and a plurality of inactive pixels, each of the plurality of inactive pixels including a second transmission transistor, a second reset transistor, a second drive transistor, a second selection transistor, and a switching transistor connected to a node between the second drive transistor and the second selection transistor in the inactive pixel region. The plurality of switching transistors included in the plurality of inactive pixels are interconnected with each other via interconnect wiring.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0051380, filed with the Korean Intellectual Property Office on April 28, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an image sensor. Background Technology

[0004] An image sensor is a semiconductor-based sensor that receives light to generate electrical signals, and may include a pixel array having multiple pixels, logic circuitry and / or the like for driving the pixel array and generating an image. The logic circuitry can obtain pixel signals from the pixels to generate image data. Recently, with the increase in the number of pixels included in image sensors and the decrease in the area of ​​a single pixel, various efforts have been made to improve the noise characteristics of the pixel signals. Summary of the Invention

[0005] An example embodiment provides an image sensor that can (potentially) significantly reduce pixel output voltage fluctuations by obtaining a reset voltage from a pixel and then connecting the column lines connected to the pixel to each other.

[0006] According to some example embodiments, an image sensor includes: a substrate including an active pixel region and an inactive pixel region, the inactive pixel region having an area smaller than the active pixel region; a plurality of active pixels, each of the plurality of active pixels including a first transmission transistor, a first reset transistor, a first drive transistor, and a first selection transistor in the active pixel region; and a plurality of inactive pixels, each of the plurality of inactive pixels including a second transmission transistor, a second reset transistor, a second drive transistor, a second selection transistor, and a switching transistor connected to a node between the second drive transistor and the second selection transistor in the inactive pixel region. Each of the plurality of switching transistors included in the plurality of inactive pixels is interconnected with each other via interconnect wiring.

[0007] According to some example embodiments, an image sensor includes: a plurality of active pixels, wherein the plurality of active pixels include a first selection transistor connected to one of a plurality of column lines extending in the second direction in a first direction and a second direction intersecting the first direction; a plurality of inactive pixels, wherein the plurality of inactive pixels include a second selection transistor connected to one of the column lines in the first direction; a plurality of switching transistors, each of the plurality of switching transistors being connected to a corresponding second selection transistor included in each of the plurality of inactive pixels and a connection wiring extending in the first direction; and logic circuitry configured to: obtain pixel data output by the plurality of active pixels and turn on the plurality of switching transistors while the plurality of second selection transistors are turned on.

[0008] According to some example embodiments, an image sensor includes: a plurality of pixels connected to a plurality of row lines extending in a first direction and a plurality of column lines extending in a second direction intersecting the first direction; and logic circuitry configured to obtain pixel data from the plurality of pixels. Each of the plurality of pixels includes a photoelectric element, a floating diffusion region storing a charge generated by the photoelectric element, a transfer transistor between the floating diffusion region and the photoelectric element, a driving transistor connected to the floating diffusion region, and a selection transistor connected between one of the column lines and the driving transistor. The logic circuitry is configured to obtain a reset signal from a selected pixel among the plurality of pixels during a first time period, to obtain a pixel signal from the selected pixel during a second time period after the first time period, and to electrically connect the plurality of column lines to each other and turn on the transfer transistor of each of the selected pixels during a transmission time between the first time period and the second time period. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 This is a schematic block diagram of an image sensor according to an example embodiment.

[0011] Figures 2 to 5 A pixel array of an image sensor according to an example embodiment is shown.

[0012] Figure 6 A portion of the pixels included in an image sensor according to an example embodiment is shown.

[0013] Figure 7 and Figure 8 It shows Figure 6 The operation of the image sensor according to an example embodiment is shown in the figure.

[0014] Figure 9 A portion of the pixels included in an image sensor according to an example embodiment is shown.

[0015] Figure 10 and Figure 11 It shows Figure 9 The operation of the image sensor according to an example embodiment is shown in the figure.

[0016] Figure 12 A portion of the pixels included in an image sensor according to an example embodiment is shown.

[0017] Figure 13 It shows Figure 12 The operation of the image sensor according to an example embodiment is shown in the figure.

[0018] Figure 14 A portion of the pixels included in an image sensor according to an example embodiment is shown.

[0019] Figure 15 It shows Figure 14 The operation of the image sensor according to an example embodiment is shown in the figure.

[0020] Figure 16 A portion of the pixels included in an image sensor according to an example embodiment is shown.

[0021] Figure 17 A portion of the pixels included in an image sensor according to an example embodiment is shown.

[0022] Figure 18 It shows Figure 17 The operation of the image sensor according to an example embodiment is shown in the figure.

[0023] Figure 19 A portion of the pixels included in an image sensor according to an example embodiment is shown.

[0024] Figure 20 It shows Figure 19 The operation of the image sensor according to an example embodiment is shown in the figure.

[0025] Figure 21 and Figure 22 This is a schematic diagram of an image sensor according to an example embodiment.

[0026] Figure 23 and Figure 24 This is a schematic diagram of an image sensor according to an example embodiment.

[0027] Figure 25 This is a schematic block diagram of a mobile system including an image sensor according to an example embodiment. Detailed Implementation

[0028] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic block diagram of an image sensor according to an example embodiment.

[0030] Reference Figure 1 The image sensor 1 may include a pixel array 10, logic circuitry 20, and / or the like.

[0031] The pixel array 10 may include a plurality of pixels PX arranged in an array along multiple rows and columns. Each of the plurality of pixels PX may include at least one photoelectric element that generates charge in response to light, pixel circuitry and / or the like that generate a pixel signal corresponding to the charge generated by the photoelectric element. The photoelectric element may include a photodiode formed of a semiconductor material and / or an organic photodiode formed of an organic material.

[0032] As an example, the pixel circuit may include a floating diffusion region, a transfer transistor, a reset transistor, a drive transistor, a select transistor, and / or the like. The configuration of the pixel PX may vary depending on the example embodiment. As an example, each of the pixels PX may include an organic photodiode comprising organic materials, or may be implemented as a digital pixel. When the pixel PX is implemented as a digital pixel, each of the pixels PX may include an analog-to-digital converter for outputting a digital pixel signal.

[0033] The logic circuit 20 may include circuitry for controlling the pixel array 10. As an example, the logic circuit 20 may include a row driver 21, a readout circuit 22, a column driver 23, control logic circuitry 24, and / or the like. The row driver 21 may drive the pixel array 10 on a row-line basis. For example, the row driver 21 generates transfer control signals for the transfer transistors controlling the pixel circuitry, reset control signals for the reset transistors controlling the select transistors, and / or the like, and may input the generated signals to the pixel array 10 on a row-line basis.

[0034] The readout circuit 22 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), and / or the like. The correlated double sampler can be connected to the pixel PX via column lines. The correlated double sampler can read pixel signals from the pixel PX connected to a row line selected by the row line selection signal of the row driver 21 via the column lines. The ADC can convert the pixel signals detected by the correlated double sampler into digital pixel signals and can send the digital pixel signals to the column driver 23.

[0035] Column driver 23 may include latches or buffer circuits for temporary storage of digital pixel signals, amplifier circuits, and / or the like, and may process digital pixel signals received from readout circuit 22. Row driver 21, readout circuit 22, and column driver 23 may be controlled by control logic circuit 24. Control logic circuit 24 may include a timing controller for controlling the operating timing of row driver 21, readout circuit 22, and column driver 23.

[0036] In pixels PX, pixels PX positioned at the same location in a first direction (horizontal direction) can share the same column line. As an example, pixels PX positioned at the same location in a second direction (vertical direction) are simultaneously selected by row driver 21 and can output pixel signals via the column line. In some example embodiments, readout circuit 22 can simultaneously obtain pixel signals from pixels PX selected by row driver 21 via the column line. The pixel signal can have a reset voltage and a pixel voltage, and the pixel voltage can be a voltage in which the charge generated in response to light in each of the pixels PX is reflected in the reset voltage.

[0037] In some example embodiments, the readout circuit 22 can sequentially read the reset voltage and pixel voltage from each of the pixels PX selected by the row driver 21. After the readout circuit 22 reads the reset voltage, the charge generated by the photoelectric element in each pixel PX can be transferred to the floating diffusion region. For example, the voltage on the column lines may fluctuate due to switching operations, during which the charge of the photoelectric element is transferred to the floating diffusion region or the like. The voltage on the column lines may not be maintained at the reset voltage.

[0038] In some example embodiments, by connecting the column lines to each other while transferring the charge of the photoelectric element to the floating diffusion region, voltage fluctuations in the column lines can be significantly reduced. Therefore, the noise characteristics of the image sensor 1 can be improved.

[0039] Figures 2 to 5 A pixel array of an image sensor according to an example embodiment is shown.

[0040] Reference Figure 2 The image sensor 100 may include a pixel array 110, a row driver 120, a readout circuit 130, and / or the like. The pixel array 110 may include a plurality of pixels 101 and 102 and may be connected to the row driver 120 via row lines R1 to Rm and to the readout circuit 130 via column lines C1 to Cn. The operation of the row driver 120 and the readout circuit 130 may be similar to that described in reference [reference needed]. Figure 1 Describe the row driver and readout circuitry.

[0041] The pixel array 110 may include an active pixel region 111 in which active pixels 101 are disposed, and an inactive pixel region 115 in which inactive pixels 102 are disposed. Each of the active pixels 101 and each of the inactive pixels 102 may have the same structure. As an example, each of the active pixels 101 and each of the inactive pixels 102 may include a photoelectric element, a transmission transistor, a driving transistor, and a selection transistor, and may include pixel circuits having the same structure and formed by the same process.

[0042] exist Figure 2 In the example embodiment shown, inactive pixels 102 can be disposed in the first direction (horizontal direction) and can be disposed below the active pixel area 111 in the pixel array 110. Therefore, in the first direction, the width of the inactive pixel area 115 can be the same as the width of the active pixel area 111. The number of inactive pixels 102 can be less than the number of active pixels 101. As an example, the number of active pixels 101 can be N times the number of inactive pixels 102 (where N is a positive integer).

[0043] In some example embodiments, the inactive pixel 102 and / or readout circuitry 130 may include switching transistors that connect column lines C1 to Cn to each other. The switching transistors may be connected to a node where the drive transistors and select transistors in the inactive pixel 102 are connected to each other, or they may be connected between column lines C1 to Cn.

[0044] When the row driver 120 selects one of the row lines R1 to Rm-1 connected to the active pixel area 111, the readout circuit 130 can obtain a pixel signal from the active pixel 101 connected to the selected row line. Simultaneously with the readout circuit 130 obtaining the pixel signal, a switching transistor can be turned on for a predetermined time or alternatively, a desired time, to electrically connect the column lines C1 to Cn to each other. As an example, in the active pixel 101 connected to the selected row line, the switching transistor can be turned on while the transmission transistor is on, thereby allowing for a significant reduction in voltage fluctuations on the column lines C1 to Cn.

[0045] Reference Figure 3 The image sensor 100A may include a pixel array 110A, a row driver 120, a readout circuit 130, and / or the like. Figure 3 In the example embodiment shown, the pixel array 110A may include a first inactive pixel area 115A and a second inactive pixel area 116A disposed on opposite sides of the active pixel area 111A in a second direction (vertical direction). (Refer to...) Figure 3The number of inactive pixels 102 included in the first inactive pixel area 115A can be the same as the number of inactive pixels 102 included in the second inactive pixel area 116A. The inactive pixels 102 can be adjacent to the active pixel 101 on one side in the second direction.

[0046] Each of the inactive pixels 102 included in the first inactive pixel area 115A and the inactive pixels 102 included in the second inactive pixel area 116A may include a switching transistor that can connect or disconnect column lines C1 to Cn from each other. Figure 3 In the example embodiment shown, when the row driver 120 selects one of the row lines R2 to Rm-1 connected to the active pixel area 111A in inactive pixel areas 115A and 116A, it can also select a pixel area close to the selected row line. For example, in the case of selecting the second row line R2, the first inactive pixel area 115A can be selected. When the transmission transistor of the active pixel 101 connected to the second row line R2 is turned on, the switching transistors included in the inactive pixels 102 of the first inactive pixel area 115A can be turned on to electrically connect the column lines C1 to Cn to each other.

[0047] Alternatively, according to the example embodiment, all inactive pixels 102 can be selected simultaneously regardless of the position of the selected row line. For example, when the transmission transistor of the active pixel 101 selected by the row driver 120 is turned on, the switching transistors included in the inactive pixels 102 in the first inactive pixel region 115A and the second inactive pixel region 116A can be turned on to electrically connect the column lines C1 to Cn to each other.

[0048] Reference Figure 4 The image sensor 100B may include a pixel array 110B, a row driver 120, a readout circuit 130, and / or the like. Figure 4 In the illustrated example embodiment, pixel array 110B includes active pixel areas 111B and 112B and inactive pixel areas 115B and 116B. The active pixel areas 111B and 112B and the inactive pixel areas 115B and 116B can be alternately arranged in a second direction (vertical direction). Therefore, the inactive pixel 102 included in the first inactive pixel area 115B can be adjacent to the active pixel 101 on opposite sides in the second direction.

[0049] The operation of inactive pixel 102 can be similar to that of reference. Figure 3The operation described. In the example embodiment, during the time when a pixel signal is selected from the active pixel 101 by the row driver 120, only one of the inactive pixel areas 115B and 116B can be selected. For example, when the switching transistor in the selected inactive pixel 102 included in the inactive pixel area 115B and 116B is turned on, the column lines C1 to Cn can be electrically connected to each other.

[0050] Additionally, in some example embodiments, all inactive pixel areas 115B and inactive pixel areas 116B can be selected during the time when pixel signals are selected from active pixel 101 by row driver 120. For example, column lines C1 to Cn can be electrically connected to each other during the conduction of switching transistors in inactive pixels 102 included in both inactive pixel areas 115B and 116B.

[0051] Reference Figure 5 The image sensor 100C may include a pixel array 110C, a row driver 120, a readout circuit 130, and / or the like. Figure 5 In the illustrated example embodiment, pixel array 110C includes active pixel regions 111C to 113C and inactive pixel regions 115C to 117C. The active pixel regions 111C and 113C, as well as the inactive pixel regions 115C and 117C, can be alternately arranged in a second direction (vertical direction). Therefore, in inactive pixels 102, at least a portion of the inactive pixels can be adjacent to the active pixels 101 on opposite sides in the second direction. The operation of inactive pixels 102 can be similar to that described in the reference... Figure 3 and Figure 4 The described operation.

[0052] exist Figures 2 to 5 In the example embodiment shown, the number of active pixels 101 can be 100 to 5000 times the number of inactive pixels 102. As an example, the number of inactive pixels 102 can be appropriately selected considering the number of active pixels 101 included in image sensors 100, 100A, 100B, and 100C. Considering the capacitors present in the column lines C1 to Cn, voltage fluctuations on column lines C1 to Cn can be effectively reduced or prevented by increasing the number of inactive pixels 102 while simultaneously turning on inactive pixels 102 located at different positions in the second direction. However, since inactive pixels 102 do not output pixel data corresponding to the light reflected from the subject, the quality of the resulting image output by image sensors 100, 100A, 100B, and 100C may deteriorate when too many inactive pixels 102 are set. In view of the foregoing, the number of active pixels 101 and the number of inactive pixels 102 can be appropriately selected.

[0053] In addition, with Figures 2 to 5 Unlike the example embodiment shown, two or more inactive pixels 102 can be continuously arranged in a second direction (vertical direction) in which the column lines extend in the pixel array. As an example, in... Figure 5 In a variation of the example embodiment shown, at least a portion of the inactive pixel areas 115C to 117C may be arranged continuously adjacent to each other in the second direction.

[0054] exist Figures 3 to 5 In the exemplary embodiment shown, two or more inactive pixel regions are provided, at least one of which can operate as an active pixel region. For example, in Figure 4 In the illustrated example embodiment, the row driver 120 is selected to be connected to the i-th row line Ri of the first inactive pixel area 115B, and the readout circuit 130 can obtain pixel data from the inactive pixels 102 included in the first inactive pixel area 115B via column lines C1 to Cn. When the row driver 120 turns on the transmission transistor of the inactive pixel 102 included in the first inactive pixel area 115B, the switching transistor connected to the inactive pixel 102 of the second inactive pixel area 116B can be turned on to connect column lines C1 to Cn to each other. Additionally, when the row driver 120 selects the m-th row line Rm and the readout circuit 130 obtains pixel data from the inactive pixel 102 included in the second inactive pixel area 116B, the switching transistor connected to the inactive pixel 102 of the inactive pixel area 115B can be controlled to connect / deconnect column lines C1 to Cn to each other.

[0055] As described above, the switching transistors that connect / disconnect column lines C1 to Cn can be connected to the pixel circuit of inactive pixel 102, and can be disposed in inactive pixel 102 or readout circuit 130, as described above. Figures 3 to 5 In the exemplary embodiment shown, there are two or more inactive pixel areas. When the switching transistors are set in the readout circuit 130, switching transistors corresponding to the two or more inactive pixel areas can be set in the readout circuit 130 respectively.

[0056] As an example, the readout circuit 130 may include analog-to-digital converters corresponding to column lines C1 to Cn, and switching transistors may be included in the analog-to-digital converters. The analog-to-digital converters and column lines C1 to Cn may be configured in a one-to-one correspondence. For example, in Figure 3 and Figure 4In the example embodiment shown, when the switching transistors are placed in the readout circuit 130, two switching transistors may be included in a single analog-to-digital converter. The two switching transistors included in the single analog-to-digital converter may be connected to inactive pixels 102 in the first inactive pixel areas 115A and 115B and inactive pixels 102 in the second inactive pixel areas 116A and 116B, respectively.

[0057] Figure 6 A portion of the pixels included in an image sensor according to some example embodiments is shown. Figure 7 and Figure 8 It shows Figure 6 The operation of the image sensor according to an example embodiment is shown in the figure.

[0058] First refer to Figure 6 The pixel array 200 of the image sensor according to an example embodiment includes an active pixel region 210 in which active pixels 211 and 212 are disposed, an inactive pixel region 220 in which inactive pixels 221 and 222 are disposed, and / or the like. Active pixels 211 and 212 and inactive pixels 221 and 222 disposed at the same position in a first direction (horizontal direction) may share column lines COL1 and COL2. As an example, the first active pixel 211 and the first inactive pixel 221 may share the first column line COL1, and the second active pixel 212 and the second inactive pixel 222 may share the second column line COL2.

[0059] Each of active pixels 211 and 212 may include a photoelectric element PD, a transmission transistor TX, a reset transistor RX, a drive transistor SF, a selection transistor SX, and / or the like. Each of inactive pixels 221 and 222 includes a photoelectric element PD, a transmission transistor TX, a reset transistor RX, a drive transistor SF, a selection transistor SX, a switching transistor SW, and / or the like. The elements included in each of the active pixels 211 and 212 and the inactive pixels 221 and 222 can be controlled by a row driver connected to the pixel array 200.

[0060] In each of the inactive pixels 221 and 222, a switching transistor SW can be connected to a node between the driving transistor SF and the selection transistor SX, as well as a connecting line, such as connecting wiring 205. When the switching transistor SW and the selection transistor SX are turned on in the inactive pixels 221 and 222, column lines COL1 and COL2 can be electrically connected to each other via connecting wiring 205.

[0061] Connection wiring 205 can be connected to a power node to supply a predetermined or alternatively desired constant voltage via connection pad 230 and wiring transistor CT. When switching transistor SW is off, wiring transistor CT can be turned on to reduce or prevent connection wiring 205 from floating.

[0062] In the following text, reference will be made to Figure 7 and Figure 8 Description based on Figure 6 The operation of the image sensor in the example embodiment shown is illustrated.

[0063] Figure 7 The operation of obtaining pixel signals from active pixels 211 and 212 is shown. (Refer to...) Figure 7 The reset control signal RG turns on the reset transistor RX to reset the voltage of the floating diffusion region FD of active pixels 211 and 212. When the reset operation is complete, the reset transistor RX turns off, and during the first time T1, the selection transistor SX can be turned on by the selection control signal SEL.

[0064] The readout circuit of the image sensor can obtain the reset signal RST by comparing the first output voltage OUT1 output through the first column line COL1 during the first time T1 with the ramp voltage RMP. As an example, the readout circuit can obtain the reset signal RST by counting the time the ramp voltage RMP is higher than the first output voltage OUT1 of the first column line COL1. The readout circuit can simultaneously obtain the reset signals RST of the first active pixel 211 and the second active pixel 212 through the first column line COL1 and the second column line COL2.

[0065] When the readout circuit receives a reset signal and a first time T1 has elapsed, during the transmission time TT, the selection transistor SX can be turned off and the transmission transistor TX can be turned on. According to an example embodiment, the on-time of the transmission transistor TX can be shorter than the off-time of the selection transistor SX. When the transmission transistor TX is turned on by the transmission control signal TG during the transmission time TT, the charge generated in the photoelectric elements PD of active pixels 211 and 212 can be transferred to the floating diffusion region FD. Therefore, as... Figure 7 As shown, the first output voltage OUT1 can be reduced. After the transmission transistor TX is turned on, the second output voltage OUT2 can also be reduced according to the amount of charge transferred from the photoelectric element PD of the second active pixel 212 to the floating diffusion region FD.

[0066] When the transmission transistor TX is turned off and the selection transistor SX is turned on again, the readout circuit can obtain the pixel signal SIG by counting for a second time T2 when the ramp voltage RMP is higher than the first output voltage OUT1. The time required for the readout circuit to obtain the pixel signal SIG can be defined as the second time T2. Similar to the reset signal RST, the readout circuit can simultaneously obtain the pixel signals of the first active pixel 211 and the second active pixel 212 through the first column line COL1 and the second column line COL2.

[0067] The operation of inactive pixels 221 and 222 can differ from the operation of active pixels 211 and 212. The inactivity reset control signal NRG input to inactive pixels 221 and 222 can be the same as the reset control signal RG input to active pixels 211 and 212. On the other hand, in Figure 7 In the example embodiment shown, the transmission transistors TX of inactive pixels 221 and 222 can be kept off by the inactive transmission control signal NTG during the first time T1, the second time T2 and the transmission time TT.

[0068] Because the transmission transistors TX of inactive pixels 221 and 222 remain in the off state, excessive charge may be generated in the photoelectric elements PD of inactive pixels 221 and 222. In some example embodiments, the operation of resetting the photoelectric elements PD of inactive pixels 221 and 222 can be performed during the time when active pixels 211 and 212 do not output pixel data (e.g., the time between frame periods).

[0069] The enable signal EN input to the selection transistor SX and the switching transistor SW of inactive pixels 221 and 222 can be a complementary signal to the selection control signal SEL input to the selection transistor SX of active pixels 211 and 212. Therefore, the selection transistor SX and the switching transistor SW of inactive pixels 221 and 222 can be turned on during the transmission time TT to electrically connect column lines COL1 and COL2 to each other. To simultaneously receive the enable signal EN, the gates of the selection transistor SX and the switching transistor SW can be connected to each other.

[0070] In active pixels 211 and 212, the transfer transistor TX can be turned on during the transfer time TT to transfer the charge of the photoelectric element PD to the floating diffusion region FD. For example, the voltages on column lines COL1 and COL2 may not be maintained at the reset voltage and may fluctuate due to coupling effects caused by the on / off operation of the transfer transistor TX or similar. Figure 6In the example embodiment shown, the selection transistor SX and the switching transistor SW of inactive pixels 221 and 222 can be turned on during the transmission time TT, allowing column lines COL1 and COL2 to be electrically connected to each other to eliminate voltage fluctuations occurring in each column line COL1 and COL2. Therefore, reset voltage fluctuations can be significantly reduced, and the impact of reset voltage fluctuations on noise in the pixel signal can be reduced or prevented, thereby improving the noise characteristics of the image sensor.

[0071] The wiring transistor CT connected to the connection wiring 205 can be controlled by the wiring control signal CNT, and the wiring control signal CNT can be the selection control signal SEL input to the active pixels 211 and 212. Therefore, during the time period when column lines COL1 and COL2 are electrically separated from each other (e.g., during the first time T1 and the second time T2), the connection wiring 205 may not float and can be maintained at a predetermined voltage or alternatively, a constant voltage.

[0072] exist Figure 8 In the example embodiment shown, while charge is transferred from the active pixels 211 and 212 of the image sensor to the floating diffusion region FD, the column lines COL1 and COL2 may not be connected to each other. Therefore, the output voltages OUT1 and OUT2 of the column lines COL1 and COL2 may not be held at the reset voltage and can be increased or decreased. On the other hand, in the reference... Figure 7 In the described example embodiment, while charge is transferred from active pixels 211 and 212 to the floating diffusion region FD, column lines COL1 and COL2 can be connected to each other, so that fluctuations in the reset voltage occurring in each column line COL1 and COL2 can cancel each other out.

[0073] Reference Figures 6 to 8 The difference described is that the switching transistor SW connecting column lines COL1 and COL2 to each other can be located in the readout circuit, rather than in the inactive pixels 221 and 222. Even when the switching transistor SW is located in the readout circuit, one end of the switching transistor SW can be connected to the connection wiring 205, while the other end of the switching transistor SW can be connected to the node between the driving transistor SF and the selection transistor SX of each of the inactive pixels 221 and 222.

[0074] Figure 9 A portion of the pixels included in an image sensor according to some example embodiments is shown.

[0075] Figure 10 and Figure 11 It shows Figure 9 The operation of the image sensor according to an example embodiment is shown in the figure.

[0076] First refer to Figure 9 According to some example embodiments, the pixel array 300 of an image sensor may include active pixel areas 310 and 320 and inactive pixel areas 330 and 340. The active pixel areas 310 and 320 and the inactive pixel areas 330 and 340 may each extend in a first direction (horizontal direction) and may share column lines COL1 and COL2. Figure 9 In the example embodiment shown, active pixel areas 310 and 320 and inactive pixel areas 330 and 340 can be alternately arranged in the second direction (vertical direction).

[0077] The operation of active pixels 311, 312, 321, and 322, and inactive pixels 331, 332, 341, and 342 can be similar to that described above. Figure 6 and Figure 7 The operation is described below. Active pixels 311, 312, 321, 322 and inactive pixels 331, 332, 341, 342 can operate in response to the reset control signal RG, transfer control signal TG, and selection control signal SEL input from the row driver. The readout circuitry obtains the reset signal and pixel signal from the active pixels 311, 312, 321, and 322 via column lines COL1 and COL2. The transfer transistor TX of inactive pixels 331, 332, 341, and 342 can remain in the off state while the readout circuitry obtains the reset signal and pixel signal. The reset transistor RX of inactive pixels 331, 332, 341, and 342 can operate in the same manner as the reset transistor RX of active pixels 311, 312, 321, and 322.

[0078] Figure 10 The operation of the readout circuitry obtaining pixel data from active pixels 311 and 312 included in the first active pixel region 310 can be illustrated. (Refer to...) Figure 10 The readout circuit can sequentially obtain the reset signal RST and the pixel signal SIG from active pixels 311 and 312 at the first time T1 and the second time T2, respectively. When the readout circuit obtains the reset signal RST, it can turn off the selection transistor SX of active pixels 311 and 312 during the transmission time TT using the first selection signal SEL1, and turn on the switching transistor SW and the selection transistor SX in inactive pixels 331 and 332 of the first inactive pixel area 330 using the first enable signal EN1. When the switching transistor SW and the selection transistor SX are turned on, column lines COL1 and COL2 can be electrically connected to each other through the first connection wiring 305. The first connection wiring 305 can be connected to the first wiring transistor CT1 through the first connection pad 350.

[0079] Since column lines COL1 and COL2 are connected to each other during the transmission time TT, voltage fluctuations occurring in each column line COL1 and COL2 due to coupling effects caused by the operation of the transmission transistor TX or the like can cancel each other out. Therefore, the time required for the voltages on column lines COL1 and COL2 to stabilize after the transmission transistor TX is turned on / off can be reduced, improving readout speed and noise characteristics. During the time when column lines COL1 and COL2 are not connected, the first wiring transistor CT1 can be turned on by the first control signal CNT1 to input a constant voltage to the first connection wiring 305.

[0080] exist Figure 10 In the example embodiment shown, while a readout operation is performed on the first active pixel area 310, the second inactive pixel area 340 may remain inactive. (Refer to...) Figure 10 During the readout operation of the first active pixel area 310, the second inactive reset control signal NRG2 and the second enable signal EN2 can keep all the reset transistor RX, select transistor SX, and switch transistor SW included in the inactive pixels 341 and 342 of the second inactive pixel area 340 in the off state. On the other hand, the second wiring transistor CT2 can be turned on by the second control signal CNT2, so a constant voltage can be input to the second connection wiring 307. The second connection wiring 307 can be connected to the second wiring transistor CT2 through the second connection pad 360.

[0081] Figure 11 The operation of the readout circuitry obtaining pixel data from active pixels 321 and 322 included in the second active pixel area 320 can be illustrated. (Refer to...) Figure 11 The readout circuit can sequentially obtain the reset signal RST and the pixel signal SIG from active pixels 321 and 322. Similar to the reference... Figure 10 As described, during the transmission time TT, the second selection signal SEL2 and the switching transistor SW can turn off the selection transistor SX of active pixels 321 and 322, and the second enable signal EN2 can turn on the selection transistor SX in inactive pixels 341 and 342 of the second inactive pixel area 340, and the column lines COL1 and COL2 can be connected to each other through the second connection wiring 307. Therefore, while the second transmission control signal TG2 turns on the transmission transistor TX, voltage fluctuations occurring in the respective column lines COL1 and COL2 can be eliminated.

[0082] Additionally, similar to references Figure 10 As described, during a readout operation on the second active pixel area 320, the first inactive pixel area 330 may remain inactive. (See reference...) Figure 11During the readout operation of the second active pixel area 320, the first enable signal EN1 can keep all the reset transistor RX, select transistor SX, and switch transistor SW included in the inactive pixels 331 and 332 of the first inactive pixel area 330 in the off state. In addition, the first wiring transistor CT1 can be turned on by the first control signal CNT1, so a constant voltage can be input to the first connection wiring 305.

[0083] Figure 12 A portion of the pixels included in an image sensor according to some example embodiments is shown, and Figure 13 It shows Figure 12 The operation of the image sensor according to an example embodiment is shown in the figure.

[0084] refer to Figure 12 The pixel array 300A of the image sensor according to the example embodiment may include active pixel areas 310 and 320 and inactive pixel areas 330A and 340A. Figure 12 In the example embodiment shown, inactive pixel areas 330A and 340A can also output reset signals and pixel signals to the readout circuit. To output the reset signals and pixel signals, different signals from inactive pixels 331A, 332A, 341A, and 342A can control the switching transistor SW and the selection transistor SX, respectively. These will be referred to together below. Figure 13 This will be described in more detail.

[0085] Figure 13 The operation of the readout circuitry reading the reset signal RST and pixel signal SIG from the first inactive pixels 331A and 332A included in the first inactive pixel area 330A can be illustrated. Figure 13 In the example embodiment shown, the floating diffusion regions FD of inactive pixels 331A and 332A can be reset by the first inactive reset control signal NRG1, and the readout circuit can read out the reset signal RST during the first time T1. During the first time T1, the selection transistors SX of inactive pixels 331A and 332A can be turned on in response to the first inactive selection signal NSEL1, and the switching transistor SW can be kept off by the first enable signal EN1.

[0086] During the transmission time TT following the first time period T1, the transmission transistors TX of inactive pixels 331A and 332A can be turned on by the first inactive transmission control signal NTG1, and the charge of the photoelectric element PD can be transferred to the floating diffusion region FD. During the transmission time TT, the switching transistor SW and the selection transistor SX of the second inactive pixel area 340A can be turned on to electrically connect column lines COL1 and COL2 to each other. In other words, when pixel data is obtained from the first inactive pixel area 330A, column lines COL1 and COL2 can be connected to each other through the second inactive pixel area 340A. Additionally, when pixel data is obtained from the second inactive pixel area 340A, column lines COL1 and COL2 can be connected to each other through the first inactive pixel area 330A.

[0087] When the transmission time TT has elapsed, the selection transistors SX of inactive pixels 331A and 332A can be turned on during the second time T2, and the readout circuit can obtain the pixel signal SIG from the inactive pixels 331A and 332A. The selection transistors SX of inactive pixels 331A and 332A can be continuously kept in the off state.

[0088] Figure 14 A portion of the pixels included in an image sensor according to some example embodiments is shown, and Figure 15 It shows Figure 14 The operation of the image sensor according to an example embodiment is shown in the figure.

[0089] Reference Figure 14 The pixel array 400 of an image sensor according to some example embodiments may include active pixel areas 410 and 420 and inactive pixel areas 430 and 440. (Refer to...) Figure 9 The example embodiments described are used to understand the setup of active pixel areas 410 and 420 and inactive pixel areas 430 and 440, the circuit configuration and operation of active pixels 411, 412, 421 and 422 and / or the like.

[0090] exist Figure 14 In the example embodiment shown, inactive pixels 431, 432, 441, and 442 can operate simultaneously. As an example, all inactive pixels 431, 432, 441, and 442 can operate simultaneously while performing a readout operation on the first active pixel area 410. Additionally, all inactive pixels 431, 432, 441, and 442 can operate simultaneously while performing a readout operation on the second active pixel area 420.

[0091] Reference Figure 14The reset transistors RX of inactive pixels 431, 432, 441, and 442 can jointly receive the inactivity reset control signal NRG, and the transmission transistors TX of inactive pixels 431, 432, 441, and 442 can jointly receive the inactivity transmission control signal NTG. Additionally, the enable signal EN can be jointly input to the switching transistors SW and selection transistors SX of inactive pixels 431, 432, 441, and 442. These will be referred to together below. Figure 15 To describe the operation of the image sensor.

[0092] Figure 15 The diagram illustrates a readout operation performed on active pixels 411 and 412 included in the first active pixel region 410. (Refer to...) Figure 15 The first reset control signal RG1 turns on the reset transistor RX to reset the voltage of the floating diffusion region FD, and the readout output circuit can read the reset signal RST from active pixels 411 and 412 during the first time T1 when the first selection control signal SEL1 turns on the selection transistor SEL1. During the transmission time TT, the first selection control signal SEL1 turns off the selection transistor SEL1, and the first transmission control signal TG1 turns on the transmission transistor TX, so that the charge of the photoelectric element can be transferred to the floating diffusion region FD. Then, the readout circuit can read the pixel signal SIG during the second time T2.

[0093] Reference Figure 15 The inactive pixels 431, 432, 441, and 442 included in the inactive pixel areas 430 and 440 can operate in the same manner. The transmission transistor TX of the inactive pixels 431, 432, 441, and 442 can be kept in the off state by the inactive transmission control signal NTG. In addition, the inactive reset control signal NRG can be the same signal as the first reset control signal RG1, and the enable signal EN can be complementary to the first selection control signal SEL1. Therefore, the selection transistor SX and the switching transistor SW of the inactive pixels 431, 432, 441, and 442 can operate in the opposite manner to the selection transistor SX of the active pixels 411 and 412.

[0094] When the transfer transistor TX in active pixels 411 and 412 is turned on to transfer charge to the floating diffusion region FD, the select transistor SX and the switching transistor SW in inactive pixels 431, 432, 441, and 442 can be turned on, and column lines COL1 and COL2 can be connected to each other by connection wiring 405 and 407. Therefore, the voltage fluctuations on column lines COL1 and COL2 caused by the on / off operation of the transfer transistor TX can cancel each other out, thus significantly reducing noise characteristics and improving noise performance.

[0095] The wiring control signal CNT for the wiring transistor CT connected to the connection wirings 405 and 407 can be a complementary signal to the enable signal EN. Therefore, when column lines COL1 and COL2 are not connected to each other, the connection wirings 405 and 407 can receive a constant voltage through the wiring transistor CT, and the floating of the connection wirings 405 and 407 can be reduced or prevented.

[0096] Figure 16 A portion of the pixels included in an image sensor according to some example embodiments is shown.

[0097] Reference Figure 16 The pixel array 500 of the image sensor according to some example embodiments may include an active pixel area 510, an inactive pixel area 520, and / or the like. The operation of active pixels 511 to 514 included in the active pixel area 510 will be understood with reference to the above example embodiments.

[0098] exist Figure 16 In the example embodiment shown, at least a portion of the inactive pixels 521 to 524 may include a switching transistor SW connected between column lines COL1 to COL4. The switching transistor SW may be controlled by an enable signal EN, which in turn controls a selection transistor SX for each of the inactive pixels 521 to 524. The switching transistor SW may not be included in at least one of the inactive pixels 521 to 524.

[0099] The operation of inactive pixels 521 to 524 can be similar to the above reference. Figure 7 The operation of the described example embodiment is as follows. During the readout operation where the readout circuit obtains pixel data from active pixels 511 to 514 via column lines COL1 to COL4, the reset transistors RX of inactive pixels 521 to 524 can operate in the same manner as the reset transistors RX of active pixels 511 to 514. The transfer transistors TX of inactive pixels 521 to 524 can remain in the off state.

[0100] In inactive pixels 521 to 524, the selection transistor SX and the switching transistor SW can be controlled by complementary signals of the selection control signal SEL input to active pixels 511 to 514. Therefore, during the time when the readout circuit receives the reset signal and the pixel signal, the selection transistor SX and the switching transistor SW of inactive pixels 521 to 524 can be turned off. On the other hand, during the time when the transfer transistor TX of active pixels 511 to 514 is turned on to transfer charge to the floating diffusion region FD, the selection transistor SX and the switching transistor SW of inactive pixels 521 to 524 can be turned on, and the column lines COL1 to COL4 can be electrically connected to each other. Therefore, voltage fluctuations on column lines COL1 to COL4 can be significantly reduced.

[0101] Figure 17 A portion of the pixels included in an image sensor according to some example embodiments is shown, and Figure 18 It shows Figure 17 The operation of the image sensor according to an example embodiment is shown in the figure.

[0102] Reference Figure 17 In the pixel array 600 of an image sensor according to some example embodiments, two or more adjacent pixels may share a portion of the elements included in the pixel circuitry. Figure 17 In the example embodiment shown, four adjacent pixels can share the reset transistor RX, the drive transistor SF, and the select transistor SX.

[0103] Active pixel groups 611 and 612 may each include four photoelectric elements PD1 to PD4 and four transmission transistors TX1 to TX4. The four transmission transistors TX1 to TX4 of each of the active pixel groups 611 and 612 can share a reset transistor RX, a drive transistor SF, and a select transistor SX through a single floating diffusion region FD. Similarly, inactive pixel groups 621 and 622 may each include four photoelectric elements PD1 to PD4 and four transmission transistors TX1 to TX4. The transmission transistors TX1 to TX4 of each of the inactive pixel groups 621 and 622 can not only share the reset transistor RX, the drive transistor SF, and the select transistor SX, but also share a switching transistor SW.

[0104] The readout circuit can simultaneously acquire pixel data corresponding to the charge generated by the first photoelectric element PD1 of the first active pixel group 611, and pixel data corresponding to the charge generated by the first photoelectric element PD1 of the second active pixel group 612. Figure 17 In the example embodiment shown, the first photoelectric element PD1 to the fourth photoelectric element PD4 can sequentially acquire pixel data, but the order in which the pixel data is acquired is not limited to this.

[0105] Let's refer to each other. Figure 18 While the readout circuit reads the reset signal and pixel signal to obtain pixel data, the reset transistor RX included in the inactive pixel groups 621 and 622 can operate in the same manner as the reset transistor RX included in the active pixel groups 611 and 612. On the other hand, all the transmission transistors TX1 to TX4 included in the inactive pixel groups 621 and 622 can be kept in the off state, and the selection transistor SX included in the inactive pixel groups 621 and 622 can operate in the opposite manner to the selection transistor SX included in the active pixel groups 611 and 612.

[0106] While the select transistor SX is turned off and the charge of the first photoelectric element PD1 is transferred to the floating diffusion region FD in the active pixel groups 611 and 612, the select transistor SX and the switching transistor SW can be turned on in the inactive pixel groups 621 and 622. Therefore, column lines COL1 and COL2 can be electrically connected to each other, and the voltage fluctuations on column lines COL1 and COL2 caused by the on / off operation of the first transistor TX1 in each of the active pixel groups 611 and 612 can be significantly reduced. Similar to the other example embodiments described above, the wiring transistor CT connected to the connection wiring 605 can operate in the opposite direction to the switching transistor SW.

[0107] Figure 19 A portion of the pixels included in an image sensor according to some example embodiments is shown.

[0108] exist Figure 19 In the example embodiment shown, pixel array 700 may include active pixel area 710 and inactive pixel area 720. Active pixels 711 and 712 may each include a dual transistor DT with adjustable conversion gain and a capacitor CC. The dual transistor DT and capacitor CC may be connected to a floating diffusion region FD in each of the active pixels 711 and 712.

[0109] As an example, when high conversion gain is required, the dual transistor DT can be turned off to reduce the capacitance of the floating diffusion region FD. Conversely, when low conversion gain is required, the dual transistor DT can be turned on to increase the capacitance of the floating diffusion region FD. In some example embodiments, the image sensor can determine the ambient illuminance at the time of image capture. When the illuminance is low, the image sensor can increase the conversion gain, and when the illuminance is high, the image sensor can decrease the conversion gain.

[0110] Reference Figure 19 Inactive pixels 721 and 722 may each include a dual transistor DT and a capacitor CC. The dual transistor DTs of inactive pixels 721 and 722 can be controlled in the same manner as the dual transistor DTs of active pixels 711 and 712. For example, when the dual transistor DTs of active pixels 711 and 712 are turned on and the conversion gain decreases, the dual transistor DTs of inactive pixels 721 and 722 can also be turned on. When the dual transistor DTs of active pixels 711 and 712 are turned off and the conversion gain increases, the dual transistor DTs of inactive pixels 721 and 722 can also be turned off.

[0111] Figure 20 It shows the results based on including Figure 19 The operation of some example embodiments of the image sensor, including the pixel array 700 shown. (Refer to...) Figure 20The image sensor's readout circuit can read reset signals RST1 and RST2, as well as pixel signals SIG1 and SIG2, twice from active pixels 711 and 712. In some example embodiments, the first conversion gain of active pixels 711 and 712 while the readout circuit reads the first reset signal RST1 and the first pixel signal SIG1 can be different from the second conversion gain of active pixels 711 and 712 while the readout circuit reads the first reset signal RST1 and the first pixel signal SIG1. As an example, the first conversion gain can be greater than the second conversion gain.

[0112] like Figure 20 As shown, the conversion gain of active pixels 711 and 712 can be adjusted, and the readout circuit can acquire pixel data two or more times to improve the dynamic range of the resulting image generated by the image sensor. For example, the dynamic range of the resulting image can be improved by applying pixel data acquired with low conversion gain to pixels representing bright areas and pixel data acquired with high conversion gain to pixels representing dark areas.

[0113] Reference Figure 20 As described above, the inactive dual control signal NDG of the dual transistor DT controlling inactive pixels 721 and 722 can be the same as the active dual control signal DG input to the transistor DT of active pixels 711 and 712. Furthermore, the enable signal EN of the switching transistor SW and the selection transistor SX controlling each of the inactive pixels 721 and 722 can be complementary to the selection control signal SEL of the selection transistor SW controlling the active pixels 711 and 712.

[0114] Figure 21 and Figure 22 This is a schematic diagram of an image sensor according to some example embodiments.

[0115] refer to Figure 21 According to some example embodiments, the image sensor 800 may include a first layer 810 and a second layer 820. The first layer 810 and the second layer 820 may be stacked in the vertical direction.

[0116] The first layer 810 may include a pixel array 811, and the second layer 820 may include logic circuits 821 and 822. The pixel array 811 can be connected to the logic circuits 821 and 822 via multiple row lines and multiple column lines. (See reference...) Figures 1 to 20As described, the pixel array 811 may include active pixel areas and inactive pixel areas. Active pixels, which output pixel data required to generate the resulting image, can be located in the active pixel areas. Conversely, inactive pixels located in the inactive pixel areas may not output pixel data. Therefore, while performing a readout operation on the pixel array 811, the transmission transistor connected between the floating diffusion region and the photoelectric element in each of the inactive pixels can be kept in an off state.

[0117] Logic circuits 821 and 822 may include a first logic circuit 821 and a second logic circuit 822. The first logic circuit 821 may include row drivers, readout circuits, column drivers, control logic circuits, and / or the like required to drive the pixel array 811. The second logic circuit 822 may include power supply circuits, input / output interfaces, image signal processors, and / or the like. The area, configuration, and / or likes of each of the first logic circuit 821 and the second logic circuit 822 may vary.

[0118] Inactive pixels included in pixel array 811 can be connected to switching transistors that can electrically connect column lines to each other. The switching transistors can be connected to a single node among the nodes of the pixel circuitry included in each of the inactive pixels, or they can be directly connected to the column lines. The switching transistors can be disposed in each of the inactive pixels, or they can be disposed in the first logic circuit 821. When the switching transistors are disposed in the first logic circuit 821, the switching transistors can be included in an analog-to-digital converter connected to the column lines.

[0119] Reference Figure 22 The image sensor 800A may include a first layer 810, a second layer 820, and a third layer 830 disposed between the first layer 810 and the second layer 820. The first layer 810 and the second layer 820 may be similar to those in the reference numeral. Figure 21 The first and second layers of the described example embodiment. The third layer 830 may include a memory element array 831. The memory element array 831 may include, for example, a metal-insulator-metal (MIM) capacitor, a charge trapping element, a magnetic tunnel junction (MTJ) element, a germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) element, or the like. The memory elements may be connected to at least one of the pixels and / or logic circuits 821 and 822 formed in the first layer 810.

[0120] The configurations of the image sensors 800 and 800A are not limited to... Figure 21 and Figure 22 The configuration shown can be modified in various ways. As an example, a portion of logic circuits 821 and 822, such as at least a portion of the first logic circuit 821, can be disposed on the first layer 810 together with the pixel array 811.

[0121] Figure 23 and Figure 24 This is a schematic diagram of an image sensor according to some example embodiments.

[0122] Figure 23 and Figure 24 This may be a schematic cross-sectional view of active pixels 901 and inactive pixels 902 included in image sensors 900 and 900A according to some example embodiments. Active pixels 901 and inactive pixels 902 may be adjacent to each other in a first direction (Y-axis direction). Therefore, it will be understood that column lines extend in the first direction in image sensors 900 and 900A.

[0123] Reference Figure 23 The image sensor 900 may include a substrate 905 comprising a semiconductor material. A photodiode PD may be formed in the substrate 905 as a photoelectric element. According to some example embodiments, the photodiode PD may be replaced with another element that generates charge in response to light.

[0124] Multiple elements 910 electrically connected to the photodiode PD can be formed on one surface of the substrate 905. Elements 910 can provide pixel circuitry and may include, for example, transfer transistors, reset transistors, drive transistors, select transistors, and / or the like. As described above, inactive pixels 902 may also include switching transistors that can electrically connect column lines to each other.

[0125] According to some example embodiments, the switching transistor may be located in the logic circuitry instead of in the inactive pixel 902. However, even when the switching transistor is located in the logic circuitry, it may be connected via metal wiring 921 to at least a portion of the elements 910 included in the inactive pixel 902. As an example, the switching transistor may be connected via metal wiring 921 to the node between the driving transistor and the selection transistor included in the inactive pixel 902.

[0126] Component 910 can be connected to metal wiring 921, and component 910 and metal wiring 921 can be covered by insulating layer 922. Metal wiring 921 and insulating layer 922 can provide a wiring layer 920 not disposed on one surface of substrate 905. Color filter 930 and microlens 940 can be disposed on another surface of substrate 905 opposite to the surface where wiring layer 920 is disposed.

[0127] Reference Figure 24Instead of color filter 930, a blocking layer 950 can be formed on one surface of inactive pixel 902 in image sensor 900A. Unlike color filter 930, which transmits light of a specific wavelength band, blocking layer 950 blocks light. Therefore, light may not strike the photodiode PD included in inactive pixel 902.

[0128] As described above, during the readout operation where the readout circuit obtains pixel data from the active pixel 901, the transfer transistor connected between the photodiode PD in the inactive pixel 902 and the floating diffusion region can be kept in the off state. Therefore, charge can be generated in the photodiode PD due to light incident on the inactive pixel 902. When excessive charge is generated, charge leakage may occur.

[0129] exist Figure 24 In the example embodiment shown, instead of the color filter 930, a blocking layer 950 can be provided on a surface on which light is incident in the inactive pixel 902. The blocking layer 950 can reduce or prevent excessive charge generation in the photodiode PD of the inactive pixel 902, and can reduce or prevent charge leakage. Alternatively, as in Figure 23 As shown in the example embodiment, the charge of the photodiode PD included in the inactive pixel 902 can be reset every predetermined time period or alternatively desired time period without the blocking layer 950.

[0130] Figure 25 This is a schematic block diagram of a mobile system including an image sensor according to some example embodiments.

[0131] Reference Figure 25 The mobile system 1000 may include a camera 1100, a display 1200, an audio processing unit 1300, a modem 1400, DRAMs 1500a and 1500b, flash memory devices 1600a and 1600b, input / output (I / O) devices 1700a and 1700b, and / or an application processor (hereinafter referred to as "AP") 1800.

[0132] The mobile system 1000 can be implemented as a laptop computer, mobile terminal, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, the mobile system 1000 can be implemented as a server or PC.

[0133] Camera 1100 can capture still images or videos under user control. Mobile system 1000 can use the still images / videos captured by camera 1100 to obtain specific information, or can convert and store the still images / videos as other types of data such as text. Alternatively, mobile system 1000 can recognize strings included in the still images / videos captured by camera 1100 and can provide text or audio translations corresponding to those strings. As described above, camera 1100 in mobile system 1000 is intended for use in a variety of application areas. In some example embodiments, camera 1100 can send data such as still images / videos to AP 1800 according to the D-PHY or C-PHY interface in the MIPI standard.

[0134] Camera 1100 may include, according to reference Figures 1 to 24 At least one image sensor in the described example embodiments. For example, the image sensor included in camera 1100 may include: active pixels that output pixel data during readout operations; and inactive pixels that electrically connect or disconnect column lines from each other, at least during a specific period of the readout operation. In some example embodiments, the column lines may be electrically connected to each other during the time it takes for charge to transfer from the active pixels that read pixel data to the floating diffusion region, thereby significantly reducing voltage fluctuations occurring in the column lines and improving the noise characteristics of the image sensor.

[0135] Display 1200 can be implemented in various forms, such as liquid crystal display (LCD), organic light-emitting diode (OLED) display, active-matrix organic light-emitting diode (AMOLED) display, plasma display panel (PDP), field emission display (FED), electronic paper, and / or the like. In some example embodiments, display 1200 may provide touchscreen functionality to also serve as an input device for mobile system 1000. Additionally, display 1200 may be integrated with a fingerprint sensor or the like to provide security features for mobile system 1000. In some example embodiments, AP 1800 may send image data to be displayed on display 1200 via a D-PHY or C-PHY interface according to the MIPI standard.

[0136] The audio processing unit 1300 can process audio data stored in flash memory devices 1600a and 1600b, or audio data included in content received from external sources via modem 1400 or I / O devices 1700a and 1700b. For example, the audio processing unit 1300 can perform various processes on the audio data, such as encoding / decoding, amplification, and noise filtering, or the like.

[0137] The modem 1400 can modulate and transmit signals to send and receive wired / wireless data, and can demodulate signals received from an external source to recover the original signal. I / O devices 1700a and 1700b can provide digital input and output, and may include input devices such as ports capable of connecting to external recording media, touchscreens, or mechanical button keys, and output devices capable of outputting vibrations in a tactile manner. In some examples, I / O devices 1700a and 1700b can connect to external recording media via ports such as USB, Lightning cable, SD card, microSD card, DVD, network adapter, or the like.

[0138] AP 1800 can control the overall operation of mobile system 1000. For example, AP 1800 can control display 1200 to display a portion of the content stored in flash memory devices 1600a and 1600b on the screen. When user input is received through I / O devices 1700a and 1700b, AP 1800 can perform control operations corresponding to the user input.

[0139] The AP 1800 can be provided as a system-on-a-chip (SoC) driving applications, operating systems (OS), or the like. Alternatively, the AP 1800 can be included in a single semiconductor package along with other devices included in the mobile system 1000, such as DRAM 1500a, flash memory 1620, and / or memory controller 1610. For example, the AP 1800 and at least one device can be provided in package form, such as package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), system-in-package (SIP), multi-chip package (MCP), wafer-level assembly package (WFP), or a wafer in a package form such as a multi-processor stack package (WSP). The kernel of the operating system driving the AP 1800 can include device drivers and I / O schedulers for controlling flash memory devices 1600a and 1600b. Device drivers can control the access performance of flash devices 1600a and 1600b by referring to the number of synchronization queues managed by the input / output scheduler, or they can control the CPU mode, dynamic voltage and frequency scaling (DVFS) level and / or similar within the SoC.

[0140] In some example embodiments, the AP 1800 may include: a processor block that performs operations or drives applications and / or an operating system; and various other peripheral components connected via a system block and a system bus. Peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, and / or the like. The processor block may include one or more cores. When multiple cores are included in a processor block, each core includes a cache memory, and a common cache shared by the cores may be included in the processor block.

[0141] In some embodiments, AP 1800 may include an accelerator block 1820, dedicated circuitry for A1 data operations. Alternatively, according to an example embodiment, a separate accelerator chip may be provided to be separate from AP 1800, and DRAM 1500b may be additionally connected to accelerator block 1820 or the accelerator chip. Accelerator block 1820 may be a function block dedicated to performing specific functions of AP 1800, and may include a graphics processing unit (GPU) as a function block dedicated to processing graphics data, a neural processing unit (NPU) as a function block dedicated to performing AI computations and inference, a data processing unit (DPU) as a function block dedicated to transmitting data, or the like.

[0142] According to an example embodiment, the mobile system 1000 may include multiple DRAMs 1500a and 1500b. In some example embodiments, the AP 1800 may include a controller 1810 for controlling the DRAMs 1500a and 1500b, and the DRAM 1500a may be directly connected to the AP 1800.

[0143] The AP 1800 can configure command and mode register setting (MRS) commands according to JEDEC standards to control DRAM, or it can configure the specifications and functions required by the mobile system 1000 (such as low voltage, high speed, and reliability), as well as the DRAM interface protocol for CRC / ECC execution communication. For example, the AP 1800 can configure a new DRAM interface protocol to control DRAM 1500b for accelerators, in which accelerator block 1820 or accelerator chip provided by the AP 1800 has a higher bandwidth than DRAM 1500a for communication.

[0144] exist Figure 25Only DRAMs 1500a and 1500b are shown, but the configuration of the mobile system 1000 is not limited to these. Depending on the bandwidth and response speed of the AP 1800 and accelerator block 1820, as well as voltage conditions, the mobile system 1000 may include memories other than DRAMs 1500a and 1500b. As an example, the controller 1810 and / or the accelerator block 1820 can control various types of memory, such as PRAM, SRAM, MRAM, RRAM, FRAM, hybrid RAM, and / or the like. Compared to input / output devices 1700a and 1700b or flash memory devices 1600a and 1600b, DRAMs 1500a and 1500b have relatively lower latency and higher bandwidth. DRAMs 1500a and 1500b can be initialized at the power-on time of the mobile system 1000. When loading operating system and application data, DRAM 1500a and 1500b can be used as a temporary storage location for operating system and application data, or as space for executing various software code.

[0145] Four basic arithmetic operations (e.g., addition, subtraction, multiplication, and division), as well as vector operations, address operations, or FFT operations, can be stored in DRAMs 1500a and 1500b. In another example embodiment, DRAMs 1500a and 1500b can be provided as processing within a Processing Memory (PIM) with operational functions. For example, functions for performing inference in DRAMs 1500a and 1500b can be executed. For example, inference can be performed using an artificial neural network with a deep learning algorithm. The deep learning algorithm can include a training step and an inference step, in which a model is learned from various data, and in the inference step, the trained model is used to identify data. For example, functions used in inference can include hyperbolic tangent functions, sigmoid functions, rectified linear unit (ReLU) functions, and the like.

[0146] As an example embodiment, an image captured by a user through camera 1100 can be processed and stored in DRAM 1500b, and accelerator block 1820 or accelerator chip can use the data stored in DRAM 1500b to perform AI data operations and functions for identifying data in inference.

[0147] According to some example embodiments, the mobile system 1000 may include multiple storage devices or multiple flash memory devices 1600a and 1600b with a capacity higher than that of DRAMs 1500a and 1500b. Flash memory devices 1600a and 1600b may include a controller 1610 and flash memory 1620. The controller 1610 may receive control commands and data from the AP 1800, and may write data to the flash memory 1620 in response to control commands, or may read data stored in the flash memory 1620 and send the read data to the AP 1800.

[0148] According to some example embodiments, accelerator block 1820 or accelerator chip can use flash memory devices 1600a and 1600b to perform training steps and AI data computations. As an example embodiment, operational logic capable of performing predetermined or alternatively desired operations in flash memory devices 1600a and 1600b can be implemented in controller 1610. Instead of AP 1800 and / or accelerator block 1820, the operational logic can use data stored in flash memory 1620 to perform at least a portion of the training steps and inferences performed by AP 1800 and / or accelerator block 1820.

[0149] In some example embodiments, AP 1800 may include interface 1830. Therefore, flash memory devices 1600a and 1600b can be directly connected to AP 1800. For example, AP 1800 can be implemented as a SoC, flash memory device 1600a can be implemented as a chip independent of AP 1800, and AP 1800 and flash memory device 1600a can be mounted in a single package. However, the example embodiments are not limited to this, and multiple flash memory devices 1600a and 1600b can be electrically connected to mobile system 1000 via interconnection.

[0150] Flash memory devices 1600a and 1600b can store data captured by camera 1100 (e.g., still images / videos) or data received via a communication network and / or ports included in input and output devices 1700a and 1700b. For example, flash memory devices 1600a and 1600b can store augmented reality / virtual reality, high-definition (HD), or ultra-high-definition (UHD) content.

[0151] Any element disclosed above may include or be implemented in processing circuitry (including hardware, including logic circuitry); a hardware / software combination (a processor executing software); or a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), or the like.

[0152] As described above, according to the example embodiment, the pixel array may include active and inactive pixels, and a switching transistor can be controlled to connect the pixel circuits of inactive pixels to each other to electrically connect or disconnect column lines. The switching transistor may be turned on for a predetermined time or alternatively desired time to electrically connect the column lines to each other. As a result, fluctuations in the output voltage of pixels output through the column lines can be significantly reduced, and the noise characteristics of the image sensor can be improved.

[0153] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An image sensor, comprising: The substrate includes active pixel regions and inactive pixel regions, wherein the inactive pixel regions have a smaller area than the active pixel regions; Multiple active pixels, each of the multiple active pixels in the active pixel area includes a first transmission transistor, a first reset transistor, a first drive transistor, and a first selection transistor; A plurality of inactive pixels, each of the plurality of inactive pixels in the inactive pixel area including a second transmission transistor, a second reset transistor, a second drive transistor, a second selection transistor and a switching transistor connected to a node between the second drive transistor and the second selection transistor, wherein each of the plurality of switching transistors included in the plurality of inactive pixels is connected to each other by connection wiring. Multiple row lines, extending in a first direction and connected to the multiple active pixels or the multiple inactive pixels; and Multiple column lines extend in a second direction intersecting the first direction and connect to the multiple active pixels and the multiple inactive pixels. Wherein, at least one of the plurality of inactive pixels and a portion of the plurality of active pixels are located at the same position in the first direction and are jointly connected to one of the plurality of column lines. The switching transistor is turned on during the transmission time between the first time and the second time, wherein the logic circuit receives a reset signal during the first time and receives a pixel signal during the second time.

2. The image sensor according to claim 1, wherein, The active pixel area and the inactive pixel area have the same width in the first direction.

3. The image sensor according to claim 1, wherein, Each of the plurality of active pixels includes a first photoelectric element, and each of the plurality of inactive pixels includes a second photoelectric element. The light-receiving area of ​​each of the plurality of first optoelectronic elements is the same as the light-receiving area of ​​each of the plurality of second optoelectronic elements.

4. The image sensor according to claim 3, wherein, Each of the plurality of inactive pixels includes a blocking layer that blocks each of the plurality of second photoelectric elements from receiving light.

5. The image sensor according to claim 1, wherein, The inactive pixel area includes multiple inactive pixel areas, and the active pixel area is located between the multiple inactive pixel areas.

6. The image sensor according to claim 5, wherein, In each of the plurality of inactive pixel regions, the plurality of inactive pixels are adjacent to at least one of the plurality of active pixels in the first direction and in the second direction intersecting the first direction.

7. The image sensor according to claim 6, wherein, The plurality of inactive pixels are not adjacent to the plurality of inactive pixels in other inactive pixel areas.

8. The image sensor according to claim 1, wherein, The ratio of the area of ​​the active pixel region to the area of ​​the inactive pixel region is from 100:1 to 5000:

1.

9. The image sensor according to claim 1, wherein, In each of the plurality of inactive pixels, the gate of the corresponding switching transistor is connected to the gate of the corresponding second selection transistor.

10. An image sensor, comprising: A plurality of active pixels, in a first direction and a second direction intersecting the first direction, each of the plurality of active pixels includes a first selection transistor connected to one of a plurality of column lines extending in the second direction; A plurality of inactive pixels, each of which, in the first direction, includes a second selection transistor connected to one of the plurality of column lines; A plurality of switching transistors, each of the plurality of switching transistors being connected to a corresponding second selection transistor included in each of the plurality of inactive pixels and a connection wiring extending in the first direction; as well as A logic circuit is configured to: obtain pixel data output by the plurality of active pixels, and during a transmission time between a first time and a second time, turn on a plurality of second selection transistors and the plurality of switching transistors, wherein the logic circuit obtains a reset signal during the first time and obtains a pixel signal during the second time.

11. The image sensor according to claim 10, wherein, Each of the plurality of active pixels includes a first photoelectric element, a first transmission transistor, a first reset transistor, and a first driving transistor, and Each of the plurality of inactive pixels includes a second photoelectric element, a second transmission transistor, a second reset transistor, and a second drive transistor.

12. The image sensor according to claim 11, wherein, The logic circuit is configured to receive a reset signal during the first time period and to receive a pixel signal from a selected pixel among the plurality of active pixels during a second time period after the first time period. The logic circuit is configured to turn on a first transmission transistor included in the selected pixel during the transmission time between the first time and the second time, and is configured to turn off a first selection transistor included in the selected pixel during the transmission time.

13. The image sensor according to claim 12, wherein, The on-time of the first transmission transistor is shorter than the on-time of the second selection transistor and the on-time of the switching transistor.

14. The image sensor according to claim 13, wherein, The logic circuit is configured to turn off the second transmission transistor during the transmission time.

15. The image sensor according to claim 12, wherein, Each of the plurality of switching transistors is connected to a node between the corresponding second driving transistor and the corresponding second selection transistor.

16. The image sensor according to claim 11, wherein, The number of active pixels is N times the number of inactive pixels, where N is a positive integer.

17. An image sensor, comprising: Multiple pixels are connected to multiple row lines extending in a first direction and multiple column lines extending in a second direction intersecting the first direction; as well as Logic circuitry is configured to obtain pixel data from the plurality of pixels. Each of the plurality of pixels includes a photoelectric element, a floating diffusion region storing the charge generated by the photoelectric element, a transfer transistor between the floating diffusion region and the photoelectric element, a driving transistor connected to the floating diffusion region, and a selection transistor connected between one of the column lines and the driving transistor. The logic circuit is configured to obtain a reset signal from a selected pixel among the plurality of pixels during a first time period, to obtain a pixel signal from the selected pixel during a second time period after the first time period, and to electrically connect the plurality of column lines to each other and turn on the transmission transistor of each of the selected pixels during a transmission time between the first time period and the second time period. The plurality of pixels includes a plurality of active pixels and a plurality of inactive pixels. Each of the plurality of inactive pixels further includes a switching transistor connected to a node between the driving transistor and the selection transistor. Each of the plurality of switching transistors included in the plurality of inactive pixels is connected to each other via interconnect wiring. The logic circuit is configured to turn on the transmission transistor of each of the plurality of inactive pixels during the transmission time to electrically connect the plurality of column lines to each other through the connection wiring.

18. The image sensor according to claim 17, wherein, The logic circuit is configured to electrically separate the plurality of column lines from each other during the first time and the second time.

19. The image sensor according to claim 17, wherein, The logic circuit is configured to keep the transmission transistor of each of the inactive pixels in an off state, while being configured to obtain the reset signal and the pixel signal from each of the active pixels.

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