Detect changes to the storage key used to protect the memory

Abstract

Detection of a storage key change for protecting a memory includes determining whether a storage key change event has occurred within a processor of a computing environment. The determining includes checking whether one or more selected fields of the storage key have been updated. The storage key is associated with a memory block and controls access to the memory block. Based on the checking indicating that one or more selected fields of the storage key have been updated, a storage key change event has been detected. Based on determining that the storage key change event has occurred, a notification is provided.

Description

BACKGROUND OF THE INVENTION

[0001] In general, one or more aspects relate to facilitating processing within a computing environment, and more particularly to facilitating processing associated with securing access to memory.

[0002] In a hardware architecture provided by International Business Machines Corporation of Armonk, New York a storage key is used to control access to memory. For example, each memory block has a storage key associated therewith for controlling access to that memory block. The storage key includes a plurality of fields that can be set or changed by various instructions executed by a program. Certain fields are set or changed by instructions executed by a privileged program such as an operating system or other privileged program.

[0003] By convention, only certain programs are expected to change the storage key. When other programs change the storage key, adverse consequences may result. In addition, if the program issuing the storage key change instruction has a programming error, the storage key may be incorrectly changed and corrupted. SUMMARY OF THE INVENTION

[0004] By providing the method as recited in claim 1, as well as corresponding systems and computer programs, the disadvantages of the prior art are overcome and additional advantages are provided.

[0005] By detecting a change in the storage key, a program can determine whether the storage key has been corrupted and take actions to, for example, identify an incorrect program that changed the storage key and / or a program that incorrectly changed the storage key. Both security and performance within the processor are improved.

[0006] As an example, providing the notification includes providing a notification of the storage key change event via an interrupt based on determining that the storage key change event has occurred.

[0007] In one example, the checking includes checking whether one or more selected fields of the storage key have been updated without an access exception. Based on the checking indicating that one or more selected fields of the storage key have been updated and there is no access exception, a storage key change event has occurred.

[0008] In one example, determining whether a storage key change event has occurred also includes determining whether a memory block is within a specified storage area. Based on the checking indicating that one or more selected fields of the storage key have been updated and the memory block is within the specified storage area, a storage key change event has occurred.

[0009] Further, in one example, the check includes checking whether one or more selected fields of the stored key have been updated without an access exception, and the stored key change event is based on the check indicating that one or more selected fields of the stored key have been updated and there is no access exception, and the memory block is located within a specified storage area.

[0010] As an example, the specified storage area is defined by a starting address of the memory specified in a first location and an ending address of the memory specified in a second location. For example, the first location is a selected control register, and the second location is another selected control register.

[0011] In one example, the ending address wraps around to the starting address, and a selected number of low-order bits for the starting address and for the ending address are used in the definition of the specified storage area to include more than one memory block.

[0012] Further, in one example, determining whether a memory block is located within a specified storage area includes determining whether one or more memory cells of the memory block are located within the specified storage area.

[0013] As an example, one or more selected fields include an access control field of the stored key and / or an acquisition protection field of the stored key.

[0014] Computer-implemented methods and systems related to one or more aspects are also described and claimed herein. In addition, services related to one or more aspects are described and may be claimed herein.

[0015] Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered to be part of the claimed aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more aspects are particularly pointed out and distinctly claimed in the claims. The foregoing objects, features, and advantages of one or more aspects are apparent from the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0017] Figure 1A An example of a computing environment incorporating and using one or more aspects of the present invention is depicted;

[0018] Figure 1B Depicts further details of a Figure 1A processor in accordance with one or more aspects of the present invention;

[0019] Figure 2 Another example of a computing environment incorporating and using one or more aspects of the present invention is depicted;

[0020] Figure 3 Depicts an example of storing a key according to one aspect of the present invention;

[0021] Figure 4 Depicts further details of a stored key change detection component used according to one aspect of the present invention;

[0022] Figure 5 Depicts an example of a process associated with detecting an update to a stored key according to one aspect of the present invention;

[0023] Figures 6A - 6B Depicts an example of facilitating processing within a computing environment according to one aspect of the present invention;

[0024] Figure 7A Depicts another example of a computing environment that incorporates and uses one or more aspects of the present invention;

[0025] Figure 7B Depicts Figure 7A further details of the memory of;

[0026] Figure 8 Depicts an embodiment of a cloud computing environment; and

[0027] Figure 9 Depicts an example of an abstract model layer. DETAILED DESCRIPTION

[0028] According to one aspect of the present invention, a capability is provided to facilitate processing within a computing environment. For example, a capability is provided to detect that a stored key for protecting a memory block of the computing environment has been changed. For example, the functionality includes a program event record (PER) event interrupt indicating that the stored key has been changed. By detecting a change in the stored key, a program can determine whether the stored key has been corrupted and perform actions to, for example, identify an incorrect program that changed the stored key and / or a program that incorrectly changed the stored key. As an example, a memory block (also referred to herein as storage) is a memory page, e.g., a 4K-byte memory. In other examples, a memory block may not be a memory page and / or a memory page may not be 4K bytes. Many variations are possible.

[0029] An embodiment of a computing environment that incorporates and uses one or more aspects of the present invention is described with reference to Figure 1A . The computing environment 100 includes, for example, a processor 102 (e.g., a central processing unit), a memory 104 (e.g., a main memory; also referred to as a system memory, main memory, central memory, memory), and one or more input / output (I / O) devices and / or interfaces 106, coupled to each other via, for example, one or more buses 108 and / or other connections.

[0030] In one example, the processor 102 is based on the hardware architecture of z / Architecture and is part of a server, such as an IBM server, provided by International Business Machines Corporation and implementing the z / Architecture hardware architecture. An embodiment of the z / Architecture hardware architecture is described in the IBM publication numbered SA22-7832-11, 12th Edition, September 2017, titled "Principles of Operation of z / Architecture". However, the z / Architecture hardware architecture is just an example architecture; other architectures and / or other types of computing environments may include and / or use one or more aspects of the present invention. In one example, the processor executes an operating system, such as an operating system.

[0031] The processor 102 includes a plurality of functional components for executing instructions. As Figure 1B shown. These functional components include, for example: a fetch component 120 for fetching the instructions to be executed; an instruction decoding unit 122 for decoding the fetched instructions to obtain the operands of the decoded instructions; an instruction execution component 124 for executing the decoded instructions; a memory access component 126, if needed, for accessing the memory for instruction execution; and a write-back component 130 for providing the results of the executed instructions. According to one or more aspects of the present invention, one or more of these components may include at least a part of or have access to one or more other components for storing key change detection (or other processing using one or more aspects of the present invention), as described herein. One or more other components include, for example, a stored key change detection component (or other component) 136.

[0032] In one example, the memory access component 126 uses one or more stored keys 128 to determine whether an instruction requesting access to one or more memory blocks is authorized for the requested type of access. In one example, the stored keys are associated, for example, with each memory block available in the configuration (e.g., each 4K byte block).

[0033] Another example of a computing environment that incorporates and uses one or more aspects of the present invention is referenced Figure 2 for description. In one example, the computing environment is based on the z / Architecture hardware architecture; however, the computing environment may be based on other architectures provided by International Business Machines Corporation or other companies.

[0034] Refer to Figure 2, in one example, the computing environment includes a Central Electronics Complex (CEC) 200. The CEC 200 includes multiple components. For example, a memory 202 (also known as system memory, main memory, primary storage, central storage, storage) is coupled to one or more processors (also referred to as Central Processing Units (CPUs)) 204 and an input / output subsystem 206.

[0035] The memory 202 includes, for example, one or more logical partitions 208, a hypervisor 210 that manages the logical partitions, processor firmware 212, and an associated storage key 214 (described herein). An example of the hypervisor 210 is the Processor Resource / System Manager (PR / SM TM ) hypervisor, provided by International Business Machines Corporation of Armonk, New York. As used herein, firmware includes, for example, the microcode of the processor. For example, it includes hardware-level instructions and / or data structures for implementing high-level machine code. In one embodiment, it includes, for example, proprietary code that is typically delivered as microcode, which includes trusted software or microcode specific to the underlying hardware and controls the operating system's access to the system hardware.

[0036] Each logical partition 208 is capable of being used as a separate system. That is, each logical partition can be independently reset, run a guest operating system 220 such as the z / OS operating system or another operating system, and operate with different programs 222. The operating system or application running in the logical partition may appear to have access to the entire and complete system, but in fact only a portion of it is available.

[0037] The memory 202 is coupled to a processor (e.g., a CPU) 204, which is a physical processor resource that can be allocated to a logical partition. For example, the logical partition 208 includes one or more logical processors, and each logical processor represents all or a portion of the physical processor resource 204 that can be dynamically allocated to the logical partition.

[0038] In addition, the memory 202 is coupled to the I / O subsystem 206. The I / O subsystem 206 can be part of or separate from the Central Electronics Complex, and it guides the flow of information between the main memory 202, the input / output control unit 230, and the input / output (I / O) devices 240 coupled to the Central Electronics Complex.

[0039] Multiple types of I / O devices can be used. One particular type is the data storage device 250. The data storage device 250 can store one or more programs 252, one or more computer-readable program instructions 254, and / or data, etc. The computer-readable program instructions can be configured to perform the functions of the embodiments of various aspects of the present invention.

[0040] As an example, each processor 204 includes and / or has access to a storage key change detection component (or other component) 260 that is operative to detect changes to the storage key (and / or other operations of one or more aspects of the present invention). In various examples, there may be one or more components that perform these functions. Many variations are possible.

[0041] The central electronic complex 200 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. By way of example, it may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as a “hard disk drive”), a disk drive for reading from and writing to removable, non-volatile disks (e.g., a “floppy disk”), and / or an optical disk drive for reading from or writing to removable, non-volatile optical disks (e.g., a CD-ROM, a DVD-ROM, or other optical media). It should be understood that other hardware and / or software components may be used in conjunction with the central electronic complex 200. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, among others.

[0042] In addition, the central electronic complex 200 may operate in conjunction with many other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for the central electronic complex 200 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, fat clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, among others.

[0043] Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with a variety of types of environments. The computing environments provided herein are only examples.

[0044] As noted above, the storage key is used to control access to memory blocks. In one example, with reference to Figure 3 , the storage key 300 includes the following fields:

[0045] Access Control (ACC) 302: Four access control bits, bits 0-3, that match a four-bit access key in, for example, a program status word (PSW) if the reference is protected by key control when storing information and when retrieving information from a protected location.

[0046] Fetch - Protect (F) 304: If the reference is protected by key control, obtain the protection bit to control whether key control protection applies to the fetch type reference: 0 means only monitor the store type reference and allow any access key to be used for fetching; 1 means key control protection applies to both fetching and storing. There is no difference between fetching an instruction and fetching an operand.

[0047] Reference (R) 306: The reference bit is typically set to 1 each time the location in the corresponding storage block is referenced for storing or fetching information.

[0048] Change (C) 308: The change bit is set to 1 each time information is stored at a location in the corresponding storage block.

[0049] In one embodiment, although the reference and change fields are part of the storage key, if they are changed, e.g., implicitly changed by a fetch or store operation, no PER storage key change event is detected.

[0050] To facilitate the detection of incorrect program - altered storage keys and / or corrupted storage keys, according to one aspect of the present invention, a capability to detect storage key changes is provided. This functionality includes, for example, using a storage key change detection component (e.g., storage key change detection component 136 or storage key change detection component 260). For more details associated with the storage key change detection component, reference is made according to one aspect of the present invention Figure 4 is described.

[0051] As Figure 4 shown, in one example, the processor 400 (e.g., processor 102 or processor 204) includes a storage key change detection component 402 (e.g., storage key change detection component 136 or storage key change detection component 260) that includes or has access to a program event recording component (PER) 404. The program event recording component 404 is used to detect certain events, such as, according to one aspect of the present invention, changes in the storage key, and provide notifications of such events, allowing actions to be taken based thereon. Such actions include, for example, determining whether the storage key change is corrupted and, if so, identifying the incorrect program and / or the program that has incorrectly changed the storage key that changed the storage key. Based on this, the program and / or instructions that caused the storage key corruption can be corrected. Additionally, in one example, the program can perform (e.g., automatically) one or more tasks based on receiving the notification, such as providing an alert, blocking the execution of a part of the program, etc.

[0052] The program event recording component 404 has a plurality of registers 410 associated therewith, including, for example:

[0053] Control register 9 (420), including, for example, the following fields:

[0054] Per-Event Masks (EM) 422: Used to specify which types of events to identify.

[0055] Branch Address Control (B) 424: Used to indicate when a successful branch event occurs.

[0056] Event Suppression Control (ES) 426: Used to indicate the suppression of notifications for selected events.

[0057] Storage Change Space Control (S) 428: Used to indicate storage change events within a specified address space.

[0058] Control Register 10 (430) includes the starting address of the specified storage area.

[0059] Control Register 11 (440) includes the ending address of the specified storage area.

[0060] Each control register is described in further detail below with reference to the description of Program Event Records (PER), as defined for one embodiment of the z / Architecture hardware architecture.

[0061] In the description herein, specific locations, specific fields, and / or fields of a specific size (e.g., specific bytes and / or bits) of registers, other locations, and / or instructions may be indicated. However, other locations, fields, and / or sizes may be provided. Additionally, while it may be specified that a bit is set to a particular value, such as 1 or 0, this is merely an example. In other examples, the bit may be set to a different value, such as the opposite value or another value. Many variations are possible.

[0062] Continue Figure 4 , as an example, the processor 400 is coupled to a memory 450 (e.g., memory 104 or memory 202), which includes data used by the PER. For example, the memory 450 includes Program Status Word (PSW) data 452 and actual memory locations 150 - 151 (454), as well as other actual locations and / or data not shown.

[0063] In one example, storage location 454 includes, for example: a PER code 456 for indicating the occurrence of a PER event; an Addressing and Translation Mode Identification (ATMID) field 458 for indicating the cause of the PER event; and a PER ASCE Identification (AI) field 460 for identifying, in a particular instance, an Address Space Control Element (ASCE) for translating the reference for the event-causing event. Storage location 454 may include additional, fewer, and / or other fields. Additionally, the use of particular fields may depend on the type of event being detected. For example, in one embodiment, the AI field 460 is not used for detecting a storage key change event, but is used for other types of events. Other variations are possible. Each field is described in more detail below.

[0064] In one example, a storage key change detection component (e.g., component 402) uses PER to detect a storage key change event and provide a notification of the event to the program. Refer to Figure 5 Further details regarding detecting a storage key change event are described. In one example, the processing is performed by a processor (e.g., processor 102, 204, or 400). As a particular example, the processing is performed by the hardware and / or firmware of the processor.

[0065] Refer to Figure 5 , in one example, to detect a storage key change event and potentially detect a corrupted storage key, the processor determines whether a selected field of the storage key (e.g., storage key 300) has been updated, query 500. As an example, the storage key may be updated via one or more instructions of an Instruction Set Architecture (ISA), including, for example, the Set Storage Key Extended instruction, the Perform Frame Management Function instruction, the Test Block instruction, and the Move Page instruction, each of which is part of the z / Architecture hardware architecture. These instructions are merely examples; other instructions may be used to update the storage key.

[0066] In one example, when one or more of these instructions updates one or more selected fields of the storage key, the program (executing one or more of these instructions) indicates, via PER, an event to be identified, e.g., a storage key change event according to one aspect of the present invention.

[0067] As an example, the selected fields are the access control field (e.g., access control 302) and the acquire protection field (e.g., acquire protection 304). The update can include updating the selected fields to the same value or a different value. In this example, updating the reference field (e.g., reference 306) and the change field (e.g., change 308) without updating one or more of the access control field and the acquire protection field does not result in a storage key change event.

[0068] If the selected fields (e.g., access control and / or acquire protection) are updated, then in one embodiment, it is further determined whether there is an access exception, query 502. If the selected fields have been updated without an access exception, then in one embodiment, it is further queried whether the memory block associated with the storage key (e.g., 4K byte block) is within a specified region of the memory (e.g., defined by a start address 432 and an end address 442), query 504. In another embodiment, the checking of the specified memory region and / or the access exception is optional.

[0069] If the selected fields are updated without an access exception and the associated memory block is within the specified region, then a storage key change event has been detected, step 506. In one example, it is the PER tool executed within the processor that makes the determination and detects the storage key change event. Based on the detected storage key change event, a program interrupt is provided, step 508. In one example, the program interrupt has a program interrupt code of 0x80. Additionally, in one embodiment, additional information is provided at a fixed location in storage, for example, to identify the cause and provide more information to the program, as described below, step 510.

[0070] Return to query 500. If the selected fields are not updated, or if an access exception has occurred, query 502, or if the memory block is not within the specified region, then in one example, a storage key change event is not detected.

[0071] As described herein, in one example, a program event recording (PER) tool using the z / Architecture hardware architecture is used to perform the detection of the storage key change event. The PER provides a mechanism to detect and alert the program of selected events, such as, according to one aspect of the present invention, the storage key change event. More details of the program event recording tool are described below. For completeness, aspects of tools that are not required except for one or more aspects for detecting the storage key change event and providing its notification are described according to one aspect of the present invention. Additionally, although the PER is used in the embodiments described herein to detect and provide notification of the storage key change event, in other embodiments, other tools and / or mechanisms can be used to detect and provide notification of the storage key change event.

[0072] Program Event Record (PER)

[0073] In one embodiment, the PER is used to assist in debugging a program. For example, it allows the program to receive event alerts of the following types.

[0074] · Execution of a successful branch instruction. The option to provide an event occurrence is available only when the branch target location is within a specified storage area. The specified storage area is further described herein.

[0075] · Fetching an instruction from a specified storage area.

[0076] · Changing the content of a specified storage area. The option to provide an event that occurs only when the storage area is within a specified address space is available.

[0077] · Performing a store using an actual address instruction.

[0078] · Execution of a transaction end instruction.

[0079] · Executing an instruction that accesses a store using an operand address formed by a general register containing zero, based on, for example, a PER zero-address detection tool being installed.

[0080] · Executing a set storage key extension instruction, a frame management function instruction, a move page instruction, or a test block instruction that updates the storage key of a specified storage area, based on, for example, a PER storage key change tool being installed according to an aspect of the present invention.

[0081] The program can selectively specify to identify one or more of the above types of events. Information about PER events is provided to the program through, for example, a program interrupt (or other mechanism), and the cause of the interrupt is identified in the interrupt code.

[0082] PER Instruction-Fetching Invalid

[0083] As an example, the PER-3 tool may be available on a model implementing the z / Architecture hardware architecture. After installing this function, bit 39 of control register 9 specifies that the PER instruction fetch event is forced invalid when it is 1. When bit 33 (instruction fetch PER event mask bit) of control register 9 is also 1, bit 39 is effective for this. When bit 33 is 0, the PER instruction fetch event cannot be recognized, and bit 39 is invalid. When the PER-3 tool is not installed or bit 39 is 0, the PER instruction fetch event is not forced invalid. The forced invalid PER instruction fetch event is called a PER instruction fetch invalid event. The PER event that is not forced invalid is called a PER basic event.

[0084] When the PER-3 tool is installed and bit 39 is 1, the interrupt caused by the PER instruction fetch event occurs before the instruction fetch execution, indicating a PER instruction fetch invalid event, no other PER events, no other program interrupt conditions reported, and the instruction execution is invalid. When the PER-3 tool is not installed or bit 39 is 0, it is not forced to be invalid, indicating a PER instruction fetch basic event, other PER events, and other program interrupt conditions may be reported concurrently, and the instruction execution can be completed, terminated, cancelled, or aborted. In the absence of other conditions, the interrupt caused by the PER instruction fetch basic event occurs after the instruction fetch or its operation unit has finished execution.

[0085] Control register allocation and address space control unit

[0086] Information for controlling PER, for example, resides in control registers 9, 10, and 11 and the address space control unit.

[0087] Depending on the model, when any or all of control registers 9, 10, or 11 contain non-zero values, the address comparison control can be disabled and remains disabled even if control registers 9 to 11 are converted back to zero.

[0088] The information format in the control registers is as follows in one example, refer to Figure 4 .

[0089] Control register 9 (420) includes, for example:

[0090] PER Event Mask (EM) 422: Bits 32 - 39 specify which types of events to identify. Bits 32 - 34 and 36 are available and control successful branch events, instruction fetch basic events, and store change events. According to one aspect of the present invention, when the PER store key change tool is installed, bit 35 of the PER event mask is also used. When the PER zero address detection tool is installed, bit 37 of the PER event mask is used. When the PER-3 tool is installed, bit 39 of the PER event mask is used. In ESA / 390 compatible mode, whether storage key change, zero address detection, instruction fetch invalid mask (bits 35, 37, and 39 respectively) are supported is unpredictable. In one example, these bit assignments are as follows:

[0091] Bit 32: Successful branch event

[0092] Bit 33: Instruction fetch event

[0093] Bit 34: Store change event

[0094] Bit 35: Store key change event

[0095] 36th bit: Store usage actual address event (the 34th bit should also be 1)

[0096] 37th bit: Zero address detection event

[0097] 38th bit: Transaction end event

[0098] 39th bit: Instruction fetch invalid event (the 33rd bit is 1)

[0099] Bits 32 - 34 and 36, when 1, specify that the corresponding type of event is recognized. However, when the 34th bit is also 1, the 36th bit is valid for this. When the 34th bit is 1, store change events are recognized. When the 34th and 36th bits are 1, both store change events and store usage actual address events are recognized. When a bit is 0, the corresponding event type is not recognized. When the 34th bit is 0, store change events and store usage actual address events cannot be recognized.

[0100] When the PER-3 tool is not installed, the 39th bit is ignored. When the 3rd bit is also 1, the 39th bit is valid. When the 33rd bit is 1, the PER-3 tool is installed, and the 39th bit is 1, the PER instruction fetch invalid event is recognized. When the 33rd bit is 1 and the 39th bit is 0 (or the PER-3 tool is not installed), the PER instruction fetch basic event is recognized. When the 33rd bit is 0, neither the PER instruction fetch basic event nor the PER instruction fetch invalid event is recognized.

[0101] When the transaction execution tool is not installed, or when the tool is installed and bit 38 is 0, the transaction end event is not recognized. When the transaction execution tool is installed and the 38th bit is 1, the transaction end event is recognized as the result of the completion of the outermost transaction end instruction. In ESA / 390 compatibility mode, the 38th bit of control register 9 is ignored.

[0102] When the PER storage key change tool is not installed, the 35th bit is ignored. When the 35th bit is 1 and the PER storage key change tool is installed, according to one aspect of the present invention, for example, when any of the following instructions is executed and updates the ACC or F bit of the storage key associated with a 4K-byte storage block located within the specified area:

[0103] When the move page and set key tool is installed and the key function control (KFC) (bits 51 - 53 of general register 0) contains the value 4 or 5, move page

[0104] Execute the frame management function when SK (bit 46 of general register R1) is 1

[0105] Set storage key extension

[0106] Test block when the implementation of the model updates the storage key.

[0107] In addition to the PER-Event Mask 422, Control Register 9 includes various controls described below. Additional, fewer, and / or other controls may be used.

[0108] Branch Address Control (B) 424: Specified when bit 40 of Control Register 9 is 1, a successful branch event occurs only for branches that reach a location within the specified storage area. When bit 40 is zero, a successful branch event occurs regardless of the branch target address.

[0109] Event Suppression Control (ES) 426: Specified when bit 41 of Control Register 9 is 1 when the CPU is in transaction execution mode at the start of an instruction, the PER event masks in bits 32 - 34, 36, 37, and 39 will be ignored and assumed to contain 0. Except as noted below, when the CPU is not in transaction execution mode at the start of an instruction, or when bit 41 of the register is 0, all PER event masks operate as defined.

[0110] When (a) the outermost transaction start instruction is executed, (b) there are no concurrent program exception conditions, and (c) the ES control is 1, any PER store change or zero address detection event and any instruction fetch basic event for the transaction diagnostic block (TDB) specified for TBEGIN are suppressed; in this case, the instruction fetch invalid event is not suppressed. In ESA / 390 compatibility mode, the event suppression control is ignored.

[0111] Store Change Space Control (S) 428: Specified when bit 42 of Control Register 9 is 1, a store change event occurs as a result of a reference to a specified storage area within a specified address space only. The address space is specified as the address space in which store change events occur via the store change event bit in the address space control unit, which is used to translate references to the address space. When DAT (Dynamic Address Translation) is invalid, bit 42 will be ignored. When DAT is invalid or bit 42 is 0, store change events are not limited to occurring only for a specific address space.

[0112] Control Register 10 (430) includes, for example:

[0113] PER Starting Address 432: Bits 0 - 63 of Control Register 10 are the starting address of the specified storage area. In ESA / 390 compatibility mode, it is unpredictable whether bit 32 of the PER starting address is considered 0.

[0114] Control Register 11 (440) includes, for example:

[0115] PER End Address 442: Bits 0 - 63 of Control Register 11 are the end address of the specified storage area. In ESA / 390 compatibility mode, it is unpredictable whether bit 32 of the PER start address is considered 0.

[0116] Address Space Control Element (ASCE):

[0117] When the Storage Change Space Control in Control Register 9 is 1 and bit 56 of the Address Space Control Element is 1, it specifies that the address space defined by the Address Space Control Element is the address space for which storage change events can occur. When the Address Space Control Element is used for dynamic address translation of a store operand store reference, bit 56 of the ASCE is checked.

[0118] PER Operations

[0119] In one embodiment, PER is controlled by bit 1 of the PSW (e.g., PSW 452) and the PER mask. For example, when the PER mask and a specific PER event mask bit are 1, the CPU is enabled for the corresponding type of event; otherwise, it is disabled.

[0120] Since interrupts for PER base events typically occur after the execution of the instruction responsible for the event. The occurrence of the event does not affect the execution of the instruction, and the instruction may complete, partially complete, terminate, be inhibited, or be invalidated. However, the recognition of a storage change event causes the storage of up to 4K bytes starting from the byte that caused the event, and the recognition of a zero address detection event may occur when completing an operation unit. The recognition of these PER events may cause the partial completion of an interruptible instruction. When a storage key change event is detected on an instruction that updates the storage keys of multiple 4K byte blocks, in one example, the instruction is interrupted immediately after setting the storage key for the block where the event was detected.

[0121] When the CPU is disabled at the occurrence of a specific PER event, whether through the PER mask in the PSW or through the mask in Control Register 9, the event cannot be recognized.

[0122] Changes to the PER mask in the PSW or the PER control fields in Control Registers 9, 10, and 11 affect PER starting from the execution of the instruction immediately following. Thus, if as a result of the change, an instruction fetch invalid event applies to the instruction immediately following, the execution of that instruction will be invalidated and the instruction fetch invalid event will be reported.

[0123] Changes to the store change event bit in the address space control unit in control registers 1, 7, or 13 also affect the PER starting from the execution of the instruction immediately following. A change to the store change event bit in the address space control unit that can be obtained from the main memory or an ASN - second - table entry in the ALB during register access does not necessarily have an immediate effect on the PER, if any. However, the PER is immediately affected after the execution of Clear ALB or Compare - and - Swap and Clear that clears the ALB.

[0124] If a PER basic event occurs during the execution of an instruction that changes the CPU from enabled to disabled for that type of event, the PER event is recognized.

[0125] The PER basic event can be recognized during the attempted execution of an instruction, and subsequently the instruction, DAT table entry, and operands can be refetched for actual execution. If any of the refetched fields are modified by another CPU or by a channel program between the trial execution and the actual execution, it is not possible to predict whether the indicated PER event is for the trial or the actual execution.

[0126] Cause identification

[0127] A program interrupt for the PER sets bit 8 of the interrupt code to 1 and places the identification information in the actual storage locations 150 - 159. When the PER event is a store change event or a zero - address detection event, the information is also stored in location 161. Additional information is provided by the program old program status word (PSW) and the instruction address in the ILC (Interrupt Length Code).

[0128] In one example, locations 150 - 151 (e.g., Figure 4 location 454) include:

[0129] PER code 456: The occurrence of a PER event is indicated by a 1 in bit positions 0 - 7. In one embodiment, the bit positions in the PER code for a particular type of event are as follows:

[0130]

[0131]

[0132] A 1 in bit position 2 and a 0 in bit position 4 of location 150 indicate a store change event, while 1s in bit positions 2 and 4 indicate a store using the actual address event. When a program interrupt occurs, more than one PER basic event can be indicated simultaneously. However, when a store change event and a zero - address detection event are recognized simultaneously, only the store change event is indicated. Additionally, if there is another program interrupt condition, the interrupt code for the program interrupt can indicate the PER basic event and the other condition.

[0133] When a program interrupt occurs for an invalid event for the PER instruction, bits 1 and 7 in the PER code are set to 1. No other PER events are indicated simultaneously.

[0134] When the transaction execution tool is installed and a program interrupt occurs for a transaction event, bit 6 in the PER code is set to 1. If the instruction fetch basic event occurs simultaneously with the transaction end event, bit 1 in the PER code is also set to 1. No other PER events are indicated simultaneously with the transaction end event.

[0135] Zero is stored in bit position 3 of locations 150 - 151. When the PER zero address detection tool is not installed, zero is stored in bit position 5. When the transaction execution tool is not installed, zero is stored in bit position 6. When PER-3 is not installed, zero is stored in bit position 7.

[0136] Addressing and Transformation Mode Identification (ATMID) 458: During a program interrupt, when a PER event is indicated, the execution of the instruction that causes the event for bits 31, 32, 5, 16, and 17 of the PSW (e.g., PSW 452) can be stored in bit positions 8 and 10 - 13 of the actual locations 150 - 151 respectively. If bits 31, 32, 5, 16, and 17 are stored, one bit is stored in bit position 9 of locations 150 - 151. If bits 31, 32, 5, 16, and 17 are not stored, zero bits are stored in bit positions 8 - 13 of locations 150 - 151.

[0137] Bits 8 - 13 of the actual locations 150 - 151 are named Addressing and Transformation Mode Identification (ATMID). Bit 9 is called the ATMID validity bit. When bit 9 is zero, it indicates that an invalid ATMID (e.g., all zeros) is stored.

[0138] In one embodiment, the meanings of the bits of the valid ATMID are as follows:

[0139]

[0140]

[0141] For example, a valid ATMID is stored only when the PER event is caused by one of the following instructions: Branch and Save and Set Mode (BASSM), Branch and Set Authority (BSA), Branch and Set Mode (BSM), Subspace Group Branch (BSG), Load PSW (LPWS), Load PSW Extended (LPWSE), Program Call (PC), Program Return (PR), Program Transfer (PT), Program Transfer with Instance (PTI), Resume Program (RP), Set Address Space Control (SAC), Set Address Space Control Fast (SACF), Set Addressing Model (SAM24, SAM31, SAM64), Set System Mask (SSM), Store Then And System Mask (STNSM), Store Then Or System Mask (STOSM), Supervisor Call (SVC), and Trap (TRAP2, TRAP4).

[0142] If the PER event is caused by any other instruction, it is not possible to predict whether a valid ATMID has been stored. The PER instruction obtaining the value of the invalid event mask bit does not affect the content of the ATMID field.

[0143] PER ASCE Identification (AI) 460: If the PER code contains an indication of a store change event (e.g., bit 2 is 1 and bit 4 is 0) or a zero address detection event (e.g., bit 5 is 1), and the event occurs when bit 5 of the PSW is 1 and an ASCE translation results in a reference to the event, bits 14 and 15 in positions 150 - 151 are set to identify the Address Space Control Element (ASCE) used to translate the reference to the event that caused the event, as follows, in one example:

[0144]

[0145]

[0146] In addition to the above, PER facilities include, for example:

[0147] PER Address: The PER address field in positions 152 - 159 (in memory) contains the instruction address of the instruction responsible for obtaining one or more PER events to be identified. In ESA / 390 compatibility mode, the PER address field in positions 152 - 155 contains bits 33 - 63 of the instruction address for the instruction responsible for obtaining one or more PER events to be identified. Bit 0 of position 152 is stored as zero.

[0148] When the instruction is the target of an execute type instruction (execute or execute relative long), the instruction address for obtaining the execute type instruction is placed in the PER address field.

[0149] PER Access Identification (PAID): If a store change event or zero address detection event is indicated in the PER code and the PER ASCE identification (AI, bits 14 - 15 of positions 150 - 151) contains binary 01, an indication of the address space to which the event applies is stored in position 161 (actual memory). The number of the access register used is stored in bits 4 - 7 of position 161, and zero is stored in bits 0 - 3. When the PER ASCE identification does not contain binary 01, the content of position 161 is unpredictable.

[0150] Instruction Address: The instruction address in the program old PSW is the address of the next instruction to be executed, unless another program condition is also indicated, in which case the instruction address is the address determined by the instruction that ended due to that condition. When a PER instruction fetch invalid event is recognized, the instruction address in the program old PSW is the address of the instruction responsible for that event. This is the same as the address stored in the PER address field in actual storage locations 152 - 159.

[0151] ILC: For a PER instruction invalid event, ILC is 0. For a PER basic event, ILC represents the instruction length specified by the PER address, unless in the case of a concurrent specification exception of the PSW caused by Load PSW, Load PSW Extension, Program Return, or Supervisor Call Interrupt, in which case ILC is set to 0.

[0152] Indicated Priority

[0153] When a PER instruction fetch invalid event is recognized and there are other program interrupt conditions, it indicates the program interrupt condition with the highest priority.

[0154] When a PER instruction fetch invalid event is indicated, no other PER events are indicated. When a PER instruction fetch invalid event is not indicated, more than one PER basic event may be recognized and reported. The remainder of this section applies to these cases.

[0155] When a program interrupt occurs for PER and more than one PER basic event has been recognized, all recognized PER events are indicated simultaneously in the PER code. However, when a store change or store use actual address event and a zero address detection event are recognized simultaneously, only the store change or store use actual address event is indicated.

[0156] When zero-address detection events are recognized for multiple stored operands, it is not possible to predict which operand's ASCE identification and AR number (if applicable) are stored in locations 150 - 151 and 161.

[0157] In the case of instruction fetch basic events for managing program calls, a program interruption occurs immediately after the hypervisor call interruption.

[0158] If a PER basic event is recognized during the execution of an instruction and the instruction also introduces a new PSW with an early recognized PSW format error type, both the specification exception and PER are indicated simultaneously in the interruption code at the program terminal. If the PSW format error is of the deferred recognition type, only PER is indicated in the interruption code. In both cases, the invalid PSW is stored as the program old PSW.

[0159] The recognition of a PER basic event generally does not affect the end of instruction execution. However, in the following cases, the execution of an interruptible instruction does not complete normally:

[0160] 1. When an instruction is interrupted due to an asynchronous condition (I / O, external, restart, or suppressible machine check condition), the program interruption for the PER event occurs first, and other interruptions follow (depending on the mask bits in the new PSW) in the normal priority order.

[0161] 2. When the stop function is executed, a program interruption indicating the PER event occurs before the CPU enters the stop state.

[0162] 3. When any program exception is recognized, the PER event recognized for the execution of that instruction is indicated simultaneously.

[0163] 4. According to the model, in some cases, the recognition of a PER event may appear to cause an instruction to be interrupted prematurely, without a concurrent indication of a program exception, without an interruption due to any asynchronous condition, and without the CPU entering the stop state. In particular, the recognition of a store change event causes no more than 4K bytes to be stored, starting from the byte that caused the event, and the recognition of a zero-address detection event may occur when the operation unit is completed.

[0164] In cases 1 and 2 above, if the only recognized PER event is an instruction fetch basic event and another operation unit of the instruction still remains to be executed, the event can be discarded, with the result that no program interruption occurs. Whether the event is discarded is unpredictable.

[0165] The recognition of a PER instruction fetch invalid event causes the execution of the instruction responsible for that event to be invalidated.

[0166] Storage area specification

[0167] In one embodiment, three types of PER events - instruction fetch, store change, and store key change - involve the specification of a storage region. A successful branch event may involve this specification. The storage region starts at the location specified by the start address in control register 10 and extends to and includes the location specified by the end address in control register 11. The region extends to the right of the start address.

[0168] An instruction fetch event occurs whenever the first byte of an instruction specified by an instruction address or the first byte of a target or execution type instruction is fetched from the specified region (before any address translation is applied).

[0169] A store change event occurs when a store access to the specified region is made using an operand address defined as a logical or virtual address. However, when DAT is on and the store change space control in control register 9 is 1, the storage region is within the address space where the store change event bit in the address space control unit is 1. No store change event occurs for store accesses made using an operand address defined as a physical address.

[0170] When the branch address control in control register 9 is 1, the first byte of the branch target instruction (specified by the branch address before any address translation is applied) is within the specified region.

[0171] A store key change event occurs when any byte within a 4K - byte block associated with an updated store key is within the specified region. In one example, all bits of control registers 10 and 11, including the lower 12 bits, participate in the determination of the specified region. For example, assume CR10 = 0x0000000000123017 and CR11 = 0x0000000000123016. If the definition ignores the lower 12 bits of the control registers, then in one example, there will be only a single 4K - byte block at address 0x000000000123000 in the specified region.

[0172] Furthermore, assume CR10 = 0X0000000000123001 and CR11 = 0x0000000000123FF and further assume that the definition states that only the first byte of a 4K - byte block must be within the specified region. Then, for example, an SSKE addressing 0x0000000000123000 will not hit the specified region.

[0173] In one example, if it is known that the broken storage key is within that range, the specified storage area can be set to a specific range. Alternatively, CR 10 can be set equal to 0x0000000000000000 and CR11 can be set to 0xFFFFFFFFFFFFFFFF to detect PER storage key change events when any storage key is modified. Other variations are possible.

[0174] As an example, the address is the actual address of the test block, the actual or absolute address that performs the frame management function and sets the storage key extension, and the logical address of the moving page.

[0175] The set of addresses specified for successful branches, instruction fetches, storage change events, and storage key change events wraps around at address 264 - 1; that is, address 0 is considered to be after address 264 - 1. When the start address is less than the end address, the region is continuous. When the start address is greater than the end address, the specified set of locations includes the region from the start address to address 264 - 1 and the region from address 0 to and including the end address. When the start address is equal to the end address, only one location is specified.

[0176] The address comparison for successful branches, instruction fetches, storage changes, and storage key change events is performed using 64 - bit addresses. This is achieved in 24 - bit or 31 - bit addressing modes by extending the virtual, logical, or instruction address on the left by 40 or 33 zeros respectively and then comparing it with the start and end addresses.

[0177] Example programming note: In some models, the performance of address range checking is assisted by an extension to each page table entry in the TLB (Translation Lookaside Buffer). In such an implementation, when a successful branch, instruction fetch, or storage change event mask is 1 or any of these PER event masks is set to 1, changing the contents of control registers 10 and 11 may cause entries in the TLB to be cleared. This can occur even if the CPU is disabled due to a PER event. Therefore, whenever possible, the program should avoid loading control registers 9, 10, or 11.

[0178] Example PER events include, for example:

[0179] Successful branch

[0180] When the branch address control in control register 9 is 0, the successful branch event occurs independently of the branch target address. When the branch address control is 1, the successful branch event occurs only when the first byte of the branch target instruction is within the storage area specified by control registers 10 and 11.

[0181] Subject to the influence of the branch address control, a successful branch event occurs whenever a branch is caused by one of the following instructions, for example: Branch And Link (BAL, BALR); Branch And Save (BAS, BASR); Branch And Save And Set Mode (BASSM); Branch And Set Authority (BSA); Branch And Set Mode (BSM); Branch And Stack (BAKR); Branch In Subspace Group (BSG); Branch Indirect On Condition, Branch on Condition (BC, BCR); Branch On Count (BCT, BCTR, BCTG, BCTGR); BranchOn Index High (BXH, BXHG); Branch On Index Low Or Equal (BXLE, BXLEG); Branch Relative And Save; BranchRelative And Save Long; Branch Relative On Condition (BRC); Branch Relative On Condition Long (BRCL); Branch Relative On Count (BRCT); Branch Relative On Count High (BRCTH); Branch Relative On Index High (BRXH, BRXHG); Branch Relative On Index Low Or Equal (BRXLE, BRXLG); Compare And Branch (CRB, CGRB); Compare And Branch Relative (CRJ, CGRJ); Compare Immediate And Branch (CIB, CGIB);Compare Immediate And Branch Relative (CIJ, CGIJ); Compare Logical And Branch (CLRB, CLGRB); Compare Logical And Branch Relative (CLRJ, CLRGJ); Compare Logical Immediate And Branch (CLIB, CLGIB); Compare Logical Immediate And Branch Relative (CLIJ, CLGIJ); Restore Program (RP); and Trap (TRAP2, TRAP4).;

[0182] Subject to the influence of branch address control, as long as one of the following instructions causes a branch, a successful branch event also occurs: Program Call (PC); Program Return (PR); Program Transfer (PT); and Program Transfer with Instance (PTI).

[0183] For Program Call, Program Return, Program Transfer, and Program Transfer with Instance, the branch target address is considered to be the new instruction address placed in the PSW by the instruction.

[0184] When the protected storage facility is enabled, a successful branch event is recognized as the result of a protected storage event caused by any of the following instructions: Load Guarded (LGG) and Load Logical and Shift Guarded (LLGFSG).

[0185] When the branch address control is 1, the branch address is considered to be the content of the Guarded Storage Event Handler Address (GSEHA) field in the Guarded Storage Event Parameter List (GSEPL).

[0186] If the 32nd bit of the PER event mask is 1 and the PER mask in the PSW is 1, a successful branch event results in a PER successful branch event being recognized.

[0187] A PER successful branch event is indicated by setting bit 0 or the PER code to 1.

[0188] Storage Change

[0189] A store change event occurs whenever the CPU makes a store access to a storage area specified by control registers 10 and 11 using logical or virtual addresses without an access exception. If the store change space control in control register 9 is 1, the event occurs only if the store change event bit in the address space control unit that the DAT uses to translate a reference to a storage location is 1.

[0190] Whenever the CPU executes an instruction that causes all or part of an operand to be stored within a specified storage area, the stored content is considered to have been changed. A change is considered to have occurred whenever a store is considered for the purpose of an indicated protection exception, unless the channel program identifies the data storage. A store constitutes a change for PER purposes even if the stored value is the same as the original value. In addition, the content of the TDB specified by TBEGIN is considered to have been changed by the execution of the outermost TBEGIN instruction, regardless of whether the TDB was actually stored by an aborted transaction; it is unpredictable whether a PER store change event is detected at the first operand location of an inner TBEGIN instruction.

[0191] Implicit locations referenced by the CPU are not monitored. These locations include the PSW and interrupt code locations, program interrupt transaction diagnostic blocks, enhanced monitor exception counters, and trace entries specified by control register 12. However, these locations are monitored when information is explicitly stored there by an instruction. Similarly, monitoring does not apply to data storage by the channel program. Implicit locations in the link stack (where they are stored by instructions operating on the link stack) and enhanced monitor count array entries stored by monitor call instructions are monitored.

[0192] An I / O instruction is considered to change the second operand location only if the store actually occurs.

[0193] Store changes do not apply to instructions whose operands are specified as having a real or absolute address. Thus, store changes do not apply to comparing and replacing DAT table entries, invalidating DAT table entries (invalid and clear operations), invalidating page table entries, paging in, performing frame management functions, resetting reference bit extensions, resetting multiple reference bits, setting store key extensions, storing using a real address, testing blocks, and testing for pending interrupts (when the effective address is zero). Store changes do not apply to storage of the store tool list to real location 200, nor to storage of the trace table by an instruction that causes a trace to occur.

[0194] If bit 34 of the PER event mask is 1 and the PER mask in the PSW is 1, a store change event causes a PER store change event to be recognized. Bit 36 of the PER event mask is ignored when determining whether to recognize a PER store change event.

[0195] Each memory change event is indicated by setting the second bit of the PER code to 1 and the fourth bit of the PER code to 0.

[0196] Store using the actual address

[0197] A store using the actual address event occurs whenever a store instruction using the actual address is executed.

[0198] There is no relationship between the store using the actual address event and the specified memory area.

[0199] If the 34th and 36th bits of the PER event mask are 1 and the PER mask in the PSW is 1, then storing the store using the actual address event causes the PER store using the actual address event to be recognized.

[0200] The PER store using the actual address event is indicated by setting the second and fourth bits of the PER code to 1.

[0201] Zero-address detection

[0202] When the PER zero-address detection facility is installed, a zero-address detection event occurs whenever the CPU makes a store access using a valid operand address formed by a general register containing zero or a subfield of a general register. However, during the execution of an RX-, RXE-, RXF-, RXY-, or VRX format instruction, the event occurs only when the CPU makes a store access using a valid operand address formed under one of the following conditions:

[0203] 1. The base register number is zero, the index register number is non-zero, and the index register contains zero.

[0204] 2. The index register number is zero, the base register number is non-zero, and the base register contains zero.

[0205] 3. When both the base register number and the index register number are non-zero, it is not possible to predict which of the following cases causes the event:

[0206] (a) The base register contains zero.

[0207] (b) The sum of the contents of the base register and the index register is zero.

[0208] During the execution of a VRV format instruction, if the CPU makes a store access, it is not possible to predict which one or more of the following cases will cause the event:

[0209] 1. The base register number is zero and the value of the index element of the second operand is zero.

[0210] 2. The base register number is non-zero and the base register contains zero.

[0211] 3. The sum of the content of the base register and the value of the indexed element is zero.

[0212] Unless otherwise specified, whenever a load, store, or update reference to memory is made using this address, a zero-address detection of the operand address is performed, and only when the operand address is used to access memory.

[0213] Except for the Branch Indirect On Condition, no zero-address detection is performed on the branch address of branch-type instructions. For the Branch Indirect On Condition, the zero-address detection is performed on the second operand address, rather than on the branch address obtained from the second operand. For load protection and load logical and shift protection, zero-address detection is performed on the second operand address of the instruction, even though these are considered branch-type instructions when a protected memory event is recognized.

[0214] No zero-address detection is also performed on the target instruction address of the Execute instruction and the content of the general register R2 of the test block instruction.

[0215] For compressed calls, when converting UTF-16 to UTF-32, UTF-16 to UTF-8, UTF-32 to UTF-16, UTF-32 to UTF-8, UTF-8 to UTF-16, and UTF-8 to UTF-32, when reaching the end of the first operand, it is unpredictable whether a PER zero-address detection event is recognized for any store operand, but the end of the second operand is not reached.

[0216] The conditions used to cause zero-address detection events are evaluated at the start of instruction execution. If these conditions are re-evaluated during instruction execution, the result is unpredictable.

[0217] Except as otherwise specified, the determination of whether a register content is zero depends on the current addressing mode as follows:

[0218] · In 24-bit and 31-bit addressing modes, if bits 32 - 63 are all zero, the register is considered to contain zero.

[0219] · In 64-bit addressing mode, if bits 0 - 63 are all zero, the register is considered to contain zero.

[0220] For Compare And Replace DAT Table Entry, when bit position 59 of general register R2 contains zero, general register R2 is considered to contain zero if bits 0 - 52 are all zero; when bit 59 of general register R2 is 1, general register R2 is considered to contain zero if bits 0 - 51 are all zero. For Invalidate DAT Table Entry, general register R1 is considered to contain zero if bits 0 - 51 are all zero; for Invalidate Page Table Entry, general register R1 is considered to contain zero if bits 0 - 52 are all zero, regardless of the addressing mode.

[0221] Zero Address Detection Event: If the PER mask in the PSW is 1 and bit 37 of the PER event mask is 1, the zero address detection event causes the PER zero address detection event to be recognized.

[0222] The PER zero address detection event is indicated by setting bit 5 of the PER code to 1.

[0223] Transaction End

[0224] When the CPU is in transaction execution mode at the start of the outermost transaction end instruction, a transaction end event occurs when the instruction completes.

[0225] There is no relationship between the transaction end event and the specified storage area.

[0226] If bit 38 of the PER event mask is 1 and the PER mask in the PSW is 1, the transaction end event causes the PER transaction end event to be recognized.

[0227] The PER transaction end event is indicated by setting bit 6 of the PER code to 1.

[0228] When the transaction end instruction is executed and the CPU is not in transaction execution mode, the transaction end event is not recognized.

[0229] Storage Key Change

[0230] According to one aspect of the present invention, a storage key change event occurs whenever the CPU updates the ACC or F bit of the storage key associated with a 4K - byte storage block without an access exception. Within the storage area specified by control registers 10 and 11. Changing the R or C bit does not cause this event unless it also changes the ACC or F bit. In one example, even if the new value is the same as the original value, the update of the ACC or F bit is considered a change for PER purposes.

[0231] In other embodiments, when the CPU updates, for example, a 4K-byte storage block regardless of the specified storage area. Other variations are possible.

[0232] As an example, if the 4K-byte block associated with the updated storage key is within the specified area (or in another embodiment, no specified area is specified), then four instructions can cause a storage key change event:

[0233] · Any execution of setting the storage key extension. When the conditional SSKE facility is installed, one or both of the MR and MC bits are 1, and updating the access control and fetch protection bits is not required, and if this is considered a storage key change time depends on the model. In the case where the access control and fetch protection bits are updated, for example, as long as the associated 4K-byte storage block is within the specified area, a storage key change event occurs.

[0234] · Execute the frame management function when SK (bit 46 of the general register R1) is 1. When the conditional SSKE facility is installed, the processing when the MR or MC bit is non-zero is the same as the above instruction for setting the storage key extension.

[0235] · Move pages when the move page and set key function is installed and the key function control (KFC) (bits 51 - 53 of the general register 0) contains the value 4 or 5.

[0236] · Any execution of testing the block, but in one example, only when the implementation of the model actually updates the storage key.

[0237] If, for example, bit 35 of the PER event mask is 1 and the PER mask in the PSW is 1, then the storage key change event causes a PER storage key change event to be recognized.

[0238] The PER storage key change event is indicated by setting bit 3 of the PER code to 1.

[0239] Indication of PER events occurring simultaneously with other interrupt conditions

[0240] When reporting the PER fetch instruction invalid event, no other PER events and no other program interrupt conditions are reported.

[0241] As an example, the following rules govern the indication of PER basic events caused by instructions that also cause program exceptions, monitor events, space switch events, or hypervisor call interrupts.

[0242] 1. The indication of the instruction fetch basic event does not depend on whether the execution of the instruction is completed, terminated, inhibited, or invalid. However, examples of special cases of inhibition and invalidation are as follows:

[0243] a. When the instruction is specified by an odd instruction address in the PSW, no instruction fetch event is indicated.

[0244] b. When an access exception applies to the first, second, or third halfword of the instruction specified by the PSW instruction address and the PER-3 tool is installed, no instruction fetch event is indicated. However, if the PER-3 tool is not installed, it is not possible to predict whether an instruction fetch event will be indicated.

[0245] c. When (a) an access exception applies to the first, second, or third halfword of the target location of an execute-type instruction, or (b) the target address of an Execute is odd, in one example, the following applies: If the PER-3 tool is installed, then no instruction fetch event is indicated for the target location; it is not predictable whether an instruction fetch event will be indicated for an execute-type instruction, including cases where the PER address range includes the execute-type instruction and its target. If the PER-3 tool is not installed, it is not possible to predict whether the instruction fetch event is for an execute-type instruction or for the target location.

[0246] 2. When an operation is completed or partially completed, an event is indicated regardless of whether any program exceptions, space switch events, or monitor events are also recognized.

[0247] 3. Successful branch, zero address detection; store changes and stores using the actual address are not used for operations, or in the case where an instruction is interruptible, for suppressed or invalid operation units.

[0248] 4. When the execution of an instruction terminates, a store change or zero address detection is indicated whenever an event occurs. If an event will occur after the execution of the instruction is complete, the model can indicate the event even if the content of the result field depends on the operand value. For the purposes of this definition, the occurrence of those exceptions that allow termination (addressing, protection, and data) is considered to cause termination even if the result area has not changed.

[0249] 5. When loading the PSW, loading the PSW extension, program return, setting the system mask, store then or system mask, or supervisor call causes a PER base condition, while introducing a new PSW with a PSW format error type that is recognized immediately after PSW activation, the interrupt code recognizes the PER base condition and the specification exception.

[0250] 6. When loading the PSW, loading the PSW extension, program return, or supervisor call causes a PER condition and simultaneously introduces a new PSW with a PSW format error type that is recognized as part of the execution of the next instruction, the introduced PSW is stored as the old PSW, and the next instruction is not fetched or executed, and no specification exception is recognized.

[0251] 7. When the outermost transaction start instruction causes PER basic events and concurrent program exceptions, event suppression control does not apply.

[0252] When a PER event occurs while the CPU is in transactional execution mode, the transaction is aborted.

[0253] Sample programming instructions include, for example:

[0254] 1. The execution of the interruptible instructions Compare And Form Codeword, Compare Logic Long, Compare Until Substring Equal, Compression Call, Move Long, Test Block, and UpdateTree can cause events for instruction fetch and zero address detection. The execution of the interruptible instructions performs frame management functions (when the Enhanced DAT tool is installed, the frame size code specifies a 1M-byte frame), sets storage key extension (when the Enhanced DAT tool is installed and multi-block control is one of them) and Test Block can cause instruction fetch events. The execution of Compression Call, Move Long, and UpdateTree can cause events for instruction fetch and storage change.

[0255] Interruptions of such instructions may result in PER base events being indicated more than once. Therefore, in one example, the program may remove redundant event indications from the PER data. In one example, the following rules govern the indication of applicable events during the execution of these instructions:

[0256] a. Indicates instruction fetch basic events, for example, whenever an instruction fetch is executed, whether for initial execution or resumption, it may be discarded (not indicated) unless the event is the only PER event. It should be noted that the interrupt is due to an asynchronous interrupt condition or the execution of a stop function, and an operation unit of the instruction remains to be executed.

[0257] b. A storage change event is indicated only when data has been stored within the specified storage area by the portion of the operation starting with the last start and ending with the last byte transferred before the interrupt. For premature interrupts, no special indication is given as to whether the event will occur again after resuming the operation. When the specified storage area is a single-byte location, a storage change event can be recognized only once when executing a move long or compress call, but can be recognized multiple times for an update tree.

[0258] 2. The following is an example of a summary of the general actions to be taken by the program to delete multiple entries of the PER basic event in the PER data of an interruptible instruction so that only one entry is obtained for each complete execution of the instruction:

[0259] a. Check whether the PER address is equal to the instruction address in the old PSW and whether the last executed instruction is interruptible.

[0260] b. If both conditions are met, delete the instruction fetch event.

[0261] c. If both conditions are met and the event is a store change, delete the event if some parts of the remaining target operand are within the specified storage area.

[0262] 3. An example of an indication of the PER instruction fetch basic event caused by a load PSW (or load PSW extension) instruction or a subsequent instruction, combined with an entry PSW format error or an odd instruction address introduced by the load PSW instruction.

[0263] Although one embodiment of the PER tool is described herein, other embodiments are possible. In addition, other tools or capabilities may be used to provide one or more aspects of the present invention. Many changes and variations can be made.

[0264] One or more aspects of the present invention are inseparable from computer technology and contribute to processing within a computer, improving its performance. Detection of stored key change events enables detection of incorrect program changes to stored keys and / or damaged stored keys, thereby enhancing the security of memory and processing within the computing environment. Performance is also improved by facilitating the detection of programming errors and correcting incorrect programs without having to execute many instructions to determine a damaged stored key.

[0265] Reference Figures 6A - 6B Further details of an embodiment that facilitates processing within a computing environment are described as it relates to one or more aspects of the present invention. In one example, the hardware and / or firmware of a processor is used to perform the following processing.

[0266] Reference Figure 6A , in one embodiment, it is determined whether a stored key change event has occurred (600) within the processor of a computing environment. The determination includes checking whether one or more selected fields of the stored key have been updated (602). The stored key is associated with a memory block and controls access to the memory block (604). In one example, based on the check indicating that one or more selected fields of the stored key have been updated, a stored key change event has occurred (606). Based on the determination that a stored key change event has occurred, a notification of the stored key change event is provided (608).

[0267] As an example, providing the notification includes providing a notification (609) of a storage key change event via an interrupt based on determining that the storage key change event has occurred.

[0268] In one example, the checking includes checking whether one or more selected fields of the storage key have been updated without an access exception (610). Based on the checking indicating that one or more selected fields of the storage key have been updated without an access exception, the storage key change event has occurred (612).

[0269] In one example, determining whether a storage key change event has occurred further includes determining whether a memory block is within a specified storage area (614). Based on the checking indicating that one or more selected fields of the storage key have been updated and the memory block is within the specified storage area, the storage key change event has occurred (616).

[0270] In addition, referring Figure 6B , in one example, the checking includes checking whether one or more selected fields of the storage key have been updated without an access exception (620), and a storage key change event occurs based on the checking indicating that one or more selected fields of the storage key have been updated without an access exception and the memory block is within the specified storage area (622).

[0271] As an example, the specified storage area is defined by a start address of the memory specified in a first location and an end address of the memory specified in a second location (624). For example, the first location is a selected control register and the second location is another selected control register (626).

[0272] In one example, the end address wraps around to the start address, and a selected number of low-order bits for the start address and for the end address are used in the definition of the specified storage area to include more than one memory block (628). In addition, in one example, determining whether a memory block is within the specified storage area includes determining whether one or more memory cells of the memory block are within the specified storage area (630).

[0273] As an example, one or more selected fields include an access control field of the storage key (632) and / or an acquisition protection field of the storage key (634).

[0274] Other variations and embodiments are possible.

[0275] Aspects of the present invention can be used in many types of computing environments. Another embodiment of a computing environment incorporating and using one or more aspects of the present invention refers to Figure 7Ais described. In this example, the computing environment 10 includes, for example, a local central processing unit (CPU) 12, a memory 14, and one or more input / output devices and / or interfaces 16, which are connected by, for example, one or more buses 18 and / or other connections. As an example, the computing environment 10 can include a processor provided by International Business Machines (IBM) Corporation of Armonk, New York; an HP Superdome with an Intel Itanium II processor provided by Hewlett-Packard (HP) Company of Palo Alto, California; and / or other machines based on architectures provided by International Business Machines Corporation, Hewlett-Packard (HP) Company, Intel Corporation, Oracle Corporation, or other companies. IBM, z / Architecture, IBM Z, z / OS, PR / SM, and PowerPC are trademarks or registered trademarks of International Business Machines (IBM) Corporation in at least one jurisdiction. Intel and Itanium are trademarks or registered trademarks of Intel or its subsidiaries in the United States and other countries / regions. The local central processing unit 12 includes one or more local registers 20, such as one or more general-purpose registers and / or one or more special-purpose registers used during processing within the environment. These registers include information representing the state of the environment at any given point in time.

[0276] In addition, the native central processing unit 12 executes instructions and code stored in the memory 14. In a particular example, the central processing unit executes emulator code 22 stored in the memory 14. This code enables a computing environment configured in one architecture to mimic another architecture. For example, the emulator code 22 allows a machine based on an architecture other than the z / Architecture hardware architecture, such as a PowerPC processor, an HP Superdome server, or others, to simulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0277]

[0278] Figure 7B Reference Figure 7BFurther details regarding the emulator code 22 are described. The guest instructions 30 stored in the memory 14 include software instructions (e.g., related to machine instructions) developed to execute in an architecture different from the architecture of the native CPU 12. For example, the guest instructions 30 may have been designed to execute on a processor based on the z / Architecture hardware architecture, but are emulated on the native CPU 12, such as an Intel Itanium II processor. In one example, the emulator code 22 includes an instruction fetch routine 32 to obtain one or more guest instructions 30 from the memory 14 and optionally provide local buffering for the obtained instructions. It also includes an instruction translation routine 34 to determine the type of the obtained guest instructions and translate the guest instructions into one or more corresponding native instructions 36. The translation includes, for example, identifying the functional instructions to be executed by the guest and selecting native instructions to execute that function.

[0279] In addition, the emulator code 22 includes an emulation control routine 40 to cause the native instructions to be executed. The emulation control routine 40 can cause the native CPU 12 to execute a native instruction routine that emulates one or more previously obtained guest instructions, and at the end of such execution, return control to the instruction fetch routine to emulate the obtaining of the next guest instruction or a set of guest instructions. The execution of the native instructions 36 can include loading data from the memory 14 into registers; storing data from the registers back to memory; or performing some type of arithmetic or logical operation determined by the translation routine.

[0280] Each routine is implemented in software, for example, which is stored in the memory and executed by the local central processing unit 12. In other examples, one or more routines or operations are implemented in firmware, hardware, software, or some combination thereof. The registers of the emulation processor can use the registers 20 of the native CPU or be emulated by using locations in the memory 14. In an embodiment, the guest instructions 30, the native instructions 36, and the emulator code 22 can reside in the same memory or can be distributed among different memory devices.

[0281] The above computing environments are merely examples of computing environments that can be used. Other environments can be used, including but not limited to non-partitioned environments, partitioned environments, and / or emulated environments; embodiments are not limited to any one environment.

[0282] Each computing environment can be configured to include one or more aspects of the present invention. For example, according to one or more aspects of the present invention, each can be configured to perform a stored key change detection process.

[0283] One or more aspects can relate to cloud computing.

[0284] It should be understood that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings recited herein is not limited to cloud computing environments. Instead, embodiments of the present invention are capable of being implemented in conjunction with any other type of computing environment now known or later developed.

[0285] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0286] The characteristics are as follows:

[0287] On-demand self-service: Cloud consumers can unilaterally and automatically provision computing capabilities, such as server time and network storage, as needed without human interaction with the service provider.

[0288] Broad network access: Capabilities are available over the network and accessed through standard mechanisms that promote the use of heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0289] Resource pooling: The provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to demand. There is location independence in that consumers generally have no control or knowledge of the exact location of the provided resources, but may be able to specify location at a higher level of abstraction (e.g., country, state, or data center).

[0290] Rapid elasticity: Capabilities can be rapidly and elastically provisioned in some cases to scale out quickly and released to scale in quickly. To the consumer, the capabilities available for provisioning generally appear to be unlimited and can be in any quantity at any time.

[0291] Measured service: Cloud systems automatically control and optimize resource use by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency for both the provider and consumer of the utilized services.

[0292] The service models are as follows:

[0293] Software as a Service (SaaS): The ability provided to consumers is to use the provider's applications running on a cloud infrastructure. These applications can be accessed from various client devices through a thin client interface (such as a web browser (e.g., web-based email)). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functions, except for limited user-specific application configuration settings.

[0294] Platform as a Service (PaaS): The ability provided to consumers is to deploy the applications created or acquired by the consumers onto a cloud infrastructure, where the applications are created using programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but can control the deployed applications and the configuration of the possible application hosting environment.

[0295] Infrastructure as a Service (IaaS): The ability provided to consumers is to offer processing, storage, networking, and other basic computing resources, in which the consumers can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but can control the operating systems, storage, deployed applications, and may have limited control over selected network components (such as the host firewall).

[0296] The deployment models are as follows:

[0297] Private cloud: The cloud infrastructure runs only for an organization. It may be managed by the organization or a third party and may exist either on-premises or externally.

[0298] Community cloud: The cloud infrastructure is shared by multiple organizations and supports a specific community with common concerns (such as missions, security requirements, policies, and compliance considerations). It may be managed by the organization or a third party and may exist either on-premises or externally.

[0299] Public cloud: The cloud infrastructure is available for public use or for large industry groups and is owned by the organization selling the cloud services.

[0300] Hybrid cloud: The cloud infrastructure is a combination of two or more clouds (private, community, or public), which remain distinct entities but are bound together through standardized or proprietary technologies to enable data and application portability (such as load balancing between clouds).

[0301] The cloud computing environment is service-oriented, focusing on statelessness, low coupling, modularity, and semantic interoperability. The core of cloud computing is the infrastructure that includes a network of interconnected nodes.

[0302] Now refer to Figure 8, depicts an illustrative cloud computing environment 50. As shown, cloud computing environment 50 includes one or more cloud computing nodes 52, to which local computing devices used by cloud consumers such as a personal digital assistant (PDA) or cellular telephone 54A, desktop computer 54B, laptop computer 54C, and / or automotive computer system 54N may communicate. Nodes 52 may communicate with one another. They may be physically or virtually grouped (not shown) in one or more networks, such as private, community, public, or hybrid clouds as described above, or combinations thereof. This allows cloud computing environment 50 to provide infrastructure, platforms, and / or software as services for which cloud consumers do not need to maintain resources on local computing devices. It will be understood that Figure 8 the types of computing devices 54A-N shown are for illustration only, and computing node 52 and cloud computing environment 50 may communicate with any type of computerized device through any type of network and / or network addressable connection (e.g., using a web browser).

[0303] Now referring to Figure 9 , there is shown a set of functional abstraction layers provided by cloud computing environment 50 ( Figure 8 ). It should be understood in advance that Figure 9 the components, layers, and functions shown are for illustration only and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0304] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: mainframes 61; servers 62 based on RISC (Reduced Instruction Set Computer) architecture; servers 63; blade servers 64; storage devices 65; and network and networking components 66. In some embodiments, software components include web application server software 67 and database software 68.

[0305] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers 71; virtual storage 72; virtual networks 73, including virtual private networks; virtual applications and operating systems 74; and virtual clients 75.

[0306] In one example, the management layer 80 can provide the functions described below. Resource provisioning 81 provides for the dynamic procurement of computing resources and other resources for performing tasks within a cloud computing environment. Metering and pricing 82 provides cost tracking when resources are utilized within the cloud computing environment, as well as billing or invoicing for the consumption of these resources. In one example, these resources can include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. The user portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management to meet the required service levels. Service level agreement (SLA) planning and fulfillment 85 provides pre-arrangement and procurement of cloud computing resources for future requirements projected according to the SLA.

[0307] The workload layer 90 provides examples of functions that can utilize the cloud computing environment. Examples of workloads and functions that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analysis processing 94; transaction processing 95; and storage key change detection processing 96.

[0308] Aspects of the present invention can be a system, method, and / or computer program product at any possible level of integration of technical details. The computer program product can include a computer-readable storage medium (or media) having thereon computer-readable program instructions for causing a processor to execute aspects of the present invention.

[0309] A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium can be, by way of example and not limitation, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punch card or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium as used herein should not be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through an optical fiber) or an electrical signal transmitted through a wire.

[0310] The computer-readable program instructions described herein can be downloaded to a corresponding computing / processing device from a computer-readable storage medium or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0311] The computer-readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network connection, including a LAN or WAN, or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), can execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuit in order to perform aspects of the present invention.

[0312] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0313] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block(s). These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture including instructions which implement aspects of the functions / acts specified in the flowchart and / or block diagram block(s) or multiple blocks.

[0314] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block(s).

[0315] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or combinations of special-purpose hardware and computer instructions.

[0316] In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider that provides customer environment management. For example, the service provider can create, maintain, support, etc. computer code and / or a computer infrastructure that performs one or more aspects for one or more customers. In return, as an example, the service provider can receive payment from a customer in accordance with a subscription and / or fee agreement. Additionally or alternatively, the service provider can receive payment from selling advertising content to one or more third parties.

[0317] In one aspect, an application can be deployed to execute one or more embodiments. As an example, the deployment of an application includes providing a computer infrastructure operable to execute one or more embodiments.

[0318] As another aspect, a computing infrastructure can be deployed, including integrating computer-readable code into a computing system, where the code combined with the computing system is capable of performing one or more embodiments.

[0319] As yet another aspect, a process for integrating a computing infrastructure can be provided, including integrating computer-readable code into a computer system. The computer system includes a computer-readable medium, where the computer medium includes one or more embodiments. The code combined with the computer system is capable of performing one or more embodiments.

[0320] Although various embodiments are described above, these are merely examples. For example, computing environments of other architectures can be used to incorporate and use one or more embodiments. Additionally, different tools can be used to detect storage key changes. Many variations are possible.

[0321] Furthermore, other types of computing environments can be benefited from and used. As an example, a data processing system suitable for storing and / or executing program code is available, which includes at least two processors directly or indirectly coupled to memory elements via a system bus. The memory elements include, for example, local memory used during the actual execution of the program code, mass storage, and cache memory that provides at least some temporary storage of the program code to reduce the number of times code must be retrieved from mass storage during execution.

[0322] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASD, tapes, CDs, DVDs, thumb drives, and other storage media, etc.) can be coupled to the system directly or through an intervening I / O controller. A network adapter can also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices via a private or public network. Modems, cable modems, and Ethernet cards are just some of the available types of network adapters.

[0323] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "this", and "that" are also intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0324] All structural, material, acts, and equivalents (if any) of the apparatus or steps plus function elements in the following claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically recited. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the various aspects and practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications suited to the particular use contemplated.

Claims

1. A computer-implemented method for facilitating processing within a computing environment, the method comprising the steps of: Determining whether a stored key change event has occurred within a processor of the computing environment, the determining including checking whether one or more selected fields of a stored key have been updated without an access exception, the stored key being associated with a memory block and controlling access to the memory block, wherein based on a check indicating that one or more selected fields of the stored key have been updated without an access exception, a stored key change event has occurred; And Based on determining that a stored key change event has occurred, providing a notification of the stored key change event.

2. The method according to claim 1, wherein providing the notification includes providing a notification of the stored key change event via an interrupt based on determining that a stored key change event has occurred.

3. The method according to claim 1, wherein determining whether a stored key change event has occurred further includes determining whether the memory block is within a specified storage area, wherein based on a check indicating that one or more selected fields of the stored key have been updated without an access exception and that the memory block is within the specified storage area, a stored key change event has occurred.

4. The method according to claim 3, wherein the specified storage area is defined by a start address of a memory specified at a first location and an end address of the memory specified at a second location.

5. The method according to claim 4, wherein the first location is a selected control register and the second location is another selected control register.

6. The method according to claim 4, wherein the end address wraps around to the start address, and wherein a selected number of low-order bits for the start address and for the end address are used in the definition of the specified storage area to include more than one memory block.

7. The method according to claim 3, wherein determining whether the memory block is within the specified storage area includes determining whether one or more memory cells of the memory block are within the specified storage area.

8. The method according to claim 1, wherein the one or more selected fields include an access control field of the stored key.

9. The method according to claim 1, wherein the one or more selected fields include an acquisition protection field of the stored key.

10. A computer system, comprising means adapted to perform the steps of the method according to any one of claims 1-9.

11. A computer program product, comprising a computer-readable storage medium storing computer program instructions for performing the steps of the method according to any one of claims 1-9 when the computer program instructions are executed on a computer system.

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