Microelectronic device including low-lying structure and related method, memory device and electronic system

Abstract

The present application relates to a microelectronic device including a depression structure and related methods, memory devices and electronic systems. The microelectronic device includes a stacked structure, a depression structure within the stacked structure and a conductive contact structure. The stacked structure includes a vertical alternating sequence of conductive structures and insulating structures arranged in layers. Each of the layers includes one of the conductive structures and one of the insulating structures. The depression structure includes: a forward step structure having a step including an edge of the layer; and a reverse step structure, which is opposite to the forward step structure and has an additional step including an additional edge of the layer. The conductive contact structure extends vertically to the upper vertical boundary of at least some of the conductive structures of the stacked structure at the step of the forward step structure and the additional step of the reverse step structure, and each is integral and continuous with one of the conductive structures. Memory devices, electronic systems and methods of forming microelectronic devices are also described.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the filing date of U.S. patent application Ser. No. 16 / 864,823, filed on May 1, 2020, and entitled “MICROELECTRONIC DEVICES INCLUDING STADIUM STRUCTURES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS.” Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More specifically, the present disclosure relates to microelectronic devices including low-lying structures and related methods, memory devices, and electronic systems. Background Art

[0004] An ongoing goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as nonvolatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in nonvolatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include vertical memory strings extending through openings in one or more stacked structures including conductive structures and dielectric material layers. Each vertical memory string may include at least one selection device coupled in series with a series combination of vertically stacked memory cells. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration permits a greater number of switching devices (e.g., transistors) to be located in a cell of die area (i.e., the length and width of the active surface consumed) by building the array upward (e.g., vertically) on the die.

[0005] A vertical memory array architecture generally includes electrical connections between conductive structures of a layer of a stacked structure of a memory device and access lines (e.g., word lines) so that memory cells of the vertical memory array can be uniquely selected for write, read, or erase operations. One method of forming such electrical connections includes forming a so-called "staircase" (or "rung") structure at the edge (e.g., horizontal end) of a layer of a stacked structure of a memory device. The staircase structure includes individual "steps" that define contact regions of the conductive structures, on which conductive contact structures can be positioned to provide electrical access to the conductive structures.

[0006] As vertical memory array technology has evolved, additional memory density has been provided by forming the vertical memory array to include additional layers of conductive structures and, therefore, additional steps in the staircase structures associated therewith. However, increasing the number of steps in the staircase structure without undesirably increasing the overall width (e.g., horizontal footprint) of the staircase structure reduces the acceptable error tolerance associated with the different actions in the process of forming the increased number of steps. A conventional process of forming a staircase structure may include the actions of trimming a uniform width of a mask (e.g., photoresist) overlying alternating conductive and insulating structures, etching portions of the insulating structures not covered by the remainder of the mask, and then etching portions of the conductive structures not covered by the remainder of the insulating structures. Each of these repeated actions has an associated error tolerance, permitting the steps of the staircase structure to be appropriately sized and positioned to form contact structures thereon. As the number of repeated actions increases, deviations from a desired step width and / or desired step position may be accommodated, as errors in the size and / or position of one structure are passed on to subsequently formed structures later in the process. For a large number of steps in a staircase structure, the error margin to achieve properly sized and positioned steps may be small, e.g., less than one percent (1%). Achieving such small error margins using conventional methods may be extremely difficult, may result in improperly positioned contact structures, and may undesirably reduce yield (e.g., the number of properly programmable and erasable memory cells as a percentage of the total number of memory cells in a given batch). Additionally, as feature packing densities have increased and the tolerance for formation errors has decreased, conventional configurations have resulted in undesirable defects (e.g., contact punch-through) as well as current leakage and shorts, which can impair desired memory device performance, reliability, and endurance.

[0007] Thus, there is a continuing need for new microelectronic device (e.g., memory device, such as 3D NAND flash memory device) configurations to facilitate increased memory density while alleviating problems with conventional microelectronic device configurations, and there is a continuing need for new methods of forming microelectronic devices and new electronic systems incorporating new microelectronic device configurations. Summary of the invention

[0008] According to an embodiment of the present disclosure, a microelectronic device includes a stacked structure, a depression structure within the stacked structure, and a conductive contact structure. The stacked structure includes a vertical alternating sequence of conductive structures and insulating structures arranged in layers. Each of the layers includes one of the conductive structures and one of the insulating structures. The depression structure includes: a forward step structure having a step including an edge of the layer; and a reverse step structure, which is opposite to the forward step structure and has an additional step including an additional edge of the layer. The conductive contact structure extends vertically to the upper vertical boundaries of at least some of the conductive structures of the stacked structure at the steps of the forward step structure and the additional steps of the reverse step structure. The conductive contact structures are each integral and continuous with one of the conductive structures.

[0009] According to an additional embodiment of the present disclosure, a method of forming a microelectronic device includes forming a preliminary stacked structure, the preliminary stacked structure including a vertical alternating sequence of insulating structures and additional insulating structures arranged in layers. Each of the layers includes one of the insulating structures and one of the additional insulating structures. A trench is formed to extend vertically into the preliminary stacked structure. A horizontal alternating sequence of dielectric spacer structures and dielectric liner structures are formed within the horizontal boundaries of the trench. At least some of the dielectric liner structures physically contact the insulating structures of different preliminary stacked structures. The dielectric material of the dielectric liner structures and the insulating structures of the preliminary stacked structure are at least partially replaced by a conductive material.

[0010] According to other embodiments of the present disclosure, a memory device includes a stacked structure, a depression structure, a conductive contact structure, and a memory cell string. The stacked structure has several layers, each of which includes a conductive structure and an insulating structure vertically adjacent to the conductive structure. The depression structures are positioned at different vertical depths from each other within the stacked structure. Each of the depression structures includes: a forward step structure having a step including a horizontal end of a group of layers; and a reverse step structure, which is opposite to the forward step structure and has an additional step including an additional horizontal end of the group of layers. The conductive contact structure extends vertically from at least some of the conductive structures of the stacked structure at the steps and additional steps of the depression structure. The conductive contact structures are each integral and continuous with one of the conductive structures. The memory cell string extends vertically through the stacked structure.

[0011] According to still other embodiments of the present disclosure, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a microelectronic device structure, which includes a stacked structure, a depression structure, and a conductive contact structure. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. The depression structure is within the stacked structure and includes relative step structures each having a step including an edge of at least some of the layers. The conductive contact structure is integral and continuous with at least some of the conductive structures of the stacked structure at a step of the relative step structure of the depression structure. Each of the conductive contact structures individually has an internal horizontal boundary that is substantially coplanar with an internal horizontal boundary of one of the steps of the relative step structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1A to 1L is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure.

[0013] Figure 2 is a simplified top view of a microelectronic device according to an embodiment of the present disclosure.

[0014] Figure 3 is a simplified top view of a microelectronic device according to additional embodiments of the present disclosure.

[0015] Figures 4A to 4C is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to additional embodiments of the present disclosure.

[0016] Figures 5A to 5G is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to additional embodiments of the present disclosure.

[0017] Figure 6 is a schematic block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The following description provides specific details, such as material composition, shape and size, in order to provide a full description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that the embodiments of the present disclosure may be practiced without adopting these specific details. In fact, the embodiments of the present disclosure may be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). The structure described below does not form a complete microelectronic device. Only those process actions and structures necessary for understanding the embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structure may be performed by conventional manufacturing techniques.

[0019] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device or system. As a result of, for example, manufacturing techniques and / or tolerances, variations different from the shapes depicted in the drawings are expected. Therefore, the embodiments described herein should not be interpreted as being limited to specific shapes or regions as described, but rather include shape deviations, such as those caused by manufacturing. For example, a box-shaped region described or described may have rough and / or nonlinear features, and a circular region described or described may include some rough and / or linear features. In addition, the sharp angles described may be rounded, and vice versa. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the region and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale. In addition, common elements between the figures may retain the same numbering.

[0020] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited to memory functionality. In other words and by way of non-limiting example only, the term "memory device" includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0021] As used herein, the terms "vertical", "longitudinal", "horizontal", and "lateral" are relative to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

[0022] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to one another refer to and include features of the disclosed identity (or identities) that are located in the closest proximity (e.g., closest) to one another. Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identity (or identities) of the "adjacent" features may be placed between the "adjacent" features. In other words, the "adjacent" features may be located directly adjacent to one another, such that no other features intervene between the "adjacent" features; or the "adjacent" features may be located indirectly adjacent to one another, such that at least one feature having an identity other than the identity associated with at least one "adjacent" feature is located between the "adjacent" features. Thus, features described as being "vertically adjacent" to one another refer to and include features of the disclosed identity (or identities) that are located in the closest proximity (e.g., closest vertically) to one another. Furthermore, features described as being "horizontally adjacent" to one another refer to and include features of the disclosed identity (or identities) that are located in the closest proximity (e.g., closest horizontally) to one another.

[0023] As used herein, the terms "comprising," "including," "having," and their grammatical equivalents are inclusive or open terms that do not exclude additional unrecited elements or method steps, and also encompass the more restrictive terms "consisting of" and "consisting essentially of," and their grammatical equivalents. As used herein, the term "may" with respect to a material, structure, feature, or method act indicates that such material, structure, feature, or method act is contemplated for use in practicing embodiments of the present disclosure, and such terms are preferably used rather than the more restrictive term "is" in order to avoid any suggestion that other compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

[0024] As used herein, spatially relative terms such as "below," "below," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," "right," and similar may be used to conveniently describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of materials in addition to the orientation depicted in the figures. For example, if the materials in the drawings are reversed, an element described as being "below," "under," "under," or "on the bottom" of other elements or features will be oriented "above," or "on the top" of the other elements or features. Thus, the term "below" may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to a person of ordinary skill in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein may be interpreted accordingly.

[0025] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0026] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and the device in a predetermined manner.

[0028] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses the degree to which a given parameter, property, or condition is satisfied with a degree of variance (such as within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on a particular parameter, property, or condition being substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, may be satisfied by at least 95.0%, may be satisfied by at least 99.0%, may be satisfied by at least 99.9%, or even satisfied by 100.0%.

[0029] As used herein, "about" or "approximately" with reference to a numerical value of a particular parameter includes the numerical value, and the degree of deviation from the numerical value that one of ordinary skill in the art would understand is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within the range of 90.0 percent to 110.0 percent of the numerical value, such as within the range of 95.0 percent to 105.0 percent of the numerical value, within the range of 97.5 percent to 102.5 percent of the numerical value, within the range of 99.0 percent to 101.0 percent of the numerical value, within the range of 99.5 percent to 100.5 percent of the numerical value, or within the range of 99.9 percent to 100.1 percent of the numerical value.

[0030] Unless the context indicates otherwise, the materials described herein may be formed by any suitable process, including but not limited to spin coating, blanket coating, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), plasma-enhanced ALD, physical vapor deposition ("PVD") (including sputtering, evaporation, ionized PVD and / or plasma-enhanced CVD), or epitaxial growth. Depending on the specific material to be formed, the technique used to deposit or grow the material may be selected by one of ordinary skill in the art. In addition, unless the context indicates otherwise, the material removal described herein may be achieved by any suitable process, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, milling planarization, or other known methods.

[0031] Figures 1A to 1L 1 is a simplified partial cross-sectional view illustrating an embodiment of a method of forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). In conjunction with the description provided below, it will be apparent to one of ordinary skill in the art that the methods and structures described herein can be used in a variety of devices and electronic systems.

[0032] See also Figure 1A , the microelectronic device structure 100 can be formed to include a preliminary stacked structure 102, and a patterned mask structure 110 on or over the preliminary stacked structure 102. The preliminary stacked structure 102 includes a vertically alternating (e.g., in the Z direction) sequence of first insulating structures 104 and second insulating structures 106 arranged into layers 108. Each of the layers 108 of the preliminary stacked structure 102 can include at least one of the first insulating structures 104 vertically adjacent to at least one of the second insulating structures 106. The preliminary stacked structure 102 can be formed to include any desired number of layers 108, such as greater than or equal to sixteen (16) layers 108, greater than or equal to thirty-two (32) layers 108, greater than or equal to sixty-four (64) layers 108, greater than or equal to one hundred twenty-eight (128) layers 108, or greater than or equal to two hundred fifty-six (256) layers 108.

[0033] The first insulating structure 104 of the layer 108 of the preliminary stacked structure 102 may be formed of and include at least one dielectric material, such as at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, alumina (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrOx ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )) and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y )). A chemical formula (e.g., SiO x , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C z N y) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios and loose chemical structures, the insulating structure 104 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having an elemental composition that cannot be represented by a ratio of well-defined natural numbers and violates the law of definite proportions and the law of multiple proportions. Each of the first insulating structures 104 may individually include at least one insulating material that is substantially uniformly distributed or significantly non-uniformly distributed. As used herein, the term "homogeneously distributed" means that the amount of a material does not change across different portions of the structure (e.g., different horizontal portions, different vertical portions). In contrast, as used herein, the term "heterogeneous distribution" means that the amount of a material varies throughout different portions of a structure. In some embodiments, each of the first insulating structures 104 exhibits a substantially homogeneous distribution of an electrically insulating material. In further embodiments, at least one of the first insulating structures 104 exhibits a substantially heterogeneous distribution of at least one electrically insulating material. One or more of the first insulating structures 104 may, for example, be formed of and include a stack (e.g., a laminate) of at least two different electrically insulating materials (e.g., at least two different dielectric materials). In some embodiments, each of the first insulating structures 104 is formed of and includes a dielectric nitride material, such as SiN y (e.g., Si3N4). The first insulating structures 104 may each be substantially planar, and may each respectively exhibit a desired thickness. In addition, each of the first insulating structures 104 may be substantially identical to one another (e.g., exhibiting substantially identical material composition, material distribution, size, and shape), or at least one of the first insulating structures 104 may be different from at least one other of the first insulating structures 104 (e.g., exhibiting one or more of a different material composition, a different material distribution, a different size, and a different shape). In some embodiments, each of the first insulating structures 104 is substantially identical to each other of the first insulating structures 104.

[0034] The second insulating structure 106 of the layer 108 of the preliminary stacked structure 102 may be formed of and include at least one additional electrically insulating material. The material composition of the second insulating structure 106 and the first insulating structure 104 may be selected so that the first insulating structure 104 and the second insulating structure 106 may be selectively removable relative to each other. The second insulating structure 106 may be selectively etchable relative to the first insulating structure 104 during a common (e.g., collective, mutual) exposure to a first etchant, and the first insulating structure 104 may be selectively etchable relative to the second insulating structure 106 during a common exposure to a second, different etchant. As used herein, a material is "selectively etchable" relative to another material if it exhibits an etching rate that is at least about five times (5x) greater than the etching rate of the other material, such as about ten times (10x), about twenty times (20x), or about forty times (40x). The material composition of the second insulating structure 106 is different from the material composition of the first insulating structure 104. The second insulating structure 106 may include an additional electrically insulating material, such as at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ) and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y In some embodiments, each of the second insulating structures 106 is formed of and includes a dielectric oxide material, such as SiO x(e.g., SiO2). Each of the second insulating structures 106 may individually include a substantially homogeneous distribution of the at least one additional electrically insulating material or a substantially heterogeneous distribution of the at least one additional electrically insulating material. In some embodiments, each of the second insulating structures 106 of the preliminary stacked structures 102 exhibits a substantially homogeneous distribution of the additional electrically insulating material. In additional embodiments, at least one of the second insulating structures 106 of the preliminary stacked structures 102 exhibits a substantially heterogeneous distribution of the at least one additional electrically insulating material. The second insulating structures 106 may, for example, individually be formed by and include a stack (e.g., a laminate) of at least two different additional electrically insulating materials. The second insulating structures 106 may each be substantially planar and may each individually exhibit a desired thickness.

[0035] Continue to view Figure 1A , the patterned mask structure 110 may be formed of and include at least one material suitable for use as an etch mask (e.g., at least one hard mask material) to pattern portions of the preliminary stacked structure 102 (e.g., portions of the layer 108, portions including the first insulating structure 104, and portions of the second insulating structure 106) to form pores (e.g., openings, vias, trenches) extending vertically (e.g., in the Z direction) into the preliminary stacked structure 102, as described in further detail below. By way of non-limiting example, the patterned mask structure 110 may be formed of and include one or more hard mask materials having an etch selectivity relative to the material of the preliminary stacked structure 102 (including the first insulating structure 104 and the second insulating structure 106). In some embodiments, the patterned mask structure 110 includes polysilicon. The patterned mask structure 110 may be homogeneous (e.g., may include only one material layer), or may be heterogeneous (e.g., may include a stack exhibiting at least two different material layers). Additionally, the patterned mask structure 110 may exhibit any thickness that permits desired patterning of the preliminary stack structure 102 using the patterned mask structure 110 , such as a thickness in a range from about 1 nanometer (nm) to about 1000 nm.

[0036] like Figure 1A As shown, the patterned mask structure 110 may include at least one opening 112 (e.g., an aperture, a through hole) extending vertically therethrough. The opening 112 may extend vertically (e.g., in the Z direction) completely through the patterned mask structure 110, from the upper surface of the patterned mask structure 110 to the upper surface of the preliminary stacked structure 102 (e.g., the upper surface of the second insulating structure 106 of the uppermost layer 108 of the preliminary stacked structure 102).

[0037] The patterned mask structure 110 can be formed to exhibit any desired amount of openings 112. The amount of openings 112 included in the patterned mask structure 110 can depend at least in part on the desired amount and distribution of trenches to be formed in the preliminary stack structure 102 using the patterned mask structure 110, which in turn can depend at least in part on the amount of layer 108 included beneath the patterned mask structure 110. In some embodiments, the patterned mask structure 110 is formed to include a plurality (e.g., more than one) of openings 112.

[0038] The geometric configuration (e.g., shape, size), horizontal position (e.g., along the X direction, along the Y direction), and horizontal spacing of each opening 112 in the patterned mask structure 110 are at least partially dependent on the geometric configuration, horizontal position, and horizontal spacing of the trenches that will be subsequently formed in the preliminary stacked structure 102 using the patterned mask structure 110, as described in further detail below. In some embodiments, each opening 112 exhibits substantially the same geometric configuration (e.g., substantially the same shape and substantially the same size) as each other opening 112, is regularly (e.g., uniformly, invariably) horizontally spaced (e.g., horizontally separated, horizontally spaced) from horizontally adjacent openings 112, and is substantially horizontally aligned with horizontally adjacent openings 112 in at least one horizontal direction. In additional embodiments, at least one opening 112 in the patterned mask structure 110 exhibits one or more of a different geometric configuration (e.g., a different shape, such as a non-rectangular horizontal cross-sectional shape), a different horizontal size, and / or a different horizontal spacing than at least one other opening 112. For example, at least one opening 112 may exhibit a different (e.g., larger, smaller) width along the X direction and / or a different length along the Y direction than at least one other opening 112. As another example, some horizontally adjacent openings 112 may be horizontally separated from each other by a first distance, and other horizontally adjacent openings 112 may be horizontally separated from each other by a second distance different from (e.g., smaller than, larger than) the first distance.

[0039] Next reference Figure 1B , portions of at least one upper layer 108 (e.g., the highest layer, the top layer, the uppermost layer in the Z direction) of the preliminary stacked structure 102 exposed by the openings 112 in the patterned mask structure 110 may be removed to expose portions of a relatively lower layer 108 (e.g., the second highest layer in the Z direction) of the preliminary stacked structure 102 that is vertically underlying (e.g., vertically adjacent) the upper layer 108. The removal process may partially remove the second insulating structure 106 of the upper layer 108 and the portions of the first insulating structure 104 exposed by the openings 112 in the patterned mask structure 110 to expose (e.g., expose) portions of the second insulating structure 106 that is vertically underlying the relatively lower layer 108 of the upper layer 108.

[0040] like Figure 1B As shown, after the removal process, the remaining portion of the upper layer 108 of the preliminary stacked structure 102 exposed within the opening 112 may terminate (e.g., end) at or substantially near the horizontal centerline 114 (e.g., along the X direction) of the opening 112 in the patterned mask structure 110. Therefore, the newly exposed portion of the relatively lower layer 108 may extend horizontally (e.g., along the X direction) from and between the horizontal centerline 114 and the outer horizontal boundary (e.g., along the X direction) of the opening 112 in the patterned mask structure 110. In other words, after the removal process, the first width W1 of the remaining portion of the upper layer 108 of the preliminary stacked structure 102 exposed within the opening 112 may be substantially equal to the second width W2 of the newly exposed portion of the relatively lower layer 108 vertically underlying the upper layer 108. In additional embodiments, the remaining portion of the upper layer 108 of the preliminary stacked structure 102 exposed within the opening 112 may terminate at a position that is horizontally offset (e.g., along the X direction) from a horizontal centerline 114 (e.g., along the X direction) of the opening 112 in the patterned mask structure 110. In such embodiments, the first width W1 of the remaining portion of the upper layer 108 of the preliminary stacked structure 102 exposed within the opening 112 may be different from (e.g., greater than, less than) a second width W2 of a newly exposed portion of a relatively lower layer 108 vertically underlying the upper layer 108.

[0041] The portions of the upper layer 108 of the preliminary stack structure 102 exposed within the openings 112 in the patterned mask structure 110 may be removed using conventional material removal processes (eg, conventional photolithography patterning processes; conventional etching processes, such as conventional anisotropic etching processes), which are not described in detail herein.

[0042] Next reference Figure 1C , the microelectronic device structure 100 may be subjected to one or more material removal processes (e.g., one or more cutting processes) to form at least one trench 116 (e.g., opening, blind via) extending vertically (e.g., in the Z direction) into the preliminary stacked structure 102. Figure 1CAs shown, the trenches 116 within the preliminary stacked structure 102 may be generally confined within the horizontal boundaries of the openings 112 within the patterned mask structure 110. In embodiments where the patterned mask structure 110 includes a plurality of openings 112, different trenches 116 may be formed to extend to different vertical depths within the preliminary stacked structure 102 from one another. For example, at least one of the trenches 116 may extend vertically to a relatively lower depth within the preliminary stacked structure 102 than at least one other of the trenches 116. The vertical depths of the trenches 116 relative to one another may depend at least in part on the amount of layers 108 of the preliminary stacked structure 102, the amount of trenches 116 within the preliminary stacked structure 102, and the horizontal dimensions of the trenches 116. The trenches 116 may be configured to facilitate subsequent formation of vertically extending insulating structures in physical contact with at least some (e.g., each) of the layers 108 of the preliminary stacked structure 102, as described in further detail below.

[0043] like Figure 1C As shown, the trench 116 may include a first region 116A and a second region 116B. The second region 116B of the trench 116 may extend vertically (e.g., in the Z direction) to a relatively lower depth within the preliminary stacked structure 102 than the first region 116A of the trench 116. For example, the first region 116A of the trench 116 vertically extends to and terminates at a relatively high layer 108 of the preliminary stacked structure 102; and the second region 116B of the trench 116 may vertically extend to and terminate at a relatively low layer 108 of the preliminary stacked structure 102. The relatively high layer 108 of the preliminary stacked structure 102 and the relatively low layer 108 of the preliminary stacked structure 102 may be vertically adjacent to each other within the preliminary stacked structure 102. The first region 116A of the trench 116 may have the previously referenced Figure 1B The first width W1 described above (eg, in the X direction), and the second region 116B of the trench 116 may have the same width as previously described. Figure 1B The second width W2 is depicted (eg, in the X-direction). The first region 116A of the trench 116 may be horizontally adjacent to the second region 116B of the trench 116 .

[0044] The trench 116 may include a lower vertical boundary 118 (e.g., a bottom layer) and a horizontal boundary 120 (e.g., a side surface). The lower vertical boundary 118 of the trench 116 may have a non-planar surface morphology resulting from different vertical depths of the first region 116A of the trench 116 and the second region 116B of the trench 116. For example, the first portion 118A of the lower vertical boundary 118 of the trench 116 may be defined by the vertical depth of the first region 116A of the trench 116, and the second portion 118B of the lower vertical boundary 118 of the trench 116 may be defined by the vertical depth of the first region 116A of the trench 116. The first portion 118A and the second portion 118B of the lower vertical boundary 118 of the trench 116 may each be substantially horizontally flat, but may be vertically offset from each other (e.g., in the Z direction). The second portion 118B of the lower vertical boundary 118 of the trench 116 may be horizontally adjacent (eg, in the X direction) to the first portion 118A of the lower vertical boundary 118 of the trench 116. Figure 1C , the horizontal boundaries 120 of the trench 116 may be substantially vertically planar.

[0045] like Figure 1CAs shown, the trench 116 may be formed to vertically terminate (e.g., vertically end) at the second insulating structure 106 of two different layers 108 of the preliminary stacked structure 102 (e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102). For example, the first region 116A of the trench 116 may vertically terminate at the second insulating structure 106 of a relatively higher layer 108 of the preliminary stacked structure 102; and the second region 116B of the trench 116 may vertically terminate at the second insulating structure 106 of a relatively lower layer 108 of the preliminary stacked structure 102. In other words, the first portion 118A of the lower vertical boundary 118 of the trench 116 may be defined by the exposed portion of the second insulating structure 106 of the relatively higher layer 108 of the preliminary stacked structure 102; and the second portion 118B of the lower vertical boundary 118 of the trench 116 may be defined by the exposed portion of the second insulating structure 106 of the relatively lower layer 108 of the preliminary stacked structure 102. In additional embodiments, the trench 116 may be formed to vertically terminate at the first insulating structures 104 of two different layers 108 of the preliminary stacked structure 102 (e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102). For example, the first region 116A of the trench 116 may vertically terminate at the first insulating structure 104 of a relatively higher layer 108 of the preliminary stacked structure 102; and the second region 116B of the trench 116 may vertically terminate at the first insulating structure 104 of a relatively lower layer 108 of the preliminary stacked structure 102. In other words, the first portion 118A of the lower vertical boundary 118 of the trench 116 may be defined by the exposed portion of the first insulating structure 104 of the relatively higher layer 108 of the preliminary stacked structure 102; and the second portion 118B of the lower vertical boundary 118 of the trench 116 may be defined by the exposed portion of the first insulating structure 104 of the relatively lower layer 108 of the preliminary stacked structure 102.

[0046] Next reference Figure 1D , a first dielectric spacer structure 122-1 may be formed within the opening 112 in the patterned mask structure 110 and the trench 116 in the preliminary stacked structure 102. The first dielectric spacer structure 122-1 may partially (e.g., less than completely) fill each of the opening 112 and the trench 116, and may be formed within the horizontal boundaries (e.g., in the X and Y directions) of the trench 116 (and thus the opening 112 in the patterned mask structure 110) on the exposed surfaces of the patterned mask structure 110 and the preliminary stacked structure 102. For example, as Figure 1DAs shown, the first dielectric spacer structure 122-1 may be directly horizontally adjacent to (e.g., horizontally above) the side surfaces of the patterned mask structure 110 and the preliminary stacked structure 102 and formed at the horizontal boundary 120 of the trench 116 (e.g., coplanar therewith), and may also be directly vertically adjacent to (e.g., vertically above) the upper surface of the layer 108 of the preliminary stacked structure 102 to define the lower vertical boundary 118 ( Figure 1C , including a first portion 118A and a second portion 118B thereof). The first dielectric spacer structure 122-1 may substantially vertically extend across (e.g., in the Z direction) and cover the side surfaces of the patterned mask structure 110 and the preliminary stacked structure 102 at (e.g., coplanar with) the horizontal boundary 120 of the trench 116, and may only partially extend horizontally across (e.g., in the X and Y directions) and cover the upper surface of the layer 108 of the preliminary stacked structure 102 to define a lower vertical boundary 118 ( Figure 1C ).

[0047] like Figure 1D As shown, the first dielectric spacer structure 122-1 may include a first portion 122-1A and a second portion 122-1B. The first portion 122-1A may be formed within the horizontal boundary of the first region 116A of the trench 116, and the second dielectric spacer structure 122-2 may be formed within the horizontal boundary of the second region 116B of the trench 116. The second portion 122-1B may extend vertically (e.g., in the Z direction) to a lower vertical depth than the first portion 122-1A. The vertical depth of the first portion 122-1A may correspond to (e.g., be substantially the same as) the vertical depth of the first region 116A of the trench 116; and the vertical depth of the second portion 122-1B may correspond to (e.g., be substantially the same as) the vertical depth of the second region 116B of the trench 116. For example, the first portion 122-1A may extend vertically to and terminate at a relatively high level 108 to define a lower vertical boundary 118 ( Figure 1C ) first part 118A( Figure 1C ); and the second portion 122-1B may extend vertically to and terminate at a relatively lower layer 108 to define a lower vertical boundary 118 of the trench 116 ( Figure 1C ) of the second part 118B ( Figure 1C ).

[0048] The first dielectric spacer structure 122-1 can be formed to exhibit a third width W3 (eg, in the X direction). The third width W3 can depend at least in part on the total width of the trench 116 (eg, as described previously with reference to FIG. 1 ). Figure 1CThe third width W3 may be a combination of the first width W1 and the second width W2 described above, and the desired configuration of the depression structure to be formed within the horizontal boundary of the trench 116, as described in further detail below. By way of non-limiting example, the third width W3 may be in a range from about 25 nanometers (nm) to about 500 nm.

[0049] The first dielectric spacer structure 122-1 may be formed of and include at least one dielectric material having a different etching selectivity from the first insulating structure 104 of the preliminary stacked structure 102. The first dielectric spacer structure 122-1 may, for example, have a selective etching substantially similar to the second insulating structure 106 of the preliminary stacked structure 102. Portions of the first dielectric spacer structure 122-1 may be used to protect (e.g., shield) portions of the preliminary stacked structure 102 during subsequent processing actions (e.g., subsequent material removal actions, such as subsequent etching actions), as described in further detail below. By way of non-limiting example, the first dielectric spacer structure 122-1 may be formed of and include at least one oxygen-containing dielectric material, such as one or more of the following: a dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x and TiO x one or more of the above), dielectric oxynitride materials (e.g., SiO x N y ), and dielectric carbon oxynitride materials (e.g., SiO x C z N y ). The material composition of the first dielectric spacer structure 122-1 may be different from the material composition of the first insulating structure 104 of the preliminary stacked structure 102. The material composition of the first dielectric spacer structure 122-1 may be substantially the same as or may be different from the material composition of the second insulating structure 106 of the preliminary stacked structure 102. In some embodiments, the first dielectric spacer structure 122-1 is made of SiO x (e.g., SiO2) formed and including SiO x .

[0050] The first dielectric spacer structure 122-1 may be formed by conformally forming (e.g., by one or more of a conventional ALD process and a conventional conformal CVD process) a dielectric material (e.g., a dielectric oxide material) on or above the surface of the preliminary stacked structure 102 and the patterned mask structure 110 inside and outside the trench 116. Subsequently, the microelectronic device structure 100 may be subjected to at least one material removal (e.g., etching, such as anisotropic dry etching) process to form the first dielectric spacer structure 122-1 (including its first portion 122-1A and second portion 122-1B). The material removal process may substantially (e.g., completely) remove a portion of the dielectric material outside the trench 116 on or above the upper surface of the patterned mask structure 110, and may partially remove a lower vertical boundary 118 ( Figure 1C ) portion of the dielectric material. Figure 1D As shown, the material removal process may also remove the lower vertical boundary 118 ( Figure 1C ) to expose (e.g., expose) a portion of the first insulating structure 104 of the layer 108 within the horizontal boundary of the trench 116. The exposed portion of the first insulating structure 104 of the layer 108 can be horizontally bounded by the first dielectric spacer structure 122-1 within the horizontal boundary of the trench 116.

[0051] Next reference Figure 1E , the first dielectric liner structure 124-1 may be formed within the remaining (e.g., unfilled) portions of the openings 112 in the patterned mask structure 110 and the trenches 116 in the preliminary stacked structure 102. The first dielectric liner structure 124-1 may partially (e.g., less than completely) fill the remaining portions of each of the openings 112 and the trenches 116, and may be formed within the horizontal boundaries (e.g., in the X and Y directions) of the trenches 116 (and thus the openings 112 in the patterned mask structure 110) on the exposed surfaces of the first dielectric spacer structure 122-1 and the preliminary stacked structure 102. For example, the first dielectric liner structure 124-1 may be formed directly horizontally adjacent to (e.g., horizontally above) the inner surface of the first dielectric spacer structure 122-1 (including the first portion 122-1A and the second portion 122-1B thereof), and may also be formed directly vertically adjacent to (e.g., vertically above) the upper surface of the first insulating structure 104 of the layer 108 of the preliminary stacked structure 102 as previously described. Figure 1DThe first dielectric liner structure 124-1 may extend substantially vertically across (eg, in the Z-direction) and cover the inner side surfaces of the first dielectric spacer structure 122-1.

[0052] like Figure 1E As shown, the first dielectric liner structure 124-1 may include a first portion 124-1A and a second portion 124-1B. The first portion 124-1A may be formed within the horizontal boundary of the first region 116A of the trench 116, and the second dielectric liner structure 124-2 may be formed within the horizontal boundary of the second region 116B of the trench 116. The first portion 124-1A may be formed directly horizontally adjacent to (e.g., horizontally above) the first portion 122-1A of the first dielectric spacer structure 122-1, and the second portion 124-1B may be formed directly horizontally adjacent to (e.g., horizontally above) the second portion 122-1B of the first dielectric spacer structure 122-1. The second portion 124-1B of the first dielectric liner structure 124-1 may extend vertically (e.g., in the Z direction) to a vertical depth within the preliminary stacked structure 102 that is relatively lower than the vertical depth of the first portion 124-1A of the first dielectric liner structure 124-1. The vertical depth of the first portion 124-1A of the first dielectric liner structure 124-1 may be greater than or equal to the vertical depth of the first portion 122-1A of the first dielectric spacer structure 122-1; and the vertical depth of the second portion 124-1B of the first dielectric liner structure 124-1 may be greater than or equal to the vertical depth of the second portion 122-1B of the first dielectric spacer structure 122-1. For example, the first portion 124-1A of the first dielectric liner structure 124-1 may extend vertically to and terminate at a first insulating structure 104 of a layer 108 of the preliminary stacked structure 102 vertically adjacent to a lower vertical boundary of the first portion 122-1A of the first dielectric spacer structure 122-1; and the second portion 124-1B of the first dielectric liner structure 124-1 may extend vertically to and terminate at a first insulating structure 104 of another relatively lower layer 108 of the preliminary stacked structure 102 vertically adjacent to a lower vertical boundary of the second portion 122-1B of the first dielectric spacer structure 122-1.

[0053] The first dielectric liner structure 124-1 may be formed to exhibit a fourth width W4 (e.g., in the X direction). The fourth width W4 may, for example, be substantially equal to the vertical height (e.g., in the Z direction) of each of the first insulating structures 104 of the preliminary stacked structure 102. In additional embodiments, the fourth width W4 is different from (e.g., smaller than, larger than) the vertical height of one or more (e.g., each) of the first insulating structures 104 of the preliminary stacked structure 102.

[0054] The first dielectric liner structure 124-1 may be formed of and include at least one dielectric material having a different etch selectivity than the second insulating structure 106 of the preliminary stacked structure 102. The first dielectric liner structure 124-1 may, for example, have an etch selectivity substantially similar to that of the first insulating structure 104 of the preliminary stacked structure 102. By way of non-limiting example, if formed, the first dielectric liner structure 124-1 may be formed of at least one dielectric nitride material (e.g., SiN y ) and includes the at least one dielectric nitride material. The material composition of the first dielectric liner structure 124-1 may be different from that of the first dielectric spacer structure 122-1 ( Figure 1D ) and the material composition of the second insulating structure 106 of the preliminary stacked structure 102. The material composition of the first dielectric liner structure 124-1 may be substantially the same as or may be different from the material composition of the first insulating structure 104 of the preliminary stacked structure 102. In some embodiments, the first dielectric liner structure 124-1 is made of SiN y (e.g., Si3N4) formed and containing SiN y .

[0055] The first dielectric liner structure 124-1 may be formed by conformally forming (e.g., by one or more of a conventional ALD process and a conventional conformal CVD process) an additional dielectric material (e.g., a dielectric nitride material) on or above the surface of the preliminary stacked structure 102, the first dielectric spacer structure 122-1, and the patterned mask structure 110, inside and outside the trench 116. Subsequently, the microelectronic device structure 100 may be subjected to at least one material removal (e.g., etching, such as anisotropic dry etching) process to form the first dielectric liner structure 124-1 (including its first portion 124-1A and second portion 124-1B). The material removal process may substantially (e.g., completely) remove portions of the additional dielectric material on or above the upper surface of the patterned mask structure 110 and the first dielectric spacer structure 122-1, and may partially remove portions of the additional dielectric material on or above the surface of the preliminary stacked structure 102 at the modified lower vertical boundary of the trench 116. As Figure 1EAs shown, the material removal process may also remove a portion of the first insulating structure 104 of the layer 108 of the preliminary stacked structure 102 vertically adjacent to the lower vertical boundaries of the first portion 122-1A and the second portion 122-1B of the first dielectric spacer structure 122-1 to expose (e.g., reveal) a portion of the second insulating structure 106 of the relatively vertically lower layer 108 within the horizontal boundaries of the trench 116. The exposed portion of the second insulating structure 106 of the relatively vertically lower layer 108 may be horizontally bounded by the first dielectric liner structure 124-1 within the horizontal boundaries of the trench 116.

[0056] Next reference Figure 1F , the microelectronic device structure 100 may be subjected to at least one additional material removal (e.g., etching, such as anisotropic dry etching) process to increase the vertical depth (e.g., in the Z direction) of the remaining (e.g., unfilled) portion of the trench 116. The additional material removal process may increase the vertical depth of the remaining portion of the first region 116A of the trench 116, and may also increase the vertical depth of the remaining portion of the second region 116B of the trench 116. After the additional material removal process, the remaining portion of the second region 116B of the trench 116 may vertically extend to a relatively lower depth within the preliminary stack structure 102 than the remaining portion of the first region 116A of the trench 116. The magnitude of the vertical offset between the lower vertical boundary of the first region 116A of the trench 116 and the lower vertical boundary of the second region 116B of the trench 116 may be substantially maintained at the end of the additional material removal process. For example, the additional material removal process may increase the vertical depth of each of the remaining portion of the first region 116A of the trench 116 and the remaining portion of the second region 116B of the trench 116 by a distance (e.g., in the Z direction) that is substantially equal to the height (e.g., in the Z direction) of a single (e.g., only one) layer 108 of the preliminary stacked structure 102. In other words, the additional material removal process may remove the remaining portion of the first region 116A of the trench 116 and the remaining portion of the second region 116B of the trench 116. Figure 1E At the end of the processing stage depicted in FIG. 1 , a single (eg, only one) layer 108 of the preliminary stacked structure 102 of the modified lower vertical boundary of the first region 116A of the trench 116 is exposed; and the vertically adjacent layer 108 of the preliminary stacked structure 102 may also be removed. Figure 1E An exposed portion of another single (eg, only one) layer 108 of the preliminary stacked structure 102 of the modified lower vertical boundary of the second region 116B of the trench 116 at the end of the processing stage depicted in FIG.

[0057] like Figure 1FAs shown, after the additional material removal process, the remaining (e.g., unfilled) portion of the trench 116 (including the remaining portions of the first region 116A and the second region 116B thereof) may vertically terminate (e.g., vertically end) at the second insulating structure 106 of two different layers 108 of the preliminary stacked structure 102 (e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102). For example, the remaining portion of the first region 116A of the trench 116 may vertically terminate at the second insulating structure 106 of a relatively higher layer 108 of the preliminary stacked structure 102; and the remaining portion of the second region 116B of the trench 116 may vertically terminate at the second insulating structure 106 of a relatively lower layer 108 of the preliminary stacked structure 102. In additional embodiments, after the additional material removal process, the remaining (e.g., unfilled) portion of the trench 116 may vertically terminate at the first insulating structure 104 of two different layers 108 of the preliminary stacked structure 102 (e.g., two vertically adjacent layers 108 of the preliminary stacked structure 102). For example, the first region 116A of the trench 116 may vertically terminate at the first insulating structure 104 at a relatively higher layer 108 of the preliminary stack structure 102 ; and the second region 116B of the trench 116 may vertically terminate at the first insulating structure 104 at a relatively lower layer 108 of the preliminary stack structure 102 .

[0058] Next reference Figure 1G , the second dielectric spacer structure 122-2 can be formed within the remaining (e.g., unfilled) portion of the opening 112 in the patterned mask structure 110 and in the remaining deepened portion of the trench 116 in the preliminary stacked structure 102. The second dielectric spacer structure 122-2 can partially (e.g., less than completely) fill the remaining portion of the opening 112 and the remaining deepened portion of the trench 116; and can be formed within the first dielectric liner structure 124-1 ( Figure 1F ) and the exposed surface of the preliminary stacked structure 102 are formed within the horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trench 116 (and thus the opening 112 in the patterned mask structure 110). For example, the second dielectric spacer structure 122-2 may be directly horizontally adjacent to (e.g., horizontally above) the first dielectric liner structure 124-1 ( Figure 1F , which contains Figure 1G The first portion 124-1A and the second portion 124-1B shown in FIG. 1 and the exposed inner side surface of the preliminary stacked structure 102 are formed in the trench 116, and the upper surface of the second insulating structure 106 of the layer 108 of the preliminary stacked structure 102 may also be formed directly vertically adjacent to (e.g., vertically above) the preliminary stacked structure 102. Figure 1GThe second dielectric spacer structure 122-2 may extend substantially vertically across (eg, in the Z direction) and cover the inner side surface (eg, the inner side surface) of the first dielectric liner structure 124-1. Figure 1F ).

[0059] like Figure 1G As shown, the second dielectric spacer structure 122-2 may include a first portion 122-2A and a second portion 122-2B. The first portion 122-2A may be formed within the horizontal boundary of the first region 116A of the trench 116, and the second portion 122-2B may be formed within the horizontal boundary of the second region 116B of the trench 116. The first portion 122-2A of the second dielectric spacer structure 122-2 may be formed directly horizontally adjacent to (e.g., horizontally above) the first portion 124-1A of the first dielectric liner structure 124-1, and the second portion 122-2B may be formed directly horizontally adjacent to (e.g., horizontally above) the second portion 124-1B of the first dielectric liner structure 124-1. The second portion 122-2B of the second dielectric spacer structure 122-2 may extend vertically (e.g., in the Z direction) to a lower vertical depth within the preliminary stacked structure 102 than the first portion 122-2A of the second dielectric spacer structure 122-2. The vertical depth of the first portion 122-2A of the second dielectric spacer structure 122-2 may be greater than the vertical depth of the first portion 124-1A of the first dielectric liner structure 124-1; and the vertical depth of the second portion 122-2B of the second dielectric spacer structure 122-2 may be greater than the vertical depth of the second portion 124-1B of the first dielectric liner structure 124-1. For example, the first portion 122-2A of the second dielectric spacer structure 122-2 may vertically extend to and terminate at the first insulating structure 104 of a relatively higher layer 108 of the preliminary stacked structure 102; and the second portion 122-2B of the second dielectric spacer structure 122-2 may vertically extend to and terminate at the first insulating structure 104 of another relatively lower layer 108 of the preliminary stacked structure 102 that is vertically adjacent to the relatively higher layer 108 of the preliminary stacked structure 102.

[0060] In some embodiments, the second dielectric spacer structure 122-2 is formed to exhibit substantially equal dielectric properties to the first dielectric spacer structure 122-1 ( Figure 1D ,Include Figure 1G 1A and the second portion 122-1B shown in FIG. 1A and 1B) of the third width W3 (eg, in the X direction). In additional embodiments, the second dielectric spacer structure 122-2 is formed to exhibit a width different from (eg, greater than, less than) the third width W3.

[0061] The second dielectric spacer structure 122-2 may be formed by the first insulating structure 104 and the first dielectric liner structure 124-1 ( Figure 1F ) is formed of at least one dielectric material having different etching selectivities and includes the at least one dielectric material. The second dielectric spacer structure 122-2 may, for example, have a selectivity substantially similar to the second insulating structure 106 of the preliminary stacked structure 102 and the first dielectric spacer structure 122-1 ( Figure 1D ). By way of non-limiting example, the second dielectric spacer structure 122-2 may be formed of and include at least one oxygen-containing dielectric material, such as one or more of the following: a dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x and TiO x one or more of the above), dielectric oxynitride materials (e.g., SiO x N y ), and dielectric carbon oxynitride materials (e.g., SiO x C z N y The material composition of the second dielectric spacer structure 122-2 may be different from the first insulating structure 104 and the first dielectric liner structure 124-1 of the preliminary stacked structure 102. Figure 1F The material composition of the second dielectric spacer structure 122-2 may be substantially the same as or may be different from the material composition of the second insulating structure 106 and the first dielectric spacer structure 122-1 ( Figure 1D ) material composition. In some embodiments, the second dielectric spacer structure 122-2 is made of SiO x (e.g., SiO2) formed and including SiO x .

[0062] The second dielectric spacer structure 122-2 may be formed by conformally forming (e.g., by one or more of a conventional ALD process and a conventional conformal CVD process) a dielectric material (e.g., a dielectric oxide material) inside and outside the trench 116 on or over the surface of the preliminary stack structure 102, the first dielectric spacer structure 122-1, the first dielectric liner structure 124-1, and the patterned mask structure 110. Subsequently, the microelectronic device structure 100 may be subjected to at least one material removal (e.g., etching, such as anisotropic dry etching) process to form the second dielectric spacer structure 122-2 (including its first portion 122-2A and second portion 122-2B). The material removal process may substantially (e.g., completely) remove portions of the dielectric material on or over the upper surfaces of patterned mask structure 110, first dielectric spacer structure 122-1, and first dielectric liner structure 124-1; and may partially remove portions of the dielectric material on or over the surface of preliminary stack structure 102 at the modified lower vertical boundary of trench 116. Figure 1G As shown, the material removal process may also remove a portion of the second insulating structure 106 of the layer 108 of the preliminary stacked structure 102 defining the modified lower vertical boundary of the trench 116 to expose (e.g., reveal) a portion of the first insulating structure 104 of the layer 108 within the horizontal boundary of the trench 116. The exposed portion of the first insulating structure 104 of the layer 108 may be horizontally bounded by the second dielectric spacer structure 122-2 within the horizontal boundary of the trench 116.

[0063] Next reference Figure 1H , in reference Figure 1G After the processing stages described, the microelectronic device structure 100 may be subjected to a process similar to that previously described with reference to Figures 1E to 1G Additional processing actions to those described above to fill the remaining portion of the trench 116 with more dielectric liner structures 124 (e.g., in addition to the first dielectric liner structure 124-1) and more dielectric spacer structures 122 (e.g., in addition to the first dielectric spacer structure 122-1 and the second dielectric spacer structure 122-2) Figure 1G ), and form a low-lying structure 126 that vertically underlies and contacts the dielectric liner structure 124 and the dielectric spacer structure 122. Figure 1HAs shown, the depression structure 126 may include: a forward step structure 128 including steps 132 including horizontal ends of paired layers 108 of the preliminary stacked structure 102; a reverse step structure 130 including additional steps 134 including horizontal ends of additional pairs of layers 108 of the preliminary stacked structure 102; and a central region 136 horizontally interposed between the forward step structure 128 and the reverse step structure 130. The central region 136 of the depression structure 126 may, for example, constitute an intersection region and vertical termination location for the forward step structure 128 and the reverse step structure 130. As described in further detail below, different dielectric spacer structures 122 and different dielectric liner structures 124 may be formed to physically contact different steps 132 of the forward step structure 128 and different additional steps 134 of the reverse step structure 130.

[0064] like Figure 1H As shown, a dielectric liner structure 124 ( Figure 1G ) may include: a first dielectric liner structure 124-1 (including a first portion 124-1A and a second portion 124-1B thereof); a second dielectric liner structure 124-2 (including a first portion 124-2A and a second portion 124-2B thereof), which vertically extends relatively deeper into the preliminary stacked structure 102 than the first dielectric liner structure 124-1; a third dielectric liner structure 124-3 (including a first portion 124-3A and a second portion 124-3B thereof), which vertically extends relatively deeper into the preliminary stacked structure 102 than the second dielectric liner structure 124-2; and a fourth dielectric liner structure 124-4 (including a first portion 124-4A and a second portion 124-4B thereof), which vertically extends relatively deeper into the preliminary stacked structure 102 than the third dielectric liner structure 124-3. In additional embodiments, different amounts of dielectric liner structures 124 are formed within the horizontal boundary 120 of the trench 116 ( Figure 1G For example, greater than four (4) (e.g., greater than or equal to ten (10), greater than or equal to twenty (20), greater than or equal to fifty (50)) of the dielectric liner structures 124 may be formed within the horizontal boundary 120 of the trench 116 ( Figure 1G ), or less than four (4) of the dielectric liner structures 124 may be formed within the horizontal boundary 120 of the trench 116 ( Figure 1G ). The amount of dielectric liner structure 124 formed within the horizontal boundaries of trench 116 (e.g., by similarity to the previous reference Figure 1E The processing actions described above) may depend at least in part on the groove 116 ( Figure 1G ), the horizontal dimensions of the dielectric spacer structure 122 and the dielectric liner structure 124.

[0065] Still viewing Figure 1H , the dielectric liner structure 124 may physically contact the first insulating structure 104 of the different layers 108 of the preliminary stacked structure 102 at the step 132 and the additional step 134 of the depression structure 126. Figure 1H As shown, the first portions 124-1A, 124-2A, 124-3A, 124-4A of different dielectric lining structures 124 (e.g., the first dielectric lining structure 124-1, the second dielectric lining structure 124-2, the third dielectric lining structure 124-3, and the fourth dielectric lining structure 124-4) may physically contact at least some of the additional steps 134 of the reverse step structure 130 of the depression structure 126; and the second portions 124-1B, 124-2B, 124-3B, 124-4B of different dielectric lining structures 124 (e.g., the first dielectric lining structure 124-1, the second dielectric lining structure 124-2, the third dielectric lining structure 124-3, and the fourth dielectric lining structure 124-4) may physically contact at least some of the steps 132 of the forward step structure 128 of the depression structure 126.

[0066] like Figure 1H As depicted in FIG. 1 , a dielectric liner structure 124 ( Figure 1G ) may be individually horizontally positioned at horizontal boundaries (e.g., in the X direction, in the Y direction) of the steps 132 and the additional steps 134 of the depressed structures 126 that are in physical contact with the dielectric lining structure 124. In other words, the horizontal boundaries (e.g., the inner horizontal boundaries positioned relatively closer to the central region 136 of the depressed structures 126 than another outer horizontal boundary) of each dielectric lining structure 124 may be substantially coplanar with the horizontal boundaries (e.g., the inner horizontal boundaries positioned relatively closer to the central region 136 of the depressed structures 126 than other outer horizontal boundaries) of the steps 132 and the additional steps 134 of the depressed structures 126 that are in physical contact with the dielectric lining structure 124.

[0067] The dielectric liner structures 124 may alternate horizontally with the dielectric spacer structures 122 within the horizontal boundaries 120 of the trenches 116 ( Figure 1G ). By way of non-limiting example, Figure 1HAs shown, the first dielectric liner structure 124-1 can be horizontally inserted between the first dielectric spacer structure 122-1 and the second dielectric spacer structure 122-2; the second dielectric liner structure 124-2 can be horizontally inserted between the second dielectric spacer structure 122-2 and the third dielectric spacer structure 122-3; the third dielectric liner structure 124-3 can be horizontally inserted between the third dielectric spacer structure 122-3 and the fourth dielectric spacer structure 122-4; and the fourth dielectric liner structure 124-4 can be horizontally inserted between the fourth dielectric spacer structure 122-4 and the fifth dielectric spacer structure 122-5. Each dielectric liner structure 124 can extend horizontally from and between the dielectric spacer structures 122 horizontally adjacent to the dielectric liner structure 124.

[0068] Each of the dielectric liner structures 124 may exhibit a width that is substantially the same as each other of the dielectric liner structures 124 (e.g., in the X direction), or at least one of the dielectric liner structures 124 may exhibit a different width than at least one other of the dielectric liner structures 124. In some embodiments, the dielectric liner structures 124 each respectively exhibit a width that is substantially equal to the vertical height (e.g., in the Z direction) of one or more of the first insulating structures 104 of the preliminary stacked structures 102 that the dielectric liner structures 124 physically contact. As a non-limiting example, the dielectric liner structures 124 may each respectively exhibit the fourth width W4 ( W5 ) previously described with reference to the first dielectric liner structure 124-1. Figure 1G In additional embodiments, at least one dielectric liner structure 124 exhibits a width that is different from (eg, smaller than, larger than) a vertical height of one or more of the first insulating structures 104 of the preliminary stacked structures 102 that the dielectric liner structure 124 physically contacts.

[0069] Still viewing Figure 1H , a dielectric spacer structure 122 ( Figure 1G) may include: a first dielectric spacer structure 122-1 (including a first portion 122-1A and a second portion 122-1B thereof); a second dielectric spacer structure 122-2 (including a first portion 122-2A and a second portion 122-2B thereof), which vertically extends relatively deeper into the preliminary stacked structure 102 than the first dielectric spacer structure 122-1; a third dielectric spacer structure 122-3 (including a first portion 122-3A and a second portion 122-3B thereof), which The first dielectric spacer structure 122-2 vertically extends relatively deeper into the preliminary stacked structure 102 than the second dielectric spacer structure 122-2; the fourth dielectric spacer structure 122-4 (including its first portion 122-4A and second portion 122-4B), which vertically extends relatively deeper into the preliminary stacked structure 102 than the third dielectric spacer structure 122-3; and the fifth dielectric spacer structure 122-5, which vertically extends relatively deeper into the preliminary stacked structure 102 than the fourth dielectric spacer structure 122-4. In additional embodiments, different amounts of dielectric spacer structures 122 are formed within the horizontal boundary 120 of the trench 116 ( Figure 1G For example, greater than five (5) (e.g., greater than or equal to ten (10), greater than or equal to twenty (20), greater than or equal to fifty (50)) dielectric spacer structures 122 may be formed within the horizontal boundary 120 of the trench 116 ( Figure 1G ), or less than five (5) dielectric spacer structures 122 may be formed within the horizontal boundary 120 of the trench 116 ( Figure 1G ). The amount of dielectric spacer structure 122 formed within horizontal boundary 120 of trench 116 (e.g., by similarity to the previous reference Figure 1E The processing actions described above) may depend at least in part on the groove 116 ( Figure 1G ), the horizontal dimensions of the dielectric spacer structure 122 and the dielectric liner structure 124.

[0070] The dielectric spacer structure 122 may be formed horizontally adjacent to the dielectric spacer structure 122 over the different steps 132 and the additional steps 134 of the depression structure 126. Figure 1HAs shown, the first portions 122-1A, 122-2A, 122-3A, 122-4A of different dielectric spacer structures 122 (e.g., the first dielectric spacer structure 122-1, the second dielectric spacer structure 122-2, the third dielectric spacer structure 122-3, and the fourth dielectric spacer structure 122-4) may be formed above and below the horizontal boundaries of at least some of the additional steps 134 of the reverse step structure 130 of the depression structure 126. and second portions 122-1B, 122-2B, 122-3B, 122-4B of different dielectric spacer structures 122 (e.g., first dielectric spacer structure 122-1, second dielectric spacer structure 122-2, third dielectric spacer structure 122-3, fourth dielectric spacer structure 122-4) may be formed above and within horizontal boundaries of at least some of the steps 132 of the forward step structure 128 of the depressed structure 126. The fifth dielectric spacer structure 122-5 may be formed above and within horizontal boundaries of the central region 136 of the depressed structure 126.

[0071] As previously described, the dielectric spacer structures 122 may be horizontally alternating with the dielectric spacer structures 122 within the horizontal boundaries 120 of the trenches 116 ( Figure 1G ). By way of non-limiting example, Figure 1H As shown, the first dielectric spacer structure 122-1 may be horizontally inserted between the first dielectric liner structure 124-1 and the preliminary stacked structure 102 and the patterned mask structure 110 in the trench 116 ( Figure 1G ) at the horizontal boundary 120; the second dielectric spacer structure 122-2 can be horizontally inserted between the first dielectric lining structure 124-1 and the second dielectric lining structure 124-2; the third dielectric spacer structure 122-3 can be horizontally inserted between the second dielectric lining structure 124-2 and the third dielectric lining structure 124-3; the fourth dielectric spacer structure 122-4 can be horizontally inserted between the third dielectric lining structure 124-3 and the fourth dielectric lining structure 124-4; and the fifth dielectric spacer structure 122-5 can be horizontally inserted between the first part 124-4A of the fourth dielectric lining structure 124-4 and the second part 124-4B of the fourth dielectric lining structure 124-4.

[0072] Each of the dielectric spacer structures 122 may exhibit substantially the same width (e.g., in the X direction) as each other of the dielectric spacer structures 122, or at least one of the dielectric spacer structures 122 may exhibit a different width than at least one other of the dielectric spacer structures 122. In some embodiments, a dielectric spacer structure 122 (e.g., the fifth dielectric spacer structure 122-5) positioned within the horizontal boundary of the central region 136 of the depression structure 126 exhibits a different width (e.g., a larger width, a smaller width) than one or more (e.g., each) other of the dielectric spacer structures 122. In additional embodiments, a dielectric spacer structure 122 (e.g., the fifth dielectric spacer structure 122-5) positioned within the horizontal boundary of the central region 136 of the depression structure 126 exhibits substantially the same width (e.g., the third width W3 ( Figure 1G )).

[0073] Continue to view Figure 1H The positive step structure 128 and the reverse step structure 130 of the depression structure 126 may be horizontally opposite to each other (eg, in the X direction) and may be located in the groove 116 ( Figure 1G ). A hatch line extending from the top of the positive step structure 128 (e.g., the vertically uppermost one of the steps 132) to the bottom of the positive step structure 128 (e.g., the vertically lowermost one of the steps 132) may have a positive slope, and another hatch line extending from the top of the reverse step structure 130 (e.g., the vertically uppermost one of the additional steps 134) to the bottom of the reverse step structure 130 (e.g., the vertically lowermost one of the additional steps 134) may have a negative slope. In addition, the upper boundaries (e.g., the upper surfaces) of the steps 132 of the positive step structure 128 may be vertically offset from the upper boundaries (e.g., the upper surfaces) of the additional steps 134 of the reverse step structure 130. In some embodiments, an upper boundary of a step 132 of the forward step structure 128 is vertically offset from (e.g., vertically located below) an upper boundary of an additional step 134 of the reverse step structure 130 that is vertically closest thereto by a distance equal to the thickness of one of the layers 108 of the preliminary stacked structure 102.

[0074] An individual step 132 of the forward step structure 128 of the depressed structure 126 may include the horizontal ends of two vertically adjacent layers 108 of the preliminary stacked structure 102. In addition, an individual additional step 134 of the reverse step structure 130 of the depressed structure 126 may also include the horizontal ends of two vertically adjacent layers 108 of the preliminary stacked structure 102. An individual step 132 of the depressed structure 126 vertically adjacent to an individual additional step 134 of the depressed structure 126 may share a layer 108 of the preliminary stacked structure 102 with the individual additional step 134. For example, one of the two vertically adjacent layers 108 of the preliminary stacked structure 102 associated with (e.g., defining) an individual step 132 may also be one of the two vertically adjacent layers 108 of the preliminary stacked structure 102 associated with an individual additional step 134 vertically adjacent to the individual step 132. The layer 108 shared by the individual step 132 and the individual additional step 134 vertically adjacent to the individual step 132 may be the vertical upper portion of the individual step 132 and the vertical lower portion of the individual additional step 134, or vice versa. As a non-limiting example, the uppermost additional step 134 of the reverse step structure 130 may include the horizontal ends of two vertically adjacent layers 108 of the preliminary stacking structure 102; and the uppermost step 132 of the forward step structure 128 may include the horizontal ends of two additional vertically adjacent layers 108 of the preliminary stacking structure 102, wherein one of the two additional vertically adjacent layers 108 is the same layer 108 as one of the two vertically adjacent layers 108. The first of the two vertically adjacent layers 108 may form an upper portion of the uppermost additional step 134 and may physically contact the first portion 124-1A of the first dielectric liner structure 124-1; and the second of the two vertically adjacent layers 108 may form a lower portion of the uppermost additional step 134 and may not physically contact the first portion 124-1A of the first dielectric liner structure 124-1. The layer 108 forming the lower portion of the upper additional step 134 may in turn constitute the first of the two additional vertically adjacent layers 108 and may form an upper portion of the uppermost step 132 in physical contact with the second portion 124-1B of the first dielectric liner structure 124-1; and the second of the two additional vertically adjacent layers 108 may form a lower portion of the uppermost step 132 and may not physically contact the second portion 124-1B of the first dielectric liner structure 124-1.

[0075] Next reference Fig. 1I , through the patterned mask structure 110 ( Figure 1H ) and the dielectric spacer structure 122 and the dielectric liner structure 124 in the trench 116 ( Figure 1C ) may be removed while maintaining the dielectric spacer structure 122 and the dielectric liner structure 124 in the trench 116 ( Figure 1C) within the vertical boundary (e.g., the lower portion). Fig. 1I As shown, the removal process may expose the uppermost surface of the preliminary stacked structure 102 of the microelectronic device structure 100. The uppermost boundaries (e.g., uppermost surfaces) of the remaining portions (e.g., lower portions) of the dielectric spacer structure 122 and the dielectric liner structure 124 may be substantially coplanar with the exposed uppermost surface of the preliminary stacked structure 102. In other words, after the removal process, the uppermost boundaries (e.g., uppermost surfaces) of the dielectric spacer structure 122, the dielectric liner structure 124, and the preliminary stacked structure 102 may form a substantially flat uppermost surface 138 of the microelectronic device structure 100.

[0076] The patterned mask structure 110 ( Figure 1H ) and the dielectric spacer structure 122 and the dielectric liner structure 124 in the trench 116 ( Figure 1C ) can be removed using conventional processes (eg, conventional etching processes, conventional planarization processes), which are not described in detail herein. For example, the patterned mask structure 110 ( Figure 1H ) and the dielectric spacer structure 122 and the dielectric liner structure 124 in the trench 116 ( Figure 1C ) outside the vertical boundary (e.g., an upper portion) can be removed using one or more of an etching process (e.g., a wet etching process) and a chemical mechanical planarization (CMP) process.

[0077] Next reference Figure 1J The capping material 140 may be formed on the substantially planar uppermost surface 138 ( Fig. 1I ) on or above the microelectronic device structure 100. The capping material 140 may be continuous across the substantially planar uppermost surface 138 ( Fig. 1I ) extending horizontally. Capping material 140 may cover (e.g., cap) an uppermost surface of dielectric liner structure 124 and may facilitate replacement of dielectric material of at least some of dielectric liner structure 124 and first insulating structure 104 of preliminary stacked structure 102 with one or more conductive materials by a so-called “replacement gate” or “gate-sustaining” process action, as described in further detail below.

[0078] The capping material 140 may be formed of and include at least one dielectric material having an etching selectivity different from that of the first insulating structure 104 and the dielectric liner structure 124 of the preliminary stacked structure 102. The capping material 140 may, for example, have an etching selectivity substantially similar to that of the second insulating structure 106 and the dielectric spacer structure 122 of the preliminary stacked structure 102. By way of non-limiting example, the capping material 140 may be formed of and include at least one oxygen-containing dielectric material, such as one or more of the following: a dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x and TiO x one or more of the above), dielectric oxynitride materials (e.g., SiO x N y ), and dielectric carbon oxynitride materials (e.g., SiO x C z N y ). The material composition of the capping material 140 may be different from the material composition of the first insulating structure 104 and the dielectric liner structure 124 of the preliminary stacked structure 102. The material composition of the capping material 140 may be substantially the same as or may be different from the material composition of the second insulating structure 106 and the dielectric spacer structure 122 of the preliminary stacked structure 102. In some embodiments, the capping material 140 is made of SiO x (e.g., SiO2) formed and containing SiO x .

[0079] The capping material 140 may be formed using conventional processes (e.g., conventional deposition processes such as one or more of PVD, CVD, ALD, and spin coating; conventional material removal processes such as conventional polishing processes). Such processes are known in the art and are therefore not described in detail herein. In some embodiments, the dielectric material is conventionally deposited on the substantially planar uppermost surface 138 ( Fig. 1I ) to form capping material 140, and then capping material 140 is subjected to at least one polishing process (e.g., at least one lapping process) to reduce (e.g., substantially remove) undesirable irregularities (e.g., deviations from flatness) at its uppermost surface. The uppermost surface of capping material 140 may be substantially flat.

[0080] Next reference Figure 1K , a dielectric liner structure 124 (eg, Figure 1JThe first portion (eg, Figure 1J The first portion 124-1A, 124-2A, 124-3A, 124-4A) shown in FIG. 1 may be connected to the dielectric liner structure 124 ( Figure 1J ) (for example, Figure 1J The second portion 124-1B, 124-2B, 124-3B, 124-4B) shown in FIG. 1 is physically separated (eg, physically separated); and the dielectric liner structure 124 ( Figure 1J ) and the preliminary stacking structure 102 ( Figure 1J ) of the first insulating structure 104 ( Figure 1J ) may be at least partially replaced with a conductive material to remove the dielectric material from the first insulating structure 104 ( Figure 1J ) to form a conductive structure 142, from the dielectric liner structure 124 ( Figure 1J ) forms a conductive contact structure 144, and from the dielectric liner structure 124 ( Figure 1J ) forms an additional conductive contact structure 146. Figure 1K As shown, the process can modify the preliminary stack structure 102 ( Figure 1J ) of layer 108( Figure 1J ) to form a stacked structure 148, which includes a vertically alternating (eg, in the Z direction) sequence of conductive structures 142 and insulating structures 150 arranged in a modified layer 152. The insulating structures 150 may correspond to the preliminary stacked structure 102 ( Figure 1J ) of the second insulating structure 106 ( Figure 1J ) of the remaining portion (eg, remaining portion, unremoved portion). The modified layer 152 of the stacked structure 148 may be formed from the preliminary stacked structure 102 ( Figure 1J ) of layer 108( Figure 1J ) is formed and corresponds to the layer. The modified layers 152 of the stacked structure 148 may each include a conductive structure 142 vertically adjacent to the insulating structure 150. Figure 1J ) of the first insulating structure 104 ( Figure 1J ) is replaced by the conductive structure 142, the modified layer 152 of the stacked structure 148 may also include the first insulating structure 104 ( Figure 1J )'s remaining portion (e.g., remaining portion, unremoved portion).

[0081] The dielectric liner structure 124 is formed by removing (eg, etching) a region at the intersection of the first portion and the second portion thereof, and then replacing the dielectric liner structure 124 with a dielectric liner having a dielectric layer that is consistent with the dielectric liner structure 124 and the preliminary stacked structure 102 ( Figure 1J ) of the first insulating structure 104 ( Figure 1J ) fills the resulting opening with at least one electrically insulating material having a different etch selectivity, and the dielectric liner structure 124 (eg, Figure 1J The first portion (eg, Figure 1J The first portion 124-1A, 124-2A, 124-3A, 124-4A) shown in FIG. 1 may be connected to the dielectric liner structure 124 ( Figure 1J ) (for example, Figure 1J The electrical insulating material may be, for example, selectively substantially similar to the preliminary stacking structure 102 ( Figure 1J ) of the second insulating structure 106 ( Figure 1J ) and etching of the dielectric spacer structure 122. The material composition of the electrically insulating material may be substantially the same as or may be different from that of the second insulating structure 106 ( Figure 1J ) of the material composition and dielectric spacer structure 122 ( Figure 1J In some embodiments, the electrically insulating material is SiO x (e.g., SiO2) formed and containing SiO x .

[0082] In some embodiments, the dielectric liner structures 124 ( Figure 1J ) (for example, Figure 1J The first part 124-1A, 124-2A, 124-3A, 124-4A and the second part (eg, Figure 1J 1B, 124-2B, 124-3B, 124-4B) is controlled to physically separate substantially only the first and second portions of the dielectric liner structure 124 from each other. The material removal process may, for example, form discrete openings that extend vertically through individual dielectric liner structures 124 but not through dielectric spacer structures 122 that are horizontally adjacent to the dielectric liner structure 124. The discrete openings may then be filled with an electrically insulating material to form discrete pillar structures (e.g., discrete cylindrical structures) that are horizontally inserted between the separated portions of the dielectric liner structure 124 in a first horizontal direction and between the horizontally adjacent dielectric spacer structures 122 in a second horizontal direction orthogonal to the first horizontal direction.

[0083] In additional embodiments, the dielectric liner structures 124 are physically separated from each other. Figure 1J ) (for example, Figure 1JThe first part 124-1A, 124-2A, 124-3A, 124-4A and the second part (eg, Figure 1J The material removal process of the second portion 124-1B, 124-2B, 124-3B, 124-4B) shown in FIG. 1 is controlled to also remove the individual dielectric spacer structures 122 (eg, Figure 1J The first portion (eg, Figure 1J The first part 122-1A, 122-2A, 122-3A, 122-4A and the second part (eg, Figure 1J The material removal process may, for example, form at least one linear opening (e.g., at least one trench) extending vertically through the individual dielectric liner structures 124 and the individual dielectric spacer structures 122 horizontally adjacent to the individual dielectric liner structures 124. The linear opening may then be filled with an electrically insulating material to form at least one linear pillar structure (hereinafter referred to as a linear pillar structure). Figure 2 Further described in detail) (e.g., a horizontally elongated rectangular column structure), which is horizontally inserted between the separated portions of the individual dielectric liner structures 124 and the separated portions of the individual dielectric spacer structures 122 in a first horizontal direction; and continuously extends horizontally through the dielectric liner structures 124 and the dielectric spacer structures 122 horizontally adjacent to each other in a second horizontal direction orthogonal to the first horizontal direction.

[0084] In addition to physically separating the individual dielectric liner structures 124 ( Figure 1J ) of at least a first portion (e.g., Figure 1J The first part 124-1A, 124-2A, 124-3A, 124-4A and the second part (eg, Figure 1J In addition to the second portions 124-1B, 124-2B, 124-3B, 124-4B shown in FIG. 1 , structures (e.g., pillar structures, linear pillar structures) formed between the separated portions of the individual dielectric liner structures 124 may also be used to modify the preliminary stacked structure 102 ( FIG. 1 ) during so-called “replacement gate” or “gate-sustaining” processing actions. Figure 1J ) provide structural support to form the conductive structure 142, the conductive contact structure 144, and the additional conductive contact structure 146. The structure may, for example, prevent undesirable layer deformation (e.g., layer distortion) and / or layer collapse during the formation of the conductive structure 142, the conductive contact structure 144, and the additional conductive contact structure 146. The preliminary stacked structure 102 ( Figure 1J) at desired locations within the preliminary stacked structure 102 (e.g., pillar structures, such as dielectric pillar structures) to provide support for the preliminary stacked structure 102 ( Figure 1J ) provide further structural support.

[0085] Continue to view Figure 1K , the amount and position (eg, horizontal position, vertical position) of the conductive contact structure 144 may correspond to the dielectric liner structure 124 ( Figure 1J ) of the first portion; and the amount and position (eg, horizontal position, vertical position) of the additional conductive contact structure 146 may correspond to the dielectric liner structure 124 ( Figure 1J ) of the second part. As a non-limiting example, Figure 1K As shown, the conductive contact structure 144 may include a conductive contact structure 144-1, a second conductive contact structure 144-2, a third conductive contact structure 144-3 and a fourth conductive contact structure 144-4, which respectively correspond to the first dielectric liner structure 124-1 ( Figure 1J ) Part 124-1A( Figure 1J )、Second dielectric liner structure 124-2 ( Figure 1J ) Part 124-2A( Figure 1J ), the third dielectric liner structure 124-3 ( Figure 1J ) Part 124-3A( Figure 1J ), and the fourth dielectric liner structure 124-4 ( Figure 1J ) Part 124-4A( Figure 1J As another non-limiting example, Figure 1K As shown in FIG. 1 , the additional conductive contact structure 146 may include a first additional conductive contact structure 146-1, a second additional conductive contact structure 146-2, a third additional conductive contact structure 146-3, and a fourth additional conductive contact structure 146-4, which correspond to the first dielectric liner structure 124-1 ( Figure 1J ) Part 2 124-1B( Figure 1J ), the second dielectric liner structure 124-2 ( Figure 1J ) Part 2 124-2B( Figure 1J ), the third dielectric liner structure 124-3 ( Figure 1J ) Part II 124-3B( Figure 1J ) and the fourth dielectric liner structure 124-4 ( Figure 1J ) Part 2 124-4B( Figure 1J ).

[0086] like Figure 1K As shown, the conductive contact structure 144 may be integral and continuous with some of the conductive structures 142 of the modified stacked structure 148, and the additional conductive contact structure 146 may be integral and continuous with some other of the conductive structures 142 of the modified stacked structure 148. For example, the individual conductive contact structure 144 may be integral and continuous with the individual conductive structure 142 of the modified stacked structure 148 at the additional step 134 of the reverse step structure 130 of the depression structure 126, and the individual additional conductive contact structure 146 may be integral and continuous with other individual conductive structures 142 of the modified stacked structure 148 at the step 132 of the forward step structure 128 of the depression structure 126. The individual conductive contact structure 144 and the individual conductive structure 142 in physical contact therewith may constitute different parts of the individual monolithic structure. As a non-limiting example, the first conductive contact structure 144-1 and one of the conductive structures 142 of the modified stacked structure 148 in physical contact therewith (e.g., at the uppermost additional step 134 of the reverse stepped structure 130) may together form a first monolithic structure including the first conductive contact structure 144-1 and the one of the conductive structures 142. In addition, the individual additional conductive contact structures 146 and the other individual conductive structures 142 in physical contact therewith may constitute different parts of the other individual monolithic structures. As a non-limiting example, the first additional conductive contact structure 146-1 and the other one of the conductive structures 142 of the modified stacked structure 148 in physical contact therewith (e.g., at the uppermost step 132 of the forward stepped structure 128) may together form a first additional monolithic structure including the first additional conductive contact structure 146-1 and the other one of the conductive structures 142.

[0087] The conductive structure 142, the conductive contact structure 144, and the additional conductive contact structure 146 may each be formed of and include at least one conductive material, such as one or more of a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material. By way of non-limiting example, the conductive structure 142, the conductive structure 142, the conductive contact structure 144, and the additional conductive contact structure 146 may each be formed of and include one or more of: tungsten (W), tungsten nitride (WN y ), nickel (Ni), tantalum (Ta), tantalum nitride (TaN y ), Tantalum silicide (TaSi x ), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN y ), titanium silicide (TiSi x ), titanium silicon nitride (TiSix N y ), titanium aluminum nitride (TiAl x N y ), molybdenum nitride (MoN x ), iridium (Ir), iridium oxide (IrO z ), ruthenium (Ru), ruthenium oxide (RuO z ), and conductively doped silicon. In some embodiments, the conductive structure 142, the conductive contact structure 144, and the additional conductive contact structure 146 are each formed of and include tungsten (W).

[0088] Continue to view Figure 1K In order to form the modified stack structure 148 (including the conductive structure 142 and the insulating structure 150 thereof), the conductive contact structure 144, and the additional conductive contact structure 146, a slot (e.g., a slit, a trench) may be formed extending vertically through the dielectric spacer structure 122, the dielectric liner structure 124 ( Figure 1J ) and the preliminary stacking structure 102 ( Figure 1J ) to form discrete blocks. The slots and blocks may each extend in a first horizontal direction (e.g., X direction); and the slots and blocks may alternate with each other in a second horizontal direction (e.g., Y direction) orthogonal to the first horizontal direction. The dielectric liner structure 124 ( Figure 1J ) and the preliminary stacking structure 102 ( Figure 1J ) of the first insulating structure 104 ( Figure 1J Subsequently, the dielectric liner structure 124 ( Figure 1J ) and the first insulating structure 104 ( Figure 1J ) to form the conductive structure 142, the conductive contact structure 144, and the additional conductive contact structure 146. The slots may then be filled with at least one dielectric material.

[0089] Next reference Figure 1L, dielectric structure 154 may be formed on or over capping material 140; portions of dielectric structure 154 and capping material 140 may be removed (e.g., etched) to form openings (e.g., vias, pores) exposing portions of conductive contact structure 144 and additional conductive contact structure 146; and conductive plug structure 156 may then be formed within the openings in contact (e.g., physical contact, electrical contact) with conductive contact structure 144 and additional conductive contact structure 146. Conductive plug structure 156 may facilitate electrical communication between additional conductive structures (e.g., conductive line structures, such as access line structures) to be formed over depression structure 126 (and therefore, additional structures and / or devices to be electrically coupled to the additional conductive structures, such as one or more control devices) and conductive contact structure 144 and additional conductive contact structure 146.

[0090] The dielectric structure 154 may be formed of and include at least one dielectric material having a different etching selectivity from the capping material 140. The dielectric structure 154 may serve as a mask for patterning the capping material 140. The dielectric structure 154 may be selectively etched relative to the capping material 140 during mutual exposure to a first etchant, and the capping material 140 may be selectively etched relative to the dielectric structure 154 during mutual exposure to a second, different etchant. The material composition of the dielectric structure 154 is different from the material composition of the capping material 140, and may include at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ) and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ) In some embodiments, the dielectric structure 154 is made of SiN y (e.g., Si3N4) formed and containing SiN yThe dielectric structure 154 may be substantially homogeneous, or may be substantially heterogeneous. In some embodiments, the dielectric structure 154 is substantially homogeneous. In additional embodiments, the dielectric structure 154 is substantially heterogeneous. The dielectric structure 154 may be substantially planar, and may exhibit a desired thickness (eg, height in the Z direction).

[0091] The conductive plug structure 156 can be formed of at least one conductive material and contain at least one conductive material, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, steel, low-carbon steel, stainless steel), a conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), and a conductive doped semiconductor material (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe). Each of the conductive plug structures 156 may have substantially the same material composition, or at least one of the conductive plug structures 156 may have a different material composition than at least one other of the conductive plug structures 156 .

[0092] The conductive plug structures 156 may each be provided at a desired horizontal position (e.g., in the X direction and the Y direction) on or above one of the conductive contact structures 144 or one of the additional conductive contact structures 146, respectively. The conductive plug structures 156 may each contact a single (e.g., only one) conductive contact structure 144 or a single (e.g., only one) additional conductive contact structure 146, respectively. In some embodiments, each of the conductive plug structures 156 is individually substantially horizontally centered on one of the conductive contact structures 144 or one of the additional conductive contact structures 146. In additional embodiments, one or more of the conductive plug structures 156 are individually horizontally offset (e.g., in the X direction and / or in the Y direction) from the horizontal center of the conductive contact structure 144 or the additional conductive contact structure 146 with which they are in contact. Additionally, as Figure 1LAs shown, in some embodiments, at least some of the conductive plug structures 156 are substantially horizontally aligned with each other. For example, at least some (e.g., all) of the conductive plug structures 156 that are horizontally adjacent to each other in a first horizontal direction (e.g., the X direction) may be substantially aligned with each other in a second horizontal direction (e.g., the Y direction) that is orthogonal to the first horizontal direction. In additional embodiments, at least some of the conductive plug structures 156 are offset from each other in multiple horizontal directions (e.g., the X direction and the Y direction). For example, at least some (e.g., all) of the conductive plug structures 156 that are horizontally adjacent to each other in a first horizontal direction (e.g., the X direction) may be offset from each other in a second horizontal direction (e.g., the Y direction) that is orthogonal to the first horizontal direction.

[0093] The dielectric structure 154 and the conductive plug structure 156 may be formed using conventional processes (eg, conventional material deposition processes, conventional photolithography processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein.

[0094] Therefore, according to an embodiment of the present disclosure, a method of forming a microelectronic device includes forming a preliminary stacked structure, the preliminary stacked structure including a vertical alternating sequence of insulating structures and additional insulating structures arranged in layers. Each of the layers includes one of the insulating structures and one of the additional insulating structures. A trench is formed to extend vertically into the preliminary stacked structure. A horizontal alternating sequence of dielectric spacer structures and dielectric liner structures is formed within the horizontal boundaries of the trench. At least some of the dielectric liner structures physically contact the insulating structures of the preliminary stacked structures that are different from each other. The dielectric material of the dielectric liner structures and the insulating structures of the preliminary stacked structure are at least partially replaced by a conductive material.

[0095] In addition, according to an embodiment of the present disclosure, a microelectronic device includes a stacked structure, a depression structure within the stacked structure, and a conductive contact structure. The stacked structure includes a vertical alternating sequence of conductive structures and insulating structures arranged in layers. Each of the layers includes one of the conductive structures and one of the insulating structures. The depression structure includes: a forward step structure having a step including an edge of the layer; and a reverse step structure, which is opposite to the forward step structure and has an additional step including an additional edge of the layer. The conductive contact structure extends vertically to the upper vertical boundary of at least some of the conductive structures of the stacked structure at the steps of the forward step structure and the additional steps of the reverse step structure. The conductive contact structures are each integral and continuous with one of the conductive structures.

[0096] According to the microelectronic device structure of the embodiment of the present disclosure (for example, the previously referenced Figure 1LThe microelectronic device structure 100 described herein may be included in an embodiment of a microelectronic device (eg, a memory device, such as a 3D NAND flash memory device) of the present disclosure. For example, Figure 2 A simplified partial top view of a microelectronic device 200 is illustrated that includes a microelectronic device structure 201. The microelectronic device structure 201 may be substantially similar to that described in the previous reference. Figure 1L The microelectronic device structure 100 is depicted at a processing stage.

[0097] See also Figure 2 , the microelectronic device 200 includes a stacked structure 202, which includes a vertically alternating (eg, in the Z direction) sequence of conductive structures and insulating structures arranged in layers. The stacked structure 202 may be substantially similar to the previously described Figure 1K The modified stacking structure 148 is described. Figure 2 As shown, the stacked structures 202 may be separated in the Y direction by slots 203. The slots 203 may be filled with a dielectric material and correspond to the previously referenced formation of the conductive structure 142, the conductive contact structure 144, and the additional conductive contact structure 146 by a so-called "replacement gate" or "gate-sustaining" process action. Figure 1K The slots 203 can divide the stacked structure 202 (e.g., in the Y direction) into a plurality of blocks 205. In addition, the stacked structure 202 includes a memory array region 207 and a distributed low-lying region 209 horizontally adjacent (e.g., in the X direction) to the memory array region 207. As described in further detail below, the microelectronic device 200 also includes additional components (e.g., features, structures, devices) within the boundaries of different horizontal regions (e.g., memory array region 207, distributed low-lying region 209) of the stacked structure 202.

[0098] Within the horizontal boundaries of the memory array region 207 of the stacked structure 202, the microelectronic device 200 can include a vertically extending pillar structure 211. The vertically extending pillar structure 211 can extend vertically (e.g., in the Z direction) from, for example, a data line 215 (e.g., a digit line, a bit line) or near the data line, through the memory array region 207 of the stacked structure 202, and to, for example, a source structure 217 (e.g., a source plate) or near the source structure. Figure 2 , the source structure 217 is represented by a dashed line to indicate that the source structure 217 can be located vertically below the stacked structure 202. Each of the vertically extending pillar structures 211 can include a semiconductive pillar (e.g., a polysilicon pillar, a silicon germanium pillar) that is at least partially surrounded by one or more charge storage structures (e.g., a charge trapping structure, such as a charge trapping structure including an oxide-nitride-oxide ("ONO") material; a floating gate structure). The layers of the stacked structure 202 (e.g., corresponding to the previous reference Figure 1KThe modified layer 152 described above may include vertically extending pillar structures 211 and conductive structures (eg, corresponding to the previously described modified layer 152). Figure 1K The intersection of the conductive structures 142 described above can define a vertically extending (e.g., in the Z direction) memory cell string 223 that is coupled in series with each other within the memory array region 207 of the stacked structure 202. In some embodiments, the memory cells 223 formed at the intersection of the conductive structures and the vertically extending pillar structures of the layers of the stacked structure 202 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 223 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In further embodiments, the memory cells 223 include so-called "floating gate" memory cells that include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally interposed between the vertically extending pillar structures 211 of the different layers of the stacked structure 202 and the central structure of the conductive structure. The microelectronic device 200 may include any desired amount and distribution of vertically extending pillar structures 211 within the memory array region 207 of the stacked structure 202 .

[0099] Continue to view Figure 2 , within the horizontal boundaries of the distributed depressions 209 of the stacked structure 202, the microelectronic device 200 may include depressions 226 distributed within the stacked structure 202. The depressions 226 may individually have a geometric configuration (e.g., shape and size) substantially similar to that previously described with respect to the depressions 126 (including the geometric configurations of the forward step structures 128, the reverse step structures 130, and the central region 136 thereof) ( Figures 1H to 1L ), except that at least some of the low-lying structures 226 may be positioned at different elevations (e.g., vertical positions in the Z direction) from each other within the stacked structure 202. In addition to at least some of the different elevations within the stacked structure 202, each of the low-lying structures 226 may have a substantially identical geometric configuration (e.g., substantially identical shapes and sizes, including substantially identical shapes and sizes of individual components thereof, and substantially identical shapes and sizes resulting from a combination of different components thereof) as each other of the low-lying structures 226. In additional embodiments, at least one of the low-lying structures 226 has a different geometric configuration (e.g., a different shape and / or one or more different sizes, including substantially different shapes and / or one or more different sizes of one or more individual components thereof, and / or a different shape and / or one or more different sizes resulting from a combination of different components thereof) than at least one other low-lying structure of the low-lying structures 226.

[0100] like Figure 2 As shown, the portions of the individual blocks 205 of the stacked structure 202 within the distributed depressions 209 of the stacked structure 202 may include segments of the individual depression structures 226 separated (e.g., divided, segmented, isolated) from other segments of the individual depression structures 226 by the slots 203. For example, the first segment 226A of the individual (e.g., single, one) depression structure 226 may be located within the first of the blocks 205 of the stacked structure 202 and partially (e.g., less than completely) span its horizontal extension (e.g., in the Y direction), and the second segment 226B of the individual depression structure 226 may be located within the second of the blocks 205 horizontally adjacent (e.g., in the Y direction) to the first of the blocks 205 and partially (e.g., less than completely) span its horizontal extension (e.g., in the Y direction). One of the slots 203 may be horizontally inserted (e.g., in the Y direction) between the first segment 226A of the individual depression structure 226 and the second segment 226B of the individual depression structure 226. Individual blocks 205 of the stacked structure 202 may include first sections 226A of a plurality of the depressions 226, and second sections 226B of a plurality of other depressions 226. Figure 2 As shown, within individual blocks 205 of the stacked structure 202, multiple first sections 226A of the low-lying structures 226 may be substantially horizontally aligned with each other in a first horizontal direction (e.g., the X direction), multiple second sections 226B of other low-lying structures in the low-lying structures 226 may also be substantially horizontally aligned with each other in the first horizontal direction (e.g., the X direction), and multiple first sections 226A of the low-lying structures 226 may be horizontally adjacent to multiple second sections 226B of other low-lying structures in the low-lying structures 226 in a second horizontal direction (e.g., the Y direction) that is orthogonal to the first horizontal direction.

[0101] Continue to view Figure 2 In the individual blocks 205 of the stacked structure 202, the word line bridge region 213 may extend horizontally continuously from and between sections of different depression structures 226 located within the horizontal boundaries (e.g., in the X direction and the Y direction) of the blocks 205 of the stacked structure 202. Figure 2 As shown, for a given block 205 of the stacked structure 202, its word line bridge region 213 may extend horizontally continuously from and between the first section 226A and the second section 226B of different low-lying structures 226 located within the horizontal boundary of the block 205. The word line bridge region 213 may include conductive structures of the stacked structure 202 (e.g., corresponding to the previously described conductive structures) extending horizontally continuously from and between the sections of the different low-lying structures 226. Figure 1KThe word line bridge region 213 facilitates proper word line driving using the die center step location and configuration.

[0102] Still viewing Figure 2 In the individual blocks 205 of the stacked structure 202, the conductive contact structure 244 and the additional conductive contact structure 246 may be provided at the steps (eg, corresponding to the steps in the previous reference) of the sections (eg, the first section 226A, the second section 226B) of the depression structure 226. Figures 1H to 1L described step 132) and additional steps (eg, corresponding to the steps previously described in reference Figures 1H to 1L The additional step 134 described above is integral and continuous with the conductive structure of the stack structure 202. The conductive contact structure 244 and the additional conductive contact structure 246 may correspond to the previously described conductive contact structure 244. Figure 1K The conductive contact structure 144 and the additional conductive contact structure 146 are described. Figure 2 As shown, the dielectric spacer structure 222 may be horizontally interposed between and separate the horizontally adjacent conductive contact structure 244 and the horizontally adjacent additional conductive contact structure 246; and the additional dielectric structure 245 may be horizontally interposed between and separate the conductive contact structure 244 horizontally adjacent to the additional conductive contact structure 246. The dielectric spacer structure 222 may correspond to the previously described Figures 1I to 1L The dielectric spacer structure 122 described above; and the additional dielectric structure 245 may correspond to the previously described dielectric spacer structure 122; Figure 1K Discrete column structures and / or linear column structures described.

[0103] Additionally, within the individual blocks 205 of the stacked structure 202, the conductive plug structures 256 may contact (eg, physically contact, electrically contact) the conductive contact structures 244 and the additional conductive contact structures 246. The conductive plug structures 256 may correspond to the previously referenced Figure 1LConductive plug structure 156 is depicted. Conductive plug structure 256 can, for example, be connected (eg, physically connected, electrically connected) to an access line 219 (eg, a word line) of microelectronic device 200 . The access line 219 can be formed of and include at least one conductive material, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel), a conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), and a conductive doped semiconductor material (e.g., conductive doped Si, conductive doped Ge, conductive doped SiGe).

[0104] Still viewing Figure 2 , the microelectronic device 200 may also include at least one control unit 221 (e.g., a control device). The control unit 221 may include one or more of a string driver circuit, a pass gate, a circuit for selecting a gate, a circuit for selecting a conductive line, a circuit for amplifying a signal, and a circuit for sensing a signal. The control unit 221 may, for example, be electrically coupled to the data line 215, the source structure 217, and the access line 219. In some embodiments, the control unit 221 is vertically located below the memory array region 207 of the stacked structure 202 (e.g., in the Z direction) and is generally confined within the horizontal boundaries of the memory array region. Figure 2 2, the control unit 221 is represented by a dashed line to indicate that the control unit 221 can be located vertically below the stacked structure 202. The control unit 221 can be located vertically below the source structure 217 of the microelectronic device 200. In some embodiments, the control unit 221 includes CMOS circuitry. In some such embodiments, the control unit 221 can be characterized as having a "CMOS under array" ("CuA") configuration.

[0105] Next reference Figure 3 , according to the microelectronic device structure of the embodiment of the present disclosure (for example, previously referenced Figure 1L The described microelectronic device structure 100 may be included in additional embodiments of the microelectronic devices of the present disclosure (e.g., additional memory devices, such as additional 3D NAND flash memory devices). For example, Figure 3 A simplified partial top view of a microelectronic device 300 is illustrated that includes a microelectronic device structure 301. The microelectronic device structure 301 may be substantially similar to that described in the previous reference. Figure 1LThe microelectronic device structure 100 is shown at a processing stage as described. Figure 3 and the associated description below, are functionally similar to the previous reference Figure 2 Features (eg, structures, materials, regions) of the described microelectronic device 200 are referred to by like reference numerals incremented by 100. To avoid repetition, the present invention is not described in detail herein. Figure 3 Unless otherwise described below, all features shown in Figure 3 In the previous reference Figure 2 Reference numerals incremented by 100 denote features described herein that will be understood to be substantially similar to previously described features.

[0106] like Figure 3 As shown, within the horizontal boundaries of the distributed depressions 309 of the stacked structure 302, the microelectronic device 300 may include a depression 326 having the same structure as previously described. Figure 2 The described microelectronic device 200 has different horizontal geometric configurations (e.g., different horizontal shapes, different horizontal sizes) of the depression structures 226. For example, individual depression structures 326 within the distributed depression region 309 can be configured so that different sections of the individual depression structures 326 extend horizontally substantially (e.g., completely) across individual blocks 305 of the stacked structure 302 in a first horizontal direction (e.g., the Y direction) and are separated from each other by slots 303 extending horizontally in a second horizontal direction (e.g., the X direction) orthogonal to the first horizontal direction. For example, a first section 326A of an individual (e.g., a single, one) depression structure 326 can be located within and extend substantially horizontally (e.g., in the Y direction) across a first one of the blocks 305 of the stacked structure 302, and a second section 326B of the individual depression structure 226 can be located within and extend substantially horizontally (e.g., in the Y direction) across a second one of the blocks 205 that is horizontally adjacent (e.g., in the Y direction) to the first one of the blocks 205. One of the slots 303 may be horizontally inserted (e.g., in the Y direction) between a first section 326A of an individual low-lying structure 326 and a second section 326B of an individual low-lying structure 326. A first block 305 of the stacked structure 302 may include a plurality of first sections 326A of the low-lying structures 326 separated from one another in the X direction and each extending substantially horizontally across the first block 305 in the Y direction; and a second block 305 horizontally adjacent to the first block 305 in the Y direction may include a plurality of second sections 326B of the low-lying structures 326 separated from one another in the X direction and each extending substantially horizontally across the second block 305 in the Y direction.

[0107] like Figure 3 As shown, the low-lying structure 326 of a given microelectronic device 300 is relatively large relative to the microelectronic device 200 ( Figure 2) of low-lying structures 226( Figure 2 ) of those horizontal geometric configurations, the individual blocks 305 of the stacked structure 302 do not contain substantially similar to the previously referenced Figure 2 Rather, since different sections (e.g., first section 326A, second section 326B) of individual depression structures 326 extend generally horizontally (e.g., in the Y direction) across individual blocks 305 of stacked structures 302 with which they are associated, such word line bridging regions may not exist (e.g., be omitted) in blocks 305 of stacked structures 302. Figure 3 The configuration of the microelectronic device 300 shown facilitates proper word line driving using die end step locations and configurations.

[0108] Therefore, according to an embodiment of the present disclosure, a memory device includes a stacked structure, a depression structure, a conductive contact structure, and a memory cell string. The stacked structure has several layers, each of which includes a conductive structure and an insulating structure vertically adjacent to the conductive structure. The depression structures are positioned at different vertical depths from each other within the stacked structure. Each of the depression structures includes: a forward step structure having a step including a horizontal end of a group of layers; and a reverse step structure, which is opposite to the forward step structure and has an additional step including an additional horizontal end of the group of layers. The conductive contact structure extends vertically from at least some of the conductive structures of the stacked structure at the steps and additional steps of the depression structure. The conductive contact structures are each integral and continuous with one of the conductive structures. The memory cell string extends vertically through the stacked structure.

[0109] Return to reference Figure 1L In additional embodiments, the microelectronic device structure of the present disclosure is formed to have Figure 1L 1 and 2. The microelectronic device structure 100 may be configured in different processing stages as depicted in FIG. By way of non-limiting example, Figures 4A to 4C is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device structure 400 according to additional embodiments of the present disclosure. Figure 4A The method of forming a microelectronic device structure 400 at the processing stages depicted in the foregoing description incorporates the foregoing descriptions up to and including the foregoing descriptions. Figure 1E The processing actions and features are described with respect to the formation of the microelectronic device structure 100 with reference to the described processing stages. Figures 4A to 4C The processing stages depicted in and described in further detail below may, for example, include replacements and / or combinations of previously referenced Figures 1F to 1L Described to form the previous reference Figure 1L The processing actions performed by the microelectronic device structure 100 are described. Figures 4A to 4C and the associated description below, are functionally similar to the previous reference Figures 1A to 1LFeatures (eg, structures, materials, regions) of one or more of the features of the microelectronic device structure 100 described in the accompanying drawings are referred to by like reference numerals incremented by 100. To avoid repetition, the microelectronic device structure 100 will not be described in detail herein. Figures 4A to 4C Rather, unless otherwise described below, Figures 4A to 4C In the previous reference Figures 1A to 1L Reference numerals that increment the reference numerals of one or more of the described features by 100 denote features that will be understood to be substantially similar to previously described features.

[0110] like Figure 4A As shown, in the formation of the first dielectric liner structure 424-1 (e.g., by substantially similar to the previous reference Figure 1E ), the microelectronic device structure 400 may be subjected to at least one additional material removal (e.g., etching, such as anisotropic dry etching) process to increase the vertical depth (e.g., in the Z direction) of the remaining (e.g., unfilled) portion of the trench 416 formed in the preliminary stack structure 402. As described in further detail below, similar to the previously described reference 402, Figure 1F 4. The additional material removal process may increase the vertical depth of the remaining portion of the trench 416 by a relatively greater amount than the increase in the vertical depth of the remaining portion of the trench 416 described above. The additional material removal process may increase the vertical depth of the remaining portion of the first region 416A of the trench 416, and may also increase the vertical depth of the remaining portion of the second region 416B of the trench 416. After the additional material removal process, the remaining portion of the second region 416B of the trench 416 may extend vertically to a relatively lower depth within the preliminary stack structure 402 than the remaining portion of the first region 416A of the trench 416. The magnitude of the vertical offset between the lower vertical boundary of the first region 416A of the trench 416 and the lower vertical boundary of the second region 416B of the trench 416 may be substantially maintained at the end of the additional material removal process. For example, the additional material removal process may increase the vertical depth of each of the remaining portion of the first region 416A of the trench 416 and the remaining portion of the second region 416B of the trench 416 by a distance (e.g., in the Z direction) that is greater than or equal to the combined height (e.g., in the Z direction) of the at least two (e.g., at least three) layers 408 of the preliminary stacked structure 402. Figure 4A As shown, in some embodiments, the additional material removal process increases the vertical depth of each of the remaining portion of the first region 416A of the trench 416 and the remaining portion of the second region 416B of the trench 416 by a distance that is substantially equal to the combined height of three (3) of the layers 408 of the preliminary stacked structure 402.

[0111] Next reference Figure 4B , in reference Figure 4AAfter the processing stages described, the microelectronic device structure 400 may be subjected to a process generally similar to that previously described with reference to Figure 1D , 1E 4A to fill trench 416 with more dielectric liner structures 424 (e.g., in addition to first dielectric liner structure 424-1) and more dielectric spacer structures 422 (e.g., in addition to first dielectric spacer structure 422-1). Figure 4A ) and form a low-lying structure 426 that is vertically underlying and in contact with the dielectric liner structure 424 and the dielectric spacer structure 422. Figure 4B As shown, the depression structure 426 may include: a forward step structure 428, which includes steps 432 each including a plurality of (e.g., greater than or equal to three (3), greater than or equal to four (4)) horizontal ends of the layers 408 of the preliminary stacked structure 402; a reverse step structure 430, which includes additional steps 434 each including a plurality of (e.g., greater than or equal to three (3), greater than or equal to four (4)) horizontal ends of the layers 408; and a central region 436 horizontally inserted between the forward step structure 428 and the reverse step structure 430. The central region 436 of the depression structure 426 may, for example, constitute an intersection region and a vertical termination position for the forward step structure 428 and the reverse step structure 430. As previously described with reference to FIG. Figure 1H In substantially the same manner as described for dielectric spacer structure 122 and different dielectric liner structure 124 , different dielectric spacer structure 422 and different dielectric liner structure 424 may be formed to physically contact mutually distinct steps 432 of forward step structure 428 and mutually distinct additional steps 434 of reverse step structure 430 .

[0112] like Figure 4BAs shown, in some embodiments, the individual steps 432 of the forward step structure 428 of the depression structure 426 are formed to include the horizontal ends of four (4) of the layers 408 of the preliminary stacked structure 402; and the individual additional steps 434 of the reverse step structure 430 of the depression structure 426 are also formed to include the horizontal ends of four (4) of the layers 408 of the preliminary stacked structure 402. The individual steps 432 of the depression structure 426 vertically adjacent to the individual additional steps 434 of the depression structure 426 may share multiple (e.g., three (3)) layers 408 of the preliminary stacked structure 402 with the individual additional steps 434. For example, three (3) of the four (4) layers 408 of the preliminary stacked structure 402 associated with the individual steps 432 may also be three (3) of the four (4) layers 408 of the preliminary stacked structure 402 associated with the individual additional steps 434 vertically adjacent to the individual steps 432. One of the three (3) layers 408 shared by the individual step 432 and the individual additional step 434 vertically adjacent to the individual step 432 may form a vertical upper portion of the individual step 432 and a vertical lower portion of the individual additional step 434, or vice versa. As a non-limiting example, the uppermost additional step 434 of the reverse step structure 430 may include a horizontal end of a first group of four (4) layers 408 of the preliminary stacking structure 402; and the uppermost step 432 of the forward step structure 428 may include a horizontal end of a second group of four (4) layers 408 of the preliminary stacking structure 102, wherein three (3) of the second group of four (4) layers 408 are the same as three (3) of the first group of four (4) layers 408. The relatively highest layer 408 among the first group of four (4) layers 408 may form an upper portion of the uppermost additional step 434 and may physically contact the first portion 424-1A of the first dielectric lining structure 424-1; and the three (3) relatively lower layers 408 of the first group of four (4) layers 408 may form a lower portion of the uppermost additional step 434 and may not physically contact the first portion 424-1A of the first dielectric lining structure 424-1. Furthermore, the relatively highest layer 408 among the three (3) relatively lower layers 408 that form the lower portion of the upper additional step 434 may constitute the relatively highest layer 408 among the second group of four (4) layers 408 and may form an upper portion of the uppermost step 432 that is in physical contact with the second portion 424-1B of the first dielectric lining structure 424-1; and the three (3) relatively lower layers 408 among the second group of four (4) layers 408 may form a lower portion of the uppermost step 432 and may not physically contact the second portion 424-1B of the first dielectric lining structure 424-1.

[0113] Next reference Figure 4C ,exist Figure 4B After the processing stages depicted in FIG. 4 , the microelectronic device structure 400 may be subjected to a process generally similar to that previously described with reference to FIG. Figures 1I to 1L The additional processing actions described above are used to achieve Figure 4C The configuration of the microelectronic device structure 400 depicted in FIG. Figure 4B The method of forming a microelectronic device structure 400 after the processing stages depicted in the previous reference is incorporated herein by reference. Fig. 1I The processing stages described in previous references Figure 1L Described Processing Stages The processing stages and features are described with respect to the formation of the microelectronic device structure 100 .

[0114] refer to Figure 4C The described microelectronic device structure 400 may be included in an embodiment of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) of the present disclosure. As a non-limiting example, in Figure 4C The microelectronic device structure 400 at the processing stage depicted in FIG. 4 may be included in the previously described reference Figure 2 The microelectronic device 200 is described as a microelectronic device structure 201 ( Figure 2 In some such embodiments, the low-lying structure 226 ( Figure 2 ) may individually have a geometric configuration (e.g., shape and size) substantially similar to that previously described with respect to the depression structure 426 (including the geometric configuration of its positive step structure 428, reverse step structure 430, and central region 436) ( Figure 4B and 4C ), the difference is that the low-lying structure 226 ( Figure 2 ) may be positioned at different elevations (e.g., vertical positions in the Z direction) from each other within the stacked structure 202. Figure 2 ) of individual blocks 205 ( Figure 2 ), the conductive contact structure 244 ( Figure 2 ), additional conductive contact structure 246 ( Figure 2 ) and dielectric spacer structure 222 ( Figure 2 ) can correspond to Figure 4C 4, and the conductive contact structure 444, the additional conductive contact structure 446, and the dielectric spacer structure 422 of the microelectronic device structure 400 at the processing stage depicted in FIG. Figure 2 ) of individual blocks 205 ( Figure 2 ), individual (eg, single, one) low-lying structures 226 ( Figure 2 ) of the first segment 226A ( Figure 2 ) may include additional individual low-lying structures 226 ( Figure 2 ) of the second section 226B ( Figure 2) of the step 432 and the additional step 434 are vertically offset (eg, vertically above, vertically below) the step 432 and the additional step 434. The low-lying structure 226 ( Figure 2 ) of the first segment 226A ( Figure 2 ) of the positive step structure 428 can be accessed from the additional low-lying structure 226 ( Figure 2 ) of the second section 226B ( Figure 2 ) of the positive step structure 428 is vertically offset (eg, vertically above or vertically below) by one (1) layer 408; and the depression structure 226 ( Figure 2 ) of the first segment 226A ( Figure 2 ) of the reverse step structure 440 can be removed from the additional low-lying structure 226 ( Figure 2 ) of the second section 226B ( Figure 2 )'s additional step 434 of the reverse step structure 430 is vertically offset (eg, vertically above or vertically below) by one (1) layer 408.

[0115] And the additional steps 434 of the first section 226A of the depressed structure 226 may each be vertically offset from the vertically adjacent steps 432 and the additional steps 434 of the second section 226B of the additional depressed structure 226 , respectively.

[0116] In another embodiment, the microelectronic device structure of the present disclosure is formed to have Figure 1L The microelectronic device structure 100 at the processing stage depicted in Figure 4C Each of the different configurations of the microelectronic device structure 400 at the processing stage depicted in FIG. By way of non-limiting example, Figures 5A to 5G is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device structure 500 according to additional embodiments of the present disclosure. Figures 5A to 5G The processing stages depicted in and described in further detail below may, for example, include replacements and / or combinations of previously referenced Figures 1A to 1L Described to form the previous reference Figure 1L The processing actions performed by the microelectronic device structure 100 are described. Figures 5A to 5G and the associated description below, are functionally similar to the previous reference Figures 1A to 1L Features (eg, structures, materials, regions) of one or more of the features of the microelectronic device structure 100 described in the accompanying drawings are referred to by like reference numerals incremented by 100. To avoid repetition, the microelectronic device structure 100 will not be described in detail herein. Figures 5A to 5G Rather, unless otherwise described below, Figures 5A to 5G In the previous reference Figures 1A to 1LReference numerals that increment the reference numerals of one or more of the described features by 100 denote features that will be understood to be substantially similar to previously described features.

[0117] See also Figure 5A , the microelectronic device structure 500 can be formed to include a preliminary stacked structure 502 and a patterned mask structure 510 on or above the preliminary stacked structure 502. The preliminary stacked structure 502 includes a vertically alternating (e.g., in the Z direction) sequence of first insulating structures 504 and second insulating structures 506 arranged in a layer 508. The patterned mask structure 510 can include at least one opening 512 (e.g., an orifice, a through-hole) extending vertically therethrough. The preliminary stacked structure 502 (including its first insulating structures 504 and second insulating structures 506) and the patterned mask structure 510 (including the opening 512 therein) can be formed to be respectively substantially similar to the previously described embodiments of the present invention. Figure 1A The depicted preliminary stack structure 102 (including the first insulating structure 104 and the second insulating structure 106 thereof) and the patterned mask structure 110 (including the opening 112 therein) are shown.

[0118] Next reference Figure 5B , the microelectronic device structure 500 may be subjected to one or more material removal processes (e.g., one or more cutting processes) to form at least one trench 516 (e.g., opening, blind via) extending vertically (e.g., in the Z direction) into the preliminary stacked structure 502. Figure 5B As shown, the trenches 516 within the preliminary stacked structure 502 may be generally confined within the horizontal boundaries of the openings 512 within the patterned mask structure 510. In embodiments where the patterned mask structure 510 includes a plurality of openings 512, different trenches 516 may be formed to extend to different vertical depths within the preliminary stacked structure 502 from one another. For example, at least one of the trenches 516 may extend vertically to a relatively lower depth within the preliminary stacked structure 502 than at least one other of the trenches 516. The vertical depths of the trenches 516 relative to one another may depend, at least in part, on the amount of layers 508 of the preliminary stacked structure 502, the amount of trenches 516 within the preliminary stacked structure 502, and the horizontal dimensions of the trenches 516. The trenches 516 may be configured to facilitate subsequent formation of vertically extending insulating structures in physical contact with at least some (e.g., each) of the layers 508 of the preliminary stacked structure 502, as described in further detail below.

[0119] like Figure 5B As shown, the trench 516 may be formed to include a lower vertical boundary 518 (eg, bottom layer) and a horizontal boundary 520 (eg, side). The lower vertical boundary 518 of the trench 516 may be formed to be substantially horizontal and flat. For example, before forming the trench 516, the previously referenced Figure 1B 100). Thus, the different horizontal regions of the trenches 516 may all extend vertically (e.g., in the Z direction) to substantially the same vertical height within the preliminary stacked structure 502. Additionally, as Figure 5B , the horizontal boundary 520 of the trench 516 can be substantially vertically flat.

[0120] The trench 516 in the preliminary stacked structure 502 may be formed to terminate vertically (e.g., end vertically) at the second insulating structure 506 of a single (e.g., only one) layer 508 of the preliminary stacked structure 502. In additional embodiments, the trench 516 in the preliminary stacked structure 502 may be formed to terminate vertically at the first insulating structure 504 of a single (e.g., only one) layer 508 of the preliminary stacked structure 502.

[0121] Next reference Figure 5C , a first dielectric spacer structure 522-1 may be formed within the opening 512 in the patterned mask structure 510 and the trench 516 in the preliminary stacked structure 502. The first dielectric spacer structure 522-1 may partially (e.g., less than completely) fill each of the opening 512 and the trench 516, and may be formed within the horizontal boundaries (e.g., in the X and Y directions) of the trench 516 (and thus the opening 512 in the patterned mask structure 510) on the exposed surface of the patterned mask structure 510 and the preliminary stacked structure 502. For example, as Figure 5C As shown, the first dielectric spacer structure 522-1 may be directly horizontally adjacent to (e.g., horizontally above) a horizontal boundary 520 of the trench 516 formed through the side surfaces of the patterned mask structure 510 and the preliminary stacked structure 502 (e.g., coplanar therewith), and may also be directly vertically adjacent to (e.g., vertically above) a lower vertical boundary 518 (e.g., vertically above) defining the trench 516. Figure 5B ) is formed on an upper surface of the layer 508 of the preliminary stacked structure 502. The first dielectric spacer structure 522-1 may extend substantially vertically across (e.g., in the Z direction) and cover the side surfaces of the patterned mask structure 510 and the preliminary stacked structure 502 at (e.g., coplanar with) the horizontal boundary 520 of the trench 516, and may only partially extend horizontally across (e.g., in the X and Y directions) and cover the lower vertical boundary 518 ( Figure 5B ) of the upper surface of the layer 508 of the preliminary stacked structure 502. Figure 5CAs shown, the first dielectric spacer structure 522-1 may include a first portion 522-1A and a second portion 522-1B. The first portion 522-1A and the second portion 522-1B may extend vertically (eg, in the Z direction) to substantially the same depth within the preliminary stacked structure 502 as each other.

[0122] The first dielectric spacer structure 522-1 may have the same Figure 1D The first dielectric spacer structure 522-1 may have substantially the same horizontal dimensions (eg, width) and material composition as described above. Additionally, the first dielectric spacer structure 522-1 may be similar to the first dielectric spacer structure 122-1 described above. Figure 1D The first dielectric spacer structure 122 - 1 is formed in substantially the same manner as described above.

[0123] Next reference Figure 5D , the first dielectric liner structure 524-1 can be formed within the remaining (e.g., unfilled) portions of the openings 512 in the patterned mask structure 510 and the trenches 516 in the preliminary stacked structure 502. The first dielectric liner structure 524-1 can partially (e.g., less than completely) fill the remaining portions of each of the openings 512 and the trenches 516, and can be formed within the first dielectric spacer structure 522-1 ( Figure 5D ) and the exposed surface of the preliminary stacked structure 502 are formed within the horizontal boundaries of the trench 516 (and thus the opening 512 in the patterned mask structure 510) (e.g., in the X direction and the Y direction). For example, the first dielectric liner structure 524-1 can be formed directly horizontally adjacent to (e.g., horizontally on) the inner side surface of the first dielectric spacer structure 522-1, and can also be formed directly vertically adjacent to (e.g., vertically on) the upper surface of the first insulating structure 504 of the layer 508 of the preliminary stacked structure 502 in the previous reference. Figure 5C The first dielectric liner structure 524-1 may extend substantially vertically across (eg, in the Z-direction) and cover the inner side surfaces of the first dielectric spacer structure 522-1.

[0124] like Figure 5DAs shown in , the first dielectric liner structure 524-1 may include a first portion 524-1A and a second portion 524-1B. The first portion 524-1A may be formed directly horizontally adjacent to (e.g., horizontally on) the first portion 522-1A of the first dielectric spacer structure 522-1, and the second portion 524-1B may be formed directly horizontally adjacent to (e.g., horizontally on) the second portion 522-1B of the first dielectric spacer structure 522-1. The first portion 524-1A and the second portion 524-1B may extend vertically (e.g., in the Z direction) to substantially the same depth as each other within the preliminary stacked structure 502. The vertical depth of each of the first portion 524-1A and the second portion 524-1B of the first dielectric liner structure 524-1 may be greater than or equal to the vertical depth of the first dielectric spacer structure 522-1 (including the first portion 522-1A and the second portion 522-1B thereof). For example, the first portion 524-1A and the second portion 524-1B of the first dielectric liner structure 524-1 may each vertically extend to and terminate at the first insulating structure 504 of the layer 508 of the preliminary stacked structure 502 vertically adjacent to the lower vertical boundary of the first dielectric spacer structure 522-1.

[0125] The first dielectric liner structure 524-1 may have the same Figure 1E The first dielectric liner structure 524-1 may have substantially the same horizontal dimensions (eg, width) and material composition as described above. Additionally, the first dielectric liner structure 524-1 may be similar to the first dielectric liner structure 124-1 described above. Figure 1E The first dielectric liner structure 124 - 1 is formed in substantially the same manner as described above.

[0126] Next reference Figure 5E, the second dielectric spacer structure 522-2 may be formed within the remaining (e.g., unfilled) portion of the opening 512 in the patterned mask structure 510 and the remaining deepened portion of the trench 516 in the preliminary stacked structure 502. The second dielectric spacer structure 522-2 may partially (e.g., less than completely) fill the remaining portion of the opening 512 and the remaining deepened portion of the trench 516; and may be formed within the horizontal boundaries (e.g., in the X-direction and the Y-direction) of the trench 516 (and thus the opening 512 in the patterned mask structure 510) on the exposed surface of the first dielectric liner structure 524-1 and the preliminary stacked structure 502. For example, the second dielectric spacer structure 522-2 may be formed within the trench 516 directly horizontally adjacent to (e.g., horizontally above) the exposed inner side surface of the first dielectric liner structure 524-1 and the preliminary stacked structure 502. The second dielectric spacer structure 522-2 and may also be formed directly vertically adjacent to (eg, vertically above) the upper surface of the second insulating structure 506 of the layer 508 of the preliminary stacked structure 502 as previously described with reference to FIG. Figure 5D The second dielectric spacer structure 522-2 may extend substantially vertically across (eg, in the Z-direction) and cover the inner side surfaces of the first dielectric liner structure 524-1.

[0127] like Figure 5E As shown, the second dielectric spacer structure 522-2 may include a first portion 522-2A and a second portion 522-2B. The first portion 522-2A of the second dielectric spacer structure 522-2 may be formed directly horizontally adjacent to (e.g., horizontally on) the first portion 524-1A of the first dielectric liner structure 524-1, and the second portion 522-2B may be formed directly horizontally adjacent to (e.g., horizontally on) the second portion 524-1B of the first dielectric liner structure 524-1. The first portion 522-2A and the second portion 522-2B may extend vertically (e.g., in the Z direction) to substantially the same depth as each other within the preliminary stacked structure 502. The vertical depth of each of the first portion 522-2A and the second portion 522-2B of the second dielectric spacer structure 522-2 may be greater than or equal to the vertical depth of the first dielectric liner structure 524-1 (including the first portion 524-1A and the second portion 524-1B thereof). For example, the first portion 522-2A and the second portion 522-2B of the second dielectric spacer structure 522-2 may each vertically extend to and terminate at the second insulating structure 506 of the layer 508 of the preliminary stacked structure 502 vertically adjacent to the lower vertical boundary of the first dielectric liner structure 524-1.

[0128] The second dielectric spacer structure 522-2 may have the same Figure 1G The second dielectric spacer structure 122-2 described above may have substantially the same horizontal dimensions (eg, width) and material composition. Additionally, the second dielectric spacer structure 522-2 may be similar to the second dielectric spacer structure 122-2 described above. Figure 1G The second dielectric spacer structure 122 - 2 is formed in substantially the same manner as described above.

[0129] Next, refer to 5F. Figure 5E After the processing stages described, the microelectronic device structure 500 may be subjected to a process similar to that previously described with reference to Figure 5D and 5E Additional processing actions to those described above to fill trench 516 with more dielectric liner structures 524 and more dielectric spacer structures 522 ( Figure 5E ) and form a low-lying structure 526 that is vertically underlying and in contact with the dielectric liner structure 524 and the dielectric spacer structure 522. Fig. 5F As shown, the depression structure 526 may include: a forward step structure 528 including a step 532 including a horizontal end of the layer 508 of the preliminary stacked structure 502; a reverse step structure 530 including an additional step 534 including an additional horizontal end of the layer 508 of the preliminary stacked structure 502; and a central region 536 horizontally interposed between the forward step structure 528 and the reverse step structure 530. The central region 536 of the depression structure 526 may, for example, constitute an intersection area and a vertical termination position for the forward step structure 528 and the reverse step structure 530. As described in further detail below, different dielectric spacer structures 522 and different dielectric liner structures 524 may be formed to physically contact different steps 532 of the forward step structure 528 and different additional steps 534 of the reverse step structure 530.

[0130] like Fig. 5F As shown, the dielectric liner structure 524 may physically contact the first insulating structure 504 of the different layers 508 of the preliminary stacked structure 502 at the step 532 and the additional step 534 of the depression structure 526. Fig. 5FAs shown, the first parts 524-1A, 524-2A, 524-3A, 524-4A of different dielectric lining structures 524 (e.g., the first dielectric lining structure 524-1, the second dielectric lining structure 524-2, the third dielectric lining structure 524-3, and the fourth dielectric lining structure 524-4) can physically contact at least some of the additional steps 534 of the reverse step structure 530 of the low-lying structure 526; and the second parts 524-1B, 524-2B, 524-3B, 524-4B of different dielectric lining structures 524 (e.g., the first dielectric lining structure 524-1, the second dielectric lining structure 524-2, the third dielectric lining structure 524-3, and the fourth dielectric lining structure 524-4) can physically contact at least some of the steps 532 of the forward step structure 528 of the low-lying structure 526. The dielectric liner structure 524 may have a substantially similar Figure 1H The horizontal positions and horizontal dimensions of the dielectric liner structure 124 are described as those of the dielectric liner structure 124 .

[0131] The dielectric spacer structure 522 may be formed horizontally adjacent to the dielectric spacer structure 522 over the different steps 532 and additional steps 534 of the depression structure 526. Fig. 5F As shown, the first parts 522-1A, 522-2A, 522-3A, 522-4A of different dielectric spacer structures 522 (for example, the first dielectric spacer structure 522-1, the second dielectric spacer structure 522-2, the third dielectric spacer structure 522-3, and the fourth dielectric spacer structure 522-4) can be formed above and inside the horizontal boundaries of at least some of the additional steps 534 of the reverse step structure 530 of the depression structure 526; and the second parts 522-1B, 522-2B, 522-3B, 522-4B of different dielectric spacer structures 522 (for example, the first dielectric spacer structure 522-1, the second dielectric spacer structure 522-2, the third dielectric spacer structure 522-3, and the fourth dielectric spacer structure 522-4) can be formed above and inside the horizontal boundaries of at least some of the steps 532 of the forward step structure 528 of the depression structure 526. The fifth dielectric spacer structure 522-5 may be formed above and within the horizontal boundary of the central region 536 of the depression structure 526. The dielectric spacer structure 522 may have a substantially similar structure to that described previously with reference to FIG. Figure 1H The horizontal positions and horizontal dimensions of the dielectric spacer structures 122 are depicted as those horizontal positions and horizontal dimensions.

[0132] Still viewing Fig. 5F, the steps 532 of the forward step structure 528 of the depression structure 526 may each include a horizontal end of one (1) layer 508 of the preliminary stacked structure 502. In addition, the additional steps 534 of the reverse step structure 530 of the depression structure 526 may each include a horizontal end of one (1) layer 508 of the preliminary stacked structure 502. The individual steps 532 and the individual additional steps 534 of the depression structure 526 at substantially the same elevation (e.g., in the Z direction) within the preliminary stacked structure 502 may share a layer 508 of the preliminary stacked structure 502 with each other. For example, individual steps 532 (e.g., the uppermost step 532) of the forward step structure 528 may include a first horizontal end of an individual layer 508 of the preliminary stacking structure 502; and individual additional steps 534 (e.g., the uppermost additional step 534) of the reverse step structure 530 may be located at substantially the same vertical position as the individual steps 532 of the forward step structure 528, and may include a second horizontal end of the individual layer 508 of the preliminary stacking structure 502.

[0133] Next reference Figure 5G ,exist Fig. 5F After the processing stages depicted in FIG. 5 , the microelectronic device structure 500 may be subjected to a process generally similar to that previously described with reference to FIG. Figures 1I to 1L The additional processing actions described above are used to achieve Figure 5G The configuration of the microelectronic device structure 500 depicted in FIG. Fig. 5F The method of forming a microelectronic device structure 500 after the processing stages depicted in the foregoing description incorporates the foregoing description from the foregoing reference. Fig. 1I The processing stages described in previous references Figure 1L Described Processing Stages The processing stages and features are described with respect to the formation of the microelectronic device structure 100 .

[0134] refer to Figure 5G The described microelectronic device structure 500 may be included in an embodiment of a microelectronic device (eg, a memory device, such as a 3D NAND flash memory device) of the present disclosure. By way of non-limiting example, in Figure 5G The microelectronic device structure 500 at the processing stage depicted in FIG. 5 may be included in the microelectronic device 200 ( Figure 2 ) as a microelectronic device structure 201 ( Figure 2 ), or may be included in the microelectronic device 300 ( Figure 3 ) as a microelectronic device structure 301 ( Figure 3 In some such embodiments, the low-lying structure 226 ( Figure 2 ) or low-lying structure 326( Figure 3) may individually have a geometric configuration (e.g., shape and size) substantially similar to that previously described with respect to the depression structure 526 (including the geometric configuration of its positive step structure 528, reverse step structure 530, and central region 536) ( Fig. 5F and 5G ), the difference is that the low-lying structure 226 ( Figure 2 ) or at least some of the low-lying structures 326 ( Figure 3 ) may be in the stacked structure 202 ( Figure 2 ) or stacked structure 302 ( Figure 3 ) are positioned at different elevations from each other (e.g., vertical positions in the Z direction). In addition, in the stacked structure 202 ( Figure 2 ) of individual blocks 205 ( Figure 2 ) or stacked structure 302 ( Figure 3 ) of individual blocks 305 ( Figure 3 ), the conductive contact structure 244 ( Figure 2 ) or conductive contact structure 344 ( Figure 3 ), additional conductive contact structure 246 ( Figure 2 ) or additional conductive contact structure 346 ( Figure 3 ) and dielectric spacer structure 222 ( Figure 2 ) or dielectric spacer structure 322 ( Figure 3 ) can correspond to Figure 5G 4. The conductive contact structure 544, the additional conductive contact structure 546, and the dielectric spacer structure 522 of the microelectronic device structure 500 at the processing stage depicted in FIG.

[0135] According to the microelectronic device structure of the embodiment of the present disclosure (for example, the previously referenced Figure 1L The microelectronic device structure 100 described previously with reference to Figure 4C The microelectronic device structure 400 described previously with reference to Figure 5G The microelectronic device structure 500 described above and the microelectronic device (eg, previously described with reference to Figure 2 The microelectronic device 200 described previously with reference to Figure 3 The microelectronic device 300 described above may be used in embodiments of the electronic system of the present disclosure. For example, Figure 6 6 is a block diagram of an illustrative electronic system 600 according to an embodiment of the present disclosure. The electronic system 600 may include, for example, a computer or computer hardware component, a server or other network connection hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g., a or Tablet computers), electronic books, navigation devices, etc. Electronic system 600 includes at least one memory device 602. Memory device 602 may include, for example, one or more embodiments of the microelectronic device structures and microelectronic devices previously described herein. Electronic system 600 may further include at least one electronic signal processor device 604 (often referred to as a "microprocessor"). Electronic signal processor device 604 may optionally include one or more embodiments of the microelectronic device structures and microelectronic devices previously described herein. Although memory device 602 and electronic signal processor device 604 are depicted as Figure 6 600. In some embodiments, the electronic system 600 includes two (2) separate devices in the electronic system 600, but in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of the memory device 602 and the electronic signal processor device 604 is included in the electronic system 600. In such embodiments, the memory / processor device may include one or more of the microelectronic device structures and microelectronic devices previously described herein. The electronic system 600 may further include one or more input devices 606 for inputting information into the electronic system 600 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 600 may additionally include one or more output devices 608 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, and speakers. In some embodiments, the input device 606 and the output device 608 may include a single touch screen device that can be used to input information into the electronic system 600 and output visual information to the user. The input device 606 and the output device 608 may be in electrical communication with one or more of the memory device 602 and the electronic signal processor device 604.

[0136] Therefore, according to an embodiment of the present invention, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a microelectronic device structure, which includes a stacked structure, a depression structure and a conductive contact structure. The stacked structure includes a vertical alternating sequence of conductive structures and insulating structures arranged in layers. The depression structure is within the stacked structure and includes a relative step structure each having a step including an edge of at least some of the layers. The conductive contact structure is integral and continuous with at least some of the conductive structures of the stacked structure at a step of the relative step structure of the depression structure. Each of the conductive contact structures individually has an inner horizontal boundary that is substantially coplanar with an inner horizontal boundary of one of the steps of the relative step structure.

[0137] The methods, structures (e.g., microelectronic device structures 100, 400, 500), devices (e.g., microelectronic devices 200, 300), and systems (e.g., electronic system 600) of the present disclosure advantageously promote one or more of improved performance, reliability and durability, lower cost, increased component miniaturization, improved pattern quality, and greater packaging density compared to conventional structures, conventional devices, and conventional systems. The methods and structures of the present disclosure can alleviate problems associated with forming and processing conventional microelectronic devices that include stacked structures with stepped structures at their edges. For example, the methods and structures of the present disclosure do not have the relatively small size and spacing error tolerances associated with correctly forming the stepped structures of conventional microelectronic device structures to accommodate the contact structures thereon. In addition, the methods and structures of the present disclosure can reduce the risk of undesirable damage (e.g., contact punch-through) and undesirable current leakage and short circuits compared to conventional methods and conventional structures.

[0138] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0139] Embodiment 1: A microelectronic device, comprising: a stacked structure, comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers, each of the layers comprising one of the conductive structures and one of the insulating structures; a depression structure, which is within the stacked structure and comprises: a forward step structure, which has a step including an edge of the layer; and a reverse step structure, which is opposite to the forward step structure and has an additional step including an additional edge of the layer; and a conductive contact structure, which extends vertically at the steps of the forward step structure and the additional steps of the reverse step structure to the upper vertical boundaries of at least some of the conductive structures of the stacked structure, the conductive contact structures each being integral and continuous with one of the conductive structures.

[0140] Embodiment 2: A microelectronic device according to embodiment 1, wherein the conductive contact structure comprises: a first conductive contact structure which is integral and continuous with some of the conductive structures of the stacked structure at the step of the forward step structure, each of the first conductive contact structures individually having a horizontal boundary that is substantially coplanar with a horizontal boundary of one of the steps; and a second conductive contact structure which is integral and continuous with some other conductive structures of the conductive structures of the stacked structure at the additional step of the reverse step structure, each of the first conductive contact structures individually having a horizontal boundary that is substantially coplanar with a horizontal boundary of one of the additional steps.

[0141] Embodiment 3: A microelectronic device according to one of embodiments 1 and 2, wherein the horizontal width of one or more of the conductive contact structures is substantially equal to the vertical height of one or more of the conductive structures that are integral and continuous with the one or more of the conductive contact structures.

[0142] Embodiment 4: The microelectronic device of any one of Embodiments 1 to 3, further comprising dielectric spacer structures on the steps of the forward step structure and the additional steps of the reverse step structure, the dielectric spacer structures alternating horizontally with the conductive contact structures.

[0143] Embodiment 5: A microelectronic device according to embodiment 4, wherein the dielectric spacer structure comprises: a first dielectric spacer structure, which is on the step of the forward step structure and is individually horizontally inserted between horizontally adjacent pairs of the conductive contact structures; and a second dielectric spacer structure, which is on the additional step of the reverse step structure and is individually horizontally inserted between additional horizontally adjacent pairs of the conductive contact structures.

[0144] Embodiment 6: The microelectronic device of any one of Embodiments 1 to 5, wherein an upper vertical boundary of each of the steps of the forward step structure is vertically offset from an upper vertical boundary of each of the additional steps of the reverse step structure.

[0145] Embodiment 7: A microelectronic device according to any one of embodiments 1 to 6, wherein the upper surface of the step of the forward step structure is vertically offset from the upper surface of the additional step of the reverse step structure that is vertically closest thereto by a distance that is substantially equal to the vertical height of one of the layers of the stacked structure.

[0146] Embodiment 8: A microelectronic device according to any one of Embodiments 1 to 7, wherein the depression structure further includes a central area horizontally inserted between the forward step structure and the reverse step structure, the central area having a partially non-planar lower vertical boundary extending horizontally from the bottom of the forward step structure and the bottom of the reverse step structure and between the two bottoms.

[0147] Embodiment 9: A microelectronic device according to any one of embodiments 1 to 8, wherein: each of the steps of the forward step structure individually includes a pair of horizontal ends of the layers of the stacked structure; and each of the additional steps of the reverse step structure individually includes an additional pair of horizontal ends of the layers of the stacked structure.

[0148] Embodiment 10: A microelectronic device according to any one of embodiments 1 to 8, wherein: each of the steps of the forward step structure individually includes the horizontal end of a group of at least four of the layers of the stacked structure; and each of the additional steps of the reverse step structure individually includes the horizontal end of an additional group of at least four of the layers of the stacked structure.

[0149] Embodiment 11: The microelectronic device of any one of Embodiments 1 to 5 and 8 to 10, wherein upper vertical boundaries of at least some of the steps of the forward step structure are substantially coplanar with upper vertical boundaries of at least some of the additional steps of the reverse step structure.

[0150] Embodiment 12: A microelectronic device according to any one of embodiments 1 to 5 and 9 to 11, wherein the depression structure further includes a central area horizontally inserted between the forward step structure and the reverse step structure, the central area having a substantially flat lower vertical boundary extending horizontally from the bottom of the forward step structure to the bottom of the reverse step structure.

[0151] Embodiment 13: A microelectronic device according to any one of embodiments 1 to 5 and 9 to 12, wherein: one of the steps of the forward step structure includes a horizontal end of one of the layers of the stacked structure; and one of the additional steps of the reverse step structure includes an additional horizontal end of one of the layers of the stacked structure.

[0152] Embodiment 14: A method for forming a microelectronic device, comprising: forming a preliminary stacking structure including a vertical alternating sequence of insulating structures and additional insulating structures arranged in layers, each of the layers including one of the insulating structures and one of the additional insulating structures; forming a groove extending vertically into the preliminary stacking structure; forming a horizontal alternating sequence of dielectric spacer structures and dielectric liner structures within the horizontal boundaries of the groove, at least some of the dielectric liner structures physically contacting different insulating structures of the preliminary stacking structure; and at least partially replacing the dielectric material of the dielectric liner structures and the insulating structures of the preliminary stacking structure with a conductive material.

[0153] Embodiment 15: A method according to embodiment 14, wherein a horizontal alternating sequence of dielectric spacer structures and dielectric lining structures formed within the horizontal boundary of the groove includes: forming a first dielectric spacer structure within the groove; forming a first dielectric lining structure within the groove and on the horizontal inner side of the first dielectric spacer structure, the first dielectric lining structure physically contacting at least one of the insulating structures of the preliminary stacked structure; forming a second dielectric spacer structure within the groove and on the horizontal inner side of the first dielectric lining structure; and forming a second dielectric lining structure within the groove and on the horizontal inner side of the second dielectric spacer structure, the second dielectric lining structure physically contacting at least one other insulating structure of the insulating structures within the preliminary stacked structure at a relatively lower vertical position than at least one of the insulating structures.

[0154] Embodiment 16: A method according to Embodiment 15, wherein: forming a first dielectric lining structure within the groove includes: forming a first portion of the first dielectric lining structure to physically contact a first one of the insulating structures; and forming a second portion of the first dielectric lining structure to physically contact a second one of the insulating structures vertically adjacent to the first one of the insulating structures; and forming a second dielectric lining structure within the groove includes: forming a first portion of the second dielectric lining structure to physically contact a third one of the insulating structures vertically underlying the second one of the insulating structures; and forming a second portion of the second dielectric lining structure to physically contact a fourth one of the insulating structures vertically adjacent to the third one of the insulating structures.

[0155] Embodiment 17: A method according to any one of Embodiments 15 and 16, wherein: forming a first dielectric spacer structure within the groove includes: forming a first portion of the first dielectric spacer structure to physically contact a first one of the additional insulating structures; and forming a second portion of the first dielectric spacer structure to physically contact a second one of the additional insulating structures vertically adjacent to the first one of the additional insulating structures; and forming a second dielectric spacer structure within the groove includes: forming a first portion of the second dielectric spacer structure to physically contact a third one of the additional insulating structures vertically underlying the second one of the additional insulating structures; and forming a second portion of the second dielectric spacer structure to physically contact a fourth one of the additional insulating structures vertically adjacent to the third one of the additional insulating structures.

[0156] Embodiment 18: A method according to embodiment 14, wherein forming a horizontal alternating sequence of dielectric spacer structures and dielectric liner structures within the horizontal boundary of the groove includes forming a depression structure within the preliminary stacking structure and within the horizontal boundary of the groove, the depression structure including: a forward step structure having a step including a horizontal end of the layer, some portions of the dielectric liner structure being in physical contact with some of the insulating structures of the preliminary stacking structure at the step of the forward step structure; and a reverse step structure opposite to the forward step structure and having an additional step including an additional horizontal end of the layer, some other portions of the dielectric liner structure being in physical contact with some other insulating structures of the insulating structures of the preliminary stacking structure at the additional step of the reverse step structure.

[0157] Embodiment 19: The method of Embodiment 18, wherein forming the depression structure comprises forming an upper surface of each of the steps of the forward step structure to be vertically offset from an upper surface of each of the additional steps of the reverse step structure.

[0158] Embodiment 20: The method of Embodiment 18, wherein forming the depression structure comprises forming upper surfaces of some of the steps of the forward step structure to be substantially coplanar with upper surfaces of some of the additional steps of the reverse step structure.

[0159] Embodiment 21: A method according to any one of Embodiments 18 to 20, wherein forming a depression structure comprises: forming each of the steps of the forward step structure as a horizontal end of a group that individually includes at least two of the layers of the preliminary stacking structure; and forming each of the additional steps of the reverse step structure as a horizontal end of an additional group that includes at least two of the layers of the preliminary stacking structure, the additional group sharing at least one of the layers of the preliminary stacking structure with the group.

[0160] Embodiment 22: A memory device comprising: a stacked structure having layers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure; depression structures positioned at different vertical depths from each other within the stacked structure, each of the depression structures comprising: a forward step structure having steps including horizontal ends of a group of the layers; and a reverse step structure opposite to the forward step structure and having additional steps including additional horizontal ends of the group of the layers; conductive contact structures extending vertically from at least some of the conductive structures of the stacked structure at the steps and the additional steps of the depression structures, the conductive contact structures each being integral and continuous with one of the conductive structures; and a memory cell string extending vertically through the stacked structure.

[0161] Embodiment 23: A memory device according to Embodiment 22, wherein: the stacked structure is divided into a block array, adjacent blocks of the block array are separated from each other by dielectric-filled slots in a first horizontal direction and each extends in a second horizontal direction orthogonal to the first horizontal direction; and the depression structure is individually divided between two or more of the adjacent blocks of the block array, and the dielectric-filled slots are horizontally inserted between different sections of the depression structure.

[0162] Embodiment 24: The memory device of Embodiment 23, wherein at least some blocks of the block array individually include word line bridging regions extending horizontally from and between segments of some of the depressed structures horizontally adjacent to each other in the first horizontal direction.

[0163] Embodiment 25: The memory device according to any one of Embodiments 22 to 24 further comprises: a data line overlying the stacked structure and electrically coupled to the memory cell string; a source structure underlying the stacked structure and electrically coupled to the memory cell string; an access line electrically coupled to the conductive contact structure; and a control device electrically coupled to the source structure, the data line and the access line.

[0164] Embodiment 26: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device structure, the microelectronic device structure comprising: a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers; a depression structure within the stacked structure and comprising a relative step structure each having steps including edges of at least some of the layers; and a conductive contact structure integral and continuous with at least some of the conductive structures of the stacked structure at the steps of the relative step structure of the depression structure, each of the conductive contact structures individually having an internal horizontal boundary that is substantially coplanar with an internal horizontal boundary of one of the steps of the relative step structure.

[0165] Although the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been illustrated by way of example in the accompanying drawings and have been described in detail herein. However, the present disclosure is not limited to the specific forms disclosed. In fact, the present disclosure encompasses all modifications, equivalents and alternatives that fall within the scope of the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers, each of said layers comprising one of said conductive structures and one of said insulating structures; A low-lying structure, which is within the stacked structure and includes: a positive step structure having a step including an edge of the layer; and a reverse step structure opposite to the forward step structure and having an additional step including an additional edge of the layer; and A conductive contact structure extending vertically to an upper vertical boundary of at least some of the conductive structures of the stacked structure at the steps of the forward step structure and the additional steps of the reverse step structure, each conductive contact structure being continuous with a corresponding one of the conductive structures so as to form a single monolithic structure including the conductive contact structure and the corresponding one of the conductive structures.

2. The microelectronic device of claim 1 , wherein the conductive contact structure comprises: a first conductive contact structure integral and continuous with some of the conductive structures of the stacked structure at the steps of the forward staircase structure, each of the first conductive contact structures individually having a horizontal boundary that is substantially coplanar with a horizontal boundary of one of the steps; as well as A second conductive contact structure is integral and continuous with some other of the conductive structures of the stacked structure at the additional step of the reverse step structure, each of the first conductive contact structures individually having a horizontal boundary that is substantially coplanar with a horizontal boundary of one of the additional steps.

3. The microelectronic device of claim 1, wherein a horizontal width of one or more of the conductive contact structures is substantially equal to a vertical height of one or more of the conductive structures that are integral and continuous with the one or more of the conductive contact structures.

4. The microelectronic device of claim 1, further comprising dielectric spacer structures on the steps of the forward step structure and the additional steps of the reverse step structure, the dielectric spacer structures alternating horizontally with the conductive contact structures.

5. The microelectronic device of claim 4 , wherein the dielectric spacer structure comprises: first dielectric spacer structures on the steps of the forward staircase structure and individually interposed horizontally between horizontally adjacent pairs of the conductive contact structures; as well as Second dielectric spacer structures are on the additional steps of the inverted staircase structure and are individually horizontally interposed between additional horizontally adjacent pairs of the conductive contact structures.

6. The microelectronic device of any one of claims 1 to 5, wherein an upper vertical boundary of each of the steps of the forward step structure is vertically offset from an upper vertical boundary of each of the additional steps of the reverse step structure.

7. A microelectronic device according to any one of claims 1 to 5, wherein an upper surface of the step of the forward step structure is vertically offset from an upper surface of the additional step of the reverse step structure to which it is vertically closest by a distance substantially equal to the vertical height of one of the layers of the stacked structure.

8. A microelectronic device according to any one of claims 1 to 5, wherein the depression structure further includes a central area horizontally inserted between the forward step structure and the reverse step structure, the central area having a partially non-planar lower vertical boundary extending horizontally from the bottom of the forward step structure and the bottom of the reverse step structure and between the two bottoms.

9. The microelectronic device according to any one of claims 1 to 5, wherein: Each of the steps of the forward staircase structure individually comprises a horizontal end of a pair of the layers of the stacked structure; and Each of the additional steps of the reverse staircase structure individually comprises a horizontal end of an additional pair of the layers of the stacked structure.

10. The microelectronic device according to any one of claims 1 to 5, wherein: Each of the steps of the forward staircase structure individually comprises a horizontal end of a group of at least four of the layers of the stacked structure; and Each of the additional steps of the reverse staircase structure individually comprises a horizontal end of an additional group of at least four of the layers of the stacked structure.

11. The microelectronic device of any one of claims 1 to 5, wherein upper vertical boundaries of at least some of the steps of the forward step structure are substantially coplanar with upper vertical boundaries of at least some of the additional steps of the reverse step structure.

12. A microelectronic device according to any one of claims 1 to 5, wherein the depression structure further includes a central area horizontally inserted between the forward step structure and the reverse step structure, the central area having a substantially flat lower vertical boundary extending horizontally from the bottom of the forward step structure to the bottom of the reverse step structure.

13. The microelectronic device according to any one of claims 1 to 5, wherein: One of the steps of the forward staircase structure comprises a horizontal end of one of the layers of the stacked structure; and One of the additional steps of the reverse staircase structure comprises an additional horizontal end of the one of the layers of the stacked structure.

14. A method of forming a microelectronic device, comprising: forming a preliminary stacked structure comprising a vertically alternating sequence of insulating structures and additional insulating structures arranged in layers, each of the layers comprising one of the insulating structures and one of the additional insulating structures; forming a groove extending vertically into the preliminary stacking structure; forming a horizontal alternating sequence of dielectric spacer structures and dielectric liner structures within the horizontal boundaries of the trench to form depressions within the preliminary stacked structure and within the horizontal boundaries of the trench, at least some of the dielectric liner structures physically contacting mutually different insulating structures of the preliminary stacked structure, the depressions comprising: a forward step structure having steps including horizontal ends of the layer, portions of the dielectric liner structure being in physical contact with portions of the insulating structures of the preliminary stacked structure at the steps of the forward step structure; and a reverse step structure opposite to the forward step structure and having an additional step including an additional horizontal end of the layer, some other portion of the dielectric liner structure being in physical contact with some other of the insulating structures of the preliminary stacked structure at the additional step of the reverse step structure; and The dielectric material of the dielectric liner structure and the insulating structure of the preliminary stack structure is at least partially replaced with a conductive material.

15. The method of claim 14, wherein forming a horizontal alternating sequence of dielectric spacer structures and dielectric liner structures within horizontal boundaries of the trench comprises: forming a first dielectric spacer structure within the trench; forming a first dielectric liner structure within the trench and horizontally inwardly of the first dielectric spacer structure, the first dielectric liner structure physically contacting at least one of the insulating structures of the preliminary stack structure; forming a second dielectric spacer structure within the trench and horizontally inwardly of the first dielectric liner structure; as well as A second dielectric liner structure is formed within the trench and horizontally inside the second dielectric spacer structure, the second dielectric liner structure physically contacting at least one other of the insulating structures at a relatively lower vertical position within the preliminary stack structure than the at least one of the insulating structures.

16. The method of claim 15, wherein: Forming a first dielectric liner structure in the trench includes: forming a first portion of the first dielectric liner structure to physically contact a first one of the insulating structures; and forming a second portion of the first dielectric liner structure to physically contact a second one of the insulating structures vertically adjacent to the first one of the insulating structures; and Forming a second dielectric liner structure in the trench includes: forming a first portion of the second dielectric liner structure to physically contact a third one of the insulating structures vertically underlying the second one of the insulating structures; and A second portion of the second dielectric liner structure is formed to physically contact a fourth one of the insulating structures vertically adjacent to the third one of the insulating structures.

17. The method according to any one of claims 15 and 16, wherein: Forming a first dielectric spacer structure in the trench includes: forming a first portion of the first dielectric spacer structure to physically contact a first one of the additional insulating structures; and forming a second portion of the first dielectric spacer structure to physically contact a second one of the additional insulating structures vertically adjacent to the first one of the additional insulating structures; and Forming a second dielectric spacer structure in the trench comprises: forming a first portion of the second dielectric spacer structure to physically contact a third one of the additional insulating structures vertically underlying the second one of the additional insulating structures; and A second portion of the second dielectric spacer structure is formed to physically contact a fourth one of the additional insulating structures vertically adjacent to the third one of the additional insulating structures. 18 . The method of claim 14 , wherein forming a depressed structure comprises forming an upper surface of each of the steps of the forward step structure to be vertically offset from an upper surface of each of the additional steps of the reverse step structure.

19. The method of claim 14, wherein forming the depression structure comprises forming upper surfaces of some of the steps of the forward step structure to be substantially coplanar with upper surfaces of some of the additional steps of the reverse step structure.

20. The method of claim 14, wherein forming the depression structure comprises: forming each of the steps of the forward step structure to individually include a horizontal end of a group of at least two of the layers of the preliminary stacked structure; as well as Each of the additional steps of the reverse step structure is formed as a horizontal end of an additional group including at least two of the layers of the preliminary stacked structure, the additional group sharing at least one of the layers of the preliminary stacked structure with the group.

21. A memory device comprising: a stacked structure having layers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure; depressions located at different vertical depths from one another within the stacked structure, each of the depressions comprising: a forward staircase structure having steps including horizontal ends of groups of said layers; and a reverse stair structure opposite the forward stair structure and having additional steps including additional horizontal ends of the groups of the layers; conductive contact structures extending vertically from at least some of the conductive structures of the stacked structure at the step and the additional step of the depression structure, each conductive contact structure being continuous with a respective one of the conductive structures so as to form a single monolithic structure including the conductive contact structure and the respective one of the conductive structures; and A memory cell string extends vertically through the stacked structure.

22. The memory device of claim 21, wherein: The stacked structure is divided into a block array, adjacent blocks of the block array are separated from each other by dielectric-filled slots in a first horizontal direction and each extends in a second horizontal direction orthogonal to the first horizontal direction; and The depressed structures are individually divided between two or more of the adjacent blocks of the block array, and the dielectric-filled slots are horizontally inserted between different sections of the depressed structures.

23. The memory device of claim 22, wherein at least some blocks of the block array individually include word line bridging regions extending horizontally from and between segments of some of the depressed structures horizontally adjacent to each other in the first horizontal direction.

24. The memory device of any one of claims 21 to 23, further comprising: a data line overlying the stacked structure and electrically coupled to the memory cell string; a source structure underlying the stacked structure and electrically coupled to the memory cell string; an access line electrically coupled to the conductive contact structure; as well as A control device is electrically coupled to the source structure, the data line and the access line.

25. An electronic system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; as well as a memory device operatively coupled to the processor device and comprising at least one microelectronic device structure, the microelectronic device structure comprising: a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers; a depression structure within the stacked structure and comprising opposing stepped structures each having steps including edges of at least some of the layers; and a conductive contact structure that is continuous with at least some of the conductive structures of the stacked structure at the steps of the opposed stepped structure of the depression structure, each conductive contact structure is continuous with a corresponding one of the conductive structures so as to form a single monolithic structure including the conductive contact structure and the corresponding one of the conductive structures, and Each conductive contact structure has an inner horizontal boundary that is substantially coplanar with an inner horizontal boundary of a corresponding one of the steps of the opposing step structures.

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