Pixel circuit including charge storage region

Abstract

Embodiments of the present disclosure relate to pixel circuits including charge storage regions. The pixel circuit includes a photoconversion region, an insulated vertical electrode, and at least one charge storage region. The photoconversion region belongs to a first portion of a semiconductor substrate, and each charge storage region belongs to a second portion of the substrate, which is physically separated from the first portion of the substrate by the insulated vertical electrode.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority of French Patent Application No. 2004324, filed on April 30, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices or circuits. The present disclosure relates more particularly to sensor pixel circuits, and in particular, to distance sensors operating on the principle of measuring time of flight, or TOF sensors, and methods for controlling the pixel circuits. Background Art

[0004] In a TOF sensor, a light source emits light toward a scene, and a time-of-flight detection pixel circuit of the sensor, or TOF pixel circuit, receives light returned by a point of the scene associated with the pixel circuit. The measurement of the time of flight, i.e., the time taken by the light to travel from the light source to the point of the scene associated with the pixel circuit, and from the point to the pixel circuit, enables the calculation of the distance separating the pixel circuit from the point.

[0005] In a scene where it is desired to obtain a relief image of a scene, the TOF sensor comprises a matrix of TOF pixel circuits to measure the distance separating each pixel circuit and the point of the scene associated with that pixel circuit. This enables a map of the distances separating the sensor from different points of the scene associated with that pixel circuit to be obtained, and a relief image of the scene can then be reconstructed from the map of distances.

[0006] The pixel circuit of the TOF sensor comprises a charge storage area in which charge that has been photogenerated in a photosensitive region or photoconversion region of the pixel circuit is subsequently temporarily stored before being read out.

[0007] The accuracy of measuring the distance between a pixel circuit of a TOF sensor and a point of a scene associated with the pixel circuit depends at least in part on the transfer of photogenerated charge from a photoconversion region of the pixel circuit to a temporary charge storage region.

[0008] Other pixel circuits include charge storage regions, such as pixel circuits of global shutter type image sensors, in which the quality of an image obtained using the sensor also depends at least in part on the transfer of photogenerated charge from the photoconversion region of the pixel circuit to the temporary charge storage region.

[0009] There is a need in the art to solve at least some of the known problems with a pixel circuit including at least one charge storage region, in particular, the known pixel circuit belongs to a TOF sensor or to a global shutter image sensor. Summary of the invention

[0010] One embodiment addresses all or some of the disadvantages of known pixel circuits comprising at least one charge storage region, in particular known pixel circuits of TOF sensors or known pixel circuits of global shutter image sensors.

[0011] One embodiment provides a pixel circuit, comprising: a photoconversion region, an insulated vertical electrode, and at least one charge storage region, wherein the photoconversion region belongs to a first portion of a semiconductor substrate, and each charge storage region belongs to a second portion of the substrate, and the second portion of the substrate is physically separated from the first portion of the substrate by the electrode.

[0012] According to one embodiment, the electrode passes through the substrate from a first side of the substrate, and for each charge storage region, the pixel circuit also includes: a first doped region, in contact with the charge storage region; a second doped region; a gate, placed on the first side between the photoconversion region and the second region; and an electrical connection, between the first region and the second region; the electrode is configured to electrically and optically insulate a first portion of the substrate including the photoconversion region and the second region from a second portion of the substrate including the charge storage region and the first region for each storage region.

[0013] According to one embodiment, for each charge storage region, the connection is arranged outside the substrate, above the first face.

[0014] According to one embodiment, each charge storage region is laterally delimited in width direction by two portions of an electrode parallel to and facing each other, a first region in contact with the charge storage region being arranged at one end of the charge storage region in length direction.

[0015] According to one embodiment: a substrate is doped with a first conductivity type; a photoconversion zone includes a layer doped with a second conductivity type and is arranged in the substrate on a first side of a surface; for each charge storage zone, a first zone and a second zone are arranged in the substrate on a side of a first surface, and the charge storage zone is doped with the second conductivity type; and each charge storage zone includes a box doped with the second conductivity type, which is arranged in the substrate on a side of the first surface.

[0016] According to one embodiment, for each charge storage region: the first region and the second region have the same doping level; and / or the first region and the second region have the same doping level as a layer of the photoconversion region; and / or the box of the charge storage region is more heavily doped than the first region.

[0017] According to one embodiment, for each charge storage region, the gate is placed on a channel region extending from the second zone to the layer of the photoconversion zone, the channel region being more lightly doped with the second conductivity type than the layer of the photoconversion zone and the second zone.

[0018] According to one embodiment, for each charge storage region, the channel region comprises a first portion and a second portion, the second portion being more lightly doped than the first portion, the second portion extending from the layer of the photoconversion zone to the first portion, and the first portion extending from the second portion to the second zone.

[0019] According to one embodiment, for each charge storage region, the second region is separated from the layer of the photoconversion region by a channel region and a region of the semiconductor substrate doped with the first conductivity type.

[0020] According to one embodiment, for each charge storage region, the pixel circuit includes: a doped reading region arranged in the substrate on the side of the first surface in the second part of the substrate including the charge storage region; and an additional gate placed on a portion of the substrate that extends between the charge storage region and the reading region, preferably, the additional gate is distributed to the charge storage region.

[0021] According to one embodiment, at least two charge storage regions belong to the same second portion of the substrate.

[0022] Another embodiment provides a sensor comprising a plurality of pixel circuits as described.

[0023] According to one embodiment, two adjacent pixel circuits share the same second portion of the substrate or the same first portion of the substrate.

[0024] According to one embodiment, the sensor includes a circuit configured to apply a first polarization potential to a first portion of a substrate of each pixel circuit, and for each charge storage region of each pixel circuit: during each read phase of the storage region, apply the first polarization potential to a second portion of the substrate including the storage region; and apply a second polarization potential to the second portion outside the read phase of the storage region, the first polarization potential and the second polarization potential being preferably configured such that a potential well in the charge storage region is deeper when the second polarization potential is applied to the second portion of the substrate than when the first polarization potential is applied to the second portion of the substrate.

[0025] Another embodiment provides a control method for the described pixel circuit, including polarization of a first portion of a substrate using a first potential; and for each charge storage region: during each read phase of the charge storage region, polarizing a second portion of the substrate using the first potential; and outside the read phase of the storage region, polarizing the second portion using a second polarization potential; the charge storage region is deeper when the second potential is applied to the second portion of the substrate than when the first potential is applied to the second portion of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0027] Figure 1 is a top view schematically illustrating an exemplary TOF sensor;

[0028] Figure 2 A circuit diagram of an exemplary TOF pixel circuit is shown;

[0029] Figure 3 It is a graphic Figure 2 A timing diagram of a control method for a TOF pixel circuit;

[0030] Figure 4 The schematic top view shows Figure 2 An embodiment of a pixel circuit of the type shown in;

[0031] Figure 5 is along Figure 4 A schematic cross-sectional view of the dashed line AA in FIG.

[0032] Figure 6 is along Figure 4 A schematic cross-sectional view of plane BB in FIG.

[0033] Figure 7 is along Figure 4 A schematic cross-sectional view of plane CC in FIG.

[0034] Figure 8 The schematic top view shows Figure 4 , Figure 5 , Figure 6 and Figure 7 A variant embodiment of a pixel circuit;

[0035] Fig. 9 The schematic top view shows Figure 4 , Figure 5 , Figure 6 and Figure 7 Another variant embodiment of the pixel circuit;

[0036] Fig.10 According to a variant embodiment, a schematic top view is shown. Figure 4 , Figure 5 , Figure 6 and Figure 7 A portion of a pixel circuit;

[0037] Fig.11 is along Fig.10 A schematic cross-sectional view of the dashed line AA in FIG.

[0038] Fig.12 yes Fig.10A schematic cross-sectional view of another example of a portion of a pixel circuit of; and

[0039] Fig.13 The schematic top view shows the Figures 4 to 12 Embodiments of combinations of several pixel circuits of the type described. DETAILED DESCRIPTION

[0040] In the various figures, similar features have been designated by similar reference numerals. Specifically, common structural features or / and functional features in various embodiments may have the same reference numerals and may be provided with the same structure, size and material properties.

[0041] For clarity, only operations and elements that are useful for understanding the embodiments described herein are illustrated and described in detail.

[0042] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0043] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.), or qualifiers referring to directions (such as "vertical", "horizontal", etc.), reference is made to the directions shown in the figures.

[0044] Unless otherwise specified, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, preferably within 5%.

[0045] Figure 1 is a schematic top view of an exemplary TOF sensor. The sensor 1 comprises a matrix 3 of TOF pixel circuits, for example a matrix of one thousand rows by one thousand columns. The matrix 3 is associated with a row decoder 7 and a column decoder 9. The row decoder 7 provides a signal 11 enabling selection of one or another of the rows of the matrix. The column decoder 9 enables reading of the pixel circuits of the selected row. The row decoder 7 and the column decoder 9 are controlled by a signal 13 provided by a control and processing circuit 15. The control and processing circuit 15 comprises, for example, a processor associated with one or several memories.

[0046] In this example, where the sensor 1 is a TOF sensor, the sensor 1 is also associated with a light source 17 in order to illuminate the scene for which it is desired to obtain a relief image. The light source 17 is for example a laser, the wavelength of which may be comprised between 500 nm and 1000 nm. The light source 17 is connected to the control and processing circuit 15 in order to synchronize the control signals applied to the TOF pixel circuits of the matrix 3 and the light source 17.

[0047] As an example, the light source 17 emits a periodic signal L E , for example a sine wave, whose frequency may be comprised between 20 MHz and 100 MHz, for example equal to 25 MHz. For each pixel circuit, the phase shift The transmitted optical signal L E The light signal L received by the pixel circuit R Next, the distance separating the pixel circuit from its associated point is determined according to the phase shift to be sure.

[0048] Figure 2 A circuit diagram of a TOF pixel circuit is shown, for example Figure 1 TOF pixel circuit of sensor 1.

[0049] The TOF pixel circuit comprises a photosensitive element or photoconverting element PD, one terminal of which is connected to a node 21 and the other terminal of which is connected to a node or rail for applying a reference potential, such as ground. Node 21 is coupled to a reading node SN by means of several identical components, in this case two components S1 and S2 connected in parallel between node 21 and SN. In this example, each component S i (i is an integer equal to 1 or 2) including a transfer n-channel Tmem i MOS transistor, charge storage area mem i and has a read n-channel Tsn i MOS transistor. Transistor Tmem i The source of transistor Tmem is connected to node 21, and i The drain is connected to the memory area mem i Terminal of transistor Tmem i The signal Vmem applied to its gate i Control. Transistor Tsn i The source is connected to the memory area mem i The other terminal of the transistor Tsn i The drain of transistor Tsn is connected to the read node SN. i The signal Vsn applied to its gate i Control. Storage area mem iExamples of the invention are given below.

[0050] The TOF pixel circuit is associated with a reading device that can be shared by several pixel circuits (e.g., four pixel circuits). The reading device includes a precharged n-channel MOS transistor Tres connected as shown, an n-channel MOS transistor Tsuiv installed as a follower source, and an n-channel selection MOS transistor Tsel. The reading node SN is coupled to a node or rail for applying a power supply potential Vdd (e.g., a potential greater than a reference potential) through the transistor Tres. The transistor Tres is controlled by a signal Vres applied to its gate. The reading node SN is also coupled to the gate of the transistor Tsuiv, the drain of which is coupled to the power supply rail, and the source of which is coupled to the output node or output rail 23 of the pixel circuit by means of the transistor Tsel. The transistor Tsel is controlled by a signal Vsel applied to its gate.

[0051] In this example, the pixel circuit TOF further includes an n-channel MOS transistor Tres for resetting the photosensitive element PD. PD . Transistor Tres PD The source of transistor Tres is connected to node 21, and PD The drain of transistor Tres is connected to the power rail Vdd. PD The signal Vres applied to its gate PD control.

[0052] In order to determine the transmitted optical signal L E and the light signal L received by the pixel circuit R The phase shift between The signal L is sampled by transferring the charge generated by light in the photoconversion element PD successively and at regular intervals to the storage area mem1 and then mem2. R The total duration of performing these two consecutive transmissions is less than or equal to the signal L E and L R In addition, the set of two consecutive transfers is repeated many times, for example, at least 100000 times. Next, the charge accumulated in the storage area is read by transferring the charge of the region mem1 and then the charge of the region mem2 to the node SN.

[0053] Now combine Figure 3 Describe in more detail Figure 2 The operating modes of the TOF pixel circuit.

[0054] Figure 3 is generated by the sensor 1 ( Figure 1 ) The light signal L emitted by the associated light source 17 E, the light source L received by the TOF pixel circuit R And the digital signal Vres PD 、Vres、Vmem i 、Vsn i By default, the signal Vres PD 、Vmem i 、Vsn i and Vsel is at a low level, and the signal Vres is at a high level, the transistor Tres PD 、Tmem i 、Tsn i and Tsel are then in the off-state, and transistor Tres is in the on-state.

[0055] In this example, by switching the transistor Tres between times t0 and t1 PD Put it in the on state (signal Vres PD The integration cycle of the pixel circuit then starts at time t1 and is combined with the signal L E synchronous.

[0056] During the integration cycle, the photogenerated charges move toward the storage region mem i To this end, the transfer transistor Tmem i are placed in the on state in sequence. More specifically, transistor Tmem1 is placed in the on state (Vmem1 is high) between times t2 and t3, and then transistor Tmem2 is placed in the on state (Vmem2 is high) between times t4 and t5. As previously indicated, this set of two transmissions is then repeated many times. Throughout the entire duration of the integration cycle, signal Vres is in the high state, transistor Tres is turned on, and the potential of the read node SN is substantially equal to the potential Vdd.

[0057] At the end of the integration cycle, from time t 10 , stored in the storage area mem i Each memory area in mem i To this end, the read transistor Tsn i are placed in the on state in sequence and stored in the memory area mem i After each reading of the charge in , the potential level at the node SN is measured and stored. More specifically, the transistor Tsel is at time t 10 is placed in the on state (Vsel is high), and the precharge transistor Tres is turned on at time t 11 The transistor Tsn1 is then turned off at successive times t12 With t 13 is placed in the on state (Vsn1 is high) between the two, and then the transistor Tsn2 is turned on at successive times t 14 With t 15 The first potential level and the second potential level of the node SN are respectively at time t 13 With t 14 Between and at time t 15 and the subsequent time t 16 is measured and stored. 16 , the signal Vsel returns to a low state, and the signal Vres returns to a high state. Then, a new integration cycle can begin.

[0058] In this operating mode, the first measured potential level and the second measured potential level represent the charge stored in the memory area mem1 and in the memory areas mem1 and mem2, respectively. i After the charges accumulated in mem1 and mem2 are reset, a reset of the read node SN is provided by applying a pulse with a high potential on the transistor Tres. In this case, the first potential level and the second potential level represent charges stored in the individual storage areas of mem1 and mem2, respectively.

[0059] These two potential levels make it possible to determine the E With L R The phase shift between And therefore infer therefrom the distance separating the pixel circuit from the point of the scene associated with the pixel circuit.

[0060] Although the description has been made of two identical components S i Embodiment of TOF pixel circuit and control, but in the signal L E With L R The phase shift between It is also possible to use more than two components S i The TOF pixel circuit is determined by, for example, three or four components Si.

[0061] As an example, transfer to the storage area mem i The duration is included between 5ns and 30ns. When the signal L E and L R When the frequency is 25MHz, it is separated into the same storage area mem i The duration of two transmissions is, for example, 40 ns. In this case, when the memory area mem i Each memory area in mem iWhen the charge transfer is completed 250,000 times each, the duration of the integration cycle can be about 10 ms. i The duration of the charge transfer to the read node SN is, for example, comprised between 1 μs and 10 μs.

[0062] In the pixel circuit, when the photogenerated charge in the photoconversion element PD is transferred to the charge storage area mem in an unwanted manner, i During transmission, these charges are transferred to the corresponding transistor Tmem. i In the off state, this leads to an error in the measurement of the distance between the pixel circuit and the point of the scene associated with the pixel circuit. In addition, if the light reaching the photoconversion element PD then reaches the charge storage area mem i And since electric charges are generated by the photoconversion, this also causes errors in the measurement of the distance between the pixel circuit and the point of the scene associated with the pixel circuit.

[0063] Similarly, in the pixel circuit of the global shutter sensor, the photogenerated charge of the photoconversion element PD is transferred from the pixel circuit to the charge storage area mem of the pixel circuit. i unwanted transmission, and / or direct photoconversion in the charge storage area mem of the pixel circuit i The generation of charges in the sensor leads to a decrease in the quality of images obtained using the sensor.

[0064] In order to avoid the above phenomenon, the inventors have proposed a pixel circuit, which includes one or more charge storage regions, wherein each charge storage region is optically and electrically insulated from the photoconversion element of the pixel circuit when no transmission is performed between the photoconversion element and the charge storage region. More specifically, the inventors have proposed a pixel circuit, wherein the photoconversion region of the pixel circuit is formed in a first portion of a semiconductor substrate, and each charge storage region of the pixel circuit is formed in a second portion of the substrate physically separated from the first portion of the substrate by an insulated vertical electrode.

[0065] We will now describe Figure 4 , Figure 5 , Figure 6 and Figure 7 An embodiment of the pixel circuit.

[0066] Figure 4 , Figure 5 , Figure 6 and Figure 7 Schematically shows at least one storage area mem i In this example, the pixel circuit 100 is an embodiment of a pixel circuit 100 of FIG. Figure 2The described pixel circuit 1 corresponds to a TOF pixel circuit, and the pixel circuit 100 includes two storage areas mem1 and mem2. Figure 4 is a top view of the pixel circuit 100, Figure 5 , Figure 6 and Figure 7 Along Figure 4 The dotted line AA, Figure 4 The plane BB and Figure 4 Cross-sectional view of plane CC.

[0067] The pixel circuit 100 comprises a semiconductor substrate 102, for example made of silicon. The substrate is doped with a first conductivity type, in this example type p. Preferably, the doping level of the substrate 102 is between a surface 104 close to the substrate 102 and a surface 105 close to the substrate 102. Figure 5 , Figure 6 and Figure 7 Lower when above.

[0068] The pixel circuit 100 further comprises a photosensitive region or photoconversion region PD. The region PD is arranged in the substrate 102. The region PD is arranged on the side of a face 104 of the substrate. In other words, the region PD penetrates the substrate 102 from its face 104.

[0069] The region PD is configured so that when the region PD receives light, charges are generated in the region PD by photoconverting photons into electron-hole pairs, and photogenerated electrons or photogenerated holes (electrons in this example) are accumulated in the region PD until they are transferred to the storage region mem1 or mem2. The photogenerated charges (electrons or holes) (photogenerated holes in this example) that are not intended to be transferred to the region mem1 or mem2 are released to the polarization potential applied to the substrate 102.

[0070] For each charge storage area mem i , the pixel circuit 100 includes a mem i Contact doping region 106 i , it is said that the area 106 i With area mem i Each area 106 i is arranged in the substrate 102 on the side of the face 104 of the substrate 102. In other words, each region 106 i The substrate 102 is penetrated from the face 104 of the substrate 102 .

[0071] In this example, the pixel circuit 100 therefore comprises a region 1061 in contact with the charge storage region mem1 and a region 1062 in contact with the charge storage region mem2.

[0072] For each charge storage area mem i , the pixel circuit 100 further includes a doped region 108 iand gate Gmem i , it is said that doping region 108 i and gate Gmem i With the area mem i Associated.

[0073] 108 per district i is arranged in the substrate 102 on the side of the face 104 of the substrate 102. In other words, each region 108 i From the surface 104 of the substrate 102 through the substrate 102. Region 108 i is doped with region 106 i The same conductivity type, and more specifically, is doped with a conductivity type opposite to the conductivity type of substrate 102, in this example, region 106 i and 108 i Therefore, it is doped with type n. In addition, preferably, each region 108 i With corresponding area 106 i Same doping level.

[0074] Each gate Gmem i In region PD and gate Gmem i Associated zone mem i The substrate 102 includes a region 126. i (See Figure 5 The area 1261 in the i From zone mem i Extending to Area PD, the area 126 i Preferably, the gate Gmem i Complete coverage.

[0075] Gate Gmem i Corresponding to transistor Tmem i The gate of the transistor Tmem i The drain and source are respectively formed by regions 108 i and formed by the region PD, and the transistor Tmem i The channel region is composed of region 126 i form.

[0076] In this example of a pixel circuit 100 having two regions mem1 and mem2, the pixel circuit 100 therefore includes a region 1081 and a gate Gmem1 placed on the face 104 of the substrate 102 between the region PD and the region mem1, and also includes a region 1082 and a gate Gmem2 placed on the face 104 of the substrate 102 between the region PD and the region mem2.

[0077] For each zone mem i , the pixel circuit 100 includes a region mem i The two doping regions 106 are associated i With 108 i Electrical connection 110 between i . Electrical connection 110 i With District 106 i Contact the end and with area 108 i Here, electrical connection refers to a connection consisting of one or more conductive elements (preferably, one or more metallic conductive elements). More precisely, Figure 5 As shown in FIG. 1 , the electrical connection 110 i The connection 110 is implemented outside the substrate 102 and above the surface 104 of the substrate 102. For example, the connection 110 i Including 106 with respective districts i and 108 i The two vias are in contact with each other, and a portion of a metal level of an interconnect structure (not shown) is placed on the face 104 of the substrate 102. The metal level portion electrically connects the two vias to each other.

[0078] In the example described here, the pixel circuit 100 therefore includes an electrical connection 1101 between the doped regions 1061 and 1081 , and an electrical connection 1102 between the doped regions 1062 and 1082 .

[0079] Preferably, as in Figure 4 As shown in the figure, each area 106 i and 108 in each district i The contact recovery region 112 is more heavily doped than the region 106 to which it belongs. i or 108 i The same type, in this example, the contact recovery area is therefore doped with type n. Each electrical connection 110 i It is then contacted with region 112 at each of its ends.

[0080] The pixel circuit 100 further includes an insulated vertical electrode 114. The electrode 114 penetrates the substrate 102 from the surface 104 of the substrate 102, and the electrode 114 is substantially orthogonal to the surface 104. The electrode 114 passes through the substrate 102 throughout the thickness of the substrate 102. In other words, the electrode 114 extends from the surface 104 of the substrate 102 to another surface 116 ( Figure 5 and Figure 6 ). Although this Figure 4 Not shown in order not to overload the drawing, such as Figure 5As shown in , the electrode 114 comprises a conductive vertical wall or conductive core 1141, and an insulating core 1142 covering the wall 1141, and more precisely, the insulating core 1142 covers all side partitions of the wall 1141, and the wall 1141 is therefore separated from the substrate 102 and electrically insulated. The conductive wall 1141 is made of doped polysilicon, for example. The layer 1142 is, for example, a silicon oxide layer or a superposition of insulating layers (for example, a superposition of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer forming an ONO (oxide nitride oxide) structure).

[0081] During operation, a polarization potential is applied to electrode 114. In this example, the potential is intended to be transmitted to region mem i The photogenerated charges are photogenerated electrons, and the polarization potential is selected so as to attract holes to the subareas of the electrode 114. As an example, the polarization potential is equal to -2V.

[0082] The electrode 114 physically separates the substrate 102 into several parts. In other words, the electrode 114 defines several parts of the substrate 102 in the substrate 102, and the several parts of the substrate 102 are electrically and optically insulated from each other by the electrode 114. For example, if one of the two parts of the substrate 102 is completely surrounded by a part of the electrode 114, then two different parts of the substrate 102 are said to be electrically and optically insulated from each other.

[0083] More specifically, area PD and area 108 i belongs to the first portion of the substrate 102, and the region mem i and District 106 i The at least one second portion of the substrate 102 is electrically and optically insulated from the first portion of the substrate 102. In other words, each region mem i The first portion of the substrate 102 including the region PD is electrically and optically insulated. i , zone mem i Contact with the area mem i District 106 i belongs to the same second portion of the substrate 102 .

[0084] During operation, when light is received by region PD and charges are photogenerated and accumulated in region PD, as long as gate Gmem1 or Gmem2 is not controlled so as to transfer these photogenerated charges from region PD to region 1081 or 1082, respectively, these charges cannot reach regions mem1 and mem2, because electrical insulation is achieved by electrode 114 between a first portion of substrate 102 including region PD and (one or more) second portions of substrate 102 including regions mem1 and mem2.

[0085] In addition, when light reaches a first portion of the substrate 102 including the region PD, the light is blocked by the electrode 114 and cannot propagate to a second portion of the substrate 102 including the region mem1 and / or the region mem2 , where the light can generate charges through photoconversion.

[0086] In by Figure 4 , Figure 5 , Figure 6 and Figure 7 In the illustrated embodiment, each area mem i belong to different second portions of the substrate 102. In other words, in this example, region PD and regions 1081 and 1082 belong to a first portion of the substrate, regions mem1 and 1061 belong to one second portion of the substrate 102, and regions mem2 and 1062 belong to another second portion of the substrate 102. The second portions are electrically and optically insulated from the first portions, because in this example each second portion is completely surrounded by a corresponding portion of the electrode 114.

[0087] In top view, in other words, in a plane parallel to the faces 104 and 116, each region mem i Has a rectangular shape. Each area mem i The memory area mem is defined laterally in the width direction by two portions of the electrode 114 that are parallel and face each other. i , considered in the length direction, the area 106 associated with it i For example, it is arranged in the area mem i Preferably, the two zones 106 i and 108 i Via Connection 110 i Connected to each other, that is, with the same area mem i Two areas associated with 106 i and 108 i They are respectively arranged on each side of the same portion of the electrode 114 , for example facing each other on each side of the portion of the electrode 114 .

[0088] Preferably, if Figure 4 As shown in , region PD is at least partially delimited laterally (i.e. in a plane parallel to faces 104 and 116) by electrode 114. In other words, electrode 114 is arranged on or constitutes at least part of the outline of region PD. Figure 4 In the example of FIG. 5 , in a top view, the region PD has a substantially square shape. Figure 4 As shown in , the electrodes 114 are then arranged, for example, on three sides of the region PD. Figure 4 As shown in FIG. 1 , area 108 i It is then preferably arranged at a corner of the zone PD.

[0089] In the illustrated example, the region mem1 is arranged along a first side of the region PD, and the region mem2 is arranged along a second side of the region PD. i enables to define the area mem laterally in the width direction for a portion of the electrode 114 i , you can also define the area with mem i The sides of the adjoining region PD. This allows the pixel circuit 100 to be particularly compact.

[0090] In this embodiment, the area mem i is a fixed charge storage area or memory area, and area PD is a fixed photodiode. Therefore, in each area mem i In the region PD, there is a potential well in which charges can be stored or accumulated. i The depth of the well of the region PD depends on the depth of the well of the region PD. i Or polarization of a portion of the substrate 102 of region PD.

[0091] According to one embodiment, during operation, a first polarization potential is applied to a first portion of the substrate 102 including the region PD. i , in the area mem i During each read phase, and more precisely, in the region mem i During the entire duration of each read phase, a first polarization potential is applied to the region including mem i The second portion of the substrate 102. In the mem region i Outside the read phase, a second polarization potential is applied to the region including mem i A second portion of the substrate 102 is provided.

[0092] The first polarization potential and the second polarization potential are selected so that in the region mem i The potential well in the region mem i When the second portion of the substrate 102 is polarized by the second potential, it is deeper than when it is polarized by the first potential. i When not being read, a large amount of charge can be in the mem i Storage in .

[0093] As an example, in the case of a p-doped substrate 102 , the first potential is, for example, ground potential, and the second potential is then greater than the first potential, for example approximately equal to 1 V.

[0094] To include the area mem iProviding two polarization potentials to the second portion(s) of the substrate 102 is possible because this or these second portion(s) are electrically insulated from the first portion of the substrate including the region PD by the electrode 114 .

[0095] As an example, the first polarization potential and the second polarization potential are provided by a control circuit of the pixel circuit 100, for example, by a sensor including several pixel circuits 100 (for example, with respect to Figure 1 The sensor described above (a similar sensor) is provided by a control circuit of the pixel circuit.

[0096] For each zone mem i The pixel circuit 100 further comprises a doped reading region 118 arranged in the substrate 102 on the side of the face 104 of the substrate 102 i In other words, District 118 i From the face 104 of the substrate 102 through the substrate 102. It is said that the region 118 i With the area mem i District 118 i is doped with region 106 i and District 118 i Same conductivity type, ie type n in this example.

[0097] For each zone mem i The pixel circuit 100 further includes a gate 120 i , gate 120 i The portion 121 of the substrate 102 is placed i On this section 121 i In the zone mem i Associated with the area mem i Reading area 118 i In other words, area 121 i From zone mem i To District 118 i Extension, the area 118 i Preferably, the gate 120 i Full coverage. Gate 120 is claimed i With the area mem i Gate 120 i Corresponding to Figure 2 The transistor Tsn i The gate of the gate 120 i Associated reading area 120 i and area mem i Forming transistor Tsn i The source and drain, and the portion of the substrate 121 iThe transistor Tsn is formed i channel area.

[0098] In the example described here, the pixel circuit 100 therefore includes a region 1181 and a gate 1201 associated with the region mem1 , and a region 1182 and a gate 1202 associated with the region mem2 .

[0099] Each gate 120 i and associated with the gate 120 i Zone mem i belongs to the same second portion of the substrate 102 .

[0100] like Figure 4 and Figure 5 As shown in the area mem i Associated read zone 118 i For example, it is arranged in the area mem i On the side of one end, considering in the length direction, the area mem i One end is in the area 106 i Contact area mem i Opposite the end of the district, 106 i With the area mem i Associated.

[0101] Preferably, each gate 120 i In the charge storage area mem associated with it i distribution, which is beneficial for the charge to be transferred from the mem i To the corresponding area 118 i transmission.

[0102] The previously described area mem will now be described in more detail. i and the implementation of PD.

[0103] like Figure 5 , Figure 6 and Figure 7 As shown in the figure, the region PD includes a region 106 doped with i , 108 i and 118 i The layer 122 has the same conductivity type, ie, type n in this example. Preferably, the doping level of the layer 122 is less than or equal to (eg, equal to) that of the region 106. i and 108 i of doping level.

[0104] The layer 122 is arranged in the substrate 102 on the side of the face 104 of the substrate 102. In other words, the layer 122 penetrates the substrate 102 from the face 104 of the substrate 102.

[0105] Although this is not visible in the figures, in top view, layer 122 extends laterally over the entire surface of region PD to the portion of electrode 114 that defines region PD.

[0106] In addition, although this Figures 4 to 7 104, but preferably, layer 122 is covered on the side of face 104 with a doping layer of the same type as substrate 102, in this example type p, which layer is more heavily doped than substrate 102. This highly p-doped layer has a face bonded to face 104. Preferably, on the side of face 104, layer 122 is completely covered by this highly p-doped layer.

[0107] When in a direction orthogonal to the surface 104, the doping level of the substrate 102 decreases as it approaches the surface 104, and more precisely, decreases as it approaches the layer 122, the photogenerated charges are intended to be directed to the region mem i transfer, that is, in this example, the photogenerated electrons are more easily drawn to layer 122, and then to region mem i They may be accumulated at layer 122 prior to transmission.

[0108] Each zone mem i The doping level of each box 124 is preferably greater than that of the region 106. i and 108 i of doping level.

[0109] Although this is not visible in the figure, in the top view, each area mem i Box 124 in zone mem i The box 124 thus extends from one parallel portion to another parallel portion of the parallel portions of the electrode 114, which electrode 114 laterally defines the area mem in the width direction. i .

[0110] In addition, although this Figures 4 to 7 104, each box 124 is covered on the side of face 104 with a doping layer of the same type as substrate 102, in this example of type p, which is more heavily doped than substrate 102. This high p-doped layer has a face that is bonded to face 104. Preferably, on the side of face 104, each box 124 is completely covered by this high p-doped layer, wherein the corresponding gate 120 i Except for any part of the covered box 124. Preferably, this highly p-doped layer has the same doping level as the highly p-doped layer of the cover layer 122, for example because these layers are manufactured simultaneously.

[0111] During operation, when the electrode 114 is polarized and charges (holes in this example) accumulate along the electrode 114, this causes a passivation of the boundary between the insulating layer 1142 of the electrode 114 on the one hand and the box 124 and the n-doped layer 122 on the other hand. This passivation prevents photogenerated charges, and more specifically, in this example, photogenerated electrons from being trapped at this interface. In addition, this accumulation of holes along the electrode 114 forms a conductive layer, which is then at the same potential as the substrate 102 and laterally adjacent to the box 124 and the layer 122.

[0112] According to one embodiment, Figure 5 As shown in i Covers and is in area PD and corresponds to area 108 i Each portion 126 of the substrate 102 extending between i is doped with layer 120 and region 106 i The same conductivity type. That is, type n in this example. This makes the charge flow from region PD to region mem i During the transmission period, the trapped i The number of residual charges at the boundary between the insulators.

[0113] In addition, in this embodiment, the channel region 126 i Preferably unlike layer 122 and region 108 i are also strongly doped, the channel region 126 i In area 108 i and layer 122. Therefore, when the charge passes through region 126 i From area PD to the corresponding area mem i In addition to the transmission, the channel region 126 i Form a potential barrier against charges.

[0114] According to one embodiment, Figure 5 As shown in the figure, for each area mem i , when area 126 i When doped with a conductivity type opposite to that of substrate 102, ie, type n in this example, region 126 i Including the first part 1261 i and the second part 1262 i , Part I 1261 i and the second part 1262 i The second portion 1262 is doped with a conductivity type opposite to that of the substrate 102, that is, n-type in this example. i Than the first part 1261 iMore lightly doped. Part 1262 i From layer 122 to portion 1261 i Extension, and Section 1261 i From Section 1262 i To the corresponding area 108 i Extension. Section 1262 i Then in section 1261 i A potential barrier is formed between the layer 122, which prevents the portion 1261 from i The charges in the layer 122 are returned to the layer 122. When the corresponding gate Gmem is applied i The potential on the area 126 is i In District 108 i The first value of the potential well formed between the layer 122 is switched to the region 126 i In District 108 i When the second value of the potential barrier is formed between the layer 122, the charge is transferred from the region PD to the region mem i It is particularly beneficial at the end of a transmission.

[0115] For each zone mem i , no part of layer 122 is in contact with region 108 i Direct contact, District 108 i With the area mem i Related, such as Figure 4 , Figure 5 and Figure 7 For example, not only by the corresponding gate Gmem i Covered channel area 126 i , and also by being arranged at the gate Gmem i Region 128 of substrate 102 on either side i , District 108 i Separated from layer 122 .

[0116] According to one embodiment, as Figure 2 as described, and as Figure 4 and Figure 6 As shown in FIG. 1 , the pixel circuit 100 includes a transistor Tres PD .

[0117] In this example, the transistor Tres PD It is called a "vertical gate" transistor. In other words, the transistor Tres PDThe substrate 102 includes a doping region 129 of the same type as the layer 122, namely type n in this example, the region 129 is more heavily doped than the layer 122 and is surrounded by an insulated vertical electrode 130 or vertical gate 130 passing through the substrate 102. The vertical gate 130 includes a conductive wall 1301 and an insulating layer 1302, which separates and insulates the wall 1301 from the substrate 102. Preferably, the wall 1301 and the layer 1302 are respectively identical to the wall 1141 and the layer 1142 of the electrode 114. The space e is arranged between the two ends of the electrode 130 facing each other (at Figure 6 In this space e, layer 122 extends upward to region 129. During operation, a power supply potential is applied to region 129. In addition, depending on the control signal ( Figure 2 Vres PD ) potential level, a potential barrier is formed in the space e and prevents the photogenerated charges from passing to the region 129 (transistor Tres PD The potential barrier is lost and the photogenerated charge in layer 122 is released from region PD to the potential applied to region 129 (transistor Tres PD connected).

[0118] Figure 8 A schematic top view shows Figure 4 , Figure 5 , Figure 6 and Figure 7 A variant embodiment of the pixel circuit 100 is shown in FIG.

[0119] In this variant, several areas mem i The second portion of the substrate 102 is optically and electrically insulated from the first portion of the substrate 102 including the region PD. Figure 4 , Figure 5 , Figure 6 and Figure 7 The pixel circuit 100 and Figure 8 The difference between the pixel circuits 100.

[0120] Preferably, if Figure 8 As shown in the figure, there are several areas mem i The second portion of the substrate 102 that is shared includes a portion 132 that is not occupied by: region mem i 、and area mem i Associated District 106 i and 118 i , and the corresponding gate 120 i Therefore, a transistor (not shown) (e.g., about Figure 2The transistors Tres, Tsuiv and Tsel) may be formed in the portion 132.

[0121] More specifically, in this example, the region mem1 and the region mem2 belong to the same second portion of the substrate 102. Preferably, this second portion of the substrate 102 includes the portion 132 as described above. For example, the region mem1 is arranged along a first side of the region PD, the region mem2 is arranged along a second side of the region PD opposite to the first side, and the portion 132 is arranged along a third side of the region PD. Therefore, the portion of the electrode of the region 132 that defines the side of the region PD also defines the third side of the region PD. This allows the pixel circuit 100 to be particularly compact.

[0122] Fig. 9 A schematic top view shows Figure 4 , Figure 5 , Figure 6 and Figure 7 Another variant embodiment of the pixel circuit 100. Only the Figure 4 , Figure 5 , Figure 6 and Figure 7 The pixel circuit 100 and Fig. 9 The difference between the pixel circuits 100.

[0123] In this variation, for each zone mem i The pixel circuit 100 includes an additional charge storage area mem i ', the additional charge storage area mem i 'With area mem i Identical to and identical to the zone mem i formed in the same second portion of substrate 102, referred to as region mem i 'With area mem i Associated.

[0124] Unlike zone mem i , zone mem i ' does not contact area 106. In contrast, area mem i 'With area mem i Share the same gate 120 i and the same read zone 118 i In addition, the area mem i The doping box 124 ( Figure 5 ) including to area mem i ' is an extension (not shown) of the doping box (not shown). The extension is formed by the gate 120 i Therefore, when applied to the gate 120 i The potential of transistor Tsn i ( Figure 2) is in the off state, if it has been transferred to the area mem i If the number of photogenerated charges becomes too high, the excess charges diffuse into the mem i ', they can be stored in the mem area before being read. i The charge in the memory is also stored in the memory area. i 'middle.

[0125] Preferably, if Fig. 9 As shown in the table, each area mem i 'Along the area mem associated with it i Arranged so that the area mem is defined in the lateral direction and the width direction i One of the two portions of the electrode 114 also defines the region mem in the lateral and width directions. i 'One of the two parts of the electrode 114.

[0126] Fig.10 A schematic top view shows a schematic diagram of a Figure 4 , Figure 5 , Figure 6 and Figure 7 portion of the pixel circuit 100 . Fig.11 is along Fig.10 Schematic cross-sectional view along the dashed line AA in FIG. Fig.12 yes Fig.10 A schematic cross-sectional view of another example of a portion of a pixel circuit of FIG. Only the Figure 4 , Figure 5 , Figure 6 and Figure 7 The pixel circuit 100 and Fig.10 , Fig.11 and Fig.12 The difference between the pixel circuits 100.

[0127] Fig.10 , Fig.11 and Fig.12 , more particularly Fig.10 , showing part of the region PD, transistor Tres PD part, part of electrode 114, region mem i , and the area mem i Associated District 106 i , 108 i and 118 i , and the mem i The associated gate Gmem i and 120 i The region mem1 is shown in this example, but it is to be understood that what is described here for the region mem1 applies to all regions memi .

[0128] In this variation, regions 1061 and 1081 each include a contact recovery region 112 .

[0129] The region 112 of the region 1081 is separated from the portion of the electrode 114 that contacts the region 1081 by the insulating trench 134. This makes it possible to limit the capacitive coupling between the electrode 114 and the region 112. As an example, the trench 134 penetrates the substrate 102 from the face 104 of the substrate 102 and is smaller in depth than the region 1081. i Preferably, the region 112 of the area 1081 has, on one of its sides, a side overhanging the gate Gmem1 and is bordered on all its other sides by the trench 134 .

[0130] Similarly, region 112 of region 1061 may also be separated from the portion of electrode 114 contacting region 1061 by insulating trench 134. As an example, trench 134 penetrates substrate 102 from the surface of substrate 102 and is smaller in depth than region 1061. i Preferably, region 112 of region 1061 has one side in contact with region mem1 and is surrounded by trench 134 on all other sides thereof.

[0131] like Fig.10 and Fig.12 As shown in FIG. 1 , preferably, region 1181 is also connected to surrounding region 118 by insulating trench 134. i Preferably, trench 134 completely surrounds region 1181 except on the side of region 1181 that is aligned with a side of the corresponding gate 1201.

[0132] Fig.10 , Fig.11 and Fig.12 A variant embodiment of Figure 8 Variations and / or Fig. 9 In addition, variants 8 and 9 can be combined.

[0133] When the pixel circuit 100 is a sensor (for example, Figure 1 When the pixel circuits 100 are part of a matrix of pixel circuits 100 of a TOF sensor of the type described, adjacent pixel circuits may share common elements, specifically the first portion or the second portion of the substrate 102 .

[0134] As an example: the area mem of the pixel circuit 100 i The area mem iThe pixel circuits 100 may be connected to the same second portion of the substrate 102, or in other words, two adjacent pixel circuits 100 may share the same second portion of the substrate 102; and / or the two adjacent pixel circuits 100 may share the same electrode 114; and / or the region PD of the pixel circuit 100 may belong to the same first portion of the substrate 102 as the region PD of the adjacent pixel circuit 100, or in other words, the two adjacent pixel circuits 100 may share the same first portion of the substrate 102; and / or the region mem of the pixel circuit 100 may be connected to the same second portion of the substrate 102 as the region PD of the adjacent pixel circuit 100. i and the region mem of the adjacent pixel circuit 100 i Can be read with the same area 118 i and / or all regions of the pixel circuit 100 mem i The second portion of the substrate 102 may be a region of all adjacent pixel circuits 100. i Also belonging to the second portion, the second portion of the substrate can include an area 132 shared by two adjacent pixel circuits 100 .

[0135] One specific example of association of several pixel circuits 100 including common elements (or in other words, elements shared by several adjacent pixel circuits 100 ) will now be described.

[0136] Fig.13 An embodiment of a combination of several adjacent pixel circuits 100 of a sensor, such as sensor 1 , comprising a matrix of pixel circuits 100 is shown in a schematic top view.

[0137] More specifically, Fig.13 Three pixel circuits 100 are shown in the same row or the same column of a matrix of pixel circuits 100 (preferably, the same column of the matrix), which are referred to as 100-1, 100-2 and 100-3 respectively below. Pixel circuit 100-2 is, for example, arranged between pixel circuits 100-1 and 100-3, and each of pixel circuits 100-1 and 100-3 is adjacent to pixel circuit 100-2. Fig.13 , a partially shown pixel circuit 100 - 1 is arranged at the top of the figure, a completely shown pixel circuit 100 - 2 is arranged at the center of the figure, and a partially shown pixel circuit 100 - 3 is arranged at the bottom of the figure.

[0138] In this exemplary embodiment, as described in relation to Figure 8 As described above, each pixel circuit 100-1, 100-2, 100-3 has two regions mem1 and mem2, and the two regions mem1 and mem2 belong to the same second portion of the substrate 102, and the second portion of the substrate 102 includes the region 132. In addition, as described with respect to Fig. 9As described above, each area mem of each pixel circuit 100-1, 100-2, 100-3 i With additional zone mem i 'Associated. Finally, as about Fig.10 , Fig.11 and Fig.12 As described above, for each zone 108 i 106 per district i and 118 in each district i , an insulation trench 134 is provided.

[0139] In this embodiment, all pixel circuits 100-1, 100-2 and 100-3 share the same electrode 114. Indeed, although Fig.13 It seems that several separate electrodes 114 are shown, but the latter actually correspond to parts of the same electrode 114. Preferably, although this Fig.13 It is not visible in FIG. 1 , but all pixel circuits 100 of the matrix of pixel circuits 100 of the sensor share the same electrode 114 .

[0140] In this embodiment, the region PD of the pixel circuit 100-2 and the region PD of the pixel circuit 100-1 belong to the same first portion of the substrate 102. In contrast, the region PD of the pixel circuit 100-3 belongs to another first portion of the substrate 102.

[0141] Preferably, if Fig.13 As shown in FIG. 1 , two pixel circuits 100 - 1 and 100 - 2 sharing the same first portion of substrate 102 share the same transistor Tres PD In this example, the transistor Tres PD Being a vertical gate transistor, the electrode 130 then includes two separate parts. A space e is arranged on the side of the region PD of the pixel circuit 100-1 between the first end of the first part of the electrode 130 and the first end of the second part of the electrode 130, and another space e is arranged on the side of the region PD of the pixel circuit 100-2 between the second end of the first part of the electrode 130 and the second end of the second part of the electrode 130.

[0142] Additionally, since pixel circuits 100-1 and 100-2 share the same first portion of substrate 102, even though pixel circuit 100-1 does not share its region 108 with pixel circuit 100-2, i , but the area 108 of the pixel circuit 100-1 i The groove 134 is preferably aligned with the corresponding area 108 of the pixel circuit 100-2. i The groove 134 is the same groove as the groove.

[0143] In this embodiment, the region mem of the pixel circuit 100-2i and mem i 'The area mem with the pixel circuit 100-3 i and mem i ' belongs to the same second portion of the substrate 102. In contrast, the region mem i and mem i 'Belongs to another second portion of the substrate 102.

[0144] Since the pixel circuits 100-2 and 100-3 share the same second portion of the substrate 102, the region 132 included therein is shared by the two pixel circuits 100-2 and 100-3, such as Fig.13 Thus, the transistor is formed in the common region 132, in this example, Figure 2 The transistors Tres, Tsiv and Tsel are shared by the two pixel circuits 100 - 2 and 100 - 3 .

[0145] In addition, since the pixel circuits 100-2 and 100-3 share the same second portion of the substrate 102, the two regions mem i and mem i ' can be associated with the two corresponding areas mem associated with the pixel circuit 100-3 i and mem i 'District 118 i Same area 118 i In other words, in this example, pixel circuits 100-2 and 100-3 share the same region 1181 and share the same region 1182. As an example, Fig.13 As shown in FIG. 1 , two regions mem of the pixel circuit 100 - 2 are i and mem i 'Each has a corresponding area 118 facing i The ends of the pixel circuit 100-3 are arranged on the same first side, and the two corresponding regions mem i and mem i 'Each has a facing area 118 i One end is arranged on the same second side of the first side, and the second side is opposite to the first side.

[0146] As an example, the association of the three pixel circuits 100-1, 100-2 and 100-3 described above may be repeated in the first direction in which the pixel circuits 100-1, 100-2 and 100-3 follow each other. Fig.13 A column of pixel circuits 100 is formed vertically in the image processing apparatus 100. The column of pixel circuits is repeated in a second direction orthogonal to the first direction to form a matrix of pixel circuits.

[0147] When the association of the above three pixel circuits 100-1, 100-2 and 100-3 is also in the second direction (in Fig.13 When repeated horizontally in the middle, each area mem of the pixel circuit 100 i 'Then preferably in the width direction by the portion of the electrode 114 laterally bounded, the portion of the electrode 114 also bounding the corresponding area mem of the adjacent pixel circuit 100 i '.

[0148] about Fig.13 The described embodiment allows a particularly compact matrix of pixel circuits 100 to be achieved.

[0149] The above has described Figures 4 to 13 In the exemplary pixel circuit 100, two storage areas mem i The present invention relates to an embodiment and variant embodiments of the pixel circuit 100 in the case of FIG. 1 . A person skilled in the art can adapt the description of this example to a pixel circuit 100 including only one region mem i Or relatively including more than two areas mem i As an example, only one region mem is included. i The pixel circuit 100 is used as a pixel circuit of a global shutter image sensor. As an example, similar to the previously described, the pixel circuit 100 includes three regions: i The pixel circuit 100 may be used in a TOF sensor.

[0150] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily appreciate other variations. Specifically, the pixel circuit 100 has been described as an example of an embodiment intended to be transmitted to the region mem i The case where the photogenerated charges are photogenerated electrons is described. A person skilled in the art is able to adapt the disclosure to the case where these charges are photogenerated holes, in particular by reversing all conductivity types indicated as an example and by adapting the control and polarization potential levels.

[0151] Finally, based on the functional description provided above, the actual implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art. Specifically, for example, using simulation tools implemented by a computer, a person skilled in the art is able to select the gate Gmem i 130 and 120 i The high and low levels of the control signals and / or the level(s) of polarization potentials applied to the substrate 102 and / or the levels of polarization potentials applied to the electrode 114 and / or the doping levels of the various layers, regions and boxes described.

Claims

1. A pixel circuit, comprising: Photoconversion zone; Insulated vertical electrodes; as well as at least one charge storage region; wherein the light conversion region belongs to the first portion of the semiconductor substrate; as well as wherein each charge storage region belongs to a second portion of the semiconductor substrate, the second portion being physically separated from the first portion of the semiconductor substrate by the insulated vertical electrode; The insulated vertical electrode passes through the semiconductor substrate from the first surface of the semiconductor substrate, and for each charge storage region, the pixel circuit further includes: a first doped region in contact with the charge storage region in the second portion; a second doped region in the first portion; a gate disposed on the first surface of the semiconductor substrate between the photoconversion region and the second doping region; and an electrical connector between the first doped region and the second doped region; The insulated vertical electrodes are configured to electrically and optically insulate, for each charge storage region, the first portion of the semiconductor substrate including the photoconversion region and the second doped region from the second portion of the semiconductor substrate including the charge storage region and the first doped region. 2 . The pixel circuit according to claim 1 , wherein for each charge storage region, the electrical connection is arranged outside the semiconductor substrate over the first face of the semiconductor substrate.

3. A pixel circuit according to claim 1, wherein each charge storage region is laterally defined in the width direction by two parts of the insulated vertical electrode that are parallel to and facing each other, and the first doped region in contact with the charge storage region is arranged at one end of the charge storage region along the length direction.

4. The pixel circuit according to claim 1, wherein: The semiconductor substrate is doped with a first conductivity type; The light conversion region includes a layer doped with a second conductivity type, the layer of the second conductivity type being arranged in the semiconductor substrate on the first face of the semiconductor substrate; For each charge storage region, the first doped region and the second doped region are arranged in the semiconductor substrate on the first face of the semiconductor substrate, and the first doped region and the second doped region are doped with the second conductivity type; as well as Each charge storage region comprises a region doped with the second conductivity type, the region being arranged in the semiconductor substrate on the first face of the semiconductor substrate.

5. The pixel circuit according to claim 4, wherein: For each charge storage region, the first doping region and the second doping region have the same doping level.

6. The pixel circuit according to claim 4, wherein: For each charge storage region, the first doped region and the second doped region have the same doping level as the layers of the photoconversion region.

7. The pixel circuit according to claim 4, wherein: For each charge storage region, the region of the charge storage region is more heavily doped than the first doped region.

8. The pixel circuit according to claim 4, wherein: For each charge storage region, the gate is placed on a channel region extending from the second doped region to the layer of the photoconversion region, the channel region being more lightly doped with the second conductivity type than the layer of the photoconversion region and the second doped region.

9. The pixel circuit according to claim 8, wherein: For each charge storage region, the channel region includes a first portion and a second portion, the second portion being more lightly doped than the first portion, the second portion extending from a layer of the photoconversion zone to the first portion, and the first portion extending from the second portion to the second doped region.

10. The pixel circuit according to claim 8, wherein: For each charge storage region, the second doped region is separated from the layer of the photoconversion region by the channel region and a region of the semiconductor substrate doped with the first conductivity type.

11. The pixel circuit according to claim 1, wherein: For each charge storage region, the pixel circuit comprises: a doped read region arranged in the semiconductor substrate on the side of the first face in the second portion of the semiconductor substrate having the charge storage region; and An additional gate is placed on a portion of the semiconductor substrate extending between the charge storage region and the reading region, the additional gate extending to the charge storage region. 12 . The pixel circuit according to claim 1 , wherein at least two charge storage regions belong to the same second portion of the semiconductor substrate.

13. The pixel circuit according to claim 1, comprising a circuit configured to: applying a first polarization potential to the first portion of the semiconductor substrate; as well as For each charge storage region: applying the first polarization potential to the second portion of the semiconductor substrate during each read phase of the charge storage region; as well as applying a second polarization potential to the second portion of the semiconductor substrate outside of a read phase of the charge storage region; Wherein the first polarization potential and the second polarization potential are configured such that a potential well in the charge storage region is deeper when the second polarization potential is applied than when the first polarization potential is applied.

14. A sensor comprising a plurality of pixel circuits according to claim 1.

15. The sensor of claim 14, wherein two adjacent pixel circuits share the same second portion of the semiconductor substrate.

16. The sensor of claim 14, wherein two adjacent pixel circuits share the same first portion of the semiconductor substrate.

17. The sensor of claim 14, further comprising a circuit configured to: applying a first polarization potential to the first portion of the semiconductor substrate; as well as For each charge storage region: applying the first polarization potential to the second portion of the semiconductor substrate including the storage region during each read phase of the charge storage region; as well as applying a second polarization potential to the second portion outside of a read phase of the charge storage region; Wherein the first polarization potential and the second polarization potential are configured such that a potential well in the charge storage region is deeper when the second polarization potential is applied to the second portion of the semiconductor substrate than when the first polarization potential is applied to the second portion of the semiconductor substrate.

18. A control method for the pixel circuit according to claim 1, comprising: polarizing the first portion of the semiconductor substrate using a first polarization potential; as well as For each charge storage region: polarizing the second portion of the semiconductor substrate with the first polarization potential during each read phase of the charge storage region; as well as polarizing the second portion with a second polarization potential outside of a read phase of the charge storage region; Wherein the first polarization potential and the second polarization potential are configured such that a potential well in the charge storage region is deeper when the second polarization potential is applied to the second portion of the semiconductor substrate than when the first polarization potential is applied to the second portion of the semiconductor substrate.

19. A pixel circuit comprising: Semiconductor substrate; a photoconversion region in the first portion of the semiconductor substrate; a charge storage region in a second portion of the semiconductor substrate; an insulated vertical electrode extending completely through the semiconductor substrate and positioned to electrically and optically insulate the charge storage region from the photoconversion region; a first doped region, in the second portion of the semiconductor substrate, in contact with the charge storage region; a second doped region in the first portion of the semiconductor substrate; a gate structure on the semiconductor substrate and positioned between the light conversion region and the second doped region; as well as An electrical connection is provided between the first doped region and the second doped region.

20. The pixel circuit of claim 19, wherein the electrical connection is arranged above the semiconductor substrate and extends over the insulated vertical electrode.

21. A pixel circuit according to claim 19, wherein two portions of the insulated vertical electrode extending parallel to each other and facing each other define the charge storage region in width, and wherein two other portions of the insulated vertical electrode extending parallel to each other and facing each other define the charge storage region in length.

22. The pixel circuit according to claim 19, further comprising: a doped read region in the second portion of the semiconductor substrate; as well as An additional gate structure is disposed on a portion of the second portion of the semiconductor substrate, the second portion extending above the semiconductor substrate and positioned between the charge storage region and the doped read region.

23. The pixel circuit according to claim 19, wherein: The semiconductor substrate is doped with a first conductivity type; The photoconversion region includes a layer doped with a second conductivity type; and The charge storage region is doped with the second conductivity type.

24. The pixel circuit of claim 23, wherein the second doped region is separated from the layer of the light conversion region by a channel region over which the gate structure extends.

25. The pixel circuit according to claim 24, wherein the channel region comprises: a first doped portion, contacting the second doped region; as well as The second doped portion is in contact with the light conversion region.

26. The pixel circuit of claim 19, further comprising a circuit configured to: applying a first polarization potential to the first portion of the semiconductor substrate; applying the first polarization potential to the second portion of the semiconductor substrate during each read phase of the charge storage region; as well as Outside of a read phase of the charge storage region, a second polarization potential different from the first polarization potential is applied to the second portion of the semiconductor substrate.

Images