A multi-threshold comparator

Abstract

The present invention provides a multi-threshold comparator, which includes: a first circuit unit, which includes a first current source and a first MOS tube, the input end of the first current source is connected to the power supply end, and the output end is connected to the first connection end of the first MOS tube; the second connection end of the first MOS tube is connected to the input voltage, and the control end is connected to the first connection end; a plurality of second circuit units, in each second circuit unit, the input end of the second current source is connected to the power supply end, and the output end is connected to the first connection end of the second MOS tube; the second connection end of the second MOS tube is connected to the threshold voltage, and the control end is connected to the control end of the first MOS tube; the input end of the third current source is connected to the power supply end, and the output end is connected to the first connection end of the third MOS tube; the control end of the third MOS tube is connected to the first connection end of the second MOS tube, and the second connection end is grounded; the output end of the second circuit unit is connected to the first connection end of the third MOS tube. Compared with the prior art, the present invention occupies less chip area and consumes less working current.

Description

[Technical field]

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a multi-threshold comparator. [Background technology]

[0002] Comparison circuits are widely used in various analog circuits. In some applications, it may be necessary to compare an input voltage with multiple thresholds. The traditional design is: if N threshold comparisons are required, N comparators are required. This occupies a large chip area, has a high cost, and has a high operating current. Please refer to Figure 1 As shown, it is a circuit diagram of a multi-threshold comparator in the prior art, which includes a comparator 1 and a comparator 2, and generates two output signals CO1 and CO2.

[0003] Therefore, it is necessary to propose an improved technical solution to overcome the above problems. [Summary of the invention]

[0004] The object of the present invention is to provide a multi-threshold comparator which occupies less chip area and consumes less operating current.

[0005] According to one aspect of the present invention, the present invention provides a multi-threshold comparator, which includes: a first circuit unit, which includes a first current source I1 and a first MOS transistor MN1, the input end of the first current source I1 is connected to the power supply end VDD, and the output end thereof is connected to the first connection end of the first MOS transistor MN1, the second connection end of the first MOS transistor MN1 is connected to the input voltage VA, and the control end of the first MOS transistor MN1 is connected to the first connection end thereof; a plurality of second circuit units, wherein each second circuit unit includes a second current source, a second MOS transistor, a third current source, a third MOS transistor, a threshold voltage and an output end, and the input end of the second current source is connected to the input end of the second MOS transistor MN1. The third current source is connected to the power supply terminal VDD, and its output end is connected to the first connection end of the second MOS tube; the second connection end of the second MOS tube is connected to the threshold voltage, and the control end of the second MOS tube is connected to the control end of the first MOS tube MN1; the input end of the third current source is connected to the power supply terminal VDD, and the output end is connected to the first connection end of the third MOS tube; the control end of the third MOS tube is connected to the first connection end of the second MOS tube, and the second connection end of the third MOS tube is grounded; the output end of the second circuit unit is connected to the first connection end of the third MOS tube, and the threshold voltage in each of the second circuit units is different.

[0006] Compared with the prior art, the present invention reuses part of the circuits and has a simple structure, so that the multi-threshold comparator provided by the present invention occupies less chip area and consumes less operating current.

Brief Description of the Drawings

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0008] Figure 1 It is a circuit diagram of a multi-threshold comparator in the prior art;

[0009] Figure 2 A circuit diagram of a multi-threshold comparator in one embodiment of the present invention;

[0010] Figure 3 FIG. 4 is a circuit diagram of a multi-threshold comparator in another embodiment of the present invention. [Specific implementation method]

[0011] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "connected", "connected", and "connected" herein that indicate electrical connection all refer to direct or indirect electrical connection.

[0013] Please refer to Figure 2 As shown, it is a circuit diagram of a multi-threshold comparator in one embodiment of the present invention. Figure 2 The multi-threshold comparator shown includes a circuit unit 210 , a circuit unit 220 , and a circuit unit 230 .

[0014] The circuit unit 210 includes a current source I1 and a MOS transistor MN1, wherein the input end of the current source I1 is connected to the power supply end VDD, and the output end thereof is connected to the first connection end of the MOS transistor MN1, the second connection end of the MOS transistor MN1 is connected to the input voltage VA, the control end of the MOS transistor MN1 is connected to the first connection end thereof, and the substrate end of the MOS transistor MN1 is grounded.

[0015] The circuit unit 220 includes a current source I2, a MOS transistor MN2, a current source I3, a MOS transistor MN3, an inverter INV1 and an output terminal CO1. The input terminal of the current source I2 is connected to the power supply terminal VDD, and the output terminal thereof is connected to the first connection terminal of the MOS transistor MN2; the second connection terminal of the MOS transistor MN2 is connected to the threshold voltage V1, the control terminal thereof is connected to the control terminal of the MOS transistor MN1, and the substrate terminal thereof is grounded; the input terminal of the current source I3 is connected to the power supply terminal VDD, and the output terminal thereof is connected to the first connection terminal of the MOS transistor MN3; the second connection terminal and the substrate terminal of the MOS transistor MN3 are grounded, and the control terminal thereof is connected to the first connection terminal of the MOS transistor MN2; the input terminal of the inverter INV1 is connected to the first connection terminal of the MOS transistor MN3, and the output terminal thereof is connected to the output terminal CO1 of the circuit unit 220.

[0016] The circuit unit 230 includes a current source I4, a MOS transistor MN4, a current source I5, a MOS transistor MN5, an inverter INV2 and an output terminal CO2. The input terminal of the current source I4 is connected to the power supply terminal VDD, and the output terminal thereof is connected to the first connection terminal of the MOS transistor MN4; the second connection terminal of the MOS transistor MN4 is connected to the threshold voltage V2, the control terminal thereof is connected to the control terminal of the MOS transistor MN1, and the substrate terminal thereof is grounded; the input terminal of the current source I5 is connected to the power supply terminal VDD, and the output terminal thereof is connected to the first connection terminal of the MOS transistor MN5; the second connection terminal and the substrate terminal of the MOS transistor MN5 are grounded, and the control terminal thereof is connected to the first connection terminal of the MOS transistor MN4; the input terminal of the inverter INV2 is connected to the first connection terminal of the MOS transistor MN5, and the output terminal thereof is connected to the output terminal CO2 of the circuit unit 230.

[0017] exist Figure 2 In the specific embodiment shown, MOS transistors MN1 to MN5 are all NMOS transistors, and the first connection terminal, the second connection terminal and the control terminal of MOS transistors MN1 to MN5 are respectively the drain, the source and the gate of the NMOS transistors; the voltage values ​​of the threshold voltage V1 and the threshold voltage V2 are different. In the design, the current of the current source I1 is equal to the current of the current source I2, and is also equal to the current of the current source I3, and is also equal to the current of the current source I4, and is also equal to the current of the current source I5; the width-to-length ratio of the MOS transistor MN1 is equal to the width-to-length ratio of the MOS transistor MN2, and is also equal to the width-to-length ratio of the MOS transistor MN3, and is also equal to the width-to-length ratio of the MOS transistor MN4, and is also equal to the width-to-length ratio of the MOS transistor MN5.

[0018] Among them, the circuit unit 210 and the circuit unit 220 can form a first comparator, which is used to compare the input voltage VA and the threshold voltage V1, and output the comparison result through the output terminal CO1. For example, when the threshold voltage V1 is greater than the input voltage VA, the output signal CO1 output by the output terminal CO1 of the first comparator is a first logic level; when the threshold voltage V1 is less than the input voltage VA, the output signal CO1 output by the output terminal CO1 of the first comparator is a second logic level. Figure 2 In the illustrated embodiment, the drain voltage VN1 of the MOS transistor MN1 is equal to (VA+Vgs_N1), where VA is the voltage value of the input voltage VA, and Vgs_N1 is the gate-source voltage value of the MOS transistor MN1. When the voltage of the threshold voltage V1 is greater than the voltage of the input voltage VA, the drain current of the MOS transistor MN2 is less than the current of the current source I2, and the drain voltage of the MOS transistor MN2 is pulled up by the current source I2. Therefore, the current of the MOS transistor MN3 increases, causing the drain voltage of the MOS transistor MN3 to decrease. After passing through the inverter INV1, the output signal CO1 is a high level (which can be called a first logic level). On the contrary, when the voltage of the threshold voltage V1 is less than the voltage of the input voltage VA, the drain current of the MOS transistor MN2 is greater than the current of the current source I2, and the drain voltage of the MOS transistor MN2 is pulled down. Therefore, the current of the MOS transistor MN3 decreases, causing the drain voltage of the MOS transistor MN3 to be pulled up by the current source I3. After passing through the inverter INV1, the output signal CO1 is a low level (which can be called a second logic level). It can be seen that Figure 2 The first comparator composed of the circuit unit 210 and the circuit unit 220 can realize the function of comparing the input voltage VA with the threshold voltage V1.

[0019] Among them, the circuit unit 210 and the circuit unit 230 can form a second comparator, which is used to compare the input voltage VA and the threshold voltage V2, and output the comparison result through the output terminal CO2. For example, when the threshold voltage V2 is greater than the input voltage VA, the output signal CO2 output by the output terminal CO2 of the second comparator is a first logic level; when the threshold voltage V2 is less than the input voltage VA, the output signal CO2 output by the output terminal CO2 of the second comparator is a second logic level. Figure 2In the illustrated embodiment, the drain voltage VN1 of the MOS transistor MN1 is equal to (VA+Vgs_N1), where VA is the voltage value of the input voltage VA, and Vgs_N1 is the gate-source voltage value of the MOS transistor MN1. When the voltage of the threshold voltage V2 is greater than the voltage of the input voltage VA, the drain current of the MOS transistor MN4 is less than the current of the current source I4, and the drain voltage of the MOS transistor MN4 is pulled up by the current source I4. Therefore, the current of the MOS transistor MN5 increases, causing the drain voltage of the MOS transistor MN5 to decrease. After passing through the inverter INV2, the output signal CO2 is a high level (which can be called a first logic level). On the contrary, when the voltage of the threshold voltage V2 is less than the voltage of the input voltage VA, the drain current of the MOS transistor MN4 is greater than the current of the current source I4, and the drain voltage of the MOS transistor MN4 is pulled down. Therefore, the current of the MOS transistor MN5 decreases, causing the drain voltage of the MOS transistor MN5 to be pulled up by the current source I5. After passing through the inverter INV2, the output signal CO2 is a low level (which can be called a second logic level). It can be seen that Figure 2 The second comparator composed of the circuit unit 210 and the circuit unit 230 can realize the function of comparing the input voltage VA with the threshold voltage V2.

[0020] Please refer to Figure 3 As shown, it is a circuit diagram of a multi-threshold comparator in another embodiment of the present invention. Figure 2 compared to, Figure 3 The multi-threshold comparator shown has an additional circuit unit 240. Figure 3 The multi-threshold comparator shown includes a circuit unit 210 , a circuit unit 220 , a circuit unit 230 , and a circuit unit 240 .

[0021] Figure 3 The circuit unit 210, the circuit unit 220, and the circuit unit 230 are shown in FIG. Figure 2 The circuit structures and working principles of the circuit unit 210 , the circuit unit 220 , and the circuit unit 230 are the same, and are not described in detail herein.

[0022] The circuit unit 240 includes a current source I6, a MOS transistor MN6, a current source I7, a MOS transistor MN7, an inverter INV3 and an output terminal CO3. The input terminal of the current source I6 is connected to the power supply terminal VDD, and the output terminal thereof is connected to the first connection terminal of the MOS transistor MN6; the second connection terminal of the MOS transistor MN6 is connected to the threshold voltage V3, the control terminal thereof is connected to the control terminal of the MOS transistor MN1, and the substrate terminal thereof is grounded; the input terminal of the current source I7 is connected to the power supply terminal VDD, and the output terminal thereof is connected to the first connection terminal of the MOS transistor MN7; the second connection terminal and the substrate terminal of the MOS transistor MN7 are grounded, and the control terminal thereof is connected to the first connection terminal of the MOS transistor MN6; the input terminal of the inverter INV3 is connected to the first connection terminal of the MOS transistor MN7, and the output terminal thereof is connected to the output terminal CO3 of the circuit unit 240.

[0023] exist Figure 3 In the specific embodiment shown, MOS transistors MN1-MN7 are all NMOS transistors, and the first connection terminal, the second connection terminal and the control terminal of MOS transistors MN1-MN7 are respectively the drain, the source and the gate of the NMOS transistors; the voltage values ​​of threshold voltage V1, threshold voltage V2 and threshold voltage V3 are different. In the design, the current of current source I1 is equal to the current of current source I2, and is also equal to the current of current source I3, and is also equal to the current of current source I4, and is also equal to the current of current source I5, and is also equal to the current of current source I6, and is also equal to the current of current source I7; the width-to-length ratio of MOS transistor MN1 is equal to the width-to-length ratio of MOS transistor MN2, and is also equal to the width-to-length ratio of MOS transistor MN3, and is also equal to the width-to-length ratio of MOS transistor MN4, and is also equal to the width-to-length ratio of MOS transistor MN5, and is also equal to the width-to-length ratio of MOS transistor MN6, and is also equal to the width-to-length ratio of MOS transistor MN7.

[0024] The circuit unit 210 and the circuit unit 240 can form a third comparator, which is used to compare the input voltage VA and the threshold voltage V3, and output the comparison result through the output terminal CO3. For example, when the threshold voltage V3 is greater than the input voltage VA, the output signal CO3 output by the output terminal CO3 of the third comparator is a first logic level; when the threshold voltage V3 is less than the input voltage VA, the output signal CO3 output by the output terminal CO3 of the third comparator is a second logic level. Figure 3In the embodiment shown, the voltage VN1 at the drain terminal of the MOS transistor MN1 is equal to (VA+Vgs_N1), where VA is the voltage value of the input voltage VA, and Vgs_N1 is the gate-source voltage value of the MOS transistor MN1. When the voltage of the threshold voltage V3 is greater than the voltage of the input voltage VA, the drain current of the MOS transistor MN6 is less than the current of the current source I6, and the drain voltage of the MOS transistor MN6 is pulled up by the current source I6. Therefore, the current of the MOS transistor MN7 increases, causing the drain voltage of the MOS transistor MN7 to decrease. After passing through the inverter INV3, the output signal CO3 is a high level (which can be called a first logic level). On the contrary, when the voltage of the threshold voltage V3 is less than the voltage of the input voltage VA, the drain current of the MOS transistor MN6 is greater than the current of the current source I6, and the drain voltage of the MOS transistor MN6 is pulled down. Therefore, the current of the MOS transistor MN7 decreases, causing the drain voltage of the MOS transistor MN7 to be pulled up by the current source I7. After passing through the inverter INV3, the output signal CO3 is a low level (which can be called a second logic level). It can be seen that Figure 3 The third comparator composed of the circuit unit 210 and the circuit unit 240 can realize the function of comparing the input voltage VA with the threshold voltage V3.

[0025] Among them, the circuit unit 210 can be called the first circuit unit 210. Since the circuit structures of the circuit units 220, 230, and 240 are consistent or the same, the circuit units 220, 230, and 240 can all be called second circuit units 220, 230, and 240. The current source I1 can be called the first current source. Since the relative positional relationship of the current sources I2, I4, and I6 in the second circuit units 220, 230, and 240 is consistent or the same, the current sources I2, I4, and I6 can all be called second current sources. Since the relative positional relationship of the current sources I3, I5, and I7 in the second circuit units 220, 230, and 240 is consistent or the same, the current sources I3, I5, and I7 can all be called third current sources. The MOS transistor MN1 can be called a first MOS transistor. Since the relative positions of the MOS transistors MN2, MN4, and MN6 in the second circuit units 220, 230, and 240 are consistent or the same, the MOS transistors MN2, MN4, and MN6 can all be called second MOS transistors. Since the relative positions of the MOS transistors MN3, MN5, and MN7 in the second circuit units 220, 230, and 240 are consistent or the same, the MOS transistors MN3, MN5, and MN7 can all be called third MOS transistors. Figure 2 and Figure 3 The inverters INV1 , INV2 , and INV3 in the second circuit units 220 , 230 , and 240 are shown removed.

[0026] exist Figure 2The multi-threshold comparator shown includes a first circuit unit 210 and two second circuit units 220 and 230, which can compare an input voltage with two threshold voltages V1 and V2. Figure 3 The multi-threshold comparator shown includes a first circuit unit 210 and three second circuit units 220, 230, 240, which can compare the input voltage with three threshold voltages V1, V2 and V3. By analogy, the multi-threshold comparator in the present invention can include a first circuit unit 210 and N second circuit units 220, 230, 240, which can compare the input voltage VA with N threshold voltages, wherein N is a natural number greater than or equal to 2.

[0027] In summary, the multi-threshold comparator provided by the present invention includes:

[0028] The first circuit unit 210 includes a first current source I1 and a first MOS transistor MN1, wherein the input end of the first current source I1 is connected to the power supply end VDD, the output end thereof is connected to the first connection end of the first MOS transistor MN1, the second connection end of the first MOS transistor MN1 is connected to the input voltage VA, the control end of the first MOS transistor MN1 is connected to the first connection end thereof, and the substrate end of the first MOS transistor MN1 is grounded;

[0029] A plurality of second circuit units, wherein each second circuit unit comprises a second current source I2, I4, I6, a second MOS transistor MN2, MN4, MN6, a third current source I3, I5, I7, a third MOS transistor MN3, MN5, MN7, a threshold voltage V1-VN and an output terminal CO1-CON, the input terminal of the second current source I2, I4, I6 is connected to the power supply terminal VDD, and the output terminal thereof is connected to the first connection terminal of the second MOS transistor MN2, MN4, MN6; the second connection terminal of the second MOS transistor MN2, MN4, MN6 is connected to the threshold voltage V1-VN, and the second MOS transistor MN2, MN4, MN6 is connected to the threshold voltage V1-VN. The control end of MN6 is connected to the control end of the first MOS transistor MN1, and the substrate ends of the second MOS transistors MN2, MN4, and MN6 are grounded; the input ends of the third current sources I3, I5, and I7 are connected to the power supply end VDD, and the output ends thereof are connected to the first connection ends of the third MOS transistors MN3, MN5, and MN7; the control ends of the third MOS transistors MN3, MN5, and MN7 are connected to the first connection ends of the second MOS transistors MN2, MN4, and MN6, and the second connection ends and substrate ends of the third MOS transistors MN3, MN5, and MN7 are both grounded; the output ends CO1 to CON are connected to the first connection ends of the third MOS transistors MN3, MN5, and MN7. The threshold voltages V1 to VN in each second circuit unit are different.

[0030] In one embodiment, the first MOS transistor MN1, the second MOS transistors MN2, MN4, MN6 and the third MOS transistors MN3, MN5, MN7 are all NMOS transistors; the first connection end, the second connection end and the control end of the first MOS transistor MN1 are respectively the drain, the source and the gate of the NMOS transistor; the first connection end, the second connection end and the control end of the second MOS transistors MN2, MN4, MN6 are respectively the drain, the source and the gate of the NMOS transistor; the first connection end, the second connection end and the control end of the third MOS transistors MN3, MN5, MN7 are respectively the drain, the source and the gate of the NMOS transistor.

[0031] In one embodiment, the current of the first current source I1 is equal to the current of the second current source I2, I4, I6, and the current of the first current source I1 is equal to the current of the third current source I3, I5, I7; the width-to-length ratio of the first MOS tube MN1 is equal to the width-to-length ratio of the second MOS tubes MN2, MN4, MN6, and the width-to-length ratio of the first MOS tube MN1 is equal to the width-to-length ratio of the third MOS tubes MN3, MN5, MN7.

[0032] In one embodiment, the second circuit unit further includes an inverter INV1-INVN, the input end of the inverter INV1-INVN is connected to the first connection end of the third MOS tube MN3, MN5, MN7, and the output end of the inverter INV1-INVN is connected to the output end CO1-CON of the second circuit unit. Each second circuit unit and the first circuit unit 210 form a comparator, which is used to compare the input voltage VA with the threshold voltage V1-VN in the second circuit unit of the comparator, and output the comparison result through the output end CO1-CON in the second circuit unit of the comparator. For example, when the threshold voltage V1-VN of a second circuit unit is greater than the input voltage VA, the output signal output by the output end CO1-CON of the second circuit unit is a first logic level; when the threshold voltage V1-VN of a second circuit unit is less than the input voltage VA, the output signal output by the output end CO1-CON of the second circuit unit is a second logic level. Specifically, the drain voltage VN1 of the first MOS tube MN1 is equal to (VA+Vgs_N1), wherein VA is the voltage value of the input voltage VA, and Vgs_N1 is the gate-source voltage value of the first MOS tube MN1. When the voltage value of the threshold voltage Vn of the nth second circuit unit (or any one of the second circuit units) is greater than the voltage value of the input voltage VA, the drain (or first connection end) current of the second MOS tubes MN2, MN4, MN6 is less than the current of the second current sources I2, I4, I6, and the drain (or first connection end) voltage of the second MOS tubes MN2, MN4, MN6 is pulled up by the second current sources I2, I4, I6. Therefore, the current of the third MOS tubes MN3, MN5, MN7 increases, resulting in a decrease in the drain (or first connection end) voltage of the third MOS tubes MN3, MN5, MN7. After passing through the inverter INVn, the output signal COn is a high level (which can be called a first logic level). On the contrary, when the threshold voltage Vn of the nth second circuit unit (or any one of the second circuit units) is less than the voltage of the input voltage VA, the drain (or first connection end) current of the second MOS tubes MN2, MN4, MN6 is greater than the current of the second current sources I2, I4, I6, and the drain (or first connection end) voltage of the second MOS tubes MN2, MN4, MN6 is pulled down. Therefore, the current of the third MOS tubes MN3, MN5, MN7 is reduced, resulting in the drain (or first connection end) voltage of the third MOS tubes MN3, MN5, MN7 being pulled up by the third current sources I3, I5, I7. After passing through the inverter INVn, the output signal COn is a low level (which can be called a second logic level), wherein 2≦n≦N, and n and N are natural numbers greater than or equal to 2.

[0033] Since the multi-threshold comparator provided by the present invention reuses the first circuit unit 210 and has a simple structure, it can occupy less chip area and consume less operating current.

[0034] In the present invention, words such as "connect", "connected", "connect", "connected", etc., which indicate electrical connection, indicate direct or indirect electrical connection unless otherwise specified. The direct electrical connection indicates a direct connection between two or more objects without any intervening objects, and the indirect electrical connection indicates a connection between two or more objects with one or more objects (such as electrical components or electrical units such as resistors, capacitors, inductors, switches, filters, etc.) intervening.

[0035] It should be noted that any changes made by those skilled in the art to the specific embodiments of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the above specific embodiments.

Claims

1. A multi-threshold comparator, characterized in that: It includes: A first circuit unit includes a first current source I1 and a first MOS transistor MN1, wherein an input end of the first current source I1 is connected to a power supply end VDD, an output end thereof is connected to a first connection end of the first MOS transistor MN1, a second connection end of the first MOS transistor MN1 is connected to an input voltage VA, and a control end of the first MOS transistor MN1 is connected to a first connection end thereof; A plurality of second circuit units, wherein each second circuit unit comprises a second current source, a second MOS transistor, a third current source, a third MOS transistor, a threshold voltage and an output end, wherein an input end of the second current source is connected to the power supply end VDD, and an output end thereof is connected to a first connection end of the second MOS transistor; a second connection end of the second MOS transistor is connected to the threshold voltage, and a control end of the second MOS transistor is connected to a control end of the first MOS transistor MN1; an input end of the third current source is connected to the power supply end VDD, and an output end thereof is connected to a first connection end of the third MOS transistor; a control end of the third MOS transistor is connected to the first connection end of the second MOS transistor, and a second connection end of the third MOS transistor is grounded; an output end of the second circuit unit is connected to the first connection end of the third MOS transistor, and the threshold voltage in each second circuit unit is different.

2. The multi-threshold comparator according to claim 1, characterized in that: Each of the second circuit units and the first circuit unit form a comparator, which is used to compare the input voltage VA with the threshold voltage in the second circuit unit of the comparator, and output the comparison result through the output end of the second circuit unit of the comparator.

3. The multi-threshold comparator according to claim 1, characterized in that: When the threshold voltage of one of the second circuit units is greater than the input voltage VA, the output end of the second circuit unit outputs the first logic level of the output signal; when the threshold voltage of one of the second circuit units is less than the input voltage VA, the output end of the second circuit unit outputs the second logic level of the output signal.

4. The multi-threshold comparator according to claim 1, characterized in that: The first MOS transistor MN1, the second MOS transistor and the third MOS transistor are all NMOS transistors; The first connection terminal, the second connection terminal and the control terminal of the first MOS transistor MN1 are respectively the drain, the source and the gate of the NMOS transistor; The first connection terminal, the second connection terminal and the control terminal of the second MOS tube are respectively the drain, the source and the gate of the NMOS transistor: The first connection terminal, the second connection terminal and the control terminal of the third MOS transistor are respectively the drain, the source and the gate of the NMOS transistor.

5. The multi-threshold comparator according to claim 1, characterized in that: The substrate ends of the first MOS transistor MN1, the second MOS transistor and the third MOS transistor are all grounded.

6. The multi-threshold comparator according to claim 1, characterized in that: The current of the first current source I1 is equal to the current of the second current source, and the current of the first current source I1 is equal to the current of the third current source; The width-to-length ratio of the first MOS transistor MN1 is equal to the width-to-length ratio of the second MOS transistor, and the width-to-length ratio of the first MOS transistor MN1 is equal to the width-to-length ratio of the third MOS transistor.

7. The multi-threshold comparator according to claim 1, characterized in that: The second circuit unit further includes an inverter, an input end of the inverter is connected to the first connection end of the third MOS tube, and an output end of the inverter is connected to an output end of the second circuit unit.

8. The multi-threshold comparator according to claim 3, characterized in that: When the voltage value of the threshold voltage of the second circuit unit is greater than the voltage value of the input voltage VA, the current of the first connection end of the second MOS transistor is less than the current of the second current source, and the voltage of the first connection end of the second MOS transistor is pulled up by the second current source, so the current of the third MOS transistor increases, causing the voltage of the first connection end of the third MOS transistor to decrease, so that the output signal output by the output end of the second circuit unit is a first logic level; When the voltage value of the threshold voltage of the second circuit unit is less than the voltage value of the input voltage VA, the current at the first connection end of the second MOS tube is greater than the current of the second current source, and the voltage at the first connection end of the second MOS tube is pulled down. Therefore, the current of the third MOS tube is reduced, resulting in the voltage at the first connection end of the third MOS tube being increased by the third current source, so that the output signal outputted by the output end of the second circuit unit is at the second logic level.

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