Display device

Abstract

The present disclosure relates to a display device, which includes: a substrate, which includes a display area, a non-display area and a conductive material; a display layer, which is located on the top surface of the substrate and includes a light-emitting element; a signal line, which extends from the display layer and enters the non-display area; a conductive adhesive member, which is located on the bottom surface of the substrate; and a circuit board, which is electrically connected to the signal line through contact between the circuit board and the conductive adhesive member and contact between the conductive material in the substrate and both the signal line and the conductive adhesive member.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the development of multimedia, display devices have become increasingly important. Various types of display devices have been used, such as liquid crystal display ("LCD") devices, organic light emitting diode ("OLED") display devices, and the like.

[0003] Foldable display devices are gaining increasing attention. Because they are portable and have a wide display screen, they have advantages over smartphones and tablet personal computers ("PCs"). In a foldable display device, a pad portion on which a driver integrated circuit ("IC") or other printed circuit board is provided may be provided at an edge portion of an outer portion of a substrate forming the foldable display device. The pad portion may correspond to a frame of the foldable display device, which is a non-display area where no image is displayed. Summary of the Invention

[0004] Embodiments provide a display device including a pad portion and minimizing the size of a bezel.

[0005] However, the embodiments are not limited to those described herein. The above and other embodiments will become more apparent to those skilled in the art to which the present invention pertains by referencing the detailed description given below.

[0006] According to an embodiment, a display device includes: a substrate including a display area, a non-display area and a conductive material; a display layer located on a top surface of the substrate and including a light-emitting element; a signal line extending from the display layer and entering the non-display area; a conductive adhesive member located on a bottom surface of the substrate; and a circuit board electrically connected to the signal line through contact between the circuit board and the conductive adhesive member and contact between the conductive material in the substrate and both the signal line and the conductive adhesive member.

[0007] In an embodiment, the conductive material may include a plurality of first conductive balls, and the substrate may further include a polymer resin in which the first conductive balls are dispersed.

[0008] In an embodiment, the conductive adhesive member may include a plurality of second conductive balls and an adhesive resin.

[0009] In an implementation, the conductive adhesive member may overlap the non-display area and the signal line.

[0010] In an embodiment, the signal line may define a conductive pad, and the conductive pad may be electrically connected to the substrate at a pad hole defined in the display layer.

[0011] In an embodiment, in the non-display area, the conductive pad, the first conductive ball, and the second conductive ball may overlap and contact each other.

[0012] In an embodiment, the circuit board may include a bump electrode, the bump electrode may overlap the first conductive ball and the second conductive ball that are in contact with each other, and the bump electrode may be in contact with the second conductive ball.

[0013] In an embodiment, the outer side surfaces of the substrate, the conductive adhesive member, and the circuit board may be aligned with each other and in contact with each other.

[0014] In embodiments, the conductive material may be throughout the substrate.

[0015] According to an embodiment, the display device includes a substrate including a display area, a non-display area, a first substrate area and a second substrate area, a display layer located on the upper surface of the substrate and including a light-emitting element, a signal line in the second substrate area extending from the display layer to the non-display area, a conductive adhesive member located on the bottom surface of the second substrate area of ​​the substrate, and a circuit board that is electrically connected to the signal line through contact between the circuit board and the conductive adhesive member and contact between the conductive material in the second substrate area and both the signal line and the conductive adhesive member.

[0016] Other features and aspects will become apparent from the following detailed description, the accompanying drawings, and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above embodiments and features and other embodiments and features will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0018] Figure 1 is a perspective view showing an embodiment of the front side of the display device;

[0019] Figure 2 It shows Figure 1 A perspective view of an embodiment of the back side of the display device;

[0020] Figure 3 yes Figure 1 A cross-sectional view of an embodiment of a display device;

[0021] Figure 4 It shows Figure 1 A plan view of an embodiment of a sensor electrode layer of a display device;

[0022] Figure 5 It shows Figure 4 A plan view of an embodiment of a driving electrode, a sensing electrode and a first connecting portion;

[0023] Figure 6 It is along Figure 5 A sectional view taken along line II';

[0024] Figure 7 It shows Figure 1 A plan view of an embodiment of a display pad region of a display device;

[0025] Figure 8 It is along Figure 7 A sectional view taken along line II-II';

[0026] Figure 9 It shows Figure 8 An enlarged cross-sectional view of an embodiment of region B;

[0027] Figure 10 It is along Figure 7 A sectional view taken along line III-III';

[0028] Figure 11 is a cross-sectional view of an embodiment of a display device;

[0029] Figure 12 yes Figure 11 A plan view of an embodiment of a substrate of a display device;

[0030] Figure 13 yes Figure 11 A cross-sectional view of an embodiment of a display device;

[0031] Figure 14 yes Figure 13 An enlarged cross-sectional view of an embodiment of a portion of a display device;

[0032] Figure 15 is a plan view of an embodiment of a substrate of a display device;

[0033] Figure 16 yes Figure 15 A cross-sectional view of an embodiment of a display device;

[0034] Figure 17 yes Figure 15 a cross-sectional view of an embodiment of a portion of a display device; and

[0035] Figures 18 to 20 It is a plan view showing a structure in an embodiment of a method of providing a substrate for a display device. DETAILED DESCRIPTION

[0036] The present invention will now be described more fully below with reference to the accompanying drawings that illustrate embodiments of the invention. However, the present invention can be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0037] It should also be understood that when a layer is referred to as being associated with another layer (such as, "on" another layer or substrate), the layer may be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when a layer is referred to as being associated with another layer (such as, "directly on" another layer or substrate), there are no other layers, substrates, or intervening layers. Throughout the specification, the same reference numerals refer to the same components.

[0038] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “one”, “a kind of”, “the” and “at least one” do not represent a limit on quantity and are intended to include both the singular and the plural. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be interpreted as limiting “one” or “a kind of”. “Or” means “and / or”. As used herein, the phrase “and / or” includes any and all combinations of one or more associated listed items. It will also be understood that when the phrases “comprising” and / or “comprising”, or “including” and / or “comprising” are used in this specification, the presence of the stated features, regions, wholes, steps, operations, elements and / or components is represented, but the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0039] In addition, relative terms (such as "lower" or "bottom" and "upper" or "top") may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the accompanying drawings is flipped, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, the term "lower" may encompass both "lower" and "upper" orientations, depending on the particular orientation of the accompanying drawings. Similarly, if the device in one of the accompanying drawings is flipped, the element described as being "below" or "beneath" the other elements will be oriented as being "above" the other elements. Thus, the term "lower" or "below" may encompass both "lower" and "upper" orientations.

[0040] As used herein, "about" and "approximately" include the stated value and the mean within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0042] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but should include deviations in shape due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, sharp angles shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims presented.

[0043] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0044] Figure 1 is a perspective view showing an embodiment of the front side of the display device 10, and Figure 2 It shows Figure 1 A perspective view of the back side of the display device 10 according to an embodiment of the present invention.

[0045] refer to Figure 1 and Figure 2 The display device 10, which is an electronic device for displaying moving images or still images, can be used not only in portable electronic devices (for example, mobile phones, smart phones, tablet personal computers ("PCs"), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players ("PMPs"), navigation devices, or ultra-mobile PCs ("UMPCs"), but can also be used in various other electronic display products (such as televisions ("TVs"), notebook computers, display screens, billboards, or Internet of Things ("IoT") devices).

[0046] The display device 10 may include a display panel 100 , a display driving circuit 200 , and a circuit board 300 .

[0047] The first direction (or X-axis direction), i.e., the direction of the short side of the display device 10, may be, for example, the horizontal direction of the display device 10. The second direction (or Y-axis direction), i.e., the direction of the long side of the display device 10, may be the vertical direction of the display device 10. The third direction (or Z-axis direction) may be the thickness direction of the display device 10.

[0048] In a plan view (e.g., along the third direction), the display panel 100 may have a planar shape, such as a rectangular shape having short sides extending along a first direction (or X-axis direction) and long sides extending along a second direction (or Y-axis direction). The corners where the short sides and long sides of the display panel 100 respectively intersect with each other may be rounded to have a predetermined curvature in a plan view, or may be right angles in a plan view. The planar shape of the display panel 100 is not particularly limited, and the display panel 100 may have various other shapes in a plan view, such as a polygonal shape, a circular shape, or an elliptical shape.

[0049] The display panel 100 may be flat, such as being disposed in a plane defined by a first direction and a second direction intersecting each other, but is not limited thereto. In an embodiment, for example, the display panel 100 may include curved portions at the left and right ends of the display panel 100 along the first and / or second directions, and may have a uniform or varying curvature. The display panel 100 may be flexible, such as being foldable, bendable, and / or rollable.

[0050] The display panel 100 may be a light-emitting display panel including a light-emitting element. In embodiments, for example, the display panel 100 may be an organic light-emitting diode ("OLED") display panel using an OLED having an organic light-emitting layer, a micro light-emitting diode ("microLED") display panel using microLEDs, a quantum dot light-emitting diode ("QLED") display panel including a quantum dot light-emitting layer, or an inorganic light-emitting diode ("ILED") display panel using an ILED including an inorganic semiconductor.

[0051] The display panel 100 may be a foldable, bendable, or rollable flexible display panel. In an embodiment, for example, the display panel 100 may be a foldable display panel that can be folded or unfolded, a curved display panel having a curved display surface, a curved display panel that is curved in all areas except the display surface, a rollable display panel that can be rolled or rolled out, or a stretchable display panel that can be stretched. Alternatively, the display panel 100 may be a transparent transparent display panel so that the background or objects outside the display panel 100 at the back of the display panel 100 can be seen from the front of the display panel 100. Alternatively, the display panel 100 may be a reflective display panel that can reflect objects or background on its front.

[0052] The display panel 100 may include a display area DA that displays an image and a non-display area NDA that does not display an image. The non-display area NDA may be adjacent to the display area DA, such as extending around the display area DA in a plan view. The display area DA may include pixels that display an image (e.g., display pixels or display elements). The non-display area NDA may be defined as a planar area extending between a side of the display area DA and an outer surface or outer edge of the display panel 100. Various components or elements of the display panel 100 and / or the display device 10 may include display areas and non-display areas corresponding to the display area DA and the non-display area NDA described above.

[0053] refer to Figure 2 , the display driving circuit 200 can be set on the circuit board 300.

[0054] The display driver circuit 200 may generate voltages and electrical signals for driving and / or controlling the display panel 100. The display driver circuit 200 may be an integrated circuit ("IC") attached to the circuit board 300, such as in a chip-on-film ("COF") manner. Alternatively, the display driver circuit 200 may be attached to the circuit board 300, such as in a chip-on-glass ("COG") or chip-on-plastic ("COP") manner, or by ultrasonic bonding, to be attached to the display panel 100, thereby reducing the size of the non-display area (NDA).

[0055] The circuit board 300 may be attached to the display panel 100 at its back surface and at its first end via a conductive adhesive member CAM. Thus, the circuit board 300 may be electrically connected to both the display panel 100 and the display driver circuit 200. The display panel 100 and the display driver circuit 200 may receive electrical signals such as digital video data, timing signals, and drive voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board ("FPCB"), a printed circuit board ("PCB"), or a flexible film such as a COF.

[0056] The conductive adhesive member CAM may be an anisotropic conductive film ("ACF") including a plurality of conductive members, such as a plurality of conductive balls. The conductive adhesive member CAM may include a plurality of conductive balls dispersed in an adhesive resin ADR.

[0057] Since the circuit board 300 is attached to the back of the display panel 100 and is located within the planar area of ​​the display panel 100 in a plan view, the bezel size of the display device 10 is reduced by omitting the planar area occupied by the circuit board 300 bent along the outer surface of the display device 10.

[0058] Figure 3 yes Figure 1 sectional view of an embodiment of a display device 10 .

[0059] refer to Figure 3 , the display panel 100 may include a substrate SUB, a display layer DISL (eg, an image display layer), a sensor electrode layer SENL (eg, an input sensing layer), and a polarization film PF (eg, a polarization layer).

[0060] The substrate SUB may include or be formed of an insulating material such as a polymer resin PSM. The substrate SUB may be a foldable, bendable, and / or rollable flexible substrate.

[0061] The substrate SUB may include a conductive material. Specifically, the substrate SUB may include a conductive material dispersed in a polymer resin PSM. The conductive material may include a plurality of first conductive balls CM1 (e.g., a first conductive member) arranged in a plurality. The first conductive balls CM1 may be discrete conductive members within the polymer resin PSM. Because the substrate SUB includes the first conductive balls CM1, it can function as a conductor under certain conditions. The substrate SUB will be described in detail later.

[0062] The display layer DISL may be provided on the substrate SUB. The display layer DISL may be a layer including a light-emitting region that displays an image. The display layer DISL may include a thin film transistor ("TFT") layer, a light-emitting element layer EML, and an encapsulation layer TFEL. The thin film transistor ("TFT") layer includes a plurality of TFTs ST, the light-emitting element layer EML includes a light-emitting element 170 that generates and / or emits light and is provided in the light-emitting region. The encapsulation layer TFEL encapsulates the light-emitting element layer EML on the substrate SUB.

[0063] In the display area DA, the display layer DISL may include not only a light-emitting area but also conductive lines such as a gate signal line GLS, a data signal line DLS, and a power supply line VDS for driving and / or controlling the light-emitting element 170. In the non-display area NDA, the display layer DISL may include a scan driving unit that outputs a scan signal to the gate signal line GLS, and a fan-out line that connects the data signal line DLS and the display driving circuit 200 to each other.

[0064] The sensor electrode layer SENL may be disposed on the display layer DISL. The sensor electrode layer SENL may include sensor electrodes SE. The sensor electrode layer SENL may be a layer that detects a touch input using the sensor electrodes SE.

[0065] A polarizing film PF may be additionally provided on the sensor electrode layer SENL. The polarizing film PF may include a first base member, a linear polarizing film, a phase retardation film (such as a quarter-wavelength (λ / 4) plate), and a second base member. The first base member, the phase retardation film, the linear polarizing film, and the second base member may be stacked in sequence on the sensor electrode layer SENL.

[0066] A cover window (not shown) may be additionally provided on the polarizing film PF. The cover window may be attached to the polarizing film PF by an optically clear adhesive ("OCA") film.

[0067] A panel bottom cover (not shown) may be additionally provided below the display panel 100. The panel bottom cover may be attached to the bottom surface of the display panel 100 by an adhesive member. The adhesive member may be a pressure-sensitive adhesive ("PSA"). The panel bottom cover may include at least one of a light blocking member for absorbing incident light from outside the display device 10, a buffer member for absorbing shock from the outside, and a heat dissipation member for effectively releasing heat from the display panel 100.

[0068] The circuit board 300 to which the display driving circuit 200 is attached may be disposed under the display panel 100. The circuit board 300 may be attached to the bottom surface of the substrate SUB via the conductive adhesive member CAM.

[0069] Attaching the circuit board 300 to the substrate SUB may include heat pressing, so that the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM can be pressed into contact with each other and thus electrically connected to a plurality of lines provided on the substrate SUB. As used herein, elements in contact with each other may form an interface therebetween, without limitation. This will be described in detail later.

[0070] Figure 4 It shows Figure 1 FIG. 1 is a plan view of an embodiment of a sensor electrode layer SENL of a display device 10 .

[0071] refer to Figure 4 The sensor electrodes SE may be provided in a plurality, including a plurality of sensor electrodes SE in the sensor electrode layer SENL. The sensor electrodes SE may include two types of electrodes, for example, drive electrodes TE and sensing electrodes RE. Within the sensor electrode layer SENL, the drive electrodes TE and sensing electrodes RE may be provided in a plurality, including a plurality of drive electrodes TE and a plurality of sensing electrodes RE. The sensor electrodes SE may be driven using a mutual capacitance method, but is not limited thereto. The mutual capacitance method is achieved by applying a drive signal to the drive electrodes TE and detecting a voltage that charges the mutual capacitance from the sensing electrodes RE.

[0072] For convenience, Figure 4 Only the drive electrodes TE, the sensing electrodes RE, the dummy patterns DE provided in plural, including a plurality of dummy patterns DE, the plurality of sensor lines SL, the first sensor pads TP1 provided in plural, including a plurality of first sensor pads TP1, and the second sensor pads TP2 provided in plural, including a plurality of second sensor pads TP2, are shown. A touch drive circuit (not shown) may be connected to the sensor electrode layer SENL at the first and second sensor pads TP1 and TP2. The display pads PD, the first and second sensor pads TP1, and TP2 may each be a conductive pad.

[0073] refer to Figure 4 The sensor electrode layer SENL includes a touch sensing area TSA that detects external inputs, and a touch peripheral area TPA (e.g., a non-sensing area) that does not detect external inputs and is adjacent to the touch sensing area TSA. In embodiments, the touch peripheral area TPA may surround the touch sensing area TSA. The touch sensing area TSA may overlap with the display area DA of the display layer DISL, and the touch peripheral area TPA may overlap with the non-display area NDA of the display layer DISL.

[0074] The touch sensing area TSA may include sensor electrodes SE and dummy patterns DE. The sensor electrodes SE may be electrodes provided with mutual capacitance to detect external input, such as external input from an object or user (eg, input tool) outside the display device 10 and / or display panel 100.

[0075] The sensor electrodes SE may include drive electrodes TE and sense electrodes RE. In the touch peripheral area TPA, the sense lines RL may be provided in a plural manner, including a plurality of sense lines RL, the first drive lines TL1 may be provided in a plural manner, including a plurality of first drive lines TL1, and the second drive lines TL2 may be provided in a plural manner, including a plurality of second drive lines TL2. In an embodiment, the sense electrodes RE may be defined as first sense electrodes, and the drive electrodes TE may be defined as second sense electrodes. In this case, the sense lines RL may be defined as first sensor lines, and the first and second drive lines TL1 and TL2 may be defined as second sensor lines. Alternatively, the drive electrodes TE may be defined as first sensor electrodes, and the sense electrodes RE may be defined as second sensor electrodes. In this case, the first and second drive lines TL1 and TL2 may be defined as first sensor lines, and the sense lines RL may be defined as second sensor lines.

[0076] The sensing electrodes RE may be arranged in parallel along a first direction (or X-axis direction) and along a second direction (or Y-axis direction). The sensing electrodes RE may be electrically connected to each other along the first direction (or X-axis direction). Pairs of sensing electrodes RE adjacent to each other along the first direction (or X-axis direction) may be connected to each other. Pairs of sensing electrodes RE adjacent to each other along the second direction (or Y-axis direction) may be electrically insulated from each other.

[0077] The driving electrodes TE may be arranged in parallel along a first direction (or an X-axis direction) and along a second direction (or a Y-axis direction). The driving electrodes TE may be electrically connected to each other along the second direction (or the Y-axis direction). Pairs of driving electrodes TE adjacent to each other along the second direction (or the Y-axis direction) may be connected to each other. Pairs of driving electrodes TE adjacent to each other along the second direction (or the Y-axis direction) may be connected to each other via a first connection portion CE1. The first connection portion CE1 may be provided in a plurality, including a plurality of first connection portions CE1.

[0078] The first connection portion CE1 may have a planar shape bent at least once in a plan view. Figure 4 Each of the first connection portions CE1 is shown to have an angular bracket shape (such as "<" or ">"), but the planar shape of the first connection portion CE1 is not particularly limited. Since multiple pairs of drive electrodes TE adjacent to each other along the second direction (or Y-axis direction) are connected by the multiple first connection portions CE1, even if one of the first connection portions CE1 is disconnected, the drive electrodes TE can be stably connected to each other along the second direction (or Y-axis direction). Figure 4 It is shown that two driving electrodes TE adjacent to each other along the second direction are connected to each other through one of the first connection portions CE1 including two angle brackets, but the number of the first connection portions CE1 is not particularly limited.

[0079] Due to the presence of the first connection portion CE1, the driving electrode TE and the sensing electrode RE may be electrically insulated at the intersection therebetween. Therefore, a mutual capacitance may be provided or formed between the driving electrode TE and the sensing electrode RE.

[0080] refer to Figure 4 The planar shape of the dummy pattern DE may be surrounded by the planar shape of the driving electrode TE or the sensing electrode RE. The dummy pattern DE may be electrically isolated from the driving electrode TE or the sensing electrode RE. The dummy pattern DE may be spaced apart from the driving electrode TE or the sensing electrode RE. The dummy pattern DE may be electrically floating.

[0081] Figure 4 The driving electrodes TE, sensing electrodes RE, and dummy patterns DE are shown as each having a diamond shape in a plan view, but are not limited thereto. Alternatively, in a plan view, the driving electrodes TE, sensing electrodes RE, and / or dummy patterns DE may have various other planar shapes other than a diamond shape, such as a rectangular shape, a polygonal shape, a circular shape, or an elliptical shape.

[0082] A plurality of sensor lines SL may be provided in the touch peripheral area TPA. The plurality of sensor lines SL may include a sensing line RL connected to the sensing electrode RE, and first and second drive lines TL1 and TL2 connected to the drive electrode TE. The sensing line RL may be defined as a first sensor line, and the first and second drive lines TL1 and TL2 may be defined as a second sensor line.

[0083] The sensing electrodes RE disposed on one side of the touch sensing area TSA may be connected to the sensing lines RL one by one. Figure 4 A group of sensing electrodes RE electrically connected to each other along the first direction (or the X-axis direction) may be connected to a sensing line RL at the right end of the touch sensing area TSA. A plurality of second sensor pads TP2 may be provided in the touch peripheral area TPA, including a plurality of second sensor pads TP2. Sensing lines RL may be connected to the second sensor pads TP2 on a one-to-one basis. Therefore, the touch drive circuit may be electrically connected to the sensing electrodes RE at the second sensor pads TP2.

[0084] A group of driving electrodes TE electrically connected to each other along the second direction (or Y-axis direction) may be connected to the first driving line TL1 at a first side of the touch sensing area TSA, and may be connected to the second driving line TL2 at a second side of the touch sensing area TSA opposite to the first side thereof. Figure 4For example, a group of driving electrodes TE may be connected to a first driving line TL1 at a lower end (e.g., a first side) of the touch sensing area TSA, and connected to a second driving line TL2 at an upper end (e.g., a second side) of the touch sensing area TSA. The second driving line TL2 may be connected to the driving electrodes TE on the upper side of the touch sensing area TSA via the outer left side of the touch sensing area TSA.

[0085] The first drive line TL1 and the second drive line TL2 can be connected to the first sensor pad TP1 on a one-to-one basis. Therefore, the touch drive circuit can be electrically connected to the drive electrode TE at the first sensor pad TP1. Since the drive electrodes TE are connected to the first drive line TL1 and the second drive line TL2 at corresponding sides of the touch sensing area TSA, and each drive electrode TE receives a touch drive signal, an electrical difference between the touch drive signal applied to the drive electrode TE located on the lower side of the touch sensing area TSA and the touch drive signal applied to the drive electrode TE located on the upper side of the touch sensing area TSA due to resistance-capacitance ("RC") delay in the touch drive signal can be reduced or effectively prevented.

[0086] The touch peripheral area TPA further includes a display pad area DPA in which a plurality of display pads DP are provided. The display pads DP may be connected to the data signal lines DLS in the display area DA of the display panel 100.

[0087] The first sensor pad area TPA1 may be disposed at a first end of the display pad area DPA including the display pad DP and include the first sensor pad TP1. The second sensor pad area TPA2 may be disposed at a second end of the display pad area DPA, opposite to the first end of the display pad area DPA, and include the second sensor pad TP2. The first sensor pad area TPA1, the display pad area DPA, and the second sensor pad area TPA2 may together form a pad area of ​​the display panel 100.

[0088] In a plan view, the display pad area DPA, the first sensor pad area TPA1, and the second sensor pad area TPA2, and their components, may be disposed on the first surface of the substrate SUB at the lower side of the display panel 100 along the second direction. The circuit board 300 may be disposed on a second surface (e.g., a rear surface) of the substrate SUB, which is opposite to the first surface along the thickness direction of the display device 10, to correspond to each of the display pads DP, the first sensor pads TP1, and the second sensor pads TP2. The display pads DP, the first sensor pads TP1, and the second sensor pads TP2 may face the circuit board 300 with the substrate SUB and the conductive adhesive member CAM therebetween. The display pads DP, the first sensor pads TP1, and the second sensor pads TP2 may be electrically connected to the circuit board 300 via the substrate SUB and the conductive adhesive member CAM.

[0089] like Figure 4 As shown in FIG, the touch sensing area TSA may include a driving electrode TE and a sensing electrode RE. Therefore, a touch input or the presence of an object from outside the display device 10 and / or the display panel 100 may be detected using mutual capacitance between the driving electrode TE and the sensing electrode RE.

[0090] Figure 5 It shows Figure 4 TE, sensing electrode RE and first connection portion CE1 of the embodiment of the enlarged plan view. Specifically, Figure 5 yes Figure 4 An enlarged plan view of area A.

[0091] refer to Figure 5 The drive electrodes TE, sensing electrodes RE, and dummy patterns DE may be provided in the same layer and spaced apart from each other along the substrate SUB. That is, a gap may be provided or formed between the drive electrodes TE and sensing electrodes RE that are spaced apart from each other. Furthermore, gaps may be provided or formed between the drive electrodes TE and the dummy patterns DE, and between the sensing electrodes RE and the dummy patterns DE, along the substrate SUB. Elements in the same layer may be corresponding portions or corresponding patterns of the same material layer.

[0092] The first connection portion CE1 may be provided in a different layer from the drive electrodes TE and the sensing electrodes RE. The first connection portion CE1 may overlap with a corresponding pair of drive electrodes TE along the third direction (or the Z-axis direction), the pair of drive electrodes TE being adjacent to each other along the second direction (or the Y-axis direction) and connected to each other through the first connection portion CE1. The first connection portion CE1 may not overlap with the sensing electrode RE along the third direction (or the Z-axis direction). The first end of each of the first connection portions CE1 may be connected to one of a pair of drive electrodes TE adjacent to each other along the second direction (or the Y-axis direction) via a first touch contact hole TCNT1 (e.g., a contact hole), and the second end of each of the first connection portions CE1 may be connected to the other of the pair of drive electrodes TE via the other of the first touch contact holes TCNT1.

[0093] In a plan view, the drive electrodes TE, the sensing electrodes RE, and the first connection portion CE1 may each be arranged or formed in a mesh or fishnet structure. In addition, the dummy pattern DE may be arranged or formed in a mesh or fishnet structure in a plan view. The mesh or fishnet structure may be defined by solid portions with openings defined therebetween.

[0094] Therefore, the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the dummy pattern DE may not overlap with the emission region (e.g., the light emission region) from which light is emitted from the display panel 100. Specifically, the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the solid portion of the dummy pattern DE may not overlap with the emission region. Therefore, since the emission region is not blocked by the driving electrode TE, the sensing electrode RE, the first connection portion CE1, and the solid portion of the dummy pattern DE, a decrease in the brightness of light emitted from the emission region may be reduced or effectively prevented.

[0095] Alternatively, in a plan view, the drive electrodes TE, the sensing electrodes RE, the first connection portions CE1, and the dummy patterns DE may be disposed or formed as a surface (e.g., a single solid portion) rather than being disposed or formed in a mesh or fishnet structure. In order to prevent a decrease in the brightness of light emitted from the emission region due to the solid portions of the drive electrodes TE, the sensing electrodes RE, the first connection portions CE1, and the dummy patterns DE, the materials of the drive electrodes TE, the sensing electrodes RE, the first connection portions CE1, and the dummy patterns DE may include a transparent conductive material such as indium tin oxide ("ITO") or indium zinc oxide ("IZO").

[0096] The emission regions may include: a plurality of first emission regions E1, each comprising a plurality of first emission regions E1 that emit light of a first color; a plurality of second emission regions E2, each comprising a plurality of second emission regions E2 that emit light of a second color different from the first color; and a plurality of third emission regions E3, each comprising a plurality of third emission regions E3 that emit light of a third color different from the first and second colors. In an embodiment, for example, the first color may be red, the second color may be green, and the third color may be blue. The emission regions may correspond to display pixels in the display area DA, respectively, without limitation thereto.

[0097] The first emission region E1, the second emission region E2, and the third emission region E3 may each have a diamond or rectangular shape in a plan view, but are not limited thereto. Alternatively, in a plan view, the first emission region E1, the second emission region E2, and the third emission region E3 may have various other planar shapes other than a rectangular shape, such as a polygonal shape, a circular shape, or an elliptical shape.

[0098] Each of the first emission region E1, the second emission region E2, and the third emission region E3 has a size in a plan view (eg, a plane size). In the size of the first emission region E1, the second emission region E2, and the third emission region E3, Figure 5 It is shown that the size of the third emission area E3 is the largest size and the size of the second emission area E2 is the smallest, but is not limited thereto.

[0099] One of the first emission regions E1, two of the second emission regions E2, and one of the third emission regions E3 may be defined as a pixel emission group PXG that emits light to represent a white grayscale. That is, a white grayscale may be represented by light emitted from one of the first emission regions E1, light emitted from two of the second emission regions E2, and light emitted from one of the third emission regions E3.

[0100] The emission regions may be arranged in rows extending along a first direction (or X-axis direction) and in columns extending along a second direction (or Y-axis direction). Each emission region may have a side defining an outer edge of the emission region. The side may extend obliquely relative to the first direction (or X-axis direction) and / or the second direction (or Y-axis direction).

[0101] The second emission regions E2 may be arranged in odd-numbered rows. The second emission regions E2 may be arranged side by side along the first direction (or X-axis direction) within the odd-numbered rows. The second emission regions E2 arranged side by side along the first direction may form a group of emission regions. In each of the odd-numbered rows, one of each pair of second emission regions E2 adjacent to each other along the first direction (or X-axis direction) may have a long side extending along the first oblique direction DR1 and a short side extending along the second oblique direction DR2. However, the other of each pair of second emission regions E2 may have a long side extending along the second oblique direction DR2 and a short side extending along the first oblique direction DR1. The first oblique direction DR1 may be a direction between the first direction (or X-axis direction) and the second direction (or Y-axis direction), and the second oblique direction DR2 may be a direction intersecting the first oblique direction DR1.

[0102] The first emission regions E1 and the third emission regions E3 may be arranged in even-numbered rows. The first emission regions E1 and the third emission regions E3 may be arranged side by side along the first direction (or the X-axis direction) within even-numbered rows. The first emission regions E1 arranged side by side along the first direction may form a group of emission regions, and the third emission regions E3 arranged side by side along the first direction may form a group of emission regions. The first emission regions E1 and the third emission regions E3 may be alternately arranged in even-numbered rows.

[0103] The second emission regions E2 may be arranged in odd-numbered columns. The second emission regions E2 may be arranged side by side along the second direction (or Y-axis direction) within the odd-numbered columns. In each of the odd-numbered columns, one of each pair of second emission regions E2 adjacent to each other along the second direction (or Y-axis direction) may have a long side extending along the first oblique direction DR1 and a short side extending along the second oblique direction DR2. However, the other of each pair of second emission regions E2 may have a long side extending along the second oblique direction DR2 and a short side extending along the first oblique direction DR1.

[0104] The first emission region E1 and the third emission region E3 may be arranged in even-numbered columns. The first emission region E1 and the third emission region E3 may be arranged side by side in even-numbered columns. The first emission region E1 and the third emission region E3 may be arranged alternately along even-numbered columns.

[0105] Figure 6 It is along Figure 5 A cross-sectional view taken along line II'.

[0106] refer to Figure 6The display layer DISL, including the TFT layer TFTL, the light-emitting element layer EML, and the encapsulation layer TFEL, may be sequentially disposed on the substrate SUB. The sensor electrode layer SENL, including the sensor electrodes SE, may be disposed on the display layer DISL. That is, the sensor electrode layer SENL faces the substrate SUB, with the display layer DISL interposed therebetween.

[0107] A first buffer layer BF1 may be disposed on the first surface of the substrate SUB, and a second buffer layer BF2 may be disposed on the first buffer layer BF1. The first and second buffer layers BF1 and BF2 may be sequentially disposed on the first surface of the substrate SUB to protect the TFT ST of the TFT layer TFTL and the light-emitting layer 172 (e.g., light-emitting pattern) of the light-emitting element layer EML, which are susceptible to moisture, from moisture that may penetrate the substrate SUB.

[0108] Each of the first buffer layer BF1 and the second buffer layer BF2 may include a plurality of inorganic material layers stacked along the thickness direction of the display panel 100 (e.g., in a direction away from the substrate SUB). In an embodiment, for example, each of the first buffer layer BF1 and the second buffer layer BF2 may be formed into a multilayer structure in which one or more inorganic material layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked. In an embodiment, one of the first buffer layer BF1 and the second buffer layer BF2 may be omitted.

[0109] The first light-blocking layer BML (e.g., a first light-blocking pattern) may be provided in a plurality along the substrate SUB, including a plurality of first light-blocking layers BML provided on the first buffer layer BF1. The first light-blocking layer BML may include or be formed as a single-layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Alternatively, the first light-blocking layer BML may be an organic material layer including a black pigment.

[0110] An active layer ACT (e.g., an active layer pattern) may be provided in a plurality along the substrate SUB, including the active layer ACT of the plurality of TFTs ST provided on the second buffer layer BF2. The active layer ACT may include polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon ("LTPS"), amorphous silicon, or an oxide semiconductor material. In the active layer ACT including polycrystalline silicon or an oxide semiconductor material, the ion-doped region of the active layer ACT may be a conductive region having conductivity.

[0111] The active layer ACT may overlap or correspond to the first light-blocking layer BML along the third direction (or Z-axis direction). Since light incident through the substrate SUB can be blocked by the first light-blocking layer BML, leakage current flowing into the active layer ACT due to the incident light can be reduced or effectively prevented.

[0112] A gate insulating layer 130 may be provided or formed on the active layer ACT. The gate insulating layer 130 may include an inorganic material layer such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, or may be formed as an inorganic material layer such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0113] The gate electrode G may be provided in a plurality, including the gate electrodes G of a plurality of TFTs ST provided on the gate insulating layer 130. The gate electrodes G of the TFTs ST may overlap or correspond to the active layer ACT along the third direction (or the Z-axis direction). The gate electrode G may be provided or formed as a single-layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0114] The portion of the active layer ACT that overlaps the gate electrode G along the third direction (or the Z-axis direction) may include a plurality of channel regions CHA including a plurality of channel regions CHA. The active layer ACT may include a first conductive region COA1 and a second conductive region COA2, each of which is provided in a plurality, including the plurality of first conductive regions COA1 and the plurality of second conductive regions COA2 extending from opposite sides of the channel region CHA, respectively.

[0115] The first interlayer insulating layer 141 may be provided on the gate electrode G. The first interlayer insulating layer 141 may be provided or formed as an inorganic material layer, such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating layer 141 may include a plurality of inorganic material layers.

[0116] The capacitor electrode CAE may be provided in a plurality, including a plurality of capacitor electrodes CAE provided on the first interlayer insulating layer 141. The capacitor electrodes CAE may overlap or correspond to the gate electrode G along the third direction (or the Z-axis direction). The capacitor electrode CAE may be provided or formed as a single-layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0117] The second interlayer insulating layer 142 may be disposed on the capacitor electrode CAE. The second interlayer insulating layer 142 may be disposed or formed as an inorganic material layer, such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 142 may include multiple inorganic material layers.

[0118] The first electrode S and the second electrode D may each be provided in plural, including a plurality of first electrodes S and a plurality of second electrodes D of the TFT ST provided on the second interlayer insulating layer 142. The first electrode S and the second electrode D may be formed in a single-layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0119] The first electrode S of the TFT ST may be connected to the first conductive region COA1, which is disposed to extend from a first side of the channel region CHA of the active layer ACT, through contact holes penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142. The second electrode D of the TFT ST may be connected to the second conductive region COA2, which is disposed to extend from a second side of the channel region CHA of the active layer ACT, through contact holes penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142.

[0120] A first organic layer 150 for planarizing a height difference formed by the TFT ST may be disposed on the first and second electrodes S and D. The first organic layer 150 may be disposed or formed as an organic material layer including acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0121] The first connection electrode ANDE1 (e.g., connection electrode) may be provided in plural, including a plurality of first connection electrodes ANDE1 provided on the first organic layer 150. The first connection electrodes ANDE1 may be respectively connected to the second electrodes D of the TFTs ST through contact holes penetrating the first organic layer 150. The first connection electrode ANDE1 may be provided or formed as a single-layer structure or a multi-layer structure including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0122] The second organic layer 160 may be provided on the first connection electrode ANDE 1. The second organic layer 160 may be provided or formed as an organic material layer including acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0123] Figure 6The TFT ST is shown as being provided or formed as a top-gate TFT in which the gate electrode G is provided above the active layer ACT (e.g., the gate electrode G is provided farther from the substrate SUB than the active layer ACT), but is not limited thereto. Alternatively, the TFT ST may be formed as a bottom-gate TFT in which the gate electrode G is provided below the active layer ACT (e.g., the gate electrode G is provided closer to the substrate SUB than the active layer ACT), or as a dual-gate TFT in which the gate electrode G is provided both above and below the active layer ACT.

[0124] The light emitting element layer EML is disposed on the TFT layer TFTL. The light emitting element layer EML may include a light emitting element 170 and a third organic layer 180 sequentially disposed from the substrate SUB, wherein the light emitting element 170 is disposed in plural, including a plurality of light emitting elements 170 .

[0125] Each of the light-emitting elements 170 may include a first light-emitting electrode 171, a light-emitting layer 172, and a second light-emitting electrode 173. The first light-emitting electrode 171 faces the second light-emitting electrode 173, with the light-emitting layer 172 therebetween. Each of the second emission region E2 and the third emission region E3 may be a region in which the first light-emitting electrode 171, the light-emitting layer 172, and the second light-emitting electrode 173 are sequentially stacked along the thickness direction of the display panel 100, so that holes from the first light-emitting electrode 171 and electrons from the second light-emitting electrode 173 can combine in the light-emitting layer 172 to generate and emit light. In this case, the first light-emitting electrode 171 may be an anode electrode, and the second light-emitting electrode 173 may be a cathode electrode.

[0126] The first light emitting electrode 171 may be disposed in plural along the substrate SUB, including a plurality of first light emitting electrodes 171 disposed or formed on the second organic layer 160. The first light emitting electrodes 171 may be connected to the first connection electrodes ANDE1 through contact holes penetrating the second organic layer 160, respectively.

[0127] In a top emission structure in which the light emitting element 170 emits light in a direction from the light emitting layer 172 of the light emitting element 170 to the second light emitting electrode 173, the first light emitting electrode 171 may be configured or formed as a single material layer of Mo, Ti, Cu or Al, or may be configured or formed as a stacked material layer of Al and Ti (e.g., Ti / Al / Ti), Al and ITO (e.g., ITO / Al / ITO), a silver (Ag)-palladium (Pd)-copper (Cu) (APC) alloy, or an APC alloy and ITO (e.g., ITO / APC / ITO).

[0128] The third organic layer 180 defines the second emission region E2 and the third emission region E3. To this end, the third organic layer 180 may be provided or formed on the second organic layer 160 to expose a portion of the first light-emitting electrode 171 of the light-emitting element 170 at each emission region. The third organic layer 180 may cover the edge of each of the first light-emitting electrodes 171. The third organic layer 180 may be provided or formed as an organic material layer including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0129] The light-emitting layer 172 is disposed or formed on the first light-emitting electrode 171. The light-emitting layer 172 may include an organic material to emit light of a predetermined color. In an embodiment, for example, the light-emitting layer 172 may each include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a matrix and a dopant. The organic material layer may include a material capable of emitting light of a predetermined color and may include or be formed of a phosphorescent material or a fluorescent material.

[0130] In an embodiment, for example, the Figure 5 The organic material layer of the light-emitting layer 172 emitting the first color light in the first emission region E1 of the present invention may include a phosphorescent material or be formed of a phosphorescent material, wherein the phosphorescent material includes a base material and at least one dopant material, the base material includes carbazole biphenyl ("CBP") or 1,3-bis(carbazol-9-yl)benzene ("mCP"), and the at least one dopant material is selected from bis(1-phenylisoquinolinolato) iridium acetylacetonate (PIQIr(acac)), bis(1-phenylquinolinolato) iridium acetylacetonate (PQIr(acac)), tris(1-phenylquinolinolato) iridium (PQIr) and platinum octaethylporphyrin (PtOEP). In an embodiment, the organic material layer is provided or formed in ( Figure 5 The organic material layer of the light emitting layer 172 in the first emission region E1 may include or be formed of a fluorescent material including PBD:Eu(DBM)3(Phen) or perylene. However, embodiments are not limited to these examples.

[0131] In an embodiment, for example, the organic material layer of the light-emitting layer 172 emitting light of the second color disposed or formed in the second emission region E2 may include or be formed of a phosphorescent material, the phosphorescent material including a base material and a dopant material, the base material including CBP or mCP, and the dopant material including face-tris(2-phenylpyridine)iridium)(Ir(ppy)3). In an embodiment, the organic material layer of the light-emitting layer 172 disposed or formed in the second emission region E2 may include or be formed of a fluorescent material, the fluorescent material including tris(8-hydroxyquinoline)aluminum (Alq3). However, embodiments are not limited to these examples.

[0132] In an embodiment, for example, the organic material layer of the light-emitting layer 172 emitting light of the third color disposed or formed in the third emission region E3 may include or be formed of a phosphorescent material, the phosphorescent material including a base material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111. However, the embodiment is not limited to this example.

[0133] The second light emitting electrode 173 may be disposed or formed on the light emitting layer 172. The second light emitting electrode 173 may be disposed or formed to cover the light emitting layer 172. The second light emitting electrode 173 may be a common layer corresponding to all display pixels. A covering layer (not shown) may be disposed or formed on the second light emitting electrode 173.

[0134] In a top emission structure, the second light emitting electrode 173 may include or be formed of a transparent conductive oxide ("TCO") material (such as ITO or IZO) or a semi-transparent metal material (such as magnesium (Mg), Ag, or an alloy thereof). The second light emitting electrode 173 including or formed of a semi-transparent metal material provides improved emission efficiency of the light emitting element 170 due to the microcavity.

[0135] The light emitting layer 172 may be disposed on the top surface of the first light emitting electrode 171 and the inclined surface of the third organic layer 180. The second light emitting electrode 173 may be disposed on the top surface of the light emitting layer 172 and the inclined surface of the third organic layer 180. The top surface may be the surface farthest from the substrate SUB.

[0136] The encapsulation layer TFEL may be arranged or formed on the light-emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic material layer to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulation layer TFEL may also include at least one organic material layer to protect the light-emitting element layer EML from foreign matter such as dust. The inorganic material layer may be arranged or formed into a multilayer structure in which one or more inorganic material layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked. The organic material layer may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, or may be formed from an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0137] The sensor electrode layer SENL is provided on the encapsulation layer TFEL and may include sensor electrodes SE.

[0138] The third buffer layer BF3 may be provided on the encapsulation layer TFEL. The third buffer layer BF3 may be a layer having insulating and optical functions. The third buffer layer BF3 may include at least one inorganic material layer. In an embodiment, for example, the third buffer layer BF3 may be provided or formed as a multilayer structure in which one or more inorganic material layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked. The third buffer layer BF3 may be provided or formed by a lamination process using a flexible material, a spin coating process using a solution-based material, a slit die coating process, or a deposition process. In an embodiment, the third buffer layer BF3 may be omitted.

[0139] The first connection portion CE1 may be provided on the third buffer layer BF3. The first connection portion CE1 may be provided or formed as a single material layer of Mo, Ti, Cu, or Al, or may be formed as a stacked material layer of Al and Ti (e.g., Ti / Al / Ti), Al and ITO (e.g., ITO / Al / ITO), APC alloy, or APC alloy and ITO (e.g., ITO / APC / ITO).

[0140] The first sensor insulating layer TINS1 may be disposed on the first connection portion CE1. The first sensor insulating layer TINS1 may be a layer having both insulating and optical functions. The first sensor insulating layer TINS1 may be disposed or formed as an inorganic material layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first sensor insulating layer TINS1 may be disposed or formed by a lamination process using a flexible material, a spin coating process using a solution-based material, a slit die coating process, or a deposition process.

[0141] The drive electrodes TE and the sense electrodes RE may be disposed on the first sensor insulating layer TINS1, that is, disposed in the same layer on the first sensor insulating layer TINS1. The drive electrodes TE and the sense electrodes RE may not overlap with the second emission regions E2 and the third emission regions E3. The drive electrodes TE and the sense electrodes RE may be disposed or formed as a single layer of Mo, Ti, Cu, or Al, or may be disposed or formed as a stacked material layer of Al and Ti (e.g., Ti / Al / Ti), Al and ITO (e.g., ITO / Al / ITO), an APC alloy, or an APC alloy and ITO (e.g., ITO / APC / ITO).

[0142] The second sensor insulating layer TINS2 may be disposed on the driving electrode TE and the sensing electrode RE. The second sensor insulating layer TINS2 may face the first sensor insulating layer TINS1 with the driving electrode TE and the sensing electrode RE therebetween. The second sensor insulating layer TINS2 may be a layer having insulating and optical functions. The second sensor insulating layer TINS2 may include at least one of an inorganic material layer and an organic material layer. The inorganic material layer may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic material layer may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second sensor insulating layer TINS2 may be disposed or formed by a lamination process using a flexible material, a spin coating process using a solution-type material, a slit die coating process, or a deposition process. Reference Figure 6 , the driving electrodes TE and the sensing electrodes RE may be disposed in the same layer as each other, and may simultaneously include the same material or be formed of the same material so as to be corresponding parts of the same material layer.

[0143] Hereinafter, how to connect the conductive wires via the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 in the display device 10 will be described.

[0144] Figure 7 It shows Figure 1 FIG. 1 is a plan view of an embodiment of a pad region of a display device 10 . Figure 8 It is along Figure 7 A sectional view taken along line II-II'. Figure 9 It shows Figure 8 An enlarged cross-sectional view of region B. Figure 10 It is along Figure 7 A cross-sectional view taken along line III-III'.

[0145] refer to Figure 7 The pad area may be provided in the non-display area NDA of the substrate SUB. A plurality of signal lines disposed in the display area DA and including a plurality of lines may extend from the display area DA to the non-display area NDA, with distal ends of the plurality of lines disposed in the display pad area DPA. The distal ends of the plurality of lines may respectively define conductive pads in the non-display area NDA. The plurality of lines may include a plurality of gate signal lines GLS and a plurality of data signal lines DLS.

[0146] The non-display area NDA may further include a plurality of lines, including a power line VDS and a sensing line RL. The plurality of lines may extend from a portion of the non-display area NDA that does not include the pad area into the pad area. In an embodiment, the sensing line RL may extend into the second sensor pad area TPA2. The power line VDS may extend into the display pad area DPA or the second sensor pad area TPA2. Figure 7 Only a portion of the pad area is shown, and except for Figure 7 Various lines other than those shown in FIG. 1 may also be provided in the pad region.

[0147] The gate signal line GLS may extend from the gate signal line GLS in the display area DA and may be a conductive line through which an electrical signal, such as a gate signal, is applied to the display pixels in the display area DA. The data signal line DLS may extend from the data signal line DLS in the display area DA and may be a conductive line through which an electrical signal, such as a data signal, is applied to the display pixels in the display area DA.

[0148] The power line VDS may extend from a first power line (e.g., a power line) in the display area DA and may be a conductive line through which an electrical signal, such as a power supply voltage, is applied to the display area DA. The sensing line RL may extend from the sensing electrode RE in the display area DA and may be a conductive line through which an electrical signal, such as a touch sensing signal, is applied to the display area DA and / or an electrical signal is output from the display area DA.

[0149] The pad region includes: a plurality of gate line pads GP connected to a gate signal line GLS; a plurality of data line pads DLP connected to a data signal line DLS; a power supply pad VDP connected to a power supply line VDS; and a second sensor pad TP2 connected to a sensing line RL. The gate line pads GP may be an extension of the gate signal line GLS and may include the same material as the gate signal line GLS; the data line pads DLP may be an extension of the data signal line DLS and may include the same material as the data signal line DLS; the power supply pads VDP may be an extension of the power supply line VDS and may include the same material as the power supply line VDS; and the second sensor pads TP2 may be an extension of the sensing line RL and may include the same material as the sensing line RL. Because they include the same material, the elements can be in the same layer as one another, forming corresponding patterns of the same material layer.

[0150] In a plan view, the pad region may include a region along a first direction (eg, Figure 4The length of the pad area may extend along the edge of the display panel 100. The gate signal line GLS, the gate line pad GP, the data signal line DLS, the data line pad DLP, the power line VDS, the power pad VDP, the sensing line RL, and the second sensor pad TP2 may each have a width along the length direction of the pad area and / or the edge of the display panel 100. The width of the gate line pad GP may be greater than the width of the gate signal line GLS, the width of the data line pad DLP may be greater than the width of the data signal line DLS, the width of the power pad VDP may be greater than the width of the power line VDS, and the width of the second sensor pad TP2 may be greater than the width of the sensing line RL. However, embodiments are not limited thereto. Alternatively, the widths of the gate line pad GP, the data line pad DLP, the power pad VDP and the second sensor pad TP2 may be the same as or smaller than the widths of the gate signal line GLS, the data signal line DLS, the power line VDS and the sensing line RL, respectively.

[0151] The gate line pads GP, data line pads DLP, power pads VDP, and second sensor pads TP2 on the first surface of the substrate SUB may be electrically connected to a circuit board 300 disposed under the substrate SUB (eg, on the second surface of the substrate SUB) through the substrate SUB.

[0152] refer to Figure 8 and Figure 9 The TFT ST, the light emitting element 170, and the sensor electrode layer SENL may be disposed in the display area DA of the substrate SUB. A portion of the gate signal line GLS and the gate line pad GP may be disposed in the non-display area NDA of the substrate SUB.

[0153] The substrate SUB may include a base layer such as a polymer resin PSM and first conductive balls CM1 dispersed in the polymer resin PSM to provide conductivity within the substrate SUB. The first conductive balls CM1 may be randomly dispersed in the polymer resin PSM.

[0154] The polymer resin PSM may include polyimide ("PI"), polyethersulfone ("PES"), polyacrylate ("PA"), polyarylate ("PAR"), polyetherimide ("PEI"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyallyl ester, polycarbonate ("PC"), cellulose triacetate ("CAT"), cellulose acetate propionate ("CAP"), or a combination thereof.

[0155] Each of the first conductive balls CM1 may include a core and a conductive film surrounding the core. The core of the first conductive ball CM1 may be elastic. Therefore, the core of the first conductive ball CM1 may maintain contact with the second conductive ball CM2 of the conductive adhesive member CAM and thus be electrically connected to the second conductive ball CM2 of the conductive adhesive member CAM. The conductive film of the first conductive ball CM1 may include or be formed of a conductive material, such as gold (Au), nickel (Ni), or a double layer of Au and Ni.

[0156] In the non-display area NDA of the substrate SUB, a first buffer layer BF1, a second buffer layer BF2, and a gate insulating layer 130 may be stacked in sequence. A gate signal line GLS and a gate line pad GP may be disposed on the gate insulating layer 130. A first pad hole PH1 may extend through the first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130 to expose the first surface of the substrate SUB. The gate line pad GP may be electrically connected to the substrate SUB through the first pad hole PH1. That is, the gate line pad GP may fill the first pad hole PH1 to contact the top surface of the substrate SUB at the first pad hole PH1.

[0157] The conductive adhesive member CAM may be provided at a position of the substrate SUB corresponding to the non-display area NDA. The conductive adhesive member CAM may not overlap with the display area DA. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300 to each other.

[0158] The conductive adhesive member CAM may include a base layer, such as an adhesive resin ADR, and a plurality of second conductive balls CM2 (e.g., a second conductive member). The second conductive balls CM2 include a plurality of second conductive balls CM2 dispersed in the adhesive resin ADR. The adhesive resin ADR may include or be formed of a thermosetting resin such as an epoxy resin. The second conductive balls CM2 may have the same structure as the first conductive balls CM1 described above.

[0159] The circuit board 300 to which the display driver circuit 200 is attached may be disposed below the conductive adhesive member CAM. Specifically, the display driver circuit 200 may face the conductive adhesive member CAM, with the circuit board 300 interposed therebetween. The circuit board 300 may include first bump electrodes BPE1 on a first surface of the circuit board 300. The first bump electrodes BPE1 may be disposed on a first surface of the circuit board 300 facing the substrate SUB, and the display driver circuit 200 may be disposed on a second surface of the circuit board 300 opposite the first surface.

[0160] In the non-display area NDA, the conductive adhesive member CAM may overlap the gate signal line GLS and the gate line pad GP. The conductive adhesive member CAM may overlap or correspond to each of the circuit board 300 and the first bump electrode BPE1 along the thickness direction of the display panel 100.

[0161] The gate line pad GP, the first conductive ball CM1, the second conductive ball CM2, and the first bump electrode BPE1 may be electrically contacted with one another, such as by thermal compression. Specifically, the gate line pad GP may be in contact with the first conductive ball CM1 of the substrate SUB, the first conductive ball CM1 may be in contact with the second conductive ball CM2 of the conductive adhesive member CAM, and the second conductive ball CM2 may be in contact with the first bump electrode BPE1 of the circuit board 300. In other words, in the non-display area NDA, the circuit board 300 is electrically connected to the signal line through contact between the circuit board 300 and the conductive adhesive member CAM, and contact between the conductive material in the substrate SUB and both the signal line and the conductive adhesive member CAM.

[0162] In an embodiment, during thermal pressing, the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM may be compressed in a thickness direction of the display panel 100 in a region of the circuit board 300 that overlaps or corresponds to the first bump electrodes BPE1 of the circuit board 300. Thus, the gate line pads GP may be electrically connected to the circuit board 300 through the substrate SUB.

[0163] The entire substrate SUB may include locations where electrical conductivity is achieved, such as through the conductive material within the base layer (e.g., the first conductive balls CM1). The first conductive balls CM1 of the substrate SUB may be heat-pressed only at locations of the substrate SUB aligned with the locations of the first bump electrodes BPE1 of the circuit board 300, and thus may be electrically connected to the second conductive balls CM2 at locations corresponding to the first bump electrodes BPE1. Therefore, even if the entire substrate SUB includes locations where electrical conductivity is achieved through the first conductive balls CM1, the entire substrate SUB may not necessarily exhibit electrical conductivity, and may instead be functionally conductive only in the region of the circuit board 300 located at the first bump electrodes BPE1.

[0164] The data line pad DLP may be electrically connected to the circuit board 300 through the substrate SUB and the conductive adhesive member CAM.

[0165] refer to Figure 10 , the data signal line DLS and the data line pad DLP may be disposed in the non-display area NDA of the substrate SUB.

[0166] In the non-display area (NDA) of the substrate SUB, a first buffer layer BF1, a second buffer layer BF2, a gate insulating layer 130, a first interlayer insulating layer 141, a second interlayer insulating layer 142, and a first organic layer 150 may be stacked in sequence. A data signal line DLS and a data line pad DLP may be disposed on the second interlayer insulating layer 142. A second pad hole PH2 may extend through the first buffer layer BF1, the second buffer layer BF2, the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142 to expose the top surface of the substrate SUB. The data line pad DLP may be electrically connected to the substrate SUB through the second pad hole PH2. That is, the data line pad DLP may fill the second pad hole PH2 and may be in contact with the top surface of the substrate SUB.

[0167] A conductive adhesive member CAM may be provided at a location corresponding to the non-display area NDA of the substrate SUB. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300. The circuit board 300, to which the display driver circuit 200 is attached, may be provided below the conductive adhesive member CAM. The circuit board 300 may further include second bump electrodes BPE2 on a first surface of the circuit board 300. The second bump electrodes BPE2 may be provided on a first surface of the circuit board 300 facing the substrate SUB, and the display driver circuit 200 may be provided on a second surface of the circuit board 300 opposite the first surface.

[0168] In the non-display area NDA, the conductive adhesive member CAM may overlap the data signal line DLS and the data line pad DLP. The conductive adhesive member CAM may overlap or correspond to each of the circuit board 300 and the second bump electrode BPE2 along the thickness of the display panel 100.

[0169] The data line pad DLP, the first conductive ball CM1, the second conductive ball CM2, and the second bump electrode BPE2 may be electrically contacted with each other, such as by thermal compression. That is, the data line pad DLP may be in contact with the first conductive ball CM1 of the substrate SUB, the first conductive ball CM1 may be in contact with the second conductive ball CM2 of the conductive adhesive member CAM, and the second conductive ball CM2 may be in contact with the second bump electrode BPE2 of the circuit board 300.

[0170] In an embodiment, during thermal pressing, the first conductive balls CM1 of the substrate SUB and the second conductive balls CM2 of the conductive adhesive member CAM may be compressed along the thickness direction of the display panel 100 in a region of the circuit board 300 that overlaps or corresponds to the second bump electrodes BPE2 of the circuit board 300. Therefore, the data line pads DLP may be electrically connected to the circuit board 300 through the substrate SUB.

[0171] As described above, the entire substrate SUB may include locations where electrical conductivity is achieved, such as via a conductive material (e.g., the first conductive balls CM1). However, electrical conductivity is provided only in the region of the circuit board 300 located at the second bump electrodes BPE2, including the heat-pressed first conductive balls CM1. Therefore, even if the entire substrate SUB includes locations where electrical conductivity is achieved via the first conductive balls CM1, the entire substrate SUB does not necessarily need to be electrically conductive. Instead, the substrate SUB may be functionally conductive only in the region of the circuit board 300 located at the second bump electrodes BPE2. In embodiments, the substrate SUB may be functionally conductive only in the regions of the circuit board 300 located at the first and second bump electrodes BPE1 and BPE2.

[0172] Each of the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 may include an outer surface. The outer surfaces of the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 may be disposed to correspond to each other at the same side of the display device 10.

[0173] In an embodiment, the circuit board 300 located below the substrate SUB and the conductive lines located above the substrate SUB, which are connected to each other through the substrate SUB, can be arranged so that the outer surfaces of the substrate SUB, the conductive adhesive member CAM, and the circuit board 300 are aligned with and in contact with each other. That is, on the same side of the display device 10, the outer surface of the substrate SUB can be aligned with and in contact with the outer surface of the conductive adhesive member CAM, and the outer surface of the conductive adhesive member CAM can be aligned with and in contact with the outer surface of the circuit board 300. However, embodiments are not limited to this. Alternatively, the outer surface of the conductive adhesive member CAM can be located inside the outer surface of the substrate SUB, and / or the outer surface of the circuit board 300 can be located inside the outer surface of the substrate SUB. When located inside, the element can be spaced apart from other elements and closer to the display area DA than other elements.

[0174] Therefore, since the pad areas provided on the opposite surfaces of the substrate SUB and the circuit board 300 are connected to each other within the plane area of ​​the substrate SUB, planes such as the bending area where the circuit board 300 bends from the first surface to the second surface along the outer surface of the substrate SUB are eliminated. Therefore, the frame size of the display device 10 can be reduced.

[0175] exist Figure 10 The cross-sectional structures of the power supply pad VDP and the second sensor pad TP2 are not shown in FIG, and their description will be omitted because they are basically the same as those in FIG. Figure 10 The cross-sectional structure of the data line pad DLP is the same.

[0176] Figure 11 is a cross-sectional view of an embodiment of the display device 10 . Figure 12 yes Figure 11FIG. 1 is a plan view of an embodiment of a substrate SUB of a display device 10 . Figure 13 yes Figure 11 sectional view of an embodiment of a display device 10 . Figure 14 yes Figure 13 FIG. 1 is an enlarged cross-sectional view of a portion of the display device 10 .

[0177] refer to Figures 11 to 14 , the display device 10 may include a substrate SUB including a conductive material providing a conductive function at a hot pressing position. Figures 11 to 14 The display device 10 is basically the same as Figures 3 to 10 The display device 10 is the same or similar to the display device 10, except that the conductive material is only provided in a portion of the substrate SUB. Therefore, the following will mainly focus on the display device 10 with Figures 3 to 10 The difference between the display device 10 is described Figures 11 to 14 display device 10.

[0178] refer to Figure 11 and Figure 12 The display device 10 may include a display panel 100, a conductive adhesive member CAM, a display driving circuit 200, and a circuit board 300. The display panel 100 may include a substrate SUB, a display layer DISL, a sensor electrode layer SENL, and a polarizing film PF.

[0179] The substrate SUB may include a conductive material, for example, first conductive balls CM1. The substrate SUB may include a first substrate region 20 including or formed of a polymer resin PSM, and a second substrate region 30, which is the remaining portion of the substrate SUB excluding the first substrate region 20. The first substrate region 20 and the second substrate region 30 may be arranged in the same plane (e.g., a plane defined by a first direction and a second direction). An edge of the first substrate region 20 may contact or meet an edge of the second substrate region 30. The first substrate region 20 may overlap with the light-emitting element 170 of the display layer DISL, and the second substrate region 30 may not overlap with the light-emitting element 170.

[0180] The first substrate region 20 may be a planar region that overlaps with or corresponds to the display area DA and does not include the first conductive balls CM1. The first substrate region 20 may be a planar region that includes or is formed solely of a polymer resin PSM. The second substrate region 30 may be a planar region that overlaps with or corresponds to the non-display area NDA and includes the polymer resin PSM and the first conductive balls CM1 dispersed within the polymer resin PSM. The second substrate region 30 may be disposed at an outer region of the substrate SUB and may be outside the plane of the display area DA. The second substrate region 30 may define the outer surface of the substrate SUB.

[0181] Specifically, refer to Figure 13 and Figure 14 The TFT ST, the light emitting element 170, and the sensor electrode layer SENL may be disposed in the display area DA of the substrate SUB. The gate signal line GLS and the gate line pad GP may be disposed in the non-display area NDA of the substrate SUB.

[0182] The first substrate region 20 of the substrate SUB may overlap with the TFT ST, the light emitting element 170 , and the sensor electrode layer SENL, while the second substrate region 30 may not overlap with the TFT ST and the light emitting element 170 .

[0183] The first substrate region 20 may include only the polymer resin PSM to exhibit non-conductivity and may not include the first conductive balls CM1. The second substrate region 30 may include both the polymer resin PSM and the first conductive balls CM1 (conductive material dispersed in the polymer resin PSM) to exhibit conductivity. The first conductive balls CM1 may be randomly dispersed in the polymer resin PSM.

[0184] A first buffer layer BF1, a second buffer layer BF2, and a gate insulating layer 130 may be sequentially stacked on the second substrate region 30 of the substrate SUB. A gate signal line GLS and a gate line pad GP may be disposed on the gate insulating layer 130. A first pad hole PH1 may be provided to expose the substrate SUB to the outside of the first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130. The gate line pad GP may be electrically connected to the substrate SUB through the first pad hole PH1. That is, the gate line pad GP may fill the first pad hole PH1 to contact the top surface of the substrate SUB at the first pad hole PH1.

[0185] The conductive adhesive member CAM may be disposed below the second substrate region 30 of the substrate SUB. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300. The second substrate region 30 may overlap or correspond to the conductive adhesive member CAM and the circuit board 300. The conductive adhesive member CAM is spaced apart from the first substrate region 20 that does not include a conductive material in a direction along the substrate SUB.

[0186] The conductive adhesive member CAM may include an adhesive resin ADR and second conductive balls CM2 dispersed in the adhesive resin ADR. The circuit board 300 to which the display driving circuit 200 is attached may be disposed below the conductive adhesive member CAM. The first bump electrodes BPE1 of the circuit board 300 may be disposed on a first surface of the circuit board 300, and the display driving circuit 200 may be disposed on a second surface of the circuit board 300 opposite to the first surface.

[0187] The gate line pad GP, the first conductive ball CM1, the second conductive ball CM2, and the first bump electrode BPE1 can be thermally pressed together and thus electrically contact each other. That is, the gate line pad GP can contact the first conductive ball CM1 of the substrate SUB, the first conductive ball CM1 can contact the second conductive ball CM2 of the conductive adhesive member CAM, and the second conductive ball CM2 can contact the first bump electrode BPE1 of the circuit board 300. During the thermal pressing, the first conductive ball CM1 of the substrate SUB and the second conductive ball CM2 of the conductive adhesive member CAM can be compressed in the area of ​​the circuit board 300 that is aligned with the first bump electrode BPE1 of the circuit board 300. As a result, the gate line pad GP can be electrically connected to the circuit board 300 through the substrate SUB.

[0188] A portion of the substrate SUB (e.g., the second substrate region 30) may include first conductive balls CM1. The first conductive balls CM1 may be heat-pressed only in the region of the circuit board 300 aligned with the first bump electrodes BPE1 of the circuit board 300, and thus may be electrically connected to the second conductive balls CM2 in that region of the circuit board 300. In other words, the gate line pads GP of the display panel 100 and the first bump electrodes BPE1 of the circuit board 300 may be electrically connected to each other by providing or forming the second substrate region 30, which includes the first conductive balls CM1 and provides conductivity, in the region of the substrate SUB aligned with the display pad area DPA. Consequently, the use of conductive members may be reduced, and thus, the manufacturing cost of the display device 10 may be reduced.

[0189] Figure 15 1 is a plan view of an embodiment of a substrate SUB of the display device 10 . Figure 16 yes Figure 15 sectional view of the display device 10. Figure 17 yes Figure 15 1 is a cross-sectional view of an embodiment of a portion of a display device 10.

[0190] refer to Figures 15 to 17 , the display device 10 may include a substrate SUB including a conductive material. Figures 15 to 17 The display device 10 and Figures 3 to 14 The display device 10 is different in that the conductive material is provided as an island pattern (eg, a discrete pattern) in a portion of the substrate SUB. Therefore, the following will mainly focus on the Figures 3 to 14 The difference between the display device 10 is described Figures 15 to 17 display device 10.

[0191] refer to Figure 15The substrate SUB of the display device 10 may include a conductive material, for example, first conductive balls CM1. The substrate SUB may include a first substrate region 20 and a plurality of second substrate regions 30 provided as the remaining portion of the substrate SUB except the first substrate region 20. The first substrate region 20 includes or is formed of a polymer resin PSM, and the second substrate region 30 includes a plurality of second substrate regions 30.

[0192] The first substrate region 20 may be a planar region overlapping the display area DA and not including the first conductive balls CM1. The first substrate region 20 may be disposed to be spaced apart from the first conductive balls CM1. The first substrate region 20 may be a planar region disposed or formed only of the polymer resin PSM.

[0193] The second substrate region 30 may be a discrete planar region that does not overlap the display area DA but overlaps the non-display area NDA. The discrete planar region includes a polymer resin PSM and first conductive balls CM1 dispersed within the polymer resin PSM. The second substrate region 30 may be arranged as an island pattern within the non-display area NDA. The second substrate regions 30 may be spaced a predetermined distance apart from each other and may be surrounded by the first substrate region 20.

[0194] Specifically, refer to Figure 16 and Figure 17 , the TFT ST, the light emitting element 170, and the sensor electrode layer SENL may be disposed in the display area DA of the substrate SUB. The gate signal line GLS and the gate line pad GP may be disposed in the non-display area NDA of the substrate SUB. The cross-sectional structure of the region corresponding to the gate signal line GLS and the gate line pad GP will be described below. The cross-sectional structure of the region where the data signal line DLS and the data line pad DLP are disposed is substantially the same as that described above with reference to FIG. Figure 10 The cross-sectional structures are the same, and therefore, detailed description thereof will be omitted.

[0195] The first substrate region 20 of the substrate SUB may overlap with the TFT ST, the light emitting element 170, and the sensor electrode layer SENL. The second substrate region 30 of the substrate SUB may not overlap with the TFT ST and the light emitting element 170. In an embodiment, the light emitting element 170 is spaced apart from the second substrate region 30 including the conductive material in a direction along the substrate SUB.

[0196] The first substrate region 20 may include only the polymer resin PSM to exhibit non-conductivity and may not include the first conductive balls CM1. The second substrate region 30 may include both the polymer resin PSM and the first conductive balls CM1 (conductive material dispersed in the polymer resin PSM) to exhibit conductivity. The first conductive balls CM1 may be randomly dispersed in the polymer resin PSM.

[0197] A first buffer layer BF1, a second buffer layer BF2, and a gate insulating layer 130 may be sequentially stacked on the second substrate region 30 of the substrate SUB. A gate signal line GLS and a gate line pad GP may be disposed on the gate insulating layer 130. A first pad hole PH1 may be provided to expose the substrate SUB to the outside of the first buffer layer BF1, the second buffer layer BF2, and the gate insulating layer 130. The gate line pad GP may be electrically connected to the substrate SUB through the first pad hole PH1. That is, the gate line pad GP may fill the first pad hole PH1 to contact the top surface of the substrate SUB at the first pad hole PH1.

[0198] The conductive adhesive member CAM may be disposed below the second substrate region 30 of the substrate SUB. The conductive adhesive member CAM may electrically connect the substrate SUB and the circuit board 300 to each other. The second substrate region 30 may overlap the conductive adhesive member CAM and the circuit board 300.

[0199] The conductive adhesive member CAM may include an adhesive resin ADR and second conductive balls CM2 dispersed in the adhesive resin ADR. The circuit board 300 to which the display driving circuit 200 is attached may be disposed below the conductive adhesive member CAM. The first bump electrodes BPE1 of the circuit board 300 may be disposed on a first surface of the circuit board 300, and the display driving circuit 200 may be disposed on a second surface of the circuit board 300 opposite to the first surface.

[0200] The gate line pad GP, the first conductive ball CM1, the second conductive ball CM2, and the first bump electrode BPE1 may be thermocompressed and thus electrically contact each other. Specifically, the gate line pad GP may contact the first conductive ball CM1 of the substrate SUB, the first conductive ball CM1 may contact the second conductive ball CM2 of the conductive adhesive member CAM, and the second conductive ball CM2 may contact the first bump electrode BPE1 of the circuit board 300. During the thermocompression process, the first conductive ball CM1 of the substrate SUB and the second conductive ball CM2 of the conductive adhesive member CAM may be compressed in the region of the circuit board 300 aligned with the first bump electrode BPE1 of the circuit board 300. Consequently, the gate line pad GP of the display panel 100 may be electrically connected to the circuit board 300 at the first bump electrode BPE1 of the circuit board 300 through the substrate SUB.

[0201] A portion of the substrate SUB (e.g., the second substrate region 30) may include first conductive balls CM1. The first conductive balls CM1 may be heat-pressed only in the region of the circuit board 300 aligned with the first bump electrodes BPE1 of the circuit board 300 and thus electrically connected to the second conductive balls CM2. In other words, the gate line pad GP and the first bump electrode BPE1 of the circuit board 300 may be electrically connected to each other by forming the second substrate region 30, which includes the first conductive balls CM1 and provides conductivity, in a region overlapping the pad region. Consequently, the use of conductive members may be reduced, and thus, the manufacturing cost of the display device 10 may be reduced.

[0202] The substrate SUB may be provided by a solution process.

[0203] Figures 18 to 20 is a plan view showing an embodiment of a method of providing a substrate SUB.

[0204] refer to Figure 18 The method of providing or manufacturing a substrate SUB may include performing a solution process on a base substrate BSUB. Specifically, a base substrate BSUB is provided or prepared. The base substrate BSUB may be a rigid substrate, such as a glass substrate or a plastic substrate.

[0205] A solution containing a polymer resin (PSM) and a plurality of first conductive balls (CM1) is provided. The first conductive balls (CM1) may be present in the polymer resin (PSM) in an amount of approximately 0.1 to approximately 10 parts by weight per 100 parts by weight of the solution. In one embodiment, for example, 95 parts by weight of a polyimide resin and 5 parts by weight of nickel conductive balls may be included in 100 parts by weight of the solution. However, the content of the first conductive balls (CM1) is not particularly limited.

[0206] The solution may be applied to the base substrate BSUB using a solution process. The solution process may be performed using slit coating, nozzle coating, printing, or spin coating. The polymer resin PSM in which the first conductive balls CM1 are bonded may be applied to the base substrate BSUB (such as by a nozzle coating apparatus CN) and cured to obtain Figure 3 That is, the substrate SUB may include a base substrate BSUB having a polymer resin PSM and first conductive balls CM1 in the polymer resin PSM.

[0207] Figure 19 and Figure 20 An embodiment of a method of providing a substrate SUB is shown.

[0208] refer to Figure 19A polymer resin PSM excluding the first conductive balls CM1 is applied to the base substrate BSUB. The first substrate region 20 is provided or formed by applying the polymer resin PSM excluding the first conductive balls CM1 to a portion of the base substrate BSUB (such as using a nozzle coating apparatus CN) to form a pattern of the polymer resin PSM, and curing the pattern of the polymer resin PSM excluding the first conductive balls CM1.

[0209] refer to Figure 20 , by applying the polymer resin PSM having the first conductive balls CM1 therein to a plane region other than the plane region of the first substrate region 20 using the nozzle coating device CN, and curing the polymer resin PSM having the first conductive balls CM1 therein, a second substrate region 30 including a plurality of second substrate regions 30 arranged in a plural manner is provided or formed. In this way, a second substrate region 30 including a plurality of second substrate regions 30 can be obtained. Figure 15 Substrate SUB. Figure 12 The SUB substrate can also be used Figure 19 and Figure 20 method to obtain it.

[0210] Alternatively, a photolithography method may be used to provide a substrate SUB including the first substrate region 20 and the second substrate region 30. In an embodiment, for example, a polymer resin PSM may be applied to the entire base substrate BSUB, and a patterned first substrate region 20 may be provided or formed by photolithography. Thereafter, a polymer resin PSM including a conductive member may be applied to the entire base substrate BSUB and then patterned only in a planar region other than the first substrate region 20, thereby forming the second substrate region 30.

[0211] As described above, since the circuit board 300 electrically connected to the pad area at the front surface of the substrate SUB including the conductive material is attached to the substrate SUB at the rear surface of the substrate SUB, the flat area where the circuit board 300 and / or the substrate SUB is bent can be omitted from the display device 10. Therefore, the frame size of the display device 10 can be reduced.

[0212] At the end of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the embodiments without departing substantially from the principles of the invention. Therefore, the disclosed embodiments of the present invention are used in a general and descriptive sense only and not for purposes of limitation.

Claims

1. A display device comprising: Substrate, including: Display area, a non-display area adjacent to the display area, a top surface and a bottom surface, the bottom surface being opposite the top surface, and Conductive materials; A display layer, located in the display area, comprising a light-emitting element, the display layer being located on the top surface of the substrate; a signal line connected to the light emitting element, the signal line extending from the display layer and entering the non-display area; and In the non-display area, the display device includes: a conductive adhesive member on the bottom surface of the substrate; and a circuit board facing the signal line, with both the substrate and the conductive adhesive member between the circuit board and the signal line; Wherein, in the non-display area, the circuit board is electrically connected to the signal line through contact between the circuit board and the conductive adhesive member and contact between the conductive material in the substrate and both the signal line and the conductive adhesive member.

2. The display device according to claim 1, wherein The substrate further comprises: polymer resins, and The conductive material includes a plurality of first conductive balls located within the polymer resin, Wherein, in the non-display area, the circuit board is electrically connected to the signal line through contact between the plurality of first conductive balls in the substrate and both the signal line and the conductive adhesive member.

3. The display device according to claim 2, wherein: The conductive adhesive member comprises: binder resin, and a plurality of second conductive balls located in the binder resin, Wherein, in the non-display area, the circuit board is electrically connected to the signal line through contact between the circuit board and the multiple second conductive balls in the conductive adhesive member and contact between the multiple first conductive balls in the substrate and the signal line and the multiple second conductive balls in the conductive adhesive member.

4. The display device according to claim 3, wherein The substrate further includes a thickness direction defined between the top surface and the bottom surface of the substrate, and The conductive adhesive member is aligned with the signal line and the non-display area of ​​the substrate along the thickness direction of the substrate.

5. The display device according to claim 4, wherein The signal line extending from the display layer and entering the non-display area defines a conductive pad in the non-display area, and In the non-display area: The display layer defines a pad hole, the pad hole exposing the top surface of the substrate, At the pad hole, the conductive pad extends through the display layer to contact the top surface of the substrate exposed at the pad hole, and The circuit board is electrically connected to the signal line through contact of the plurality of first conductive balls in the substrate with the conductive pads of the signal line contacting the top surface of the substrate at the pad holes. The display device according to claim 5 , wherein: In the non-display area, the conductive pad, the first conductive ball of the substrate, and the second conductive ball of the conductive adhesive member are aligned with and respectively contact each other along the thickness direction of the substrate.

7. The display device according to claim 6, wherein The circuit board includes bump electrodes, and In the non-display area: the bump electrodes of the circuit board are aligned with the first conductive balls of the substrate and the second conductive balls of the conductive adhesive member along the thickness direction of the substrate, and The circuit board is electrically connected to the signal line through contact of the bump electrodes of the circuit board with the plurality of second conductive balls in the conductive adhesive member.

8. The display device according to claim 1, wherein Each of the substrate, the conductive adhesive member, and the circuit board includes an outer side surface farthest from the display area, and An outer surface of the substrate, an outer surface of the conductive adhesive member, and an outer surface of the circuit board are aligned with each other.

9. The display device according to claim 1, wherein The substrate further includes the conductive material dispersed along both the non-display area and the display area of ​​the substrate.

10. Display device, including Substrate, including: Display area, a non-display area adjacent to the display area, a top surface and a bottom surface, the bottom surface being opposite the top surface, Conductive materials, a first substrate region, not including the conductive material, the first substrate region corresponding to the display region, and a second substrate region, comprising the conductive material, the second substrate region corresponding to the non-display region; A display layer, located in the display area, comprising a light-emitting element, the display layer being located on the top surface of the substrate; a signal line connected to the light emitting element, the signal line extending from the display layer and entering the non-display area; as well as In the non-display area, the display device includes: a conductive adhesive member on the bottom surface of the substrate; and a circuit board facing the signal line, with both the second substrate region and the conductive adhesive member between the circuit board and the signal line; wherein, in the non-display area, the circuit board is electrically connected to the signal line by contact between the circuit board and the conductive adhesive member and contact between the conductive material in the second substrate area and both the signal line and the conductive adhesive member.

Images