Spiking synaptic elements for spiking neural networks

Abstract

A method for transmitting signals between neurons of a hardware-implemented spiking neural network (or SNN). The network includes neuronal connections, each neuronal connection including a synaptic unit connecting a presynaptic neuron to a postsynaptic neuron. Spikes received from a presynaptic neuron of each neuronal connection are first modulated in frequency based on synaptic weights stored on each synaptic unit to generate postsynaptic spikes, thereby converting a first number of spikes received from the presynaptic neuron into a second number of postsynaptic spikes. At least some of the spikes received from the presynaptic neuron can each be converted into a string of two or more postsynaptic spikes. The generated postsynaptic spikes are then transmitted to the postsynaptic neuron of each neuronal connection. The method makes it possible to obtain a higher dynamic range in the synaptic output.

Description

Background Art

[0001] The present invention generally relates to techniques for transmitting signals between neurons of a hardware-implemented spiking neural network. In particular, the present invention relates to a method for transmitting signals between neurons of a spiking neural network in which spikes received from a presynaptic neuron are modulated in frequency to generate a postsynaptic spike train (rather than being converted into a current of varying amplitude) before the presynaptic spike train is transmitted to the postsynaptic neuron.

[0002] Machine learning typically relies on artificial neural networks (ANNs), which are computational models inspired by biological neural networks in the human or animal brain. Such systems learn tasks incrementally and autonomously through examples; they have been successfully applied to, for example, speech recognition, text processing, and computer vision.

[0003] ANNs consist of a set of connected units or nodes, which are analogous to biological neurons in animal brains and are therefore called artificial neurons. Similar to synapses, signals are transmitted along the connections (also called edges) between artificial neurons. That is, the artificial neuron that receives the signal processes it and then sends a signal to the connected neuron. Typically, the signals transmitted along such connections are simulated real numbers, and the output of the artificial neuron is calculated by means of a nonlinear function of the sum of its inputs.

[0004] Connection weights (also called synaptic weights) are associated with connections and nodes; such weights are adjusted as learning proceeds. Each neuron may have several inputs, and a connection weight is assigned to each input (the weight of that particular connection). Such connection weights are learned and updated thereby during the training phase. The learning process is iterative: data cases are typically presented to the network one at a time, and the weights associated with the input values ​​are adjusted at each time step.

[0005] There are already many types of known neural networks, starting with feedforward neural networks, such as multilayer perceptrons, deep neural networks, and convolutional neural networks. In addition to these, new types of neural networks have emerged, such as spike neural networks. Spiking neural networks (SNNs) are fundamentally different from conventional neural networks because SNNs operate using spikes, which are discrete binary events that can occur asynchronously at any point in time, rather than analog values ​​calculated at regular time steps. That is, in addition to neuronal and synaptic states, SNNs also incorporate the concept of time. That is, neurons are only excited when the membrane potential reaches a specific value, rather than being excited at each propagation cycle as in, for example, a multilayer perceptron network. In the context of SNNs, excitation means that neurons generate signals that reach other neurons, which in turn increase or decrease their potentials based on the signals they receive from other neurons.

[0006] Neural networks are usually implemented in software. However, neural networks can also be implemented in hardware, for example as resistive processing units or optical neuron morphology systems. That is, a hardware-implemented ANN is a physical machine that is distinct from a classical computer (general-purpose or special-purpose) because it is primarily and specifically designed to implement ANNs (for training and / or inference purposes). A hardware-implemented ANN can best be simulated using a classical computer (although not with the same efficiency), which cannot perform many data processing tasks like a classical computer. Summary of the invention

[0007] According to a first aspect, the present invention is implemented as a method for transmitting signals between neurons of a hardware-implemented spiking neural network (or SNN). The network includes neuronal connections, each of which includes a synaptic unit connecting a presynaptic neuron to a postsynaptic neuron. Basically, the method relies on a digital modulation process that is implemented for each of the neuronal connections and at each of its synaptic units. That is, first, based on the synaptic weights stored on each of the synaptic units, the spikes received from the presynaptic neuron of each neuronal connection are modulated in frequency to generate postsynaptic spikes. In this way, a first number of spikes received from the presynaptic neuron is converted into a second number of postsynaptic spikes. The generated postsynaptic spikes are then transmitted to the postsynaptic neuron of each neuronal connection. The generated postsynaptic spikes may all have the same signal amplitude.

[0008] The present method makes it possible to obtain a higher dynamic range in the synaptic output, since the discrete events generated at the synaptic unit can be read and integrated more recognizable at each output neuron than the analog signals used in prior art solutions, where input spikes from the presynaptic neuron are converted into analog currents at the synaptic output.

[0009] Consistent with another aspect of the invention, the above process illustrates operations performed at a synaptic unit, which is directed to a synaptic unit circuit. However, in various embodiments, the above process is supplemented by additional steps, such as performed by a presynaptic neuron and a postsynaptic neuron. In particular, the process results in the generation of an output spike at a postsynaptic neuron to which each neuron is connected based on a transmitted postsynaptic spike. The output spike can be generated by integrating the postsynaptic spikes received at the postsynaptic neuron based on a count of the postsynaptic neuron.

[0010] In an embodiment of the present invention, the method further comprises maintaining (at each synaptic unit) a state determining the synaptic weight, wherein the state is modifiable according to a cognitive learning mechanism. Specifically, the method may further comprise: modifying (again, at each synaptic unit) the state based on spikes received from the presynaptic neuron on the one hand and output spikes generated at one or more postsynaptic neurons of the SNN on the other hand according to the cognitive learning mechanism.

[0011] The synaptic unit may be configured to implement a spike timing dependent plasticity (STDP) mechanism based on spikes received from the pre-synaptic neuron and output spikes generated at the post-synaptic neuron, that is, to change the state based on the STDP mechanism.

[0012] The spikes received from the presynaptic neuron can be modulated in particular at each synaptic unit by first converting the received spikes into one or more electrical signals (depending on the synaptic weights determined by the state) and then setting the frequency of the postsynaptic spikes to be generated based on the electrical signals.

[0013] In an embodiment, the method involves two states, namely a secondary state in addition to the above-mentioned state (primary state). That is, the spike modulation process further includes maintaining a secondary state, which determines a short-term synaptic weight. The secondary state depends on spikes received from the pre-synaptic neuron. The modulation scheme also includes comparing the current synaptic weight determined by the primary state with a threshold value. The latter depends on the short-term synaptic weight (as determined from the secondary state), whereby a post-synaptic spike is generated only if the current synaptic weight is greater than or equal to the threshold value.

[0014] In a given class of embodiments, the threshold is equal to the short-term synaptic weight, whereby the current synaptic weight is compared with the short-term synaptic weight and the post-synaptic spike is generated only when the current synaptic weight is greater than or equal to the short-term synaptic weight. The modulation further relies on comparing the short-term synaptic weight with a maximum value allowed by the threshold and resetting the short-term synaptic weight if the value is found to be greater than or equal to the maximum value, respectively.

[0015] In another class of embodiments, for the purpose of comparing the current synaptic weight with the threshold, the threshold is taken as the difference between the maximum value and the short-term synaptic weight. The maximum value is the maximum value allowed by the sum of the current synaptic weight and the short-term synaptic weight. That is, a post-synaptic spike is generated only when the current synaptic weight is greater than or equal to the difference. Here, the modulation process causes the short-term synaptic weight to be reset each time a post-synaptic spike is generated for transmission to the post-synaptic neuron (and after the spike has been generated).

[0016] According to another aspect, the present invention is implemented as a synaptic unit circuit for transmitting signals between neurons of a hardware-implemented SNN. The circuit is designed to connect a presynaptic neuron of the network to a postsynaptic neuron, thereby forming a neuronal connection. Consistent with the present method, the circuit is configured to modulate the spikes received from the presynaptic neuron in frequency when connected to the presynaptic neuron and the postsynaptic neuron, and transmit the generated postsynaptic spikes to the postsynaptic neuron. The spikes received from the presynaptic neuron are modulated based on the synaptic weights stored on the circuit to generate postsynaptic spikes, whereby in operation, a first number of spikes received from the presynaptic neuron are converted into a second number of postsynaptic spikes. As previously induced, the circuit can be configured to generate postsynaptic spikes all having the same amplitude.

[0017] In an embodiment, the circuit is further configured to, when connected to the pre-synaptic neuron and the post-synaptic neuron, maintain a state determining the synaptic weight and to change the state based on spikes received from the pre-synaptic neuron on the one hand and on spikes emitted by the post-synaptic neuron on the other hand.

[0018] The circuit may include a spike generation unit, which is designed to generate the post-synaptic spike in operation and transmit the latter to the post-synaptic neuron. The circuit also includes a memristive device and an update unit, which is connectable to each of the pre-synaptic neuron and the post-synaptic neuron and is configured to change the state in operation. On the one hand, the memristive device is connected to the spike generation unit and is connectable to the pre-synaptic neuron. The memristive device is otherwise configured to maintain the state so that in operation, the spike generation unit modulates the spike received by the memristive device from the pre-synaptic neuron based on the synaptic weight determined from the state and generates the post-synaptic spike. On the other hand, the memristive device is connected to the update unit, whereby in operation, any state changed by the update unit determines the synaptic weight used to modulate the spike.

[0019] In various embodiments, the update unit is configured to implement a STDP mechanism based on spikes received from the pre-synaptic neuron and output spikes generated at the post-synaptic neuron, whereby in operation, the state is changed based on the STDP mechanism.

[0020] The memristive device can be further configured to convert spikes received from the presynaptic neuron into one or more electrical signals (e.g., current or voltage), according to the synaptic weight determined by the state maintained in the memristive device, and the spike generation unit is also designed to set the frequency of the post-synaptic spikes to be generated, based on the electrical signals, so as to modulate the spikes received from the presynaptic neuron when in operation.

[0021] In an embodiment, the state is a primary state and the memristive device is a first memristive device configured to maintain the primary state. The synaptic cell circuit further comprises a second memristive device connectable to the presynaptic neuron and designed to maintain a secondary state determining a short-term synaptic weight when in operation, the secondary state being dependent on spikes received by the second memristive device from the presynaptic neuron.

[0022] The synaptic unit circuit may further include a comparator connected to each of the first memristive device and the second memristive device to compare a current synaptic weight determined from the primary state with a threshold value, the threshold value being dependent on the short-term synaptic weight determined from the secondary state. In operation, a post-synaptic spike is generated by the spike generation unit only if the current synaptic weight is greater than or equal to the threshold value.

[0023] In an embodiment, the comparator is a first comparator designed to use the short-term synaptic weight as the threshold, whereby the post-synaptic spike is generated by the spike generation unit only if the current synaptic weight is greater than or equal to the short-term synaptic weight. In that case, the circuit further comprises a second comparator configured to compare the short-term synaptic weight with a maximum value allowed for the threshold, the circuit otherwise being configured to reset the short-term synaptic weight if the latter is found to be greater than or equal to the maximum value.

[0024] The comparator is designed to rely on the difference between the maximum value and the short-term synaptic weight as the threshold value for comparing the current synaptic weight with the threshold value. The maximum value is the maximum value allowed by the sum of the current synaptic weight and the short-term synaptic weight, whereby in operation, the post-synaptic spike is generated by the spike generation unit only when the current synaptic weight is greater than or equal to the difference. Moreover, the circuit is further configured to reset the short-term synaptic weight each time a post-synaptic spike is generated for transmission to the post-synaptic neuron (after the spike has been generated).

[0025] According to a final aspect, the present invention is implemented as a hardware device for implementing a SNN, wherein the network comprises a plurality of neuron connections, each neuron connection comprising: a presynaptic neuron; a postsynaptic neuron; and a synaptic unit circuit such as described above. The circuit connects the presynaptic neuron to the postsynaptic neuron.

[0026] The postsynaptic neurons may be connected by a plurality of such circuits. In particular, each postsynaptic neuron of the neuron connection may be connected by a plurality of synaptic unit circuits of the network and configured to generate an output spike based on the postsynaptic spikes transmitted by all the synaptic unit circuits connected thereto.

[0027] In an embodiment of the present invention, each of the post-synaptic neurons is further configured to generate the output spike by integrating the post-synaptic spikes transmitted by each synaptic unit circuit based on the count thereof.

[0028] Devices, apparatus and methods embodying the invention will now be described by way of non-limiting examples and with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to further illustrate various embodiments and to explain various principles and advantages of the present disclosure, wherein like reference numerals refer to the same or functionally similar elements throughout the separate views, and are incorporated in and form a part of this specification together with the following detailed description, wherein:

[0030] Figure 1A and 1B is a diagram schematically illustrating the operation of selected components of a hardware-implemented spiking neural network (SNN) in which input spikes are converted into post-synaptic currents having varying amplitudes, as in prior art solutions;

[0031] Figure 2A-2B , Figure 3-Figure 6 ,as well as Figure 7A-7D is a diagram schematically illustrating the operation of selected components of a hardware-implemented SNN designed to transmit signals between its neurons, wherein, as in an embodiment, spikes received from a presynaptic neuron are modulated in frequency (rather than amplitude) to generate a postsynaptic spike before being transmitted from the presynaptic neuron to the postsynaptic neuron. Note that Figure 2A-2B and Figure 7A-7D The principle underlying this method is generally demonstrated. Figures 3 to 6 relates to specific classes of embodiments; and

[0032] Figure 8 is a flow chart showing high-level steps of a method for transmitting signals between neurons of a hardware-implemented SNN, according to an embodiment.

[0033] The accompanying drawings show simplified representations of devices and components or parts thereof involved in the embodiments. Similar or functionally similar elements in the drawings have been assigned the same reference numerals unless otherwise specified. DETAILED DESCRIPTION

[0034] Reliable and efficient hardware implementation of spiking neural networks (SNNs) is challenging because continuous signals (values) are typically transmitted by synapses (at their outputs) to postsynaptic neurons. As this may be achieved, this will affect the dynamic range of the signal output by the synaptic output. This discovery, along with other shortcomings of typical hardware-implemented SNNs, has prompted the inventors to develop a new technique for transmitting signals between neurons of SNNs, in which spikes received from presynaptic neurons are modulated in frequency to generate varying numbers of postsynaptic spikes (rather than being converted into currents of varying amplitude).

[0035] See also Figure 2A , Figure 2B and Figure 8 , firstly an aspect of the invention is described, which relates to a method for transmitting signals between neurons 11, 14 of a hardware-implemented spiking neural network 1, 1a-1c (hereinafter referred to as SNN). This method and its variants are collectively referred to as "the present method". It is assumed that the SNN includes several neuronal connections, each neuronal connection includes a synaptic unit 20, 20a-20c connecting the pre-synaptic neuron 11 to the post-synaptic neuron 14. The synaptic unit can be implemented in particular as a circuit, such as described later with reference to another aspect of the invention. The SNN as a whole can be implemented as a hardware device, which is also described later with reference to the final aspect of the invention.

[0036] The method necessarily relies on a modulation process implemented at each synaptic unit of the SNN (i.e., for each neuronal connection of the network). According to this process, the spike 31 received (S22) from the presynaptic neuron 11 is modulated (S26) in frequency, such as Figure 8 As reflected in the flowchart of . In view of generating S27 postsynaptic spikes 32, the modulation is performed based on the synaptic weights w stored on each synaptic unit 20, 20a-20c. Due to the frequency modulation, the number of spikes received from the presynaptic neuron is generally converted into a different number of postsynaptic spikes. For example, at least some of the spikes 31 received from the presynaptic neuron 11 can each be converted into a string of two or more postsynaptic spikes 32, such as Figure 7B and 7C The generated post-synaptic spike 32 is then sent (S28) to the post-synaptic neuron 14 connected by the pre-synaptic neuron 11 via the synaptic unit. The same process is performed along each neuron connection of the SNN.

[0037] A spike is an impulse signal that causes an action potential generated by a biological neuron. Similarly, a spike train 32 is a pulse time sequence that can be compared to an action potential train generated by a biological neuron.

[0038] According to the present method, at the output of the synaptic unit 20, a first number of input spikes received from the presynaptic neuron 11 are converted into a second number of spikes 32. The postsynaptic spikes 32 will typically all have the same amplitude (in order to simplify the generation process), but this is not a strict requirement. In a variant, the emitted postsynaptic spikes 32 may have different amplitudes. Furthermore, the emitted spikes 32 may possibly have the same amplitude as the input spikes, but this is also not a strict requirement.

[0039] The number of spikes emitted by the synaptic unit depends on the synaptic weight w stored thereon. In other words, here, the synaptic weights determine the number of spikes generated (S27) and the number of spikes emitted (S28), rather than the amplitude of the current emitted by the synaptic unit (compare Figures 1 and 2). Interestingly, the present method is still compatible with the spike timing dependent plasticity (STDP) mechanism. More generally, such methods may involve different learning mechanisms. All such mechanisms result in changing the weights of neuronal connections as learning proceeds. Once S40 training is appropriately performed, the SNN can be used for the purpose of inference in S50. Nevertheless, the present network 1, 1a to 1c may be used only for inference purposes, whereby these weights can each be set (i.e., programmed) to any suitable value as learned from the previous learning stage and remain unchanged for this purpose. That is, the synaptic weights may have been learned due to different hardware devices.

[0040] Since the number of spikes emitted (S28) by a synaptic unit is caused by the modulation of the weights stored on the unit 20, 20a-20c, not every spike 31 received (S22) may actually cause a spike 32 to be generated (S27) and transmitted (S28) to the post-synaptic neuron 14, as Fig. 7A Instead, only some of the received spikes 31 can actually be seen as being converted (modulated) into a larger (or smaller) number of spikes 32, see Figure 7B and 7C The correspondingly generated continuous spike trains can form a spike train such as Figure 7C Since the modulation is performed in frequency, the spikes 31 received (S22) will mostly be converted into a different number of spikes. Whether this conversion results in a larger or smaller number depends both on the weight values ​​and on the actual solution. For example, a spike sequence with a larger number of spikes can be obtained, as in Figure 3 and 7A -7C, or conversely, the spikes received from the presynaptic neuron 11 may be converted into a smaller number of spikes (e.g., Figure 4-67D). However, since the conversion also depends on the weight values, a spike received at step S22 may occasionally result in the emission of a single postsynaptic spike 31 (S28), or no spike at all. In some configurations, it may be necessary to receive S22 more than one spike 31 at the synaptic unit to trigger the generation of a postsynaptic spike 32 (S27). In such a case, depending on the synaptic weights, the input spike 31 may not be directly converted into one or more postsynaptic spikes 32.

[0041] This approach allows efficient and reliable implementation of neural networks that involve the transmission of discrete events rather than continuous signal values ​​(compare Figure 2B and 1B ). By definition, the present method is compatible with digital technology. It is otherwise compatible with synaptic implementations using memristive devices, as in embodiments of the invention discussed later with reference to another aspect of the invention.

[0042] Since the discrete events generated (S27) at the synaptic unit can be read and integrated more distinguishably at each output neuron 14 compared to the analog signal 34 (see Figure 1), the proposed scheme enables a higher dynamic range to be obtained in the synaptic output. In fact, in the prior art methods that rely on analog post-synaptic signals, it is necessary to fully distinguish the amplitudes of such signals to allow satisfactory distinction between the values ​​read from such amplitudes. However, this limits the dynamic range available for the signal in the synaptic output. In contrast, the present method relies on time resolution to distinguish post-synaptic events 32. Assuming that there is a sufficiently fast detection mechanism at the output neuron 14, it is understood that a higher dynamic range can be obtained in the synaptic output. The condition is that the time slots assigned to the generated spikes 32 generally result in larger time frames. However, the latter can be compensated by satisfactory time resolution when reading. In addition, the post-synaptic current 32 can be integrated in a smaller time step than the time step used for the analog signal 34 at the membrane potential in the receiving neuron 14, all things being equal in other respects. Note that the required temporal resolution and the dynamic range that can be achieved with it depends on the target application and the implementation chosen for it. As an example, assuming that the system operates in microsecond time and nanosecond pulses are used to clock spiking synapses, the range achieved already exceeds that of a standard (analog) synaptic configuration with 8-bit dynamic range.

[0043] This approach has other advantages. For example, it allows for more efficient selection of winner neurons in an all-winner network. That is, in prior methods, the difference between the membrane potential and the firing threshold is often used to estimate the winner, which is the first neuron to cross the threshold. In contrast, in embodiments contemplated herein, the winner neuron can be determined directly by thresholding without additional computation.

[0044] While ideal simulated synapses are difficult to achieve in practice, the present approach provides a solution to represent weights in a different way. Such an approach can be applied to native neuron-morphological hardware technology and thus help provide large power and efficiency gains in cognitive tasks. Hardware accelerators make it possible to accelerate such tasks, in particular in resistive processing units (RPUs) consisting of crossbar arrays of memristors.

[0045] All of this will now be described in detail with reference to a specific embodiment of the invention. First, note that the above process considers operations as specifically performed at the synaptic unit 20, 20a-20c, whether for inference or training purposes. However, additional operations are simultaneously performed at the level of the device 1, 1a to 1c, in particular at the circuitry implementing the neuron 11, 14. Such operations are included Figure 8 , whereby an external system can, for example, be coupled to the SNN and thereby transmit signals to it. Such signals are read (S12) as input at each receiving neuron, see stage S10. This in turn leads to the generation (S14) of spikes at the presynaptic neuron 11, which are then transmitted (S16) to the synaptic units 20, 20a-20c, for them to implement the process S20 as described above. The spikes transmitted by the synaptic units are then received (S32) at the corresponding postsynaptic neuron 14, resulting in the generation (S34) of output spikes and the transmission (S36) of the latter to other presynaptic neurons of other layers of the network, and so on.

[0046] Thus, in an embodiment, the method may comprise, inter alia, steps implemented at the post-synaptic neuron 14, whereby an output spike 33 is generated in S34 based on the post-synaptic spike 32 transmitted in S32, such as Figure 8 When several input neurons 11 are connected to the same output neuron 14 (see Figure 2B ), the spikes output from all adjacent synapses 20 are ultimately added 141 to form a total postsynaptic signal (e.g., current) at the receiving neuron 14. The total postsynaptic signal is integrated 142 at the receiving neuron 14, for example to generate (S34) output spikes 33.

[0047] The above process S10-S30 may be performed for training purposes, such as Figure 8as assumed in the flowchart of . When the training is completed (S40), the final weights are obtained, which can then be used for inference purposes (S50). That is, the final weights can remain unchanged at the same network or be passed to another network in order to make inferences therewith. It is to be noted that for the purpose of inference, the above steps S26-S28 can also be performed. In this case as well, the input received from the pre-synaptic neuron 11 is modulated (S26), thereby generating spikes that are transmitted to the post-synaptic neuron 14 so that the SNN output is interpreted as a signal of the result (inference).

[0048] During the training phase, the synaptic weights may be determined, for example, due to the state maintained at the synaptic unit. Figure 8 As seen in , each synaptic unit 20, 20a-20c will therefore maintain a state S25a, which determines the synaptic weight w that is then used to step modulate (S26) the input spike 31. The state can be changed according to a cognitive learning mechanism to appropriately adjust the weights. As mentioned above, the cognitive mechanism can be, for example, an STDP mechanism. In a variant, the learning mechanism can be any suitable (e.g., global) learning scheme, such as a back-propagation mechanism. However, in other variants, the SNN can simply be designed to implement an inference engine, as mentioned before. That is, the weights can be set (i.e., programmed) based on weights as learned elsewhere.

[0049] Such states may notably be captured by the resistance state of a device element forming part of the synaptic unit 20, 20a-20c. For example, memristive devices 21, 21a-21c may notably be used, see Figure 3-6 Such a device can be thought of as a resistive switch that is capable of maintaining the state of an internal resistance based on a history of applied voltage and current. That is, a memristive device is capable of maintaining the state of an internal resistance based on previously applied voltage and current (i.e., history). Such a device can be used to store and process information accordingly. In this context, the performance characteristics of a memristive device can be superior to conventional integrated circuits.

[0050] The learning mechanism causes the state maintained at the synaptic unit 20, 20a-20c to be changed at step S24 based on the spikes 31 received S22 from the presynaptic neuron 11 and the output spikes 33 generated at the postsynaptic neuron 14 of SNN1, 1a-1c at step S34. Note that in addition to the spikes received from the presynaptic neuron 11, the local learning mechanism only relies on spikes locally emitted by the postsynaptic neuron 14, such as Figure 2A-2BAs assumed in . That is, each synaptic connection learns its corresponding weight based on the spikes 31 received from the corresponding pre-synaptic neuron 11 and the output spikes 33 generated at the corresponding post-synaptic neuron 14. For example, the synaptic units 20, 20a-20c can implement an STDP mechanism or a STDP-like mechanism, as assumed in the accompanying drawings. Such a mechanism enables each synaptic unit to change (S24) the state they maintain based on the spikes 31 received (S22) from the corresponding pre-synaptic neuron 11 and the output spikes 33 generated (S34) at the corresponding post-synaptic neuron 14. In a variant, a more global learning scheme can be used, which also takes into account the output spikes emitted by other neurons.

[0051] like Figure 2B As shown, the output spike 33 may be generated (S34) by integrating the postsynaptic spikes 32 received at the postsynaptic neuron 14 based on the count of the postsynaptic neuron 14. For example, at the synaptic element 20, the input spike 31 received from the presynaptic neuron 11 may be converted into a spike train, all of which have the same amplitude, wherein the number of spikes depends on the synaptic weight. Figure 2B As seen in , at synapse j, the input spike 31 is locally converted into a spike train which, in the case of an integrate-and-fire (IF) neuron, results in the following contribution to its neuronal membrane potential:

[0052]

[0053] In the above equation, Δt sp represents the time interval of each input spike, and q j (t) represents a spike output at synapse j. All such outputs have the same amplitude, so that their sum is equal to the synaptic weight w j (up to a factor b).

[0054] Otherwise the STDP mechanism remains unchanged. The spikes from all synapses j reaching the same output neuron 14 are added to form a total postsynaptic current at the receiving neuron 14, and the total postsynaptic current is integrated into the membrane potential at the receiving neuron 14 to generate the output spike 33. Therefore, the total contribution of the postsynaptic current can be written as:

[0055]

[0056] Among them, x j (t) represents the occurrence of an input spike at synapse j at time instance t (in this case there are n connections to the output neuron of interest), w j is the synaptic weight, and b is a constant.

[0057] In contrast, in the prior art solutions (see Figure 1A and 1B ), each input spike 31 from the presynaptic neuron 11 is converted into an analog current 34 (postsynaptic current) at the synaptic output, where the amplitude of the current depends on the synaptic weight. Figure 1B As shown, the input spike 31 is locally converted into the following contribution to the membrane potential:

[0058] ΔV j (Δt sp )=w j a,

[0059] Among them, Δt sp represents the time interval of each input spike, w j is the synaptic weight, and a is a constant. The synaptic weight varies according to the activity of the presynaptic and postsynaptic neurons (e.g., according to the STDP mechanism). The currents from all synapses are added to form a total postsynaptic current at the receiving neuron, and the total postsynaptic current is integrated at the receiving neuron to generate the output spike. Therefore, in this case, the total contribution of the postsynaptic current (as in the range from t0 to t l The integral over the time period can be written as:

[0060]

[0061] Now refer to Figure 3 A first class of embodiments is described. In this example, spikes 31 received (S22) from the presynaptic neuron 11 (at each synaptic unit 20) are modulated (S26) by first converting the received spikes 31 into a current due to the memristive device 21, by S262. Note that more generally, such spikes can first be converted into electrical signals (which can depend on voltage signals). In all cases, the modulation depends on the current synaptic weight w, which itself is determined by the current state of the synapse 20. Then, based on the electrical signal, and before the spikes 32 are generated due to the spike generation unit 22, the frequency of the postsynaptic spikes 32 to be generated is set S264.

[0062] exist Figure 3 In the specific example of , the depicted device forms part of a hardware arrangement 1 and comprises a memristive device 21 storing synaptic weights w, a circuit block 15 implementing a desired learning rule, and a spike generation block 22 generating spikes (in predefined intervals) with a spike frequency depending on the current synaptic weights w. The spike generation unit 22 may be adapted, for example, by a neuronal circuit implementation such as described in the references cited in the background section. Figure 3The operation of the synaptic element shown is as follows. An input spike 31 received from the presynaptic neuron 11 generates a read event at the memristive element 21. The resulting read current sets the postsynaptic spike frequency at the spike generation block 22, based on which postsynaptic spikes are generated (S27). The synaptic weights w are concomitantly updated using a given learning rule (e.g., based on STDP).

[0063] Figure 4 and Figure 5 A similar process is involved, with the following conditions. Figure 4 and 5 Two additional classes of embodiments are reflected that require the synaptic unit to maintain S25, each of which is an additional state (which will be referred to as a secondary state). That is, the primary state determines the weight w, while the secondary state maintained at the synapse at S25 determines the short-term synaptic weight w s .like Figure 4 and 5 As shown, the latter also depends on the spike 31 received from the presynaptic neuron 11. In more detail, the spike 31 received (S22) from the presynaptic neuron 11 is now modulated (S26) by comparing the current synaptic weight w with a threshold value 23a, 23b. The latter depends on the short-term synaptic weight w s Only if the current synaptic weight w is greater than or equal to the threshold value, a post-synaptic spike 32 is generated (S27).

[0064] Comparators 23a, 23b are involved for this purpose. The above comparison amounts to a conditional construction for evaluating the current synaptic weight w relative to the threshold. This value can be defined in different ways. Specifically, the threshold can be taken to be equal to the short-term synaptic weight w s or as the difference w max –w s , where w max It is w+w s The maximum value allowed for the sum.

[0065] In more detail, in Figure 4 In the embodiment depicted in FIG, the threshold is taken to be equal to the short-term synaptic weight w s , so that only when the current synaptic weight w is greater than or equal to w s The current synaptic weight w and w s A comparison 23a is made and a postsynaptic spike 32 is generated (S27). The modulation and generation process S26-S27 includes w s With w s The maximum value w allowed max Next, if w is found s is greater than or equal to the maximum value, the short-term weight w sreset to its initial value, i.e., possibly adjusted to 0 and w max Any value between .

[0066] exist Figure 4 In the specific example of , the depicted device forms part of a hardware arrangement 1a comprising a memristive device 21a storing a synaptic weight w, a short memory memristive device 25a determining the number of post-synaptic spikes upon modulation, and two comparator blocks 23a, 24a. Figure 3 As shown, circuit block 15 implements the learning rule. However, spike generation block 22a now generates spikes based on the output of comparator block 23a. The operation of the depicted synaptic element is as follows. The input is accumulated into short memory device 25a (storing w) using a write pulse for each incoming spike. s ). The incoming spike generates a read event for both memristive elements 21a, 25a. s The output spike is generated at w s ≥w max At the same time, the synaptic weight w is updated using a given learning rule. Thus, when the synaptic weight w is small, after a few incoming events, the condition w ≥ w s will not be valid, and synapse 20a will stop firing. In contrast, when the synaptic weight w is high, the condition w ≥ w s Remains valid for several incoming events.

[0067] In such Figure 5 In the embodiment shown in FIG. 1 , the threshold is instead taken as the maximum value w max With the short-term synaptic weight w s The difference between max –w s Note that the maximum value is now w+w s Therefore, in 23b, the current weight w is now equal to the difference w max –w s The comparison is performed, and a postsynaptic spike 32 is generated at S27 only if the current synaptic weight w is greater than or equal to this difference. Whenever S27 generates a postsynaptic spike 32 for transmission to the postsynaptic neuron 14 (i.e., after S27 has generated the spike), the short-term synaptic weight w s Reset at 22b.

[0068] exist Figure 5 In the specific example of , the depicted means forms part of a hardware device 1b and comprises a device similar to Figure 4Components 15, 21a, 22a and 25a of the element 15, 21b, 22b and 25b. However, the element does not include a second comparator. Instead, the adder block 26 adds the signals obtained from the memristive elements 21b, 25b, and the spike generation block generates spikes based on the output of the comparator block 23b. The element operates as follows. With a write pulse for each input spike 31, the input is accumulated to the short memory device 25b. Moreover, the incoming spike 31 generates a read event at both elements 21b, 25b. If w+w s ≥w max , an output spike is generated. In a variant, the synapse 20b can generate multiple spikes (in predefined intervals) with a spike frequency that depends on the synaptic weight. In this case, the short memory device 25b is reset after each output start event. The synaptic weight w is updated simultaneously by the circuit block 15. When the synaptic weight w is low, the sum w+w s Reach w max Requires a number of incoming events (also increases the weight w s ). In contrast, when the synaptic weight w is already high, perhaps due to a single incoming event, the sum w+w s It is easier to reach w max .

[0069] Figure 6 Another class of embodiments is reflected in which each input spike triggers oscillation via a voltage controlled oscillator 28. Here, the frequency or damping of the oscillator circuit is controlled by a weight w stored on the memristor device 21c. Large weight values ​​result in high frequencies or low damping, while small weight values ​​result in low frequencies or high damping. For example, the weight of the memristor device 21c is used to determine the spike threshold of the cell 29c. When the voltage exceeds the threshold Vth, a single spike is generated.

[0070] refer to Figure 2A , Figure 3-6 , another aspect of the invention is now described in detail, which relates to a synaptic unit circuit 20, 20a to 20c for transmitting signals between neurons 11, 14 of a hardware-implemented SNN 1, 1a to 1c. The components and operation of such a circuit have been described with reference to the present method. The main characteristics of these circuits are therefore only briefly described below. Such a synaptic circuit is generally designed to connect a presynaptic neuron 11 of a network to a postsynaptic neuron 14, thereby forming a neuronal connection. When appropriately connected to the presynaptic neuron 11 and the postsynaptic neuron 14, this circuit allows the spike 31 received from the presynaptic neuron 11 to be modulated in frequency based on the synaptic weight w stored on the presynaptic neuron 11, so as to generate a postsynaptic spike 32. That is, in operation, the spike 31 received from the presynaptic neuron 11 can be converted into a different number of postsynaptic spikes 32 before the generated postsynaptic spike 32 is transmitted to the postsynaptic neuron 14.

[0071] As described, such a circuit may be configured to generate postsynaptic spikes 32 having all the same amplitude. Furthermore, in operation, the circuit may, for example, maintain a state determining the synaptic weight w and change the state based on spikes 31 received from the presynaptic neuron 11 on the one hand, and on spikes 33 emitted by the postsynaptic neuron 14 to which it is attached on the other hand.

[0072] like Figures 3 to 5 As shown in , the circuit may include a spike generation unit 22, 22a to 22c, wherein the unit is designed to generate a post-synaptic spike 32 and transmit the correspondingly generated post-synaptic spike 32 to the post-synaptic neuron 14 in operation. An update unit 15 generally forms part of the circuit. The unit 15 is arranged to be connectable to the pair of neurons 11, 14. The unit 15 is used to change the state of the circuit (e.g., based on the STDP mechanism), thereby allowing the weights to be learned in operation. In addition, the circuit may include a memristive device 21, 21a-21c, wherein the memristive device 21, 21a-21c is connected to each of the spike generation unit and the update unit 15. The memristive device is connected to the spike generation unit 22, 22a-22c; it is otherwise connectable to the pre-synaptic neuron 11. As explained before, the memristive device 21, 21a-21c is adapted to maintain a resistive state so that the spike generating unit 22, 22a-22c modulates the spike 31 received by the memristive device from the presynaptic neuron 11 based on the synaptic weight w determined from this state and subsequently generates, in operation, a postsynaptic spike 32. The memristive device is also connected to the updating unit 15: in operation, any state of the memristive device (as changed by the updating unit 15) determines (changes to) the synaptic weight w, which itself affects the modulation of the spike 31.

[0073] like Figure 3 As shown, the memristive device 21, 21a, 21b can be particularly configured to convert the spike 31 into a current to an extent determined by the synaptic weight w, which itself is determined by the state maintained by the memristive device. In addition, the spike generating unit 22, 22a-22c can be designed to set the frequency of the post-synaptic spike 32 based on such a current when in operation to modulate the spike 31 received from the pre-synaptic neuron 11.

[0074] The inventors have conducted a number of experiments to check the validity of the present method. In particular, they have tested and confirmed the possibility of detecting correlations with neurons connected by several input streams, which neurons are otherwise connected to a synaptic unit circuit as described above. It was concluded that such a spiking synaptic element enables unambiguous determination of whether some input data streams are statistically correlated.

[0075] See also Figure 4 , 5 , the synaptic unit circuit 20a, 20b may further be configured to maintain different states, namely a primary state and a secondary state. The primary state is maintained by a first memristive device 21a, 21b, while a second memristive device 25a, 25b is provided (again, connectable to the presynaptic neuron 11) to maintain the secondary state. The latter determines the short-term synaptic weight w s As previously described, in operation the secondary state depends on the spike 31 received from the pre-synaptic neuron 11 by the second memristive device.

[0076] As in Figure 4 , Figure 5 As further seen in FIG. 1 , the synaptic unit circuit 20a, 20b may further include a comparator 23a, 23b. The latter is connected to each of the first memristive device 21a, 21b and the second memristive device 25a, 25b so as to be able to compare the current synaptic weight w with a threshold. As mentioned above, the threshold can be defined in various ways. In all cases, this threshold depends on the short-term synaptic weight w s , which itself is determined from the secondary state. In operation, a post-synaptic spike 32 is generated by the spike generating unit 22a, 22b only if the current synaptic weight w is greater than or equal to the threshold value.

[0077] As mentioned before, this threshold can be simply set equal to the short-term synaptic weight w s (See Figure 4 ), in which case, a second comparator 24a is included to convert the short-term synaptic weight w s The maximum value w allowed by the threshold max The circuit is otherwise configured so that if it finds that the short-term synaptic weight w s is greater than or equal to the maximum value, the short-term synaptic weight w is reset due to the second comparator 24a. s .

[0078] In such Figure 5 In the variant shown in FIG. 1 , a single comparator 23 b is relied upon, which is designed to convert the difference w max –w s is used as the threshold for comparison purposes. There, in operation, only if the current synaptic weight w is found to be greater than or equal to the above difference w max –w s The postsynaptic spike 32 is generated by the spike generation unit only when the postsynaptic spike 32 is generated for transmission to the postsynaptic neuron 14 (after the spike has been generated), the circuit resets the short-term synaptic weight w s .

[0079] Next, according to a final aspect, the present invention may be implemented as a hardware device 1, 1a-1c. The device implements an SNN and comprises a plurality of neuron connections. Each of these connections comprises a presynaptic neuron 11, a postsynaptic neuron 14 and a synaptic unit circuit 20, 20a-20c, such as previously described. Each synaptic unit circuit connects the presynaptic neuron 11 to the postsynaptic neuron 14, respectively. Each postsynaptic neuron may be connected in particular via a plurality of synaptic unit circuits of the network, such as Figure 2B As shown. Therefore, each post-synaptic neuron 14 can be configured to generate an output spike 33 based on the post-synaptic spike 32 sent by each of the respective synaptic unit circuits 20, 20a to 20c. As previously explained in detail, each post-synaptic neuron 14 can be further configured to generate an output spike 33 by integrating the post-synaptic spikes 32 transmitted by the corresponding circuit 20, 20a to 20c based on the count of the transmitted spikes 32.

[0080] Although the present invention has been described with reference to a limited number of embodiments, variants and drawings, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. Specifically, the features (similar devices or similar methods) listed in a given embodiment, variant or shown in the drawings may be combined with or replace another feature in another embodiment, variant or drawing without departing from the scope of the present invention. Different combinations of features described with respect to any of the above embodiments or variations are accordingly contemplated, which are still within the scope of the appended claims. In addition, many minor modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from its scope. Therefore, the present invention is not intended to be limited to the specific embodiments disclosed, but the present invention will include all embodiments falling within the scope of the appended claims. In addition, many other variations other than those explicitly touched upon above may be envisioned.

Claims

1. A method for transmitting signals between neurons of a hardware-implemented spiking neural network, wherein: The spiking neural network comprises neuronal connections, each of the neuronal connections comprising a synaptic unit connecting a presynaptic neuron to a postsynaptic neuron, the method comprising, for each of the neuronal connections and at each of the synaptic units of each of the neuronal connections: modulating spikes received from a presynaptic neuron to which each of the neurons is connected in frequency to generate postsynaptic spikes based on a synaptic weight stored on each of the synaptic units, thereby converting a first number of spikes received from the presynaptic neuron into a second number of postsynaptic spikes; and The generated postsynaptic spike is transmitted to each postsynaptic neuron to which the neuron is connected.

2. The method according to claim 1, characterized in that The method further comprises: At the postsynaptic neuron to which each of the neurons is connected, an output spike is generated based on the transmitted postsynaptic spike.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: At each of the synaptic units, a state determining the synaptic weight is maintained, wherein the state is modifiable according to a cognitive learning mechanism.

4. The method according to claim 3, wherein: The method further comprises: At each of the synaptic units, the state is changed according to the cognitive learning mechanism based on spikes received from the presynaptic neuron on the one hand and on output spikes generated at one or more postsynaptic neurons of the spiking neural network on the other hand.

5. The method according to claim 3, wherein: The synaptic unit is configured to implement a spike timing dependent plasticity mechanism based on spikes received from the pre-synaptic neuron and output spikes generated at the post-synaptic neuron, thereby changing the state based on the spike timing dependent plasticity mechanism.

6. The method according to claim 2, wherein: The output spike is generated by integrating post-synaptic spikes received at the post-synaptic neuron based on the count of the post-synaptic neuron.

7. The method according to claim 3, wherein: At each synaptic unit, the spike received from the presynaptic neuron is modulated by first converting the received spike into one or more electrical signals according to the synaptic weight determined by the state, and then by setting the frequency of the post-synaptic spike to be generated based on the electrical signal.

8. The method according to claim 3, wherein: The state is a primary state; and Modulating the spike received from the presynaptic neuron comprises: maintaining a secondary state that determines a short-term synaptic weight based on spikes received from the presynaptic neuron; and A current synaptic weight determined by the primary state is compared to a threshold value, the threshold value being dependent on the short-term synaptic weight determined from the secondary state, whereby the post-synaptic spike is generated only when the current synaptic weight is greater than or equal to the threshold value.

9. The method according to claim 8, wherein: The threshold is equal to the short-term synaptic weight, whereby the current synaptic weight is compared with the short-term synaptic weight, and the post-synaptic spike is generated only when the current synaptic weight is greater than or equal to the short-term synaptic weight; and Modulating spikes received from the pre-synaptic neuron further includes comparing the short-term synaptic weight to a maximum value allowed for the threshold, and resetting the short-term synaptic weight if the short-term synaptic weight is accordingly found to be greater than or equal to the maximum value.

10. The method according to claim 8, wherein: The threshold is equal to the difference between the maximum value and the short-term synaptic weight, whereby the current synaptic weight is compared with the difference, the maximum value being the maximum value allowed by the sum of the current synaptic weight and the short-term synaptic weight, so that the post-synaptic spike is generated only when the current synaptic weight is greater than or equal to the difference; and Modulating spikes received from the pre-synaptic neuron further comprises resetting the short-term synaptic weight each time a post-synaptic spike is generated for transmission to the post-synaptic neuron after the spike has been generated.

11. The method according to any one of claims 1, 2 and 6, wherein: The generated postsynaptic spikes all have the same signal amplitude.

12. A synaptic unit circuit for transmitting signals between neurons of a hardware-implemented spiking neural network, wherein: The circuit is used to connect the presynaptic neurons and the postsynaptic neurons of the network to form a neuron connection; and The circuit is configured, when connected to the presynaptic neuron and the postsynaptic neuron: modulating spikes received from the presynaptic neuron in frequency to generate postsynaptic spikes based on synaptic weights stored on the circuit, whereby in operation a first number of spikes received from the presynaptic neuron are converted into a second number of postsynaptic spikes; and The generated postsynaptic spike is transmitted to the postsynaptic neuron.

13. The synaptic unit circuit according to claim 12, wherein: The circuit is further configured to generate post-synaptic spikes having all the same amplitude when connected to the pre-synaptic neuron and the post-synaptic neuron.

14. The synaptic unit circuit according to claim 12 or 13, wherein: The circuit is further configured to, when connected to the pre-synaptic neuron and the post-synaptic neuron, maintain a state determining the synaptic weight and to change the state based on spikes received from the pre-synaptic neuron on the one hand and spikes emitted by the post-synaptic neuron on the other hand.

15. The synaptic unit circuit according to claim 14, wherein: The circuit includes: a spike generation unit designed to generate said post-synaptic spike in operation and to transmit said generated post-synaptic spike to said post-synaptic neuron; an update unit connectable to each of the pre-synaptic neuron and the post-synaptic neuron and configured to change the state in operation; and A memristive device, wherein the memristive device is: The memristive device is configured to maintain the state so that in operation, the memristive device modulates a spike received by the memristive device from the presynaptic neuron based on a synaptic weight determined from the state and generates the postsynaptic spike; and, connected to the update unit, in operation, any state modified by the update unit determines the synaptic weight used to modulate the spike.

16. The synaptic unit circuit according to claim 15, wherein: The update unit is further configured to implement a spike timing dependent plasticity mechanism based on spikes received from the pre-synaptic neuron and output spikes generated at the post-synaptic neuron, thereby in operation changing the state based on the spike timing dependent plasticity mechanism.

17. The synaptic unit circuit according to claim 15, wherein: The memristive device is further configured to: convert spikes received from the presynaptic neuron into one or more electrical signals according to a synaptic weight determined by a state maintained in the memristive device; and The spike generation unit is further configured to set a frequency of a post-synaptic spike to be generated based on the electrical signal in operation to modulate spikes received from the pre-synaptic neuron.

18. The synaptic unit circuit according to claim 15, wherein: The state is a primary state, and the memristive device is a first memristive device configured to maintain the primary state; and The synaptic unit circuit also includes a second memristive device, which is connectable to the pre-synaptic neuron and is designed to maintain a secondary state determining a short-term synaptic weight, the secondary state depending on spikes received by the second memristive device from the pre-synaptic neuron in operation.

19. The synaptic unit circuit according to claim 18, wherein: The synaptic unit circuit further comprises a comparator connected to each of the first memristive device and the second memristive device for comparing a current synaptic weight determined from the primary state with a threshold value, the latter depending on the short-term synaptic weight determined from the secondary state, whereby in operation, the post-synaptic spike is generated by the spike generation unit only when the current synaptic weight is greater than or equal to the threshold value.

20. The synaptic unit circuit according to claim 19, wherein: The comparator is a first comparator designed to use the short-term synaptic weight as the threshold, whereby the post-synaptic spike is generated by the spike generation unit only when the current synaptic weight is greater than or equal to the short-term synaptic weight; and The circuit further includes a second comparator configured to compare the short-term synaptic weight with a maximum value allowed for the threshold, and if the short-term synaptic weight is found to be greater than or equal to the maximum value, the circuit is configured to reset the short-term synaptic weight.

21. The synaptic unit circuit according to claim 19, wherein: The comparator is designed to use the difference between the maximum value and the short-term synaptic weight as the threshold value for comparing the current synaptic weight with the threshold value, wherein the maximum value is the maximum value allowed by the sum of the current synaptic weight and the short-term synaptic weight, whereby in operation, the post-synaptic spike is generated by the spike generation unit only when the current synaptic weight is greater than or equal to the difference; and The circuit is further configured to, after the short-term synaptic weight has been generated, reset the short-term synaptic weight each time a post-synaptic spike is generated for transmission to the post-synaptic neuron.

22. A hardware device for implementing a spiking neural network, wherein: The network includes a plurality of neuron connections, each of which includes: presynaptic neuron; postsynaptic neurons; and a synaptic unit circuit, which connects the presynaptic neurons to the postsynaptic neurons respectively; The synaptic unit circuit is configured to transmit signals between neurons of a hardware-implemented spiking neural network, wherein: The circuit is used to connect a presynaptic neuron of the network to a postsynaptic neuron to form a neuronal connection; and The circuit is configured, when connected to the presynaptic neuron and the postsynaptic neuron: modulating spikes received from the presynaptic neuron in frequency based on synaptic weights stored on the circuit to generate postsynaptic spikes, whereby in operation a first number of spikes received from the presynaptic neuron are converted into a second number of postsynaptic spikes; and The generated postsynaptic spike is transmitted to the postsynaptic neuron.

23. The hardware device of claim 22, wherein: Each postsynaptic neuron to which the neuron is connected: connected by a plurality of synaptic unit circuits of the network; and Configured to generate output spikes based on post-synaptic spikes transmitted by one or more corresponding synaptic unit circuits.

24. The hardware device of claim 23, wherein: Each of the post-synaptic neurons is further configured to generate the output spike by integrating the post-synaptic spikes based on a count of the post-synaptic spikes sent by the respective synaptic unit circuit.

Images