Detection of low output voltage of power converters

Abstract

A device comprising a first transistor (202) coupled to a ground node and a current source (204). The first transistor includes a control terminal coupled to a reference voltage source (REF), wherein the current source is coupled to an input voltage source (VIN). The device comprises a second transistor (206) coupled to the input voltage source, wherein the second transistor includes a control terminal coupled to the first transistor. The device comprises a third transistor (208) coupled to the second transistor, wherein the third transistor includes a control terminal coupled to an output voltage node (VOUT). The device comprises a fourth transistor (210) coupled to the third transistor, wherein the fourth transistor includes a control terminal coupled to the output voltage node. The device comprises a fifth transistor (212) coupled to the fourth transistor and a resistor (214), wherein the fifth transistor includes a control terminal coupled to the fourth transistor. The resistor is coupled to the ground node.

Description

Summary of the Invention

[0001] According to at least one example of the present disclosure, a device includes a first transistor coupled to a ground node and a current source. The first transistor includes a control terminal coupled to a reference voltage source, wherein the current source is coupled to an input voltage source. The device includes a second transistor coupled to the input voltage source, wherein the second transistor includes a control terminal coupled to the first transistor. The device includes a third transistor coupled to the second transistor, wherein the third transistor includes a control terminal coupled to an output voltage node. The device includes a fourth transistor coupled to the third transistor, wherein the fourth transistor includes a control terminal coupled to the output voltage node. The device includes a fifth transistor coupled to the fourth transistor and a resistor, wherein the fifth transistor includes a control terminal coupled to the fourth transistor. The resistor is coupled to the ground node.

[0002] According to another example of the present disclosure, a device includes a first transistor coupled to a ground node, wherein the first transistor includes a control terminal coupled to a reference voltage source. The device also includes a second transistor coupled to the first transistor and a first current source, wherein the second transistor includes a control terminal coupled to the first current source. The first current source is coupled to an input voltage source. The device also includes a third transistor coupled to the input voltage source, wherein the third transistor includes a control terminal coupled to the second transistor. The device also includes a fourth transistor coupled to the third transistor, wherein the fourth transistor includes a control terminal coupled to an output voltage node. The device also includes a fifth transistor coupled to the fourth transistor and a second current source, wherein the fifth transistor includes a control terminal coupled to the output voltage node. The second current source is coupled to the ground node.

[0003] According to another example of the present disclosure, a system includes a low output voltage detection circuit, the low output voltage detection circuit including a first transistor coupled to a ground node and a current source, wherein the first transistor includes a control terminal coupled to a reference voltage source. The current source is coupled to an input voltage source. The low output voltage detection circuit also includes a second transistor coupled to the input voltage source, wherein the second transistor includes a control terminal coupled to the first transistor. The low output voltage detection circuit also includes a third transistor coupled to the second transistor, wherein the third transistor includes a control terminal coupled to an output voltage node. The low output voltage detection circuit also includes a fourth transistor coupled to the third transistor, wherein the fourth transistor includes a control terminal coupled to the output voltage node. The low output voltage detection circuit also includes a fifth transistor coupled to the fourth transistor and a resistor, wherein the fifth transistor includes a control terminal coupled to the fourth transistor. The resistor is coupled to the ground node. The system also includes a digitizer having an input coupled to a node between the third and fourth transistors and having a digital output. The system also includes a switch coupled to the digital output, the switch having a first input coupled to the input voltage source, a second input coupled to the output voltage node, and an output configured to couple to the first input in response to the digital output being asserted and to couple to the second input in response to the digital output being deasserted. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0005] Figure 1 shows a block diagram of a system according to an example;

[0006] Figure 2 shows a circuit schematic according to an example;

[0007] Figure 3 The corresponding Figure 2 The waveform of the circuit;

[0008] Figure 4 shows another circuit schematic according to an example; and

[0009] Figure 5 The corresponding Figure 4 The waveform of the circuit. DETAILED DESCRIPTION

[0010] A step-down DC-DC voltage converter regulates an output voltage, wherein the value of the output voltage is less than the value of the input voltage provided by the power supply. The buck converter topology represents a class of DC-DC voltage converters that has a switching device to control the current through an inductor (and typically a capacitor) to regulate the output voltage. A buck converter includes a high-side switching device for coupling the inductor to the power supply, and a low-side switching device for providing a current path from ground to the inductor when the high-side switching device is turned off. In some buck converters, the high-side switching device is a metal oxide semiconductor field effect transistor (MOSFET), referred to as a high-side MOSFET, and the low-side device is a MOSFET, referred to as a low-side MOSFET.

[0011] In some buck converter topologies, pulse width modulation (PWM) is used to control the regulation of the output voltage relative to the input voltage. The PWM modulator changes the duty cycle of the high-side MOSFET and the low-side MOSFET. An increased duty cycle results in a larger output voltage relative to the input voltage, while a decreased duty cycle results in a smaller output voltage relative to the input voltage. The light load efficiency of the power converter is improved by utilizing the output voltage rather than the input voltage as the supply voltage for the PWM modulator and other components of the buck core, in addition to the reference system (e.g., including the bias current and reference voltage generators). If the components of the buck core and / or the reference system are powered from the output voltage, the input current consumption is reduced depending on the duty cycle. However, if the output voltage becomes too low for any reason, the power converter should revert to using the input voltage as the supply voltage for the PWM modulator and other components of the buck core until the output voltage recovers. If the power converter does not return to the input voltage in this case, the power converter may suffer performance issues.

[0012] Examples of the present disclosure relate to a device for quickly and accurately sensing or identifying a condition in which an output voltage is too low to be used as a supply voltage for a PWM modulator and / or other components of a buck core. The device compares the output voltage to a reference voltage and generates a signal indicating a low output voltage condition when the output voltage drops below a threshold relative to the reference voltage. Both the output voltage and the reference voltage are provided to a high impedance input of the device. With respect to the reference voltage, this avoids the problem of loading the reference voltage source, which is problematic in low power applications, such as a sample-and-hold bandgap reference voltage source. The signal indicating the low output voltage condition is used to switch the supply voltage for the PWM modulator and / or other components of the buck core back to the input voltage until the low output voltage condition resolves, at which point the supply voltage for the PWM modulator and / or other components of the buck core is switched back to the output voltage. In addition, the device achieves a low quiescent current, which improves its efficiency at light loads.

[0013] Figure 1Schematic system 100 is shown that includes a DC-DC voltage converter 102. In some examples, DC-DC voltage converter 102 is a buck converter. DC-DC voltage converter 102 includes a high-side MOSFET 103, a low-side MOSFET 105, a gate driver 104, a controller 106, and a PWM modulator 108. In some examples, gate driver 104 includes a charge pump. Controller 106 is coupled to high-side MOSFET 103 and low-side MOSFET 105 via gate driver 104. In addition to PWM modulator 108, controller 106, and gate driver 104, some examples may include other modules (not shown).

[0014] High-side MOSFET 103 includes a gate, a source, and a drain. Node 111 is coupled to the source of the high-side MOSFET. Node 111 may be referred to as a switching node, and it may be a pin. Low-side MOSFET 105 also includes a gate, a source, and a drain, which are coupled to node 111.

[0015] Controller 106 is coupled to the gate of high-side MOSFET 103 via gate driver 104 to turn high-side MOSFET 103 on and off, and is coupled to the gate of low-side MOSFET 105 to turn low-side MOSFET 105 on and off to provide an output voltage (VOUT, which is also used to refer to the node at VOUT) to load 114. Load 114 is coupled to node 111 via inductor 110 and is also coupled to capacitor 112.

[0016] The drain of high-side MOSFET 103 is coupled to power supply 101, which provides an input voltage (VIN, which is also used to refer to a node at VIN) as an input voltage to DC-DC voltage converter 102. The source of low-side MOSFET 105 is coupled to ground.

[0017] Controller 106 provides logic signals to gate driver 104 for turning high-side MOSFET 103 and low-side MOSFET 105 on and off. PWM modulator 108 receives a power supply voltage (AVDD, also used to refer to the node at AVDD), which is typically either input voltage VIN or output voltage VOUT. PWM modulator 108 also receives a control signal 109, which is a feedback signal derived from VOUT. For example, feedback controller 107 receives VOUT as an input (e.g., directly or divided by a voltage divider, not shown for simplicity) and, based on internal control logic, generates a corresponding control signal 109 to control the PWM modulator. PWM modulator 108 increases or decreases the duty cycle based on control signal 109. For example, if control signal 109 indicates that VOUT is lower than desired, control signal 109 causes PWM modulator 108 to increase the duty cycle, which is then executed by control logic 106 and gate driver 104 to change the on / off times of high-side MOSFET 103 and low-side MOSFET 105. On the other hand, if control signal 109 indicates that VOUT is higher than desired, control signal 109 causes PWM modulator 108 to decrease the duty cycle, which is then executed by control logic 106 and gate driver 104 to change the on / off times of high-side MOSFET 103 and low-side MOSFET 105.

[0018] Reference has been made above to the buck core, which in some examples includes gate driver 104, control logic 106, PWM modulator 108, and feedback controller 107. As described above, the efficiency of the DC-DC voltage converter 102 is improved when components of the buck core, such as PWM modulator 108, are supplied from VOUT rather than VIN. That is, efficiency is improved when AVDD is coupled to VOUT rather than VIN. In some examples, AVDD is used only to supply PWM modulator 108, while in other examples, AVDD is used to supply some or all of the other elements of the buck core (and reference system 120, explained further below). The scope of the present disclosure is not limited to any component or group of components that is coupled to AVDD and therefore supplied from either VIN or VOUT. For ease of discussion, the PWM modulator 108 is discussed below in this context because it consumes a significant portion of the current under light loads, and therefore efficiency is improved when VOUT is supplied to the PWM modulator 108, when feasible. However, other components of the buck core may also be coupled to AVDD and therefore supplied from either VIN or VOUT.

[0019] In some cases, the PWM modulator 108 is not adequately supplied by VOUT, which may result in, for example, an undesirable decrease in the operating speed of the PWM modulator 108. For example, when VOUT becomes too low, VOUT may not provide sufficient headroom for the operation of the PWM modulator 108. If VOUT becomes too low for any reason, AVDD should be coupled to VIN until VOUT recovers.

[0020] In order to improve the overall efficiency of the DC-DC converter 102, a VOUT low detection circuit 116 is coupled to VIN, which is the supply voltage of the VOUT low detection circuit 116. The VOUT low detection circuit 116 also receives VOUT and a reference voltage (REF) as inputs. As will be further explained below, these inputs are high-impedance inputs to avoid loading of REF or VOUT. The VOUT low detection circuit 116 compares VOUT with REF and generates a VOUT_LOW signal based on the result of the comparison. The VOUT_LOW signal can include a digital signal that is asserted or deasserted.

[0021] As an example of a comparison between VOUT and REF performed by the VOUT low detection circuit 116, REF includes a reference voltage equal to a target value for VOUT, such as 1.5V. The reference system 120 generates REF (and a bias current, described further below), which can be derived by amplifying or attenuating an internal reference voltage (not shown) to the target output voltage. For example, the internal reference voltage can include a bandgap voltage that is amplified to a target level for VOUT (e.g., 1.5V) and stored on a sample-and-hold capacitor. While a sample-and-hold bandgap reference is well-suited for reducing power consumption (e.g., for ultra-low power applications), this reference should not be loaded and, therefore, should be coupled to a high-impedance input.

[0022] In the example above, since REF is set as the target value for VOUT, VOUT is not compared directly to REF because even a small decrease in VOUT would cause VOUT_LOW to assert. Therefore, the VOUT low detection circuit 116 establishes a threshold relative to REF, which causes VOUT low detection circuit 116 to assert VOUT_LOW as VOUT drops below REF minus the threshold. For example, the threshold may be 300 mV, and thus VOUT_LOW is asserted when VOUT drops below 1.2 V. Subsequently, VOUT_LOW is deasserted when VOUT returns above 1.2 volts.

[0023] exist Figure 1In Figure 1, the VOUT_LOW signal is represented by the coupling of VOUT low detection circuit 116 and switch 118. Switch 118 receives VIN and VOUT as inputs and provides AVDD to PWM modulator 108. Since VOUT_LOW is asserted, indicating that VOUT is below the value required to power PWM modulator 108, switch 118 couples VIN to AVDD. Similarly, since VOUT_LOW is deasserted, indicating that VOUT is sufficient to power PWM modulator 108, switch 118 couples VOUT to AVDD. As explained in further detail below, VOUT low detection circuit 116 avoids loading reference voltage REF, as it is a high-impedance input to the VOUT low detection circuit. Furthermore, VOUT low detection circuit 116 quickly detects a falling VOUT and, therefore, causes the switch to supply VIN to PWM modulator 108 to avoid hindering PWM modulator 108 performance. Finally, VOUT low detection circuit 116 has a sufficiently low quiescent current to maintain the efficiency benefits of supplying VOUT to PWM modulator 108.

[0024] Figure 2 FIG2 shows a circuit diagram of a VOUT low detection circuit 116 according to various examples of the present disclosure. The VOUT low detection circuit 116 includes a p-type MOSFET 202, which includes a gate, a source, and a drain. The gate of the p-type MOSFET 202 is coupled to REF (e.g., from Figure 1 The drain of the p-type MOSFET 202 is coupled to ground.

[0025] The VOUT low detection circuit 116 also includes a current source 204 that provides a reference current (Iref) and an n-type MOSFET 206 having a gate, a source, and a drain. The n-type MOSFET 206 is, for example, a natural transistor. The source of the p-type MOSFET 202 is coupled to the current source 204 and the gate of the n-type MOSFET 206, which has a voltage VGATE. As described above, VIN serves as the supply voltage for the VOUT low detection circuit 116 and is coupled to the current source 204 and the drain of the n-type MOSFET 206.

[0026] The VOUT low detection circuit 116 also includes a p-type MOSFET 208 and n-type MOSFETs 210 and 212, each of which includes a gate, a source, and a drain. The n-type MOSFET 212 is, for example, a natural transistor. In other examples, the n-type MOSFETs 206 and 212 include low VTH transistors (e.g., a VTH of approximately 150 mV), while in still other examples, the n-type MOSFETs 206 and 212 include high VTH transistors (e.g., a VTH of approximately 600 mV). The source of the n-type MOSFET 206 is coupled to the source of the p-type MOSFET 208, while the drain of the p-type MOSFET 208 is coupled to the drain of the n-type MOSFET 210, forming a node 216 that provides VOUT_LOW. The gates of both the p-type MOSFET 208 and the n-type MOSFET 210 are coupled to VOUT and thus serve as high-impedance inputs for VOUT. The source of the n-type MOSFET 210 is coupled to the drain and gate of the n-type MOSFET 212. The source of n-type MOSFET 212 is coupled to resistor 214, which in turn is coupled to ground. The current through resistor 214 is labeled Icmp. Figure 2 In the example of , VOUT_LOW is an analog signal; however, VOUT_LOW may be converted to a digital signal (eg, via a Schmitt trigger) before being provided to switch 118, as described above.

[0027] refer to Figure 3 The waveform 300 is used to describe Figure 2 1. The functionality of the exemplary VOUT low detection circuit 116 is shown. The REF, VOUT, VGATE, Iref, and Icmp waveforms correspond to the values ​​described above. The V_M_SF_S waveform corresponds to the source voltage of n-type MOSFET 206, which acts as a source follower. The V_M_BIAS_S waveform corresponds to the source voltage of n-type MOSFET 210. The V_M_PVT_S waveform corresponds to the source voltage of n-type MOSFET 212, which compensates for the process parameters of n-type MOSFET 206. The VOUT_LOW waveform corresponds to the analog voltage at node 216, while the VOUT_LOW_D waveform corresponds to a digitized version of the VOUT_LOW signal. For example, a Schmitt trigger receives analog VOUT_LOW as input and generates digital VOUT_LOW_D as output.

[0028] In addition, VGS is the gate-source voltage of the device. VTH is the threshold voltage of the device. VOV is the overdrive voltage of the device (VOV = VGS - VTH) and increases as the current through the device increases. A voltage followed by a reference number refers to the voltage of the device being referenced (e.g., VGS202 refers to the gate-source voltage of p-type MOSFET 202). Additionally, for the sake of the following discussion, certain assumptions are made, but these assumptions are not a limitation on the scope of the disclosed examples. For example, it is assumed that the device is in weak inversion (where the drain current has an exponential dependence on VGS), and the nominal value of Icmp is approximately 100 times that of Iref. It is also assumed that Figure 2 the subthreshold slope of the device is approximately 90 mV / decade. It is further assumed that p-type MOSFETs 202 and 208 are of the same device type and thus their VTH cancels out. It is also assumed that n-type MOSFETs 206 and 212 are of the same device type.

[0029] For the purposes of this example, it is assumed that REF is 1.5 V, and the additional threshold applied by the VOUT low detection circuit 116 is 350 mV. That is, when VOUT drops below approximately 1.15 V, VOUT_LOW_D should be asserted.

[0030] Figure 2 The trip point (e.g., the point at which VOUT_LOW is asserted) of the VOUT low detection circuit 116 of

[0031] VGATE = REF + VTH202 + VOV202

[0032] V_M_SF_S = VGATE - (VTH206 + VOV206); or

[0033] V_M_SF_S = REF + VTH202 + VOV202 - (VTH206 + VOV206)

[0034] To assert VOUT_LOW, and thus assert VOUT_LOW_D:

[0035] VOUT < V_M_SF_S - (VTH208 + VOV208), or

[0036] VOUT < REF + VTH202 + VOV202 - (VTH206 + VOV206) - (VTH208 + VOV208)

[0037] As described above, VTH202 and VTH208 cancel out, which results in

[0038] VOUT <REF+(VOV202-VOV208)-(VTH206+VOV206)

[0039] Since VTH 206 holds in the VOUT trip point determination, there is a process dependency introduced by the n-type MOSFET 206. Considering the above assumptions that the subthreshold slope of the device is 90 mV / decade and Icmp is 100 times Iref:

[0040] VOV202-VOV208=-180mV.

[0041] Additionally, VTH206 + VOV206 = VGS206, which is 170 mV in the example where n-type MOSFET 206 is a native transistor, and therefore VTH206 = -10 mV. Therefore, in this example, the VOUT trip point occurs when VOUT < 1.5 V - 180 mV - 170 mV = 1.15 V. In other words, when VOUT drops below 1.15 V, VOUT_LOW goes high, and therefore VOUT_LOW_D is asserted. The n-type MOSFET 212 reduces the process dependency of the n-type MOSFET 206 because a higher VTH206 reduces Icmp, which in turn reduces VOV206 and thus reduces the variation of VTH206 + VOV206 (which is used to calculate the VOUT trip point described above). In another example, the n-type MOSFETs 210, 212 can be removed from the circuit 116, although this has implications for process, temperature, and input voltage variations. In yet another example, a current source replaces the resistor 214 coupled to the source of the n-type MOSFET 212 .

[0042] Initially, VOUT and VREF are both 1.5V, and therefore the voltage applied to the gates of p-type MOSFETs 202 and 208 is the same. In this example, since p-type MOSFETs 202, 208 are the same device type and equal in size, the current through p-type MOSFETs 202, 208 is in the same range as Iref. The n-type MOSFET 210 sets the bias current Icmp as follows:

[0043] Icmp=(VOUT-VGS210-VGS212) / R

[0044] As long as the current through p-type MOSFET 208 is below Icmp, VOUT_LOW remains low. N-type MOSFET 212 is used to reduce process and temperature variations of n-type MOSFET 206. Since VOUT_LOW is low, VOUT_LOW_D remains deasserted, and thus switch 118 couples VOUT to AVDD to supply PWM modulator 108. In this configuration, the current drawn by VOUT low detection circuit 116 is limited to Iref, which is approximately 1 nA in this example. In this example, this is an acceptable tradeoff for the efficiency gained by supplying VOUT instead of VIN to PWM modulator 108.

[0045] As VOUT decreases, the drain current of p-type MOSFET 208 increases, while n-type MOSFET 206, acting as a source follower, keeps its source (and the source of p-type MOSFET 208) within VGS 206 of VGATE. Furthermore, the source voltage of n-type MOSFET 210 decreases, resulting in a lower voltage across resistor 214, which in turn reduces bias current Icmp. Once the current through p-type MOSFET 208 is greater than Icmp, the voltage at node 216, corresponding to VOUT_LOW, increases.

[0046] N-type MOSFET 206 maintains its source at VGATE-VGS206. Therefore, as VOUT approaches 1.15V, Icmp continues to increase, derived according to the equations and assumptions outlined above. Once VOUT crosses below the 1.15V threshold at time 302, p-type MOSFET 208 fully turns on, and VOUT_LOW is pulled to the source voltage of n-type MOSFET 206, or approximately 1.4V in this example. At the same time, the sources of both n-type MOSFETs 210, 212 are limited by the decreasing value of VOUT and their corresponding VGS values.

[0047] As mentioned above, VOUT_LOW is an analog voltage. However, VOUT_LOW can be provided as an input to a digitizer such as a Schmitt trigger, and thus, when VOUT_LOW crosses above a certain threshold, the output of the Schmitt trigger is asserted. The VOUT_LOW_D waveform reflects the digital signal output of the exemplary Schmitt trigger, which is provided to switch 118, causing it to couple VIN to AVDD to supply the PWM modulator.

[0048] As VOUT continues to drop beyond the threshold discussed above, ICMP begins to be limited by, for example, the decreasing gate voltage of n-type MOSFET 210. This is seen as a roughly linear decrease in ICMP after time 302. Since the maximum value of ICMP is limited by (VOUT - VGS210 - VGS212) / R, the point at which VOUT drops such that the current through p-type MOSFET 208 exceeds the maximum value of ICMP corresponds to VOUT_LOW being pulled high. Therefore, as VOUT further decreases, ICMP also decreases linearly.

[0049] Figure 3 Also demonstrated is the behavior of the VOUT low detection circuit 116 as VOUT increases above the threshold, which is essentially a mirror image of the behavior described above.

[0050] although Figure 3 The drop and ramp of VOUT shown and described above is gradual, but in some examples, a short circuit is created at load 114, causing VOUT to drop sharply to 0V. In this example, n-type MOSFET 210 acts as a fast detection transistor because it will be fully turned off with a gate voltage of 0V. At the same time, p-type MOSFET 208 will be fully turned on, and VOUT_LOW will quickly rise to the source voltage of n-type MOSFET 206. As described above, this causes VOUT_LOW_D to be asserted, which in turn causes switch 118 to couple VIN to AVDD to supply PWM modulator 108. After the short circuit is resolved and VOUT is restored, VOUT_LOW is pulled back to ground, as described above. Therefore, VOUT_LOW_D is deasserted, which in turn causes switch 118 to couple VOUT to AVDD to supply PWM modulator 108, thereby increasing the efficiency of DC-DC converter 102.

[0051] As described above, in some examples, both n-type MOSFET 206 and n-type MOSFET 212 comprise native transistors. n-type MOSFET 206, being a native transistor, allows more headroom to adjust the threshold, which causes VOUT_LOW to be pulled to the source voltage of n-type MOSFET 206 when VOUT drops below the threshold. That is, the VTH of the native transistor is quite low, and a higher VTH results in a lower voltage at the source of n-type MOSFET 206, which results in a lower voltage for detecting that VOUT has dropped too low or requires a higher input voltage to maintain. Additionally, native transistors exhibit less process variation in their threshold voltage, which is beneficial in this example because it provides a more accurate trip point for VOUT across process variations, thereby increasing the overall efficiency of DC-DC converter 102 when supplying VOUT to AVDD.

[0052] Figure 4 1 shows another circuit schematic diagram of the VOUT low detection circuit 116 according to various examples of the present disclosure. Figure 2 The example demonstrates the process dependency on the VTH of the n-type MOSFET 206 (VTH206 is maintained in the VOUT trip point determination), but Figure 4 The example circuit reduces this dependency.

[0053] The VOUT low detection circuit 116 includes a p-type MOSFET 402 including a gate, a source, and a drain. The gate of the p-type MOSFET 402 is coupled to REF (e.g., from Figure 1 120) and thus serves as a high-impedance input for REF. The drain of p-type MOSFET 402 is coupled to ground. VOUT low detection circuit 116 also includes an n-type MOSFET 404 having a gate coupled to its drain and a source coupled to the source of p-type MOSFET 402. N-type MOSFET 404 is, for example, a natural transistor.

[0054] The VOUT low detection circuit 116 also includes a current source 406 that provides a reference current (Iref) and an n-type MOSFET 408 that includes a gate, a source, and a drain. The n-type MOSFET 408 is, for example, a natural transistor. In other examples, the n-type MOSFETs 404 and 408 include low VTH transistors (e.g., 150 mV), while in still other examples, the n-type MOSFETs 404 and 408 include high VTH transistors (e.g., 600 mV). The drain of the n-type MOSFET 404 is coupled to the current source 406 and the gate of the n-type MOSFET 408, which has a voltage of VGATE. As described above, VIN serves as the supply voltage for the VOUT low detection circuit 116 and is coupled to the current source 406 and the drain of the n-type MOSFET 408.

[0055] The VOUT low detection circuit 116 also includes a p-type MOSFET 410 and an n-type MOSFET 412, each of which includes a gate, a source, and a drain. The source of the n-type MOSFET 408 is coupled to the source of the p-type MOSFET 410, while the drain of the p-type MOSFET 410 is coupled to the drain of the n-type MOSFET 412 and forms a node 416 that provides VOUT_LOW. The gates of both the p-type MOSFET 410 and the n-type MOSFET 412 are coupled to VOUT and thus serve as high impedance inputs for VOUT. The source of the n-type MOSFET 412 is coupled to a current source 414 that provides a bias current (Icmp). The current source 414 is also coupled to ground. Figure 4In the example shown, VOUT_LOW is an analog signal; however, VOUT_LOW can be converted to a digital signal (e.g., via a Schmitt trigger) before being provided to switch 118, as described above. In another example, n-type MOSFET 412 is removed and current source 414 is replaced by a resistor, although this has implications for process, temperature, and input voltage variations.

[0056] refer to Figure 5 The waveform 500 is used to describe Figure 4 The functionality of the exemplary VOUT low detection circuit 116 is shown. For example, the REF, VOUT, VGATE, Iref, and Icmp waveforms correspond to the values ​​described above. Additionally, the V_M_SF_S waveform corresponds to the source voltage of the n-type MOSFET 408, which functions as a source follower. The VOUT_LOW waveform corresponds to the analog voltage at node 416, while the VOUT_LOW_D waveform corresponds to a digitized version of the VOUT_LOW signal. For example, a Schmitt trigger receives analog VOUT_LOW as input and generates digital VOUT_LOW_D as output.

[0057] As compared to Figure 2 , assuming the device is in weak inversion (where the drain current has an exponential dependence on VGS), and that the nominal value of Icmp is about 100 times Iref. Also assume that Figure 4 The subthreshold slope of the device is about 90 mV / decade. It is further assumed that p-type MOSFETs 402 and 410 are of the same device type and therefore their VTHs cancel. It is also assumed that n-type MOSFETs 404 and 408 are of the same device type and therefore their VTHs cancel.

[0058] For the purposes of this example, assume that REF is 1.5V and that the additional threshold imposed by the VOUT low detection circuit 116 is 360mV. That is, when VOUT drops below approximately 1.14V, VOUT_LOW_D should be asserted.

[0059] Figure 4 The trip point of the VOUT low detection circuit 116 (eg, the point at which VOUT_LOW is asserted) is calculated as follows.

[0060] VGATE=REF+VTH402+VOV402+VTH404+VOV404

[0061] V_M_SF_S=VGATE-(VTH408+VOV408); or

[0062] V_M_SF_S=REF+VTH402+VOV402+VTH404+VOV404-

[0063] (VTH408 + VOV408)

[0064] To assert VOUT_LOW and thus assert VOUT_LOW_D:

[0065] VOUT < V_M_SF_S - (VTH410 + VOV410), or

[0066] VOUT < REF + VTH402 + VOV402 + VTH404 + VOV404 -

[0067] (VTH408 + VOV408) - (VTH410 + VOV410)

[0068] As described above, VTH402 and VTH410 cancel out, and VTH404 and VTH408 also cancel out, which results in

[0069] VOUT < REF + (VOV402 - VOV410) + (VOV404 - VOV408)

[0070] different from that maintained by VTH in the determination of the VOUT transition point. In Figure 2 the example of Figure 4 VTH is not maintained, which eliminates the process dependence on the n-type MOSFET 408. Considering the above assumptions that the subthreshold slope of the device is 90 mV / decade and Icmp is 100 times Iref:

[0071] VOV402 - VOV410 = -180 mV; and

[0072] VOV404 - VOV408 = -180 mV

[0073] Therefore, in this example, when VOUT < 1.5 V - 180 mV - 180 mV = 1.14 V, the VOUT transition point occurs. In other words, when VOUT drops below 1.14 V, VOUT_LOW becomes high and thus VOUT_LOW_D is asserted.

[0074] Initially, both VOUT and VREF are 1.5 V, and thus the voltages applied to the gates of the p-type MOSFETs 402 and 410 are the same. In this example, since the p-type MOSFETs 402, 410 are of the same device type and equal size, the currents through the p-type MOSFETs 202, 208 are within the same range as Iref.

[0075] As long as the current through p-type MOSFET 208 is below Icmp, VOUT_LOW remains low. Since VOUT_LOW is low, VOUT_LOW_D remains deasserted, and thus switch 118 couples VOUT to AVDD to supply PWM modulator 108. In this configuration, the current drawn by VOUT low detection circuit 116 is limited to Iref+Icmp. In this example, it is assumed that current Icmp can never exceed the current through p-type MOSFET 410, and that current source 414 is disconnected once n-type MOSFET 412 can no longer supply current Icmp. These assumptions describe the behavior of the MOSFET as a current source. In this configuration and under these assumptions, the current drawn by VOUT low detection circuit 116 is limited to 2*Iref, which is approximately 2nA in this example. In this example, this is an acceptable tradeoff for the efficiency gained by supplying VOUT instead of VIN to PWM modulator 108.

[0076] As VOUT decreases, the drain current of p-type MOSFET 410 increases, while n-type MOSFET 408, acting as a source follower, keeps its source (and the source of p-type MOSFET 410) within VGS 408 of VGATE. Once the current through p-type MOSFET 410 is greater than Icmp, the voltage at node 416 corresponding to VOUT_LOW will increase. Once VOUT decreases well below VTH 412, current source 414 is turned off, thereby accelerating short-circuit detection at the output.

[0077] N-type MOSFET 408 maintains its source at VGATE-VGS408. Therefore, as VOUT approaches 1.14V, Icmp continues to increase according to the equations and assumptions outlined above. Once VOUT crosses below the 1.14V threshold at time 302, p-type MOSFET 410 fully turns on, and VOUT_LOW is pulled to the source voltage of n-type MOSFET 408, or approximately 1.4V in this example. At the same time, the source of n-type MOSFET 410 is limited by the decreasing value of VOUT and its VGS value.

[0078] As mentioned above, VOUT_LOW is an analog voltage. However, VOUT_LOW can be provided as an input to a digitizer such as a Schmitt trigger, and thus, when VOUT_LOW crosses above a certain threshold, the output of the Schmitt trigger is asserted. The VOUT_LOW_D waveform reflects the digital signal output of the exemplary Schmitt trigger, which is provided to switch 118, causing it to couple VIN to AVDD to supply the PWM modulator.

[0079] As above relative to Figure 2 , in some examples, a short circuit is created at the load 114, causing VOUT to drop sharply to 0V. In this example, the n-type MOSFET 412 acts as a fast detection transistor because it will be fully turned off with a gate voltage of 0V. At the same time, the p-type MOSFET 410 will be fully turned on, and VOUT_LOW will quickly rise to the source voltage of the n-type MOSFET 408. As described above, this causes VOUT_LOW_D to be asserted, which in turn causes the switch 118 to couple VIN to AVDD to supply the PWM modulator 108. After the short circuit is resolved and VOUT is restored, VOUT_LOW is pulled back to ground, as described above. Therefore, VOUT_LOW_D is deasserted, which in turn causes the switch 118 to couple VOUT to AVDD to supply the PWM modulator 108, thereby increasing the efficiency of the DC-DC converter 102.

[0080] As described above, in some examples, both n-type MOSFET 408 and n-type MOSFET 404 comprise native transistors. n-type MOSFET 408, being a native transistor, allows more headroom to adjust the threshold, which, when VOUT drops below, causes VOUT_LOW to be pulled to the source voltage of n-type MOSFET 408. That is, the VTH of the native transistor is quite low, and a higher VTH results in a lower voltage at the source of n-type MOSFET 408, which results in a lower voltage for detecting that VOUT has dropped too low or requires a higher input voltage to maintain.

[0081] In the foregoing discussion and in the claims, the terms "including" and "comprising" are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to ...". In addition, the terms "couple" or "couples" are intended to refer to either an indirect or direct connection. Thus, if a first device is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. Similarly, a device coupled between a first component or location and a second component or location may be through a direct connection or through an indirect connection via other devices and connections. An element or feature that is "configured to" perform a task or function may be configured (e.g., programmed or structurally designed) by the manufacturer at the time of manufacture to perform that function, and / or may be configured (or reconfigurable) by the user after manufacture to perform that function and / or other additional or alternative functions. Configuration may be programmable through the firmware and / or software of the device, through the construction and / or layout of the hardware components and the interconnection of the devices, or a combination thereof. Furthermore, use of the phrase "ground" or similar terms in the foregoing discussion is intended to include chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is suitable or appropriate for the teachings of the present disclosure. Unless otherwise specified, the words "approximately," "about," or "substantially" preceding a value refer to + / - 10% of the stated value.

[0082] The above discussion is intended to illustrate the principles and various embodiments of the present disclosure. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. It is intended that the appended claims be interpreted as including all such changes and modifications.

Claims

1. A voltage detection device, comprising: a first transistor coupled to a ground node and a current source, the first transistor including a control terminal coupled to a reference voltage source, wherein the current source is coupled to an input voltage source; a second transistor coupled to the input voltage source, the second transistor including a control terminal coupled to the first transistor; a third transistor coupled to the second transistor, the third transistor including a control terminal coupled to an output voltage node; a fourth transistor coupled to the third transistor, the fourth transistor including a control terminal coupled to the output voltage node; as well as A fifth transistor is coupled to the fourth transistor and a resistor, the fifth transistor including a control terminal coupled to the fourth transistor, wherein the resistor is coupled to the ground node. 2 . The voltage detection device of claim 1 , wherein a node between the third transistor and the fourth transistor comprises a low output voltage indicator. 3 . The voltage detection device of claim 2 , further comprising a digitizer coupled to the low output voltage indicator. 4 . The voltage detection device according to claim 1 , wherein the second transistor and the fifth transistor comprise natural transistors.

5. The voltage detection device according to claim 1, wherein: The first transistor and the third transistor include p-type metal oxide semiconductor field effect transistors (p-type MOSFETs), each including a gate, a source, and a drain; and The second transistor, the fourth transistor, and the fifth transistor include n-type MOSFETs, each including a gate, a source, and a drain.

6. The voltage detection device according to claim 5, wherein: The first transistor gate is coupled to the reference voltage source, the first transistor drain is coupled to the ground node, and the first transistor source is coupled to the current source and the gate of the second transistor; The drain of the second transistor is coupled to the input voltage source, and the source of the second transistor is coupled to the source of the third transistor; The gate of the third transistor is coupled to the output voltage node, and the drain of the third transistor is coupled to the drain of the fourth transistor; The gate of the fourth transistor is coupled to the output voltage node, and the source of the fourth transistor is coupled to the drain and gate of the fifth transistor; and The source of the fifth transistor is coupled to the resistor.

7. A voltage detection device comprising: a first transistor coupled to a ground node, the first transistor including a control terminal coupled to a reference voltage source; a second transistor coupled to the first transistor and a first current source, the second transistor including a control terminal coupled to the first current source, wherein the first current source is coupled to an input voltage source; a third transistor coupled to the input voltage source, the third transistor including a control terminal coupled to the second transistor; a fourth transistor coupled to the third transistor, the fourth transistor including a control terminal coupled to an output voltage node; as well as a fifth transistor coupled to the fourth transistor and a second current source, the fifth transistor including a control terminal coupled to the output voltage node, wherein the second current source is coupled to the ground node. 8 . The voltage detection device of claim 7 , wherein a node between the fourth transistor and the fifth transistor comprises a low output voltage indicator. 9 . The voltage detection device of claim 8 , further comprising a digitizer coupled to the low output voltage indicator. 10 . The voltage detection device of claim 7 , wherein the second transistor and the third transistor comprise natural transistors.

11. The voltage detection device according to claim 7, wherein: The first transistor and the fourth transistor include p-type metal oxide semiconductor field effect transistors (p-type MOSFETs), each including a gate, a source, and a drain; and The second transistor, the third transistor, and the fifth transistor include n-type MOSFETs, each including a gate, a source, and a drain.

12. The voltage detection device according to claim 11, wherein: The first transistor gate is coupled to the reference voltage source, the first transistor drain is coupled to the ground node, and the first transistor source is coupled to the second transistor source; The second transistor drain is coupled to the second transistor gate, the first current source and the third transistor gate; The drain of the third transistor is coupled to the input voltage source and the source of the third transistor is coupled to the source of the fourth transistor; the fourth transistor gate being coupled to the output voltage node and the fourth transistor drain being coupled to the fifth transistor drain; and The fifth transistor gate is coupled to the output voltage node and the fifth transistor source is coupled to the second current source.

13. A voltage detection system comprising: A low output voltage detection circuit, the low output voltage detection circuit comprising: a first transistor coupled to a ground node and a current source, the first transistor including a control terminal coupled to a reference voltage source, wherein the current source is coupled to an input voltage source; a second transistor coupled to the input voltage source, the second transistor including a control terminal coupled to the first transistor; a third transistor coupled to the second transistor, the third transistor including a control terminal coupled to an output voltage node; a fourth transistor coupled to the third transistor, the fourth transistor including a control terminal coupled to the output voltage node; and a fifth transistor coupled to the fourth transistor and a resistor, the fifth transistor including a control terminal coupled to the fourth transistor, wherein the resistor is coupled to the ground node; a digitizer comprising an input coupled to a node between the third transistor and the fourth transistor and comprising a digital output; and a switch coupled to the digital output, the switch comprising: a first input coupled to the input voltage source; a second input coupled to the output voltage node; and An output configured to couple to the first input in response to the digital output being asserted and to couple to the second input in response to the digital output being de-asserted. 14 . The voltage detection system of claim 13 , wherein the output of the switch is configured to be coupled to a buck core of a power converter. 15 . The voltage detection system of claim 14 , wherein the output of the switch is configured to be coupled to a pulse width modulation modulator of the power converter.

16. The voltage detection system of claim 13, wherein the second transistor and the fifth transistor comprise natural transistors.

17. The voltage detection system according to claim 13, wherein: The first transistor and the third transistor include p-type metal oxide semiconductor field effect transistors (p-type MOSFETs), each including a gate, a source, and a drain; and The second transistor, the fourth transistor, and the fifth transistor include n-type MOSFETs, each including a gate, a source, and a drain.

18. The voltage detection system according to claim 17, wherein: The first transistor gate is coupled to the reference voltage source, the first transistor drain is coupled to the ground node, and the first transistor source is coupled to the current source and the gate of the second transistor; The drain of the second transistor is coupled to the input voltage source, and the source of the second transistor is coupled to the source of the third transistor; The gate of the third transistor is coupled to the output voltage node, and the drain of the third transistor is coupled to the drain of the fourth transistor; The gate of the fourth transistor is coupled to the output voltage node, and the source of the fourth transistor is coupled to the drain and gate of the fifth transistor; and The source of the fifth transistor is coupled to the resistor.

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