Analog-to-digital converter with dynamic range enhancer

Abstract

A circuit (100) includes a programmable gain amplifier (PGA 102) having a PGA output. The circuit (100) further includes a delta-sigma modulator (104) having an input coupled to the PGA output. The circuit (100) also includes a digital filter (114) and a dynamic range enhancer (DRE) circuit (110). The digital filter (114) is coupled to the delta-sigma modulator output and to the PGA (102). The DRE circuit (110) is configured to monitor a signal level of the delta-sigma modulator output. In response to the signal level being less than a DRE threshold, the DRE circuit (110) is configured to program the PGA to a gain level greater than unity gain and to cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA (102).

Description

BACKGROUND

[0001] Some applications process audio signals. For example, voice support applications include a signal chain that receives and processes an analog input signal (e.g., a voice signal). The signal chain can include amplifiers, analog-to-digital converters (ADCs), filters, etc. The growth of voice support applications with far-field pickup has benefited from a larger dynamic range. Unfortunately, the signal-to-noise ratio (SNR) of the signal path limits the dynamic range. SUMMARY

[0002] In one example, a circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit also includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. In response to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA to a gain level greater than unity gain and to cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA. BRIEF DESCRIPTION OF DRAWINGS

[0003] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0004] Figure 1 An example schematic of an ADC with dynamic range enhancement is shown.

[0005] Figure 2 And Figure 3 A relationship between an output signal from a delta-sigma modulator and a programmable gain setting of an ADC is illustrated.

[0006] Figure 4 The impact on the SNR of a signal path through an ADC with and without dynamic range enhancement is shown.

[0007] Figure 5 An example of an implementation of an ADC of Figure 1 with dynamic range enhancement is shown.

[0008] Figure 6 Another example of an implementation of an ADC of Figure 1 is shown. DETAILED DESCRIPTION

[0009] Figure 1An exemplary schematic of an ADC 100 that can be used, for example, to process electrical signals from an audio source (e.g., a microphone) is shown. In this example, the ADC 100 includes a programmable gain amplifier (PGA) 102, a delta-sigma modulator 104, a cascaded integrator comb filter (CIC) decimator 106, a decimation filter 112, a programmable high pass filter 114, a gain scaling coefficient coarse adjustment 116, a gain scaling coefficient fine adjustment 118, programmable biquads 120, a digital mixer 122, a volume control 124, and a dynamic range enhancement (DRE) circuit 110. The decimation filter 112, the programmable high pass filter 114, the gain scaling coefficient coarse adjustment 116, the gain scaling coefficient fine adjustment 118, the programmable biquads 120, the digital mixer 122, and the volume control 124 each include a digital signal chain. The PGA 102 includes an input that receives an analog signal (e.g., an audio signal) to be converted to a digital signal by the ADC 100. The gain of the PGA 102 is programmable. In one implementation, for example, the gain of the PGA 102 can be programmed to be at unity gain (zero DB) to an upper gain setting of 60 DB in increments of 0.5 DB (i.e., 0 DB, 0.5 DB, 1 DB, 1.5 DB, etc.).

[0010] The analog-to-digital conversion process in this example uses a delta-sigma modulator 104. The output of the delta-sigma modulator 104 is provided to the input of a CIC decimator 106. The CIC decimator 106 reduces the data output rate of the delta-sigma modulator 104, thereby reducing the power consumption of the subsequent digital logic. The output signal from the CIC decimator 106 is denoted as x(n). The signal x(n) is modified by a DRE circuit 110 and provided to a decimation filter 112, which continues to reduce the oversampled data rate to the desired Nyquist sampling rate of the output signal. A programmable high pass filter 114 includes a digital filter that removes the DC component of the signal. The filtered signal from the programmable high pass filter 114 is modified according to a gain setting implemented by a gain scaling coarse adjustment 116 and a gain scaling fine adjustment 118. The overall gain scaling compensates for any gain deviation between the analog input signal and / or the microphone. A programmable biquad filter 120 provides the user with customized frequency domain shaping. A digital mixer 122 provides the ability to combine multiple channels into a single output or improve the signal-to-noise ratio (SNR) of the input signal by feeding the same input to multiple channels and summing them equally. Finally, a volume control 124 provides fine control over the output signal level. The PGA 102, delta-sigma modulator 104, CIC decimator 106, decimation filter 112, filter 114, gain scaling adjustments 116 and 118, programmable biquad filter 120, digital mixer 122, and volume control 124 all include a signal path through the ADC 100 of the analog signal to convert the analog signal to a digital signal.

[0011] The DRE circuit 110 includes a CIC pre-processor 130, a DRE high-pass filter 132, an absolute value generator 134, a dB converter 136, a gain calculator 138, a level calculator 139, an averager 140, a group delay compensator 142, and a log-to-linear converter 144. The DRE circuit 110 increases the dynamic range of the delta-sigma modulator by increasing the gain of the PGA 102 for signal levels below a threshold level (x(n)) and then digitally attenuating the filtered signal by the same amount as the gain of the PGA 102. For example, if the PGA 102 is to be programmed by the DRE circuit 110 for a gain of +24 dB, an attenuation of -24 dB will be applied to the digital filtered signal. As a result, the signal chain will achieve unity gain between its input and output. In one implementation, the gain of the signal chain can be other than unity gain (e.g., greater than unity gain), and the gain increase and subsequent attenuation described herein will keep the overall channel gain constant regardless of whether the overall gain is unity gain or a different gain factor. By increasing the gain of the PGA 102 for low level input signals, the signal level is raised above the input reference noise level of the delta-sigma modulator 104. As a result, the delta-sigma modulator 104 would otherwise convert the low level input signal to a digital code with lower noise, which allows the use of a lower performance (e.g., higher noise), lower cost delta-sigma modulator 104 while maintaining the high dynamic range of a more expensive delta-sigma modulator.

[0012] The CIC pre-processor 130 of the DRE circuit 110 receives x(n) as an input signal. In one exemplary implementation, the CIC pre-processor 130 averages a number of CIC output samples and removes the previously applied PGA gain. The CIC pre-processor 130 implements the following logic in at least one example:

[0013]

[0014] where invPGAagain is the inverse PGA gain and N is the number of CIC outputs that are averaged together. This reduces the power consumption of the DRE and flattens any rapidly changing signals by the estimate of the input level.

[0015] The processed signal from the CIC pre-processor 130 is provided to the DRE high-pass filter 132, which removes the DC bias for accurate calculation of the input signal level. In one example, the DRE high-pass filter 132 is given by:

[0016] h(n) = b1g(n) + b2g(n - 1) - a2h(n - 1) (2)

[0017] where h(n) is the current output value from filter 132, b1, b2, and a2 are filter coefficients, g(n) is the current input value to the filter, g(n-1) is the previous input value to filter 132, and h(n-1) is the previous output value from filter 132. In one example, DRE high-pass filter 132 has a 3-dB corner of 4 Hz.

[0018] The filtered output h(n) from DRE high-pass filter 132 is provided to absolute value generator 134, which outputs the absolute value of the filter output. dB converter 136 converts the output from absolute value generator 134 from a linear value to a dB value h dB (n). The output h dB (n) of dB converter 136 is:

[0019] h dB (n) = 20*log 10 (|h(n)|) (3)

[0020] In one example, dB converter 136 includes a look-up table (LUT) that maps the input signal h dB (n) to the output dB value h (n) to reduce the power consumption of the dB conversion. The output of dB converter 136 is provided to gain calculator 138.

[0021] In this example, gain calculator 138 is programmed with parameters for processing the input value h dB (n) to generate the output value y dB (n). The parameters used by gain calculator 138 include, for example, an attack value 150, a Max Gain value 151, a sustain value 152, a threshold value 153, and a release value 154. In one example, gain calculator 138 calculates y dB (n) as follows:

[0022]

[0023] When the input value is greater than the threshold, the output value y dB (n) of the gain calculator is thus equal to the input value h dB (n), meaning that the PGA 102 should be programmed for unity gain (0 dB). If the input value h dB (n) is less than the threshold but greater than the threshold minus the programmed Max Gain value (MaxGain), the output signal level from gain calculator 138 should be held at the value of the threshold. If the input is below the threshold - MaxGain, the output of the gain calculator will be calculated as h dB (n) + MaxGain.

[0024] The computed output y from gain calculator 138 dB (n) is provided to level calculator 139, which calculates:

[0025] y L (n) = h dB (n) - y dB (n) (5)

[0026] The negative value y L (n) is the gain value that should be set for PGA 102.

[0027] The output y from level calculator 130 L (n) is provided to averager 140, which implements any of a variety of smoothing techniques to avoid glitches (e.g., sudden disconnections) in the output signal level of the PGA. The output of averager 140 is used to program the gain setting for PGA 103. In one implementation, averager 140 implements a Smooth Decoupled averaging technique that uses an attack value 150 if the input to averager 140 is greater than a threshold and increasing, or a release value 154 if the input to averager 140 is relatively low. The attack rate can be different from the release rate. One implementation of the Smooth Decoupled technique is as follows:

[0028] Z G (n) = Release * Z G (n - 1) + (1 - Release) * y L (n) (6)

[0029]

[0030] Equations (6) and (7) minimize the clipping and distortion of the output signal during the transition between attack and release. Attack and Release can be the same value or different values. In practice, the attack rate is less than the release rate (and sometimes significantly less) to prevent clipping in the delta-sigma modulator when the input signal rapidly increases. The releaseHold, attackHold, and hysteresis values prevent artifacts in the output signal when the input signal constantly toggles from high to low (or vice versa). The releaseCount is the number of consecutive releases that occur after an attack. Similarly, the attackCount is the number of consecutive attacks that occur after a release. The attackCount and releaseCount are zeroed when an attack immediately follows a release or a release immediately follows an attack. The hysteresis is the amount of change in the signal level from the previous state around the threshold value when the algorithm does not respond to the change. This allows the input signal to cross back and forth across the threshold level without causing output distortion due to constant switching of the DRE gain switch.

[0031] In other implementations, the averager 140 implements a weighted exponential moving average (WEMA) or a smoothing branch. An exemplary implementation of the WEMA includes computing the output z L (n) value as an average of:

[0032] z L (n) = Release * z G (n-1) + (1 - Attack) * y L (n) (8)

[0033] An exemplary implementation of the smoothing branch includes computing the output z L (n) as an average of the averager 140:

[0034]

[0035] where the attack and release counts are defined in a manner similar to the smoothing decoupling technique.

[0036] As described above, the DRE circuit 110 can be operated to increase the gain of the PGA 102 for signal levels (x(n)) below the threshold value and cause a corresponding amount of attenuation by the digital filter to cancel out the net effect of the gain increase of the PGA 102 and the attenuation in the digital filter, and the net gain realized by the signal chain of the ADC 100 is 0 dB. In response to the signal y dB (n) being above the threshold value, the PGA 102 is set to unity gain.

[0037] Figure 2The input (h(dB)) shown to the gain calculator 138 is related to the gain setting programmed into the PGA 102 and the corresponding attenuation programmed into the digital filter. At input signal levels above the threshold (Threshold) 153, the gain of the PGA 102 is set to unity gain (0 dB). However, at input signal levels below the threshold 153, the gain to the PGA 102 is increased as the input signal level decreases. The gain is increased as the input signal decreases until the gain setting reaches the programmed Max Gain value 151. At further decreases in the input signal, the gain setting of the PGA 102 remains at Max Gain 151. Figure 2 The inverse attenuation is also shown to be applied to the digital back end. Thus, at signal levels greater than the threshold 153, unity gain is applied to the digital back end, while for input signals below the threshold 153 and increasing, attenuation is applied to the digital back end to counteract the gain setting programmed into the PGA 102 to maintain unity gain through the entire signal chain.

[0038] Figure 3 The effect of the gain programmed into the PGA 102 for h dB (n) is shown. For h dB (n) above the threshold, unity gain is programmed into the PGA 102 and thus the output of the PGA follows its input (i.e., the PGA output signal level is equal to the input signal level). For h dB (n) below the threshold, the gain of the PGA is increased above unity gain to keep the PGA output at a constant level equal to the threshold until Max Gain is reached.

[0039] Referring back to Figure 1 The gain setting provided by the averager 142 to the PGA 102 is also provided to the group delay compensator 142. The group delay compensator 142 includes one or more delay elements to delay the application of the corresponding attenuation value to the digital back end to cause a delay through the signal chain including the PGA 102, the delta-sigma modulator 104 and the CIC decimator 106 and the processing elements of the DRE for each channel. The group delay compensator thus causes inverse attenuation to be applied into the digital back end to be consistent with the sampling applied by the output of the PGA 102, the delta-sigma modulator 104 and the CIC decimator 106. The delayed attenuation value from the group delay compensator 142 is provided to the log-to-linear converter 144 which converts the attenuation dB value to a linear value applied to the DRE digital gain element 146. In one example, the log-to-linear converter 144 includes a look-up table that maps the dB attenuation value to a corresponding linear value to reduce the power consumption of the system.

[0040] In Figure 1 In some implementations, the DRE signal level estimate occurs between the delta-sigma modulator 106 and the digital filter. In other implementations, the DRE circuit 110 can be coupled to the output of the digital filter (e.g., the output of the decimation filter 112).

[0041] Figure 4 An example is provided that illustrates the benefits of the DRE circuit 110. Figure 4 A microphone 402, PGA 404, delta-sigma modulator 406, and digital filter 408 are shown. The set of values 410, 412, 414, 416, 418, and 420 across the top of the figure represent example values for SNR, noise, etc. at various points along the signal chain. As shown by the example of 410, the microphone 402 has an SNR of 70 dB, a dynamic range of 114 dB with respect to a root mean square voltage of 2 Vrms, and an output noise value of 4 microvolts rms (4 μVrms). Value 412 illustrates that the PGA 404 has an SNR of 12 dB with respect to 2 Vrms, is set for a gain of 0 dB, and has an input reference noise value of 2 μVrms. The root mean square noise at the output of the PGA 414 is shown at 404 to be 4.47 μVrms, and is the root mean square of the 4 μVrms microphone output noise and the 2 μVrms input reference noise. In this example, the delta-sigma modulator 406 has an SNR value of 108 dB with respect to 2 Vrms, and adds 7.96 μVrms of noise. The root mean square of the PGA's output 4.47 Vrms and the delta-sigma modulator's 7.96 μVrms is calculated at 418 to be 9.13 μVrms. Reference number 420 shows that the final output noise is thus 9.13 μVrms. Therefore, the dynamic range degradation due to the signal path of the PGA 404, delta-sigma modulator 406, and digital filter 408 is 20 x log(9.13 μVrms / 4 μVrms) = 7.17 dB. Thus, without the benefit of the DRE circuit 110, the dynamic range of the ADC would be 114 dB - 7.17 dB = 106.83 dB.

[0042] As Figure 4As shown, the DRE circuit 110 adjusts the gain of the PGA 404 based on the output signal from the Δ-Σ modulator 406. The bottom set of values ​​430, 432, 434, 436, and 438 illustrates the effect of the DRE circuit 110. In this example, the gain adjustment is shown as a gain setting of +24 dB at 430. At 412, the PGA 404 is set to a gain of 0 dB, but at 430, since the Δ-Σ modulator output is below the threshold, the gain of the PGA is set to +24 dB. The digital filter 408 is set to a corresponding attenuation of -24 dB as shown at 438. The input reference noise of the PGA remains 2 μVrms (430), but the root mean square noise at the output of PGA 404 is shown at 432 as 70.88 μVrms, which is the root mean square of the 4 μVrms microphone output noise and the 2 μVrms PGA input reference noise, with an applied gain of 24 dB. As shown at 434, the noise of the Δ-Σ modulator 406 is the same, at 7.96 μVrms. Therefore, the combined root mean square noise at the output of the Δ-Σ modulator 406 is 71.31 μVrms, as shown at 434. Figure 438 shows that after applying a 24 dB attenuation through the digital filter 408, the final output noise is 4.50 μVrms. Therefore, the dynamic range degradation caused by the signal paths of PGA 404, Δ-Σ modulator 406, and digital filter 408 is 20xlog(4.50μVrms / 4μVrms) = 1.02dB. Consequently, thanks to the DRE circuit 110, the ADC's dynamic range will be 114dB - 1.02dB = 112.98dB, which is significantly higher than the 106.83dB obtained without the DRE circuit 110.

[0043] In these examples, modifications to the gain of PGA 102 are all based on the amplitude of the input signal. As mentioned above, the RMS amplitude of the input signal is determined and used to set the gain of the PGA. In another example, the average value of the input signal can be determined and used to set the gain of the PGA. In yet another example, the peak value of the input signal can be determined and used to set the gain of the PGA. In the examples above, the input signal level is determined based on the output of the Δ-Σ modulator 406. In another example, the signal level can be determined using the output signal from the digital filter 408. Furthermore, in Figure 1 and Figure 4 The diagram illustrates an ADC based on a Δ-Σ modulator. In other implementations, ADCs with architectures other than those based on Δ-Σ modulators are used. For example, an ADC based on a successive approximation register (SAR) can be used.

[0044] Figure 5 Will Figure 1An exemplary implementation of the ADC 100 of FIG. 1 is shown as ADC 500. The ADC 500 in this example provides multiple input channels (analog input 1, analog input 2, analog input 3,..., analog input N). A PGA 102, a delta-sigma modulator-based ADC 104, and a CIC decimator 106 are provided for each analog input channel. In this example, the PGAs 102, delta-sigma modulator-based ADCs 104, and CIC decimators 106 of the N input channels are coupled to and share other components shown as including a dB converter 136, a group delay compensator 142, a log-to-linear converter 144, a processor 508, and a storage device 510. The storage device 510 includes any suitable type of solid state storage device, such as a volatile memory (e.g., random access memory) or a non-volatile storage device (e.g., read only memory). In one implementation, the processor is a digital signal processor (DSP). In executing instructions 512, the processor 508 performs the functions of the CIC pre-processor 130, the DRE high pass filter 132, the absolute value generator 134, the gain calculator 138, the level calculator 139, the averager 140, the DRE digital gain 146, the decimation filter 112, the programmable high pass filter 114, the gain scaling coarse 116, the gain scaling fine 118, the programmable biquad filter 120, the digital mixer 122, and the volume control 124.

[0045] Figure 6 An exemplary implementation of an integrated circuit (IC) 600 is shown that includes four ADC channels—channel 1 through channel 4. Each ADC channel includes a PGA 602 coupled to a delta-sigma modulator ADC 604. The delta-sigma modulator ADC 604 is coupled to digital circuitry 610 that includes the DRE circuitry 110 described above as well as digital filters, biquad filters, etc. A serial interface 620 is coupled to the digital circuitry 610 through which digital output codes can be provided to external logic. A control interface 630 is included through which parameters Attack 150, Max Gain 151, Hold 152, and Threshold 154 can be programmed into the IC and stored in registers or other types of storage elements within the control interface 630 or elsewhere within the IC 600.

[0046] In this specification, the term "couple" or "couples" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection can be through a direct connection or through an indirect connection via other devices and connections. The recitation "based on" means "based at least in part on." Therefore, if X is based on Y, X can be a function of Y and any number of other factors. Modifications can be made to the described implementations, and other implementations are possible. The scope of the claims should not be limited by the described implementations.

Claims

1. A circuit comprising: a programmable gain amplifier (PGA) having a PGA output; a delta-sigma modulator having an input coupled to the PGA output, the delta-sigma modulator having a delta-sigma modulator output; a digital filter coupled to the delta-sigma modulator output; and a dynamic range enhancer (DRE) circuit coupled to the delta-sigma modulator output and the PGA, the DRE circuit configured to: monitor a signal level of the delta-sigma modulator output; and in response to the signal level being less than a DRE threshold, program the PGA to a gain level greater than unity gain and cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA.

2. The circuit of claim 1, wherein, the DRE circuit is configured to calculate the gain level of the PGA based on a comparison of an output signal derived from the delta-sigma modulator output to a threshold.

3. The circuit of claim 2, wherein, the DRE circuit is configured to program the PGA unity gain in response to the output signal derived from the delta-sigma modulator being greater than the DRE threshold.

4. The circuit of claim 1, wherein, the DRE circuit includes an averager configured to flatten the gain level to be programmed into the PGA.

5. The circuit of claim 2, wherein, the DRE circuit includes: a linear-to-log converter to convert a signal derived from the delta-sigma modulator output to a dB value; a gain calculator to determine whether the dB value is above or below the DRE threshold and to generate a gain calculator output value based in part on the comparison; and a level calculator to determine a difference between the gain calculator output value and the dB value resulting in a level calculator output value.

6. The circuit of claim 5, wherein, the DRE circuit includes an averager to determine an average of the level calculator output values.

7. The circuit of claim 5, wherein, the DRE circuit further includes a delay compensator configured to delay applying the attenuation to the digital filter relative to the PGA programmed for the gain level.

8. The circuit of claim 7, wherein, the DRE circuit includes a processor and a storage device including machine instructions that, when executed by the processor, cause the processor to implement the gain calculator, the level calculator, and the averager of the DRE circuit.

9. A circuit comprising: a programmable gain amplifier (PGA) having a PGA output; an analog-to-digital converter (ADC) having an input coupled to the PGA output, the ADC having an ADC output; a digital signal chain coupled to the ADC output; and a dynamic range enhancer (DRE) circuit configured to: monitor a signal level of the ADC output or a signal level derived from the ADC output; and in response to the signal level being less than a DRE threshold, programming the PGA to a gain level greater than unity gain and causing the digital signal chain to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA.

10. The circuit of claim 9, wherein, The ADC comprises a delta-sigma modulator.

11. The circuit of claim 9, wherein, The digital signal chain comprises a digital filter, and the DRE circuit is configured to cause the digital filter to implement the attenuation.

12. The circuit of claim 10, wherein, The DRE circuit is configured to calculate the gain level of the PGA based on a comparison of an output signal output by the ADC to a threshold or based on a comparison derived from the output signal output by the ADC and the threshold.

13. The circuit of claim 12, wherein, The DRE circuit is configured to program unity gain for the PGA in response to the output signal being greater than the DRE threshold.

14. The circuit of claim 9, wherein, The DRE circuit comprises an averager configured to flatten the gain level to be programmed into the PGA.

15. The circuit of claim 12, wherein, The DRE circuit comprises: a linear-to-log converter to convert a signal derived from a delta-sigma modulator output of the delta-sigma modulator to a dB value; a gain calculator to determine whether the dB value is above or below the DRE threshold and generate a gain calculator output value based in part on the comparison; and a level calculator to determine a difference between the gain calculator output value and the dB value to produce a level calculator output value.

16. The circuit of claim 15, wherein, The DRE circuit comprises an averager to determine an average of the level calculator output values.

17. The circuit of claim 11, wherein, The DRE circuit further comprises a delay compensator configured to delay application of the attenuation to the digital filter relative to the PGA programmed for the gain level.

18. A circuit comprising: a programmable gain amplifier (PGA) having a PGA output; a delta-sigma modulator having an input coupled to the PGA output, the delta-sigma modulator having a delta-sigma modulator output; a digital filter coupled to the delta-sigma modulator output; and a dynamic range enhancer (DRE) circuit coupled to the delta-sigma modulator output and the PGA, the DRE circuit configured to: monitor a signal level of the delta-sigma modulator output; and in response to the signal level being less than a DRE threshold, program the PGA to a gain level greater than unity gain and cause the digital filter to implement an attenuation of the same magnitude as the gain level to be programmed into the PGA, wherein the DRE circuit is configured to program the gain level of the PGA based on a comparison of an output signal derived from the delta-sigma modulator output to a threshold.

19. The circuit of claim 18, wherein, The DRE circuit comprises: a linear-to-log converter to convert a signal derived from a delta-sigma modulator output of the delta-sigma modulator to a dB value; a gain calculator to determine whether the dB value is above or below the DRE threshold and generate a gain calculator output value based in part on the comparison; and a level calculator to determine a difference between the gain calculator output value and the dB value to produce a level calculator output value. a level calculator for determining a difference between the gain calculator output value and the dB value to produce a level calculator output value; and an averager for determining an average of the level calculator output values.

20. The circuit of claim 19, wherein, The PGA has a PGA input configured to receive an electrical signal from an audio source.

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